Semiconductor device

Abstract

To provide a semiconductor device which is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena.SOLUTION: A semiconductor device according to the present disclosure includes: a first capacitive element; a first switching circuit that applies a first input voltage to one end of the first capacitive element in a sampling mode and holds the first input voltage in the first capacitive element in a hold mode; a first inversion signal generation circuit that generates a voltage that inverts the first input voltage in the sampling mode and holds the generated voltage in the hold mode; a second capacitive element to which the voltage generated by the first inversion signal generation circuit is applied to one end; and a negative feedback circuit that generates an output signal according to the voltage of a first node that is commonly connected to the other end of the first capacitive element and the other end of the second capacitive element in the hold mode, and applies a first feedback signal corresponding to the output signal to one end of the first capacitive element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device capable of operating with high precision by suppressing errors caused by dielectric relaxation phenomena. [Background technology]

[0002] Patent Document 1 discloses a charge redistribution type successive approximation AD conversion circuit that suppresses errors in AD conversion caused by dielectric relaxation phenomena. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-107985 A Summary of the Invention [Problem to be solved by the invention]

[0004] Not only the AD conversion circuit disclosed in Patent Document 1, but also semiconductor devices to which a negative feedback circuit is applied are required to suppress errors caused by the dielectric relaxation phenomenon and to operate with high precision.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure includes a first capacitive element, a first switch circuit that applies a first input voltage to one end of the first capacitive element in a sampling mode and causes the first input voltage to be held in the first capacitive element in a hold mode after the sampling mode, a first inversion signal generation circuit that generates a voltage obtained by inverting the first input voltage in the sampling mode and holds the generated voltage in the hold mode, a second capacitive element having one end to which the voltage generated by the first inversion signal generation circuit is applied, and a negative feedback circuit that generates an output signal according to a voltage of a first node to which the other end of the first capacitive element and the other end of the second capacitive element are commonly connected in the hold mode, and applies a first feedback signal corresponding to the output signal to one end of the first capacitive element. Effect of the Invention

[0007] The present disclosure can provide a semiconductor device capable of operating with high precision by suppressing errors caused by the dielectric relaxation phenomenon. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a timing chart showing the operation of the semiconductor device shown in FIG. [Diagram 3] FIG. 3 is a diagram showing an equivalent circuit of capacitance elements Cs and Cdac each having a dielectric relaxation phenomenon. [Figure 4] FIG. 4 is a timing chart showing the operation of the equivalent circuit shown in FIG. [Diagram 5] FIG. 5 is a circuit diagram showing a first modified example of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a timing chart showing another example of the operation of the semiconductor device shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a circuit diagram showing a specific example of the semiconductor device shown in FIG. [Figure 11] FIG. 11 is a circuit diagram showing a first modified example of the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a circuit diagram showing a second modified example of the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a circuit diagram showing a specific example of the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 17] FIG. 17 is a circuit diagram showing a specific example of the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a circuit diagram showing a first modified example of the semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a timing chart showing the operation of the semiconductor device shown in FIG. [Figure 20] FIG. 20 is a circuit diagram showing a second modified example of the semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a circuit diagram showing a configuration example of a semiconductor device according to the fourth embodiment. [Figure 22] FIG. 22 is a timing chart showing the operation of the semiconductor device shown in FIG. [Diagram 23] FIG. 23 is a circuit diagram showing a first configuration example of a semiconductor device that has been previously examined. [Figure 24] FIG. 24 is a timing chart showing the operation of the semiconductor device shown in FIG. [Diagram 25] FIG. 25 is a diagram showing an equivalent circuit of a capacitive element Cs having a dielectric relaxation phenomenon. [Figure 26] FIG. 26 is a circuit diagram showing a second configuration example of a semiconductor device that has been previously examined. [Figure 27] FIG. 27 is a timing chart showing the operation of the semiconductor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be interpreted narrowly based on the description in the drawings. Also, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0011] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0012] <Preliminary review by inventors, etc.> Before describing the semiconductor device according to the present embodiment, a semiconductor device previously examined by the present inventors will be described.

[0013] 23 is a circuit diagram showing a configuration example of a previously examined semiconductor device 7. The semiconductor device 7 is a so-called single-input charge redistribution type successive approximation AD converter, which converts an analog input voltage Vin into a digital output signal ADOUT using a binary search algorithm and outputs it.

[0014] Specifically, the semiconductor device 7 includes a comparator 721, a successive approximation register circuit (SAR Logic) 722, a DA converter 723, a capacitance element Cs, and switches SW71 to SW73.

[0015] The capacitance element Cs is provided between the non-inverting input terminal of the comparator 721 and the node Ns. The switch SW71 is provided between an input terminal (hereinafter referred to as the input terminal Vin) to which an input voltage Vin is supplied from outside the semiconductor device 7, and the node Ns (one end of the capacitance element Cs). The switch SW73 is provided between the non-inverting input terminal (the other end of the capacitance element Cs) of the comparator 721 and a reference voltage terminal to which a reference voltage Vss is supplied. The reference voltage Vss is supplied to the inverting input terminal of the comparator 721.

[0016] The successive approximation register circuit 722 outputs a digital signal (a control signal for controlling the switch of the DA converter 723) according to the comparison result of the comparator 721, and outputs an output signal ADOUT with a confirmed digital value. The DA converter 723 converts the digital signal output from the successive approximation register circuit 722 into an analog voltage and outputs it. Specifically, the DA converter 723 has a plurality of switches that are switched on and off based on the digital signal of the successive approximation register circuit 722, and a plurality of capacitive elements whose capacitance values ​​are binary-weighted, and performs DA conversion processing while redistributing the charges accumulated in each of the plurality of capacitive elements by switching the connections of the plurality of capacitive elements using the plurality of switches based on the input voltage Vin and the reference voltage Vref. The switch SW72 is provided between the output of the DA converter 723 and a node Ns.

[0017] 24 is a timing chart showing the operation of the semiconductor device 7. Each switch is turned off by a low-level control signal and turned on by a high-level control signal. The operation modes of the semiconductor device 7 include at least a sampling mode and a hold mode.

[0018] First, in the sampling mode, the switch SW71 indicates an on state, the switch SW72 indicates an off state, and the switch SW73 indicates an on state. As a result, the input voltage Vin is sampled. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. After that, in the hold mode, the switch SW71 switches from on to off, the switch SW72 switches from off to on, and the switch SW73 switches from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs.

[0019] At this time, in the DA converter 723, the semiconductor device 7 redistributes the charges stored in each of the multiple capacitive elements based on the input voltage Vin and the reference voltage Vref by switching the connections of the multiple capacitive elements using multiple switches, while using the comparator 721 and the successive comparison register circuit 722 to perform a successive comparison operation of the output voltage of the DA converter 723 and the input voltage Vin.

[0020] However, the semiconductor device 7 has a problem in that it cannot operate with high precision due to an error in AD conversion caused by the dielectric relaxation phenomenon.

[0021] Fig. 25 is a diagram showing an equivalent circuit of a capacitance element Cs having a dielectric relaxation phenomenon. As shown in Fig. 25, in addition to an intrinsic capacitance Cstd, a plurality of series circuits each consisting of a parasitic resistance and a parasitic capacitance are connected in parallel to the capacitance element Cs. The time constants of each of these plurality of series circuits are different from each other, and it is known that they are a distributed constant model having a wide frequency band.

[0022] 24, for example, in the semiconductor device 7, the operation mode may switch from the sampling mode to the hold mode in a state (dotted line) in which the input voltage Vin has not yet reached an ideal level (solid line), which may cause the voltage Vm of the non-inverting input terminal (the other end of the capacitive element Cs) of the comparator 721 to fluctuate in the hold mode, and as a result, the semiconductor device 7 may not be able to perform AD conversion processing with high accuracy.

[0023] Therefore, the inventors next examined the semiconductor device 8. 26 is a circuit diagram showing a configuration example of a previously examined semiconductor device 8. Compared with the semiconductor device 7, the semiconductor device 8 further includes a sub AD converter 812, a sub DA converter 813, a capacitance element Cdac, and switches SW81 to SW83.

[0024] The capacitive element Cdac has the same capacitance value as the capacitive element Cs and is provided between the inverting input terminal of the comparator 721 and a node Ndac. The switch SW81 is provided between the input terminal Vin and the node Ndac (one end of the capacitive element Cdac). The switch SW83 is provided between the inverting input terminal of the comparator 721 (the other end of the capacitive element Cdac) and a reference voltage terminal. The sub AD converter 812 and the sub DA converter 813 are provided in parallel with the switch SW81 between the input terminal Vin and the node Ndac. The AD converter 812 converts an analog input voltage Vin into a digital signal and outputs it. The DA converter 813 converts a digital signal output from the AD converter 812 into an analog voltage and outputs it. The switch SW82 is provided between the output of the DA converter 813 and the node Ndac.

[0025] 27 is a timing chart showing the operation of the semiconductor device 8. Note that each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 8 include at least a sampling mode and a hold mode.

[0026] First, in the sampling mode, the switches SW71 and SW81 indicate an on state, the switches SW72 and SW82 indicate an off state, and the switches SW73 and SW83 indicate an on state. As a result, the input voltage Vin is sampled. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). Also, a charge according to the input voltage Vin is accumulated in the node Ndac (one end of the capacitance element Cdac). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, the voltage Vdac of the node Ndac ideally indicates the input voltage Vin. After that, in the hold mode, the switches SW71 and SW81 are switched from on to off, the switches SW72 and SW82 are switched from off to on, and the switches SW73 and SW83 are switched from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs. Also, the sampled input voltage Vin is held in the capacitance element Cdac. Strictly speaking, a sequence in which the switch SW81 is switched from on to off, the switch SW82 is switched from off to on, then the switches SW73 and SW83 are switched from on to off, the switch SW71 is switched from on to off, and the switch SW72 is switched from off to on is desirable. This is because it is possible to eliminate the influence of errors in the AD converter 812 and the DA converter 813. However, this strict timing operation is not necessary when the influence of dielectric relaxation is taken into consideration.

[0027] At this time, in the DA converter 723, the semiconductor device 8 redistributes the charges stored in each of the multiple capacitive elements based on the input voltage Vin and the reference voltage Vref by switching the connections of the multiple capacitive elements using multiple switches, while using the comparator 721 and the successive comparison register circuit 722 to perform a successive comparison operation of the output voltage of the DA converter 723 and the input voltage Vin.

[0028] Here, in the semiconductor device 8, an error in the input voltage Vin occurs due to the dielectric relaxation phenomenon in each of the capacitance elements Cs and Cdac. Therefore, in the semiconductor device 8, the comparator 721 can cancel these error components and make a comparison. In other words, the semiconductor device 8 can operate with high precision by suppressing the error in AD conversion caused by the dielectric relaxation phenomenon.

[0029] 26 is based on a single-ended input, charge redistribution type successive approximation AD converter, so it was possible to apply a dielectric relaxation countermeasure circuit to the inverting input terminal of comparator 721. On the other hand, a differential input, charge redistribution type successive approximation AD converter and other existing circuits to which negative feedback is applied have a problem in that a dielectric relaxation countermeasure circuit cannot be applied to a location corresponding to the inverting input terminal of comparator 721. Therefore, a semiconductor device 1 capable of satisfying such requirements has been found.

[0030] <Embodiment 1> 1 is a circuit diagram showing a configuration example of a semiconductor device 1 according to embodiment 1. The semiconductor device 1 is a so-called charge redistribution type successive approximation AD converter, which converts an analog input voltage Vin into a digital output signal ADOUT using a binary search algorithm and outputs the converted signal.

[0031] Specifically, the semiconductor device 1 includes an inversion signal generating circuit 11, a negative feedback circuit 12, capacitance elements Cs and Cdac, and switches SW1 to SW3. The inversion signal generating circuit 11 includes a sample and hold circuit (S&H circuit) 111 and an inversion circuit 112. The negative feedback circuit 12 includes a comparator 121, a successive approximation register circuit 122, and a DA converter 123. For example, the switch SW1 configures a first switch circuit.

[0032] The capacitance element Cs is provided between the non-inverting input terminal of the comparator 121 and a node Ns. The switch SW1 is provided between an input terminal (hereinafter referred to as an input terminal Vin) to which an input voltage Vin is supplied from outside the semiconductor device 1, and a node Ns (one end of the capacitance element Cs). The switch SW3 is provided between the non-inverting input terminal (the other end of the capacitance element Cs) of the comparator 121 and a reference voltage terminal (hereinafter referred to as a reference voltage terminal Vss) to which a reference voltage Vss is supplied. The reference voltage Vss is supplied to the inverting input terminal of the comparator 121.

[0033] The successive approximation register circuit 122 outputs a digital signal according to the comparison result of the comparator 121, and outputs an output signal ADOUT having a determined digital value. The DA converter 123 converts the digital signal output from the successive approximation register circuit 122 into an analog voltage and outputs it. The switch SW2 is provided between the output of the DA converter 123 and a node Ns.

[0034] The capacitance element Cdac has the same capacitance value as the capacitance element Cs, and is provided between the non-inverting input terminal of the comparator 121 and the node Ndac. The inverted signal generating circuit 11 is provided between the input terminal Vin and the node Ndac (one end of the capacitance element Cdac). The sample & hold circuit 111 has a switch SWsh and a capacitance element Csh, and samples and holds the input voltage Vin. The inversion circuit 112 inverts the output voltage of the sample & hold circuit 111 and outputs it. Here, in the inversion of the inversion circuit 112, if the input of the inversion circuit 112 is x, the output of the inversion circuit 112 is y, and the common potential inverted by the inversion circuit 112 is Vcm1, then the relationship y=-(x-Vcm1)+Vcm1 holds. Hereinafter, the inversion of the voltage by each inversion circuit means the relationship of the above formula. In this embodiment, a case where the gain of the inversion circuit 112 is -1 will be described as an example. However, if the capacitance value of the capacitive element Cdac is Cdac and the capacitance value of the capacitive element Cs is Cs, then as long as the capacitive element Cdac is configured to exhibit a capacitance value such that Cdac=Cs / k holds, the gain of the inversion circuit 112 may be -k.

[0035] 2 is a timing chart showing the operation of the semiconductor device 1. Note that each switch is turned off by a low-level control signal and turned on by a high-level control signal. The operation modes of the semiconductor device 1 include at least a sampling mode and a hold mode.

[0036] First, in the sampling mode, the switches SW1 and SWsh indicate an ON state, the switch SW2 indicates an OFF state, and the switch SW3 indicates an ON state. As a result, sampling of the input voltage Vin is performed. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, a charge according to the input voltage Vin is accumulated in the capacitance element Csh of the sample & hold circuit 111. As a result, the output voltage of the sample & hold circuit 111 ideally indicates the input voltage Vin. Also, the inversion circuit 112 inverts the output voltage of the sample & hold circuit 111 (ideally the input voltage Vin) and outputs it. As a result, the voltage Vdac of the node Ndac ideally indicates a voltage obtained by inverting the input voltage Vin.

[0037] Then, in the hold mode, the switches SW1 and SWsh are switched from on to off, the switch SW2 is switched from off to on, and the switch SW3 is switched from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs, and the inverted voltage of the sampled input voltage Vin is held in the capacitance element Cdac. Strictly speaking, a sequence in which the switch SWsh is switched from on to off, the switch SW1 is switched from on to off, and then the switch SW3 is switched from on to off is desirable. This is because it is possible to eliminate the influence of errors in the inversion signal generating circuit 11. However, this strict timing operation is not necessary when the influence of dielectric relaxation is taken into account.

[0038] At this time, the negative feedback circuit 12 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123 and the input voltage Vin.

[0039] Here, in the semiconductor device 1, an error occurs in the capacitance element Cs due to the dielectric relaxation phenomenon, and an error of the opposite polarity occurs in the capacitance element Cdac due to the dielectric relaxation phenomenon. Therefore, in the voltage Vm of the non-inverting input terminal of the comparator 121 to which the other end of the capacitance element Cs and the other end of the capacitance element Cdac are commonly connected, these error components are cancelled out. This allows the semiconductor device 1 to operate with high precision.

[0040] Fig. 3 is a diagram showing an equivalent circuit of capacitance elements Cs and Cdac each having a dielectric relaxation phenomenon Fig. 4 is a timing chart showing the operation of the equivalent circuit shown in Fig. 3.

[0041] As shown in FIG. 3, a series circuit consisting of a parasitic resistance Rd1 and a parasitic capacitance Cd1 is provided in parallel to the capacitance element Cs considering the dielectric relaxation phenomenon. The time constant of this series circuit tends to be larger than the desired sampling time. Also, a series circuit consisting of a parasitic resistance Rd1x and a parasitic capacitance Cd1x is provided in parallel to the capacitance element Cdac considering the dielectric relaxation phenomenon. The time constant of this series circuit tends to be larger than the desired sampling time. Here, for the sake of simplicity, it is represented by a pair of RC time constants that simulate the dielectric relaxation, but it is actually represented by a model with many time constants.

[0042] Therefore, in the semiconductor device 1, as shown in Fig. 4, there is a possibility that the operation mode will switch from the sampling mode to the hold mode in a state (dotted line) in which the input voltages Vs and Vdac have not reached the ideal levels (solid lines). However, the input voltage Vs contains an error of the input voltage Vin caused by the dielectric relaxation phenomenon, and the input voltage Vdac contains an error of the opposite polarity to the input voltage Vin caused by the dielectric relaxation phenomenon. Therefore, in the voltage Vm of the non-inverting input terminal of the comparator 121 to which the other end of the capacitance element Cs and the other end of the capacitance element Cdac are commonly connected, these error components are cancelled out. This allows the semiconductor device 1 to operate with high precision.

[0043] In this way, the semiconductor device 1 according to this embodiment samples the input voltage Vin and its inverted voltage, and holds them in the capacitive elements Cs and Cdac commonly connected to the non-inverting input terminal of the comparator 121. As a result, the semiconductor device 1 according to this embodiment can cancel the error caused by the dielectric relaxation phenomenon and the error of opposite polarity caused by the dielectric relaxation phenomenon, and can therefore accurately take in the input voltage Vin, convert it into a digital output signal ADOUT, and output it.

[0044] <First Modification of Semiconductor Device 1> 5 is a circuit diagram showing a semiconductor device 1a as a first modified example of the semiconductor device 1. Compared to the semiconductor device 1, the semiconductor device 1a includes switches SW1a to SW1d instead of the switch SW1. The switches SW1c and SW1d configure a first switch circuit, and the switches SW1a and SW1b configure a second switch circuit.

[0045] The switch SW1a is provided between the node Ndac and an inverter circuit INV1 that generates an inverted voltage (-Vcm) of the common voltage Vcm. The switch SW1b is provided between the output of the inverter circuit 112 and the node Ndac. The switch SW1c is provided between the node Ns and a voltage supply terminal (hereinafter referred to as voltage supply terminal Vcm) to which the common voltage Vcm is supplied. The switch SW1d is provided between the input terminal Vin and the node Ns. That is, the switch SW1d is provided at the location where the switch SW1 was provided.

[0046] 6 is a timing chart showing the operation of the semiconductor device 1a. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 1a include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0047] First, in the first sampling mode, the switches SW1a and SW1c are in the on state, the switch SW1b is in the off state, the switches SW1d and SWsh are in the off state, the switch SW2 is in the off state, and the switch SW3 is in the on state. As a result, charges according to the common voltage Vcm and the inverted voltage of the common voltage Vcm are stored in the node Ns (one end of the capacitance element Cs) and the node Ndac (one end of the capacitance element Cdac), respectively.

[0048] Then, in the second sampling mode, the switches SW1a and SW1c are switched from on to off, the switch SW1b is switched from off to on, and the switches SW1d and SWsh are switched from off to on. This causes sampling of the input voltage Vin. That is, a charge according to the input voltage Vin is accumulated at the node Ns (one end of the capacitance element Cs).

[0049] Furthermore, in the second sampling mode, charge corresponding to the input voltage Vin is accumulated in the capacitive element Csh of the sample & hold circuit 111. As a result, the output voltage of the sample & hold circuit 111 ideally indicates the input voltage Vin. Furthermore, the inverting circuit 112 inverts the output voltage of the sample & hold circuit 111 (ideally the input voltage Vin) and outputs it. Therefore, charge corresponding to the output voltage of the inversion signal generating circuit 11 is accumulated in the node Ndac (one end of the capacitive element Cdac).

[0050] Then, in the hold mode, the switches SW1d and SWsh are switched from on to off, the switch SW2 is switched from off to on, and the switch SW3 is switched from on to off, so that the sampled input voltage Vin is held in the capacitance element Cs, and the inverted voltage of the sampled input voltage Vin is held in the capacitance element Cdac.

[0051] At this time, the negative feedback circuit 12 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123 and the input voltage Vin.

[0052] Here, in the semiconductor device 1a, an error occurs in the capacitance element Cs due to the dielectric relaxation phenomenon, and an error of the opposite polarity occurs in the capacitance element Cdac due to the dielectric relaxation phenomenon. Therefore, in the voltage Vm of the non-inverting input terminal of the comparator 121 to which the other end of the capacitance element Cs and the other end of the capacitance element Cdac are commonly connected, these error components are cancelled. As a result, the semiconductor device 1 can operate with high accuracy.

[0053] In this way, the semiconductor device 1a can achieve the same effect as the semiconductor device 1. Furthermore, the semiconductor device 1a is not limited to the above-mentioned configuration, and when the input voltage Vin is not supplied in the first sampling mode, the semiconductor device 1a can achieve the same effect by waiting in a state in which the common voltage Vcm is applied to the capacitance element Cs and an inverted voltage of the common voltage Vcm is applied to the capacitance element Cdac.

[0054] The operation of the semiconductor device 1a is not limited to the example of the timing chart shown in Fig. 6. Fig. 7 is a timing chart showing another example of the operation of the semiconductor device 1a.

[0055] First, in the first sampling mode, the switches SW1a, SW1c, and SWsh are in the on state, the switch SW1b is in the off state, the switch SW1d is in the off state, the switch SW2 is in the off state, and the switch SW3 is in the on state. As a result, charges corresponding to the common voltage Vcm and the inverted voltage (-Vcm) of the common voltage Vcm are stored in the node Ns (one end of the capacitance element Cs) and the node Ndac (one end of the capacitance element Cdac), respectively. Also, charges corresponding to the input voltage Vin are stored in the capacitance element Csh of the sample & hold circuit 111.

[0056] Thereafter, in the second sampling mode, the switches SW1a, SW1c, and SWsh are switched from on to off, and the switches SW1b and SW1d are switched from off to on, causing a charge according to the input voltage Vin to be accumulated at the node Ns (one end of the capacitance element Cs).

[0057] In the second sampling mode, the inversion circuit 112 inverts and outputs the output voltage (ideally the input voltage Vin) of the sample & hold circuit 111 held in the capacitive element Csh. Therefore, a charge according to the output voltage of the inversion signal generation circuit 11 is accumulated in the node Ndac (one end of the capacitive element Cdac).

[0058] Then, in the hold mode, the switch SW1d switches from on to off, the switch SW2 switches from off to on, and the switch SW3 switches from on to off.

[0059] In this way, the semiconductor device 1a can achieve the same effect as the operation according to the timing chart shown in Fig. 6 even when operating according to the timing chart shown in Fig. 7. Furthermore, in the operation according to the timing chart shown in Fig. 7, the output of the inversion signal generating circuit 11 is a held fixed voltage in the second sampling mode, so that the inversion signal generating circuit 11 may be simplified. However, it is necessary to accept the disadvantage that the inversion signal generating circuit 11 cannot follow the input voltage Vin if it changes significantly during the second sampling mode.

[0060] <Embodiment 2> 8 is a circuit diagram showing a configuration example of a semiconductor device 2 according to a second embodiment. Compared to the semiconductor device 1, the semiconductor device 2 includes an inversion signal generation circuit 21 instead of the inversion signal generation circuit 11. The inversion signal generation circuit 21 includes an inversion circuit 211, a sub AD converter 212, a sub DA converter 213, and switches SW1e and SW1f. In this embodiment, a case where the gain of the inversion circuit 211 is −1 will be described as an example. However, if the capacitance element Cdac is configured to exhibit a capacitance value that satisfies Cdac=Cs / k, the gain of the inversion circuit 211 may be −k.

[0061] The inversion circuit 211 inverts the input voltage Vin and outputs a voltage Vinx. The AD converter 212 samples and holds the output voltage Vinx of the inversion circuit 211, and converts the held voltage Vinx into a digital signal and outputs it. The DA converter 213 converts the digital signal output from the AD converter 212 into an analog voltage (corresponding to the voltage Vinx) and outputs it. The switch SW1f is provided between the output of the DA converter 213 and a node Ndac. The switch SW1e is provided on a path between the output of the inversion circuit 211 and the node Ndac that is different from the path on which the AD converter 212, the DA converter 213, and the switch SW1f are provided. The switches SW1e and SW1f function as a selection circuit that selects and outputs either the output of the inversion circuit 211 or the output of the DA converter 213.

[0062] 9 is a timing chart showing the operation of the semiconductor device 2. Note that each switch is turned off by a low-level control signal and turned on by a high-level control signal. The operation modes of the semiconductor device 2 include at least a sampling mode and a hold mode.

[0063] First, in the sampling mode, the switch SW1 indicates an on state, the switch SW1e indicates an on state, the switch SW1f indicates an off state, the switch SW2 indicates an off state, and the switch SW3 indicates an on state. As a result, sampling of the input voltage Vin is performed. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, a charge according to the voltage Vinx obtained by inverting the input voltage Vin is accumulated in the node Ndac (one end of the capacitance element Cdac). As a result, the voltage Vdac of the node Ndac ideally indicates the voltage Vinx.

[0064] Then, in the hold mode, the switch SW1 switches from on to off, the switch SW1e switches from on to off, the switch SW1f switches from off to on, the switch SW2 switches from off to on, and the switch SW3 switches from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs, and the voltage Vinx obtained by inverting the sampled input voltage Vin is held in the capacitance element Cdac. Also, the AD converter 212 holds the sampled voltage Vinx.

[0065] At this time, the negative feedback circuit 12 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123 and the input voltage Vin.

[0066] Here, the AD converter 212 converts the held voltage Vinx into a digital signal and outputs it. Then, the DA converter 213 converts the digital signal output from the AD converter 212 into an analog voltage (corresponding to the voltage Vinx) and outputs it to the node Ndac. That is, the hold function of the sample & hold circuit 111 is realized by the AD converter 212 and the DA converter 213.

[0067] In this way, the semiconductor device 2 according to the present embodiment samples the input voltage Vin and its inverted voltage, and holds them in the capacitance elements Cs and Cdac commonly connected to the non-inverting input terminal of the comparator 121. As a result, the semiconductor device 2 according to the present embodiment can cancel an error in the input voltage Vin caused in the positive direction by the dielectric relaxation phenomenon and an error in the input voltage Vin caused in the negative direction by the dielectric relaxation phenomenon, and can therefore accurately take in the input voltage Vin, convert it into a digital output signal ADOUT, and output it.

[0068] Next, a specific configuration example of the semiconductor device 2 will be described with reference to Fig. 10. Fig. 10 is a circuit diagram showing a specific configuration example of the semiconductor device 2.

[0069] 10, the DA converter 123 includes capacitance elements Cu0 and Cu1 exhibiting a minimum capacitance value 2^0·C, n-1 (n is an integer equal to or greater than 2) capacitance elements Cu2 to Cun that are binary-weighted with respect to the capacitance value of the capacitance element Cu1, and switches Su0, Su1 to Sun provided corresponding to the capacitance elements Cu0, Cu1 to Cun, respectively. Here, the capacitance elements Cu0, Cu1 to Cun are not only used as part of the DA converter 123, but are also used as the capacitance element Cs. Moreover, the switches Su0, Su1 to Sun are not only used as part of the DA converter 123, but are also used as the switches SW1 and SW2.

[0070] The switch control circuit 23 controls the on / off of the switches Su0, Su1 to Sun to redistribute charges for the successive approximation operation as the DA converter 123, and forms the capacitance element Cs with the capacitance elements Cu0, Cu1 to Cun.

[0071] 10, the DA converter 213 includes capacitance elements Cd0 and Cd1 exhibiting the minimum capacitance value 2^0·C, n-1 (n is an integer of 2 or more) capacitance elements Cd2 to Cdn binary-weighted with respect to the capacitance value of the capacitance element Cd1, and switches Sd0, Sd1 to Sdn provided corresponding to the capacitance elements Cd0, Cd1 to Cdn, respectively. Here, the capacitance elements Cd0, Cd1 to Cdn are not only used as part of the DA converter 213, but are also used as the capacitance element Cdac. The switches Sd0, Sd1 to Sdn are not only used as part of the DA converter 213, but are also used as switches SW1e and SW1f.

[0072] The switch control circuit 24 controls the on / off of the switches Sd0, Sd1 to Sdn to redistribute charges for the successive approximation operation as the DA converter 213, and forms the capacitance element Cdac with the capacitance elements Cd0, Cd1 to Cdn.

[0073] Other configurations of the semiconductor device 2 shown in Fig. 10 are similar to those of the semiconductor device 2 shown in Fig. 8, and therefore description thereof will be omitted. The semiconductor device 2 shown in Fig. 10 can reduce the circuit scale.

[0074] <First Modification of Semiconductor Device 2> 11 is a circuit diagram showing a semiconductor device 2a as a first modified example of the semiconductor device 2. Compared to the semiconductor device 2, the semiconductor device 2a includes an inversion signal generation circuit 21a instead of the inversion signal generation circuit 21. The inversion signal generation circuit 21a includes inversion circuits 214 and 215 instead of the inversion circuit 211.

[0075] The inversion circuit 214 is provided on a path between the input terminal Vin and the node Ndac, where the switch SW1e is provided. The inversion circuit 215 is provided on a path between the input terminal Vin and the node Ndac, where the AD converter 212, the DA converter 213, and the switch SW1f are provided. Specifically, the inversion circuit 215 is provided between the output of the AD converter 212 and the input of the DA converter 213.

[0076] The rest of the configuration of the semiconductor device 2a is similar to that of the semiconductor device 2, and therefore the description thereof will be omitted. The semiconductor device 2a can achieve effects equivalent to those of the semiconductor device 2.

[0077] <Second Modification of Semiconductor Device 2> 12 is a circuit diagram showing a second modified example of the semiconductor device 2 as a semiconductor device 2b. Compared to the semiconductor device 2, the semiconductor device 2b includes an inversion signal generation circuit 21b instead of the inversion signal generation circuit 21, and includes switches SW1a, SW1b, SW1c, and SW1d instead of the switch SW1. The switches SW1c and SW1d configure a first switch circuit, and the switches SW1a and SW1b configure a second switch circuit. The inversion signal generation circuit 21b includes an inversion circuit 211, a sub AD converter 212, and a sub DA converter 213. In the inversion signal generation circuit 21b, there is one path between the input terminal Vin and the node Ndac.

[0078] In the inversion signal generating circuit 21b, an inversion circuit 211 inverts an input voltage Vin and outputs a voltage Vinx. An AD converter 212 converts the voltage Vinx into a digital signal and outputs it. A DA converter 213 converts the digital signal output from the AD converter 212 into an analog voltage (corresponding to the voltage Vinx) and outputs it.

[0079] The switch SW1a is provided between the node Ndac and an inverter circuit INV1 that generates an inverted voltage of the common voltage Vcm. The switch SW1b is provided between the output of the DA converter 213 and the node Ndac. The switch SW1c is provided between the node Ns and the voltage supply terminal Vcm. The switch SW1d is provided between the input terminal Vin and the node Ns. That is, the switch SW1d is provided in the location where the switch SW1 was provided.

[0080] 13 is a timing chart showing the operation of the semiconductor device 2b. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 2b include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0081] First, in the first sampling mode, the switches SW1a and SW1c are in the on state, the switch SW1b is in the off state, the switch SW1d is in the off state, the switch SW2 is in the off state, and the switch SW3 is in the on state. As a result, charges according to the common voltage Vcm and the inverted voltage of the common voltage Vcm are stored in the node Ns (one end of the capacitance element Cs) and the node Ndac (one end of the capacitance element Cdac), respectively.

[0082] Then, in the second sampling mode, the switches SW1a and SW1c are switched from on to off, the switch SW1b is switched from off to on, and the switch SW1d is switched from off to on. This causes sampling of the input voltage Vin. That is, a charge according to the input voltage Vin is accumulated at the node Ns (one end of the capacitance element Cs).

[0083] In the second sampling mode, the inversion circuit 211 inverts the input voltage Vin and outputs the voltage Vinx. The AD converter 212 converts the voltage Vinx into a digital signal and outputs it. The DA converter 213 converts the digital signal output from the AD converter 212 into an analog voltage (corresponding to the voltage Vinx) and outputs it. Therefore, a charge according to the output voltage of the inversion signal generation circuit 21b is accumulated in the node Ndac (one end of the capacitance element Cdac).

[0084] Then, in the hold mode, the switch SW1d switches from on to off, the switch SW2 switches from off to on, and the switch SW3 switches from on to off. As a result, the sampled input voltage Vin is held in the capacitance element Cs, and the inverted voltage of the sampled input voltage Vin is held in the capacitance element Cdac. The AD converter 212 also holds the sampled voltage Vinx.

[0085] At this time, the negative feedback circuit 12 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123 and the input voltage Vin.

[0086] Here, the AD converter 212 converts the held voltage Vinx into a digital signal and outputs it. Then, the DA converter 213 converts the digital signal output from the AD converter 212 into an analog voltage (corresponding to the voltage Vinx) and outputs it to the node Ndac. That is, the inversion signal generating circuit 21b outputs an inverted voltage of the voltage generated at the node Ns to the node Ndac. This cancels out errors generated in the capacitance elements Cs and Cdac due to the dielectric relaxation phenomenon.

[0087] The semiconductor device 2b can achieve the same effect as the semiconductor device 2. Furthermore, the semiconductor device 2b is not limited to the above-mentioned configuration, and when the input voltage Vin is not supplied in the first sampling mode, the semiconductor device 2b can achieve the same effect by waiting in a state in which the common voltage Vcm is applied to the capacitance element Cs and an inverted voltage of the common voltage Vcm is applied to the capacitance element Cdac.

[0088] Next, a specific configuration example of the semiconductor device 2b will be described with reference to Fig. 14. Fig. 14 is a circuit diagram showing a specific configuration example of the semiconductor device 2b.

[0089] 14, the DA converter 123 includes capacitance elements Cu0 and Cu1 exhibiting a minimum capacitance value 2^0·C, n-1 (n is an integer equal to or greater than 2) capacitance elements Cu2 to Cun that are binary-weighted with respect to the capacitance value of the capacitance element Cu1, and switches Su0, Su1 to Sun provided corresponding to the capacitance elements Cu0, Cu1 to Cun, respectively. Here, the capacitance elements Cu0, Cu1 to Cun are not only used as part of the DA converter 123, but are also used as the capacitance element Cs. Moreover, the switches Su0, Su1 to Sun are not only used as part of the DA converter 123, but are also used as switches SW1c, SW1d, and SW2.

[0090] The switch control circuit 25 controls the on / off of the switches Su0, Su1 to Sun to redistribute charges for the successive approximation operation as the DA converter 123, and forms the capacitance element Cs with the capacitance elements Cu0, Cu1 to Cun.

[0091] 14, the DA converter 213 includes capacitance elements Cd0 and Cd1 exhibiting the minimum capacitance value 2^0·C, n-1 (n is an integer of 2 or more) capacitance elements Cd2 to Cdn binary-weighted with respect to the capacitance value of the capacitance element Cd1, and switches Sd0, Sd1 to Sdn provided corresponding to the capacitance elements Cd0, Cd1 to Cdn, respectively. Here, the capacitance elements Cd0, Cd1 to Cdn are not only used as part of the DA converter 213, but are also used as the capacitance element Cdac. The switches Sd0, Sd1 to Sdn are not only used as part of the DA converter 213, but are also used as switches SW1a and SW1b.

[0092] The switch control circuit 26 controls the on / off of the switches Sd0, Sd1 to Sdn to redistribute charges for the successive approximation operation as the DA converter 213, and forms the capacitance element Cdac with the capacitance elements Cd0, Cd1 to Cdn.

[0093] Other configurations of the semiconductor device 2b shown in Fig. 14 are similar to those of the semiconductor device 2b shown in Fig. 12, and therefore the description thereof will be omitted. The semiconductor device 2b shown in Fig. 14 can reduce the circuit scale.

[0094] <Embodiment 3> 15 is a circuit diagram showing a configuration example of a semiconductor device 3 according to embodiment 3. While the semiconductor devices 1 and 2 are single-ended successive approximation type AD converters, the semiconductor device 3 is a successive approximation type AD converter that performs AD conversion on a differential input signal.

[0095] Specifically, the semiconductor device 3 includes inversion signal generating circuits 31p and 31n, a negative feedback circuit 32, capacitive elements Csp and Csn, capacitive elements Cdacp and Cdacn, switches SW1p and SW1n, switches SW2p and SW2n, and a switch SW3. The negative feedback circuit 32 includes a comparator 121, a successive approximation register circuit 122, a DA converter 123p, and a DA converter 123n. For example, the switch SW1p constitutes a first switch circuit, and the switch SW1n constitutes a third switch circuit.

[0096] First, in the semiconductor device 3, an inversion signal generating circuit 31p, a comparator 121, a successive approximation register circuit 122, a DA converter 123p, capacitance elements Csp, Cdacp, and switches SW1p, SW2p, and SW3 are mainly used as a circuit for processing a positive-side input signal (input voltage) Vinp, which is one of a pair of differential input signals. Note that the inversion signal generating circuit 31p, the comparator 121, the successive approximation register circuit 122, the DA converter 123p, capacitance elements Csp, Cdacp, and switches SW1p, SW2p, and SW3 correspond to the inversion signal generating circuit 21, the comparator 121, the successive approximation register circuit 122, the DA converter 123, capacitance elements Cs, Cdac, and switches SW1, SW2, and SW3 in the semiconductor device 2 shown in FIG. 8, respectively.

[0097] In the semiconductor device 3, an inversion signal generating circuit 31n, a comparator 121, a successive approximation register circuit 122, a DA converter 123n, capacitance elements Csn, Cdacn, and switches SW1n, SW2n, and SW3 are mainly used as a circuit for processing a negative-side input signal (input voltage) Vinn, which is the other of the pair of differential input signals. Note that the inversion signal generating circuit 31n, the comparator 121, the successive approximation register circuit 122, the DA converter 123n, the capacitance elements Csn, Cdacn, and the switches SW1n, SW2n, and SW3 correspond to the inversion signal generating circuit 21, the comparator 121, the successive approximation register circuit 122, the DA converter 123, the capacitance elements Cs, Cdac, and the switches SW1, SW2, and SW3 in the semiconductor device 2 shown in FIG. 8, respectively.

[0098] The capacitance element Csp is provided between a non-inverting input terminal of the comparator 121 and a node Nsp. The switch SW1p is provided between an input terminal (hereinafter referred to as an input terminal Vinp) to which an input voltage Vinp is supplied from outside the semiconductor device 3 and a node Nsp (one end of the capacitance element Csp). The capacitance element Csn is provided between an inverting input terminal of the comparator 121 and a node Nsn. The switch SW1n is provided between an input terminal (hereinafter referred to as an input terminal Vinn) to which an input voltage Vinn is supplied from outside the semiconductor device 3 and a node Nsn (one end of the capacitance element Csn). The switch SW3 is provided between the non-inverting input terminal and the inverting input terminal of the comparator 121.

[0099] The successive approximation register circuit 122 outputs a digital signal (a control signal for controlling each switch of the DA converters 123p and 123n) according to the comparison result of the comparator 121, and also outputs an output signal ADOUT of a determined digital value. The DA converter 123p converts the digital signal output from the successive approximation register circuit 122 into an analog voltage and outputs it. The switch SW2p is provided between the output of the DA converter 123p and a node Nsp. The DA converter 123n converts the digital signal output from the successive approximation register circuit 122 into an analog voltage and outputs it. The switch SW2n is provided between the output of the DA converter 123n and a node Nsn.

[0100] The capacitive element Cdacp is provided between the non-inverting input terminal of the comparator 121 and the node Ndacp. The inverted signal generating circuit 31p is provided between the input terminal Vinn and the node Ndacp.

[0101] The inversion signal generation circuit 31p includes a sub AD converter 212p, a sub DA converter 213p, a switch SW1ep, and a switch SW1fp. The AD converter 212p, the DA converter 213p, the switch SW1ep, and the switch SW1fp correspond to the AD converter 212, the DA converter 213, the switch SW1e, and the switch SW1f provided in the inversion signal generation circuit 21 shown in Fig. 8, respectively. Here, the inversion signal generation circuit 31p receives the negative input voltage Vinn (i.e., the voltage obtained by inverting the input voltage Vinp) of the input voltages Vinp and Vinn constituting a pair of differential signals, and therefore does not require a circuit corresponding to the inversion circuit 211.

[0102] The capacitive element Cdacn is provided between the inverting input terminal of the comparator 121 and the node Ndacn. The inverted signal generating circuit 31n is provided between the input terminal Vinp and the node Ndacn.

[0103] The inversion signal generating circuit 31n includes a sub AD converter 212n, a sub DA converter 213n, a switch SW1en, and a switch SW1fn. The AD converter 212n, the DA converter 213n, the switch SW1en, and the switch SW1fn correspond to the AD converter 212, the DA converter 213, the switch SW1e, and the switch SW1f provided in the inversion signal generating circuit 21 shown in Fig. 8, respectively. Here, the inversion signal generating circuit 31n does not need a circuit corresponding to the inversion circuit 211 because the positive input voltage Vinp (i.e., the voltage obtained by inverting the input voltage Vinn) of the input voltages Vinp and Vinn constituting a pair of differential signals is input.

[0104] 16 is a timing chart showing the operation of the semiconductor device 3. Note that each switch is turned off by a low-level control signal and turned on by a high-level control signal. The operation modes of the semiconductor device 3 include at least a sampling mode and a hold mode.

[0105] First, in the sampling mode, the switches SW1p and SW1n indicate an on state, the switches SW1ep and SW1en indicate an on state, the switches SW1fp and SW1fn indicate an off state, the switches SW2p and SW2n indicate an off state, and the switch SW3 indicates an on state. As a result, sampling of the input voltages Vinp and Vinn is performed. That is, a charge according to the input voltage Vinp is accumulated in the node Nsp (one end of the capacitance element Csp), and a charge according to the input voltage Vinn is accumulated in the node Nsn (one end of the capacitance element Csn). As a result, the voltage Vsp of the node Nsp ideally indicates the input voltage Vinp, and the voltage Vsn of the node Nsn ideally indicates the input voltage Vinn. In addition, a charge according to the voltage Vinn obtained by inverting the input voltage Vinp is accumulated in the node Ndacp (one end of the capacitance element Cdacp), and a charge according to the voltage Vinp obtained by inverting the input voltage Vinn is accumulated in the node Ndacn (one end of the capacitance element Cdacn). As a result, the voltage Vdacp of the node Ndacp ideally indicates the voltage Vinn, and the voltage Vdacn of the node Ndacn ideally indicates the voltage Vinp.

[0106] Then, in the hold mode, the switches SW1p and SW1n are switched from on to off, the switches SW1ep and SW1en are switched from on to off, the switches SW1fp and SW1fn are switched from off to on, the switches SW2p and SW2n are switched from off to on, and the switch SW3 is switched from on to off. As a result, the sampled input voltages Vinp and Vinn are held in the capacitance elements Csp and Csn, respectively, and the sampled input voltages Vinn and Vinp are held in the capacitance elements Cdacp and Cdacn, respectively. The AD converter 212p holds the sampled voltage Vinn. The AD converter 212n holds the sampled voltage Vinp.

[0107] At this time, the negative feedback circuit 32 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123p and the input voltage Vinp.

[0108] At this time, the negative feedback circuit 32 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123n and the input voltage Vinn.

[0109] Here, the AD converter 212p converts the held voltage Vinn into a digital signal and outputs it.Then, the DA converter 213p converts the digital signal output from the AD converter 212p into an analog voltage (corresponding to the voltage Vinn) and outputs it to the node Ndacp.In other words, the hold function of the sample & hold circuit 111 is realized by the AD converter 212p and the DA converter 213p.

[0110] Furthermore, the AD converter 212n converts the held voltage Vinp into a digital signal and outputs it. The DA converter 213n then converts the digital signal output from the AD converter 212n into an analog voltage (corresponding to the voltage Vinp) and outputs it to the node Ndacn. That is, the hold function of the sample & hold circuit 111 is realized by the AD converter 212n and the DA converter 213n.

[0111] In this way, the semiconductor device 3 according to this embodiment can achieve effects equivalent to those of the semiconductor devices 1 and 2. It is difficult to apply the circuit for dielectric relaxation measures applied to the semiconductor device 8 shown in Fig. 26 to an AD converter that performs AD conversion of a differential input signal. In contrast, the semiconductor device 3 according to this embodiment realizes application of the circuit for dielectric relaxation measures to an AD converter that performs AD conversion of a differential input signal.

[0112] Next, a specific configuration example of the semiconductor device 3 will be described with reference to Fig. 17. Fig. 17 is a circuit diagram showing a specific configuration example of the semiconductor device 3.

[0113] First, in the example of Fig. 17, DA converters 123p and 213p have the same circuit configuration as the DA converters 123 and 213 shown in Fig. 10. The multiple capacitive elements provided in the DA converter 123p are also used as the capacitive element Csp, and the multiple switches provided in the DA converter 123p are also used as the switches SW1p and SW2p. The multiple capacitive elements provided in the DA converter 213p are also used as the capacitive element Cdacp, and the multiple switches provided in the DA converter 213p are also used as the switches SW1ep and SW1fp.

[0114] In the example of Fig. 17, the DA converters 123n and 213n have the same circuit configuration as the DA converters 123 and 213 shown in Fig. 10. The multiple capacitive elements provided in the DA converter 123n are also used as the capacitive element Csn, and the multiple switches provided in the DA converter 123n are also used as the switches SW1n and SW2n. The multiple capacitive elements provided in the DA converter 213n are also used as the capacitive element Cdacn, and the multiple switches provided in the DA converter 213n are also used as the switches SW1en and SW1fn.

[0115] Furthermore, in the example of Fig. 17, AD converter 312 is used as AD converters 212p and 212n. In other words, in the example of Fig. 17, AD converter 312 plays the role of each of AD converters 212p and 212n. Other configurations of semiconductor device 3 shown in Fig. 17 are similar to those of semiconductor device 3 shown in Fig. 15, and therefore description thereof will be omitted. Semiconductor device 3 shown in Fig. 17 can reduce the circuit scale.

[0116] <First Modification of Semiconductor Device 3> 18 is a circuit diagram showing a first modified example of the semiconductor device 3 as a semiconductor device 3a. Compared to the semiconductor device 3, the semiconductor device 3a includes inverted signal generating circuits 31bp and 31bn instead of the inverted signal generating circuits 31p and 31n, switches SW1ap, SW1bp, SW1cp and SW1dp instead of the switch SW1p, and switches SW1an, SW1bn, SW1cn and SW1dn instead of the switch SW1n. The switches SW1cp and SW1dp form a first switch circuit, and the switches SW1ap and SW1bp form a second switch circuit. The switches SW1cn and SW1dn form a third switch circuit, and the switches SW1an and SW1bn form a fourth switch circuit.

[0117] The inversion signal generation circuit 31bp includes a sub AD converter 212p and a sub DA converter 213p. The AD converter 212p and the DA converter 213p correspond to the AD converter 212 and the DA converter 213 provided in the inversion signal generation circuit 21b shown in Fig. 12, respectively. Here, the inversion signal generation circuit 31bp does not need a circuit corresponding to the inversion circuit 211 because the negative input voltage Vinn (i.e., the voltage obtained by inverting the input voltage Vinp) of the input voltages Vinp and Vinn constituting a pair of differential input signals is input to the inversion signal generation circuit 31bp.

[0118] The inversion signal generation circuit 31bn includes a sub AD converter 212n and a sub DA converter 213n. The AD converter 212n and the DA converter 213n correspond to the AD converter 212 and the DA converter 213, respectively, provided in the inversion signal generation circuit 21b shown in Fig. 12. Here, the inversion signal generation circuit 31bn does not need a circuit corresponding to the inversion circuit 211 because the positive input voltage Vinp (i.e., the voltage obtained by inverting the input voltage Vinn) of the input voltages Vinp and Vinn constituting a pair of differential input signals is input to the inversion signal generation circuit 31bn.

[0119] The switch SW1ap is provided between the node Ndacp and an inversion circuit INV1p that generates an inverted voltage of the common voltage Vcm. The switch SW1bp is provided between the output of the inversion signal generation circuit 31bp and the node Ndacp. The switch SW1cp is provided between the node Nsp and the voltage supply terminal Vcm. The switch SW1dp is provided between the input terminal Vinp and the node Nsp. That is, the switch SW1dp is provided in the place where the switch SW1p was provided.

[0120] The switch SW1an is provided between the node Ndacn and an inversion circuit INV1n that generates an inverted voltage of the common voltage Vcm. The switch SW1bn is provided between the output of the inversion signal generation circuit 31bn and the node Ndacn. The switch SW1cn is provided between the node Nsn and the voltage supply terminal Vcm. The switch SW1dn is provided between the input terminal Vinn and the node Nsn. That is, the switch SW1dn is provided in the place where the switch SW1n was provided.

[0121] 19 is a timing chart showing the operation of the semiconductor device 3a. Each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 3a include at least a sampling mode and a hold mode. The sampling mode is composed of a first sampling mode and a second sampling mode.

[0122] First, in the first sampling mode, the switches SW1ap, SW1an, SW1cp, and SW1cn are in the on state, the switches SW1bp and SW1bn are in the off state, the switches SW1dp and SW1dn are in the off state, the switches SW2p and SW2n are in the off state, and the switch SW3 is in the on state. As a result, charges corresponding to the common voltage Vcm and the inverted voltage of the common voltage Vcm are stored in the node Nsp (one end of the capacitance element Csp) and the node Ndacp (one end of the capacitance element Cdacp), respectively. In addition, charges corresponding to the common voltage Vcm and the inverted voltage of the common voltage Vcm are stored in the node Nsn (one end of the capacitance element Csn) and the node Ndacn (one end of the capacitance element Cdacn), respectively.

[0123] After that, in the second sampling mode, the switches SW1ap, SW1an, SW1cp, and SW1cn are switched from on to off, the switches SW1bp and SW1bn are switched from off to on, and the switches SW1dp and SW1dn are switched from off to on. This causes sampling of the input voltages Vinp and Vinn. That is, a charge according to the input voltage Vinp is accumulated in the node Nsp (one end of the capacitance element Csp). Also, a charge according to the input voltage Vinn is accumulated in the node Nsn (one end of the capacitance element Csn).

[0124] In the second sampling mode, the AD converter 212p converts the input voltage Vinn obtained by inverting the input voltage Vinp into a digital signal and outputs it. The DA converter 213p converts the digital signal output from the AD converter 212p into an analog voltage (corresponding to the voltage Vinn) and outputs it. Therefore, a charge according to the output voltage of the inversion signal generating circuit 31bp is accumulated in the node Ndacp (one end of the capacitive element Cdacp). The AD converter 212n converts the input voltage Vinp obtained by inverting the input voltage Vinn into a digital signal and outputs it. The DA converter 213n converts the digital signal output from the AD converter 212n into an analog voltage (corresponding to the voltage Vinp) and outputs it. Therefore, a charge according to the output voltage of the inversion signal generating circuit 31bn is accumulated in the node Ndacn (one end of the capacitive element Cdacn).

[0125] Thereafter, in the hold mode, the switches SW1dp and SW1dn are switched from on to off, the switches SW2p and SW2n are switched from off to on, and the switch SW is switched from on to off. As a result, the sampled input voltage Vinp is held in the capacitive element Csp, and the voltage Vinn obtained by inverting the sampled input voltage Vinp is held in the capacitive element Cdacp. Also, the sampled input voltage Vinn is held in the capacitive element Csn, and the voltage Vinp obtained by inverting the sampled input voltage Vinn is held in the capacitive element Cdacn. Also, the AD converter 212p holds the sampled voltage Vinn. The AD converter 212n holds the sampled voltage Vinp.

[0126] At this time, the negative feedback circuit 32 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123p and the input voltage Vinp.

[0127] At this time, the negative feedback circuit 32 uses the comparator 121 and the successive approximation register circuit 122 to perform a successive approximation operation between the output voltage of the DA converter 123n and the input voltage Vinn.

[0128] Here, the AD converter 212p converts the held voltage Vinn into a digital signal and outputs it. Then, the DA converter 213p converts the digital signal output from the AD converter 212p into an analog voltage (corresponding to the voltage Vinn) and outputs it to the node Ndacp. That is, the inversion signal generating circuit 31bp outputs an inversion voltage of the voltage generated at the node Nsp to the node Ndacp. This cancels out errors generated in the capacitance elements Csp and Cdacp due to the dielectric relaxation phenomenon.

[0129] Moreover, the AD converter 212n converts the held voltage Vinp into a digital signal and outputs it. Then, the DA converter 213n converts the digital signal output from the AD converter 212n into an analog voltage (corresponding to the voltage Vinp) and outputs it to the node Ndacn. That is, the inversion signal generating circuit 31bn outputs an inverted voltage of the voltage generated at the node Nsn to the node Ndacn. This cancels out errors generated in the capacitance elements Csn and Cdacn due to the dielectric relaxation phenomenon.

[0130] The semiconductor device 3a can achieve the same effect as the semiconductor device 3. Furthermore, the semiconductor device 3a is not limited to the above-mentioned configuration, and when the input voltages Vinp, Vinn are not supplied in the first sampling mode, the semiconductor device 3a can achieve the same effect by waiting in a state in which the common voltage Vcm is applied to the capacitance elements Csp, Csn and an inverted voltage of the common voltage Vcm is applied to the capacitance elements Cdacp, Cdacn.

[0131] Next, a specific configuration example of the semiconductor device 3a will be described with reference to Fig. 20. Fig. 20 is a circuit diagram showing a specific configuration example of the semiconductor device 3a.

[0132] First, in the example of Fig. 20, DA converters 123p and 213p have the same circuit configuration as the DA converters 123 and 213 shown in Fig. 14. The multiple capacitive elements provided in the DA converter 123p are also used as the capacitive element Csp, and the multiple switches provided in the DA converter 123p are also used as the switches SW1cp, SW1dp, and SW2p. The multiple capacitive elements provided in the DA converter 213p are also used as the capacitive element Cdacp, and the multiple switches provided in the DA converter 213p are also used as the switches SW1ap and SW1bp.

[0133] In the example of Fig. 20, the DA converters 123n and 213n have the same circuit configuration as the DA converters 123 and 213 shown in Fig. 14. The multiple capacitive elements provided in the DA converter 123n are also used as the capacitive element Csn, and the multiple switches provided in the DA converter 123n are also used as the switches SW1cn, SW1dn, and SW2n. The multiple capacitive elements provided in the DA converter 213n are also used as the capacitive element Cdacn, and the multiple switches provided in the DA converter 213n are also used as the switches SW1an and SW1bn.

[0134] Furthermore, in the example of Fig. 20, AD converter 312 is used as AD converters 212p and 212n. In other words, in the example of Fig. 20, AD converter 312 plays the role of each of AD converters 212p and 212n. Other configurations of semiconductor device 3a shown in Fig. 20 are similar to those of semiconductor device 3a shown in Fig. 18, and therefore description thereof will be omitted. Semiconductor device 3a shown in Fig. 20 can reduce the circuit scale.

[0135] <Fourth embodiment> In the first to third embodiments, the case where the dielectric relaxation countermeasure is applied to a successive approximation type AD converter has been described, but the present invention is not limited thereto. In the present embodiment, the case where the dielectric relaxation countermeasure is applied to a semiconductor device including a negative feedback circuit having an operational amplifier will be described.

[0136] 21 is a circuit diagram showing a configuration example of a semiconductor device 4 according to embodiment 4. The semiconductor device 4 is a sample and hold circuit equipped with a negative feedback circuit having an operational amplifier.

[0137] Specifically, the semiconductor device 4 includes an inversion signal generating circuit 11, a negative feedback circuit 42, a capacitive element Cs, a capacitive element Cdac, and switches SW1 to SW3. The inversion signal generating circuit 11 includes a sample & hold circuit 111 and an inversion circuit 112. The negative feedback circuit 42 includes an operational amplifier 421.

[0138] The capacitance element Cs is provided between the inverting input terminal of the operational amplifier 421 and a node Ns. The switch SW1 is provided between the input terminal Vin and the node Ns (one end of the capacitance element Cs). The switch SW3 is provided between the inverting input terminal of the operational amplifier 421 (the other end of the capacitance element Cs) and a reference voltage terminal Vss. The reference voltage Vss is supplied to the non-inverting input terminal of the operational amplifier 421.

[0139] The operational amplifier 421 amplifies the potential difference between the voltage Vm of the inverting input terminal and the voltage Vss of the non-inverting input terminal, and outputs it as an output signal ADOUT. The output voltage of the operational amplifier 421 is fed back and applied to a node Ns via a switch SW2.

[0140] The capacitance element Cdac is provided between the inverting input terminal of the operational amplifier 421 and the node Ndac. The inversion signal generation circuit 11 is provided between the input terminal Vin and the node Ndac (one end of the capacitance element Cdac). In the inversion signal generation circuit 11, the sample & hold circuit 111 has a switch SWsh and a capacitance element Csh, and samples and holds the input voltage Vin. The inversion circuit 112 inverts the output voltage of the sample & hold circuit 111 and outputs it. In this embodiment, a case where the gain of the inversion circuit 112 is −1 will be described as an example. However, if the capacitance element Cdac is configured to exhibit a capacitance value such that Cdac=Cs / k holds, the gain of the inversion circuit 211 may be −k.

[0141] 22 is a timing chart showing the operation of the semiconductor device 4. Note that each switch is turned off by a low level control signal and turned on by a high level control signal. The operation modes of the semiconductor device 4 include at least a sampling mode and a hold mode.

[0142] First, in the sampling mode, the switches SW1 and SWsh indicate an ON state, the switch SW2 indicates an OFF state, and the switch SW3 indicates an ON state. As a result, sampling of the input voltage Vin is performed. That is, a charge according to the input voltage Vin is accumulated in the node Ns (one end of the capacitance element Cs). As a result, the voltage Vs of the node Ns ideally indicates the input voltage Vin. Also, a charge according to the input voltage Vin is accumulated in the capacitance element Csh of the sample & hold circuit 111. As a result, the output voltage of the sample & hold circuit 111 ideally indicates the input voltage Vin. Also, the inversion circuit 112 inverts the output voltage of the sample & hold circuit 111 (ideally the input voltage Vin) and outputs it. As a result, the voltage Vdac of the node Ndac ideally indicates a voltage obtained by inverting the input voltage Vin.

[0143] Then, in the hold mode, the switches SW1 and SWsh are switched from on to off, the switch SW2 is switched from off to on, and the switch SW3 is switched from on to off, so that the sampled input voltage Vin is held in the capacitance element Cs, and the inverted voltage of the sampled input voltage Vin is held in the capacitance element Cdac.

[0144] Here, in the semiconductor device 4, an error occurs in the capacitance element Cs due to the dielectric relaxation phenomenon, and an error of the opposite polarity occurs in the capacitance element Cdac due to the dielectric relaxation phenomenon. Therefore, in the voltage Vm of the inverting input terminal of the operational amplifier 421 to which the other end of the capacitance element Cs and the other end of the capacitance element Cdac are commonly connected, these error components are cancelled out. This allows the semiconductor device 4 to operate with high precision.

[0145] In this way, the semiconductor device 4 according to this embodiment samples the input voltage Vin and its inverted voltage, and holds them in the capacitance elements Cs and Cdac commonly connected to the inverting input terminal of the operational amplifier 421. As a result, the semiconductor device 4 according to this embodiment can cancel the error in the input voltage Vin generated in the positive direction due to the dielectric relaxation phenomenon and the error in the input voltage Vin generated in the negative direction due to the dielectric relaxation phenomenon, and can therefore accurately capture the input voltage Vin and accurately output the output signal ADOUT.

[0146] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention.

[0147] Furthermore, in the present disclosure, a part or all of the processing of the semiconductor devices 1 to 4 can be realized by causing a CPU (Central Processing Unit) to execute a computer program.

[0148] The above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal. [Explanation of symbols]

[0149] 1,1a Semiconductor device 2, 2a, 2b Semiconductor device 3,3a Semiconductor device 4. Semiconductor Devices 11 Inverted signal generation circuit 12 Negative feedback circuit 21, 21a, 21b Inverted signal generating circuit 23 Switch control circuit 24 Switch control circuit 25 Switch control circuit 26 Switch control circuit 31p, 31n inversion signal generation circuit 31bp, 31bpn inversion signal generation circuit 32 Negative feedback circuit 42 Negative feedback circuit 111 Sample and hold circuit 112,112a Inverting circuit 121 Comparator 122 Successive approximation register circuit 123 DA Converter 211 Inverting circuit 212 A / D converter 213 DA Converter 214 Inverting Circuit 215 Inverting Circuit 421 Operational Amplifier Cdac Capacitor Cs capacitive element Csh Capacitive element SW1 Switch SW1a, SW1b, SW1c, SW1d switches SW1e, SW1f Switch SW2 switch SW3 Switch SWsh Switch

Claims

1. A first capacitive element; a first switch circuit that applies a first input voltage to one end of the first capacitance element in a sampling mode, and holds the first input voltage in the first capacitance element in a hold mode after the sampling mode; a first inversion signal generating circuit that generates a voltage obtained by inverting the first input voltage in a sampling mode and holds the generated voltage in a hold mode; a second capacitive element to one end of which the voltage generated by the first inversion signal generating circuit is applied; a negative feedback circuit that, in a hold mode, generates an output signal according to a voltage of a first node to which the other end of the first capacitive element and the other end of the second capacitive element are commonly connected, and applies a first feedback signal corresponding to the output signal to one end of the first capacitive element; A semiconductor device comprising:

2. The first inverted signal generating circuit includes: an inversion circuit that generates a voltage obtained by inverting the first input voltage in a sampling mode; a sample and hold circuit that holds the voltage generated by the inversion circuit in a hold mode; having The semiconductor device according to claim 1 .

3. the first inverted signal generating circuit generates a voltage obtained by inverting the first input voltage and having an amplitude according to the capacitance values ​​of the first capacitive element and the second capacitive element; The semiconductor device according to claim 1 .

4. The first inverted signal generating circuit includes: an inversion circuit that generates a voltage obtained by inverting the first input voltage in a sampling mode; a first sub-A / D converter that, in a hold mode, holds a voltage generated by the inversion circuit and converts the held voltage into a digital signal; a first sub-DA converter that converts a digital signal output from the first sub-AD converter into an analog voltage; a selection circuit that, in a sampling mode, selects the voltage generated by the inversion circuit and outputs it as the voltage generated by the first inversion signal generation circuit, and, in a hold mode, selects the analog voltage output from the first sub-DA converter and outputs it as the voltage generated by the first inversion signal generation circuit; Equipped with The semiconductor device according to claim 1 .

5. The first sub-DA converter includes: A plurality of first sub-capacitance elements; a plurality of first sub-switches provided corresponding to the plurality of first sub-capacitance elements, respectively; having The plurality of first sub-capacitance elements are also used as the second capacitance elements. The semiconductor device according to claim 4.

6. The first inverted signal generating circuit includes: a first inverter circuit that generates a voltage obtained by inverting the first input voltage in a sampling mode; a first sub-A / D converter that holds the first input voltage in a hold mode and converts the held first input voltage into a digital signal; a second inversion circuit that inverts the digital signal output from the first sub-AD converter and outputs the inverted signal; a first sub-DA converter that converts an output signal of the second inversion circuit into an analog voltage; a selection circuit that, in a sampling mode, selects the voltage generated by the first inversion circuit and outputs it as the voltage generated by the first inversion signal generation circuit, and, in a hold mode, selects the analog voltage output from the first sub-DA converter and outputs it as the voltage generated by the first inversion signal generation circuit; Equipped with The semiconductor device according to claim 1 .

7. The first sub-DA converter includes: A plurality of first sub-capacitance elements; a plurality of first sub-switches provided corresponding to the plurality of first sub-capacitance elements, respectively; having The plurality of first sub-capacitance elements are also used as the second capacitance elements. The semiconductor device according to claim 6.

8. a second switch circuit that applies a voltage obtained by inverting a common voltage applied to the first capacitance element to one end of the second capacitance element in the first sampling mode and that applies a voltage generated by the first inversion signal generation circuit to one end of the second capacitance element in the second sampling mode and the hold mode, the first switch circuit is configured to apply the common voltage to one end of the first capacitance element in a first sampling mode, and to apply the first input voltage to one end of the first capacitance element in a second sampling mode; The semiconductor device according to claim 1 .

9. The first inverted signal generating circuit includes: an inverter circuit that generates a voltage obtained by inverting the first input voltage; a first sub-A / D converter that, in a hold mode, holds a voltage generated by the inversion circuit and converts the held voltage into a digital signal; a first sub-DA converter that converts the digital signal output from the first sub-AD converter into an analog voltage and outputs the voltage generated by the first inverted signal generating circuit; Equipped with The semiconductor device according to claim 8.

10. The negative feedback circuit includes: a comparator having one input terminal supplied with the voltage at the first node and another input terminal supplied with a reference voltage; a successive approximation register circuit for generating a digital output signal according to a comparison result of the comparator; a DA converter that converts the output signal generated by the successive approximation register circuit into an analog voltage and outputs the analog voltage as the first feedback signal; Equipped with The semiconductor device according to claim 1 .

11. The DA converter comprises: A plurality of capacitive elements; a plurality of switches provided corresponding to the plurality of capacitance elements, having A plurality of capacitance elements provided in the DA converter are also used as the first capacitance elements. The semiconductor device according to claim 10.

12. The negative feedback circuit includes: an operational amplifier that generates an output signal according to a potential difference between a voltage of the first node and a reference voltage, and applies the first feedback signal corresponding to the output signal to one end of the first capacitance element; The semiconductor device according to claim 1 .

13. A third capacitive element; a third switch circuit that applies a second input voltage, which constitutes a differential input signal together with the first input voltage, to one end of the third capacitance element in a sampling mode, and holds the second input voltage in the third capacitance element in a hold mode; a second inversion signal generating circuit that generates a voltage obtained by inverting the second input voltage in a sampling mode and holds the generated voltage in a hold mode; a fourth capacitive element having one end to which the voltage generated by the second inversion signal generating circuit is applied; Further equipped with the negative feedback circuit is configured to generate, in a hold mode, an output signal corresponding to a potential difference between a voltage of a first node to which the other end of the first capacitive element and the other end of the second capacitive element are commonly connected, and a voltage of a second node to which the other end of the third capacitive element and the other end of the fourth capacitive element are commonly connected, and to apply a first feedback signal corresponding to the output signal to one end of the first capacitive element and a second feedback signal corresponding to the output signal to one end of the third capacitive element. The semiconductor device according to claim 1 .

14. The first inverted signal generating circuit includes: a first sub-A / D converter that holds the second input voltage in a hold mode and converts the held second input voltage into a digital signal; a first sub-DA converter that converts a digital signal output from the first sub-AD converter into an analog voltage; a first selection circuit that, in a sampling mode, selects the second input voltage and outputs it as a voltage generated by the first inversion signal generation circuit, and, in a hold mode, selects the analog voltage output from the first sub-DA converter and outputs it as a voltage generated by the first inversion signal generation circuit; Equipped with The second inverted signal generating circuit includes: a second sub-A / D converter that holds the first input voltage in a hold mode and converts the held first input voltage into a digital signal; a second sub-DA converter that converts the digital signal output from the second sub-AD converter into an analog voltage; a second selection circuit that, in a sampling mode, selects the first input voltage and outputs it as a voltage generated by the second inversion signal generation circuit, and, in a hold mode, selects the analog voltage output from the second sub-DA converter and outputs it as a voltage generated by the second inversion signal generation circuit; Equipped with The semiconductor device according to claim 13.

15. The first sub-DA converter includes: A plurality of first sub-capacitance elements; a plurality of first sub-switches provided corresponding to the plurality of first sub-capacitance elements, respectively; having the plurality of first sub-capacitance elements are also used as the second capacitance elements, The second sub-DA converter includes: A plurality of second sub-capacitance elements; a plurality of second sub-switches provided corresponding to the plurality of second sub-capacitance elements, respectively; having the plurality of second sub-capacitance elements are also used as the fourth capacitance elements; The semiconductor device according to claim 14.

16. a second switch circuit which applies a voltage obtained by inverting a common voltage applied to a first capacitance element to one end of the second capacitance element in the first sampling mode, and which applies a voltage generated by the first inversion signal generation circuit to one end of the second capacitance element in the second sampling mode and the hold mode, of a first sampling mode and a second sampling mode which constitute a sampling mode; a fourth switch circuit that applies a voltage obtained by inverting the common voltage to one end of the fourth capacitance element in a first sampling mode, and applies a voltage generated by the second inversion signal generation circuit to one end of the fourth capacitance element in a second sampling mode and a hold mode; Further equipped with the first switch circuit is configured to apply the common voltage to one end of the first capacitance element in a first sampling mode, and to apply the first input voltage to one end of the first capacitance element in a second sampling mode; the third switch circuit is configured to apply the common voltage to one end of the third capacitance element in a first sampling mode, and to apply the second input voltage to one end of the third capacitance element in a second sampling mode. The semiconductor device according to claim 13.

17. The first inverted signal generating circuit includes: a first sub-A / D converter that holds the second input voltage in a hold mode and converts the held second input voltage into a digital signal; a first sub-DA converter that converts the digital signal output from the first sub-AD converter into an analog voltage and outputs the voltage generated by the first inverted signal generating circuit; Equipped with The second inverted signal generating circuit includes: a second sub-A / D converter that holds the first input voltage in a hold mode and converts the held first input voltage into a digital signal; a second sub-DA converter that converts the digital signal output from the second sub-AD converter into an analog voltage and outputs the voltage generated by the second inverted signal generating circuit; Equipped with The semiconductor device according to claim 16.

18. The first sub-DA converter includes: A plurality of first sub-capacitance elements; a plurality of first sub-switches provided corresponding to the plurality of first sub-capacitance elements, respectively; having the plurality of first sub-capacitance elements are also used as the second capacitance elements, The second sub-DA converter includes: A plurality of second sub-capacitance elements; a plurality of second sub-switches provided corresponding to the plurality of second sub-capacitance elements, respectively; having the plurality of second sub-capacitance elements are also used as the fourth capacitance elements; The semiconductor device according to claim 17.

19. The negative feedback circuit includes: a comparator having one input terminal supplied with the voltage of the first node and another input terminal supplied with the voltage of the second node; a successive approximation register circuit for generating a digital output signal according to a comparison result of the comparator; a first DA converter that converts the output signal generated by the successive approximation register circuit into an analog voltage and outputs the analog voltage as the first feedback signal; a second DA converter that converts the output signal generated by the successive approximation register circuit into an analog voltage and outputs the analog voltage as the second feedback signal; Equipped with The semiconductor device according to claim 13.

20. The first DA converter is A plurality of capacitive elements; a plurality of switches provided corresponding to the plurality of capacitance elements, having a plurality of capacitance elements provided in the first DA converter are also used as the first capacitance elements; The second DA converter is A plurality of capacitive elements; a plurality of switches provided corresponding to the plurality of capacitance elements, having A plurality of capacitance elements provided in the second DA converter are also used as the third capacitance elements.

20. The semiconductor device according to claim 19.

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