Semiconductor device and method of manufacturing semiconductor device

Abstract

To improve insulation reliability by preventing bubbling, peeling and dew condensation of an insulation sealing member.SOLUTION: A semiconductor device 10 has: an insulation substrate 12 which comprises a plurality of wiring patterns 12b, 12c-1 and 12c-2; a semiconductor chip 1 which is arranged on at least one wiring pattern 12c-1 among the plurality of wiring patterns 12b, 12c-1 and 12c-2; metal wires 14-1, 14-2 and 14-3 which are electrically connected to the semiconductor chip 1; and a case 16 which has the insulation substrate 12 arranged at its bottom part. An insulation sealing member 15 fills a region encircled with the insulation substrate 12 and the case 16 deeply enough to cover the semiconductor chip 1 from the top surface of the insulation substrate 12 and also expose the metal wires 14-1, 14-2 and 14-3 at least in part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The semiconductor device has a structure in which an insulating circuit board on which a power semiconductor element is mounted is bonded onto a heat dissipation base, and is electrically connected to an external circuit via metal terminals. The semiconductor device and a resin case form a closed space, and the inside of the space is filled with an insulating sealing material.

[0003] As a related technique, for example, a semiconductor power module has been proposed in which a member having an open portion only on the bottom surface of a case supporting a substrate is formed, and the bottom surface of the member contacts a primary sealing resin to form an enclosed space inside (Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2001-210758 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to prevent the occurrence of air bubbles, peeling, and condensation in an insulating sealing member, thereby improving insulation reliability. [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor device is provided, which includes an insulating substrate having a plurality of wiring patterns, a semiconductor chip disposed on at least one of the plurality of wiring patterns, metal wiring electrically connected to the semiconductor chip, a case having the insulating substrate disposed at the bottom thereof, and an insulating sealing member that covers the semiconductor chip from the upper surface of the insulating substrate and fills the region surrounded by the insulating substrate and the case to a thickness that exposes at least a portion of the metal wiring. In order to solve the above problems, a method for manufacturing a semiconductor device is provided, which comprises filling an insulating sealing member into an area surrounded by an insulating substrate having a plurality of wiring patterns and a case having the insulating substrate disposed at the bottom thereof, from the upper surface of the insulating substrate, to a thickness that covers a semiconductor chip disposed on at least one of the plurality of wiring patterns and exposes at least a portion of a metal wiring electrically connected to the semiconductor chip. Effect of the Invention

[0007] According to one aspect, it is possible to prevent the occurrence of air bubbles, peeling, and condensation in the insulating sealing member, thereby improving the insulation reliability. [Brief description of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device of the present invention. [Diagram 2] 11 is a diagram showing the relationship between the depth of the insulating sealing member and the generation of bubbles. [Diagram 3] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. [Figure 4] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Diagram 5] 11A and 11B are diagrams illustrating an example of a covering operation of an insulating member. [Figure 6] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device. [Figure 9] FIG. 2 is a diagram illustrating an example of an equivalent circuit of a semiconductor device. [Figure 10] FIG. 2 is a plan view of a MOSFET. [Figure 11] 11A and 11B are diagrams illustrating an example of a terminal and a wire that are led out to the outside covered with an insulating member. [Figure 12] 1A and 1B are diagrams showing an example of filling with an insulating sealing material and covering with an insulating material, where FIG. 1A shows the filling with the insulating sealing material and the covering state of a terminal that is led out to the outside, and FIG. 1B shows the filling with the insulating sealing material and the covering state of a wire. [Figure 13] 11A and 11B are diagrams illustrating an example of a terminal and a wire that are led out to the outside covered with an insulating member. [Figure 14] 14 is a cross-sectional view of the portion X1-X2 shown in FIG. 13. [Figure 15] 1A and 1B are diagrams showing an example of filling with an insulating sealing material and covering with an insulating material, where FIG. 1A shows the filling with the insulating sealing material and the covering state of a terminal that is led out to the outside, and FIG. 1B shows the filling with the insulating sealing material and the covering state of a wire. [Figure 16] 4A and 4B are diagrams showing an example of coating a first terminal and a second terminal with an insulating member. [Figure 17] 1A and 1B are diagrams showing an example of filling with an insulating sealing material and covering with an insulating material, where FIG. 1A shows the state where the insulating sealing material is filled and the second terminal is covered, and FIG. 1B shows the state where the insulating sealing material is filled and the first terminal is covered. [Figure 18] 11A and 11B are diagrams showing an example of coating a control electrode wiring and a rear electrode wiring with an insulating member. [Figure 19] 11 is a diagram showing an example of covering the front surface main electrode wiring and the back surface electrode wiring with an insulating member. FIG. [Figure 20] 1 is a diagram showing an example of a configuration of a semiconductor device including a vertical semiconductor chip; [Figure 21] 1 is a diagram showing an example of a configuration of a semiconductor device including a vertical semiconductor chip; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The present embodiment will be described below with reference to the drawings. 1 is a diagram for explaining an example of a semiconductor device of the present invention, showing a cross-sectional view of a semiconductor device 10. The semiconductor device 10 includes a semiconductor chip 1 mounted on a cooling body 11 and an insulating substrate (insulating circuit board) 12.

[0010] The insulating substrate 12 has a ceramic 12a and patterns (foils) 12b, 12c-1, and 12c-2 (hereinafter, the patterns 12c-1 and 12c-2 are collectively referred to as pattern 12c). In addition, if the patterns 12b and 12c are, for example, copper patterns, a DCB (Direct Copper Bonding) substrate in which the patterns 12b and 12c are directly bonded to the ceramic 12a can be used.

[0011] One surface of a metal base plate (heat dissipation base) 11b is mounted on the upper surface of the cooling body 11 with heat dissipation grease (thermal grease) 11a interposed therebetween, and an insulating substrate 12 is mounted on the other surface of the metal base plate 11b. Then, a pattern 12b of the insulating substrate 12 is joined to the metal base plate 11b with solder 13a. For example, a semiconductor chip 1 made of silicon is joined onto the pattern 12c-1 of the insulating substrate 12 with the solder 13b.

[0012] On the other hand, metal wires (hereinafter, wires) 14-1, 14-2, and 14-3, which are metal wirings, are, for example, aluminum bonding wires with a wire diameter of 300 μm to 500 μm. Wire 14-1 joins pattern 12c-1 and external terminal 16a provided on case 16. The material of the wire may be copper, silver, gold, or the like.

[0013] Wire 14-2 joins an electrode of semiconductor chip 1 to pattern 12c-2 serving as a lead electrode of insulating substrate 12. Note that semiconductor chip 1 may be provided with an electrode (Al-Si electrode) covered with, for example, an Al-Si alloy film.

[0014] The wire 14-3 joins the pattern 12c-2 to an external terminal 16b provided on the case 16. Wires 14-1, 14-2, and 14-3 are bonded by ultrasonic wire bonding using a load. As the metal wiring connected to the semiconductor chip 1, a lead frame or conductive pin made of a metal plate can be used in addition to wires. These can be made of a metal material such as copper, and can be connected to the semiconductor chip 1 via solder or sintered material.

[0015] The insulating substrate 12 to which the semiconductor chip 1 is bonded is housed in a case 16, and the area surrounded by the case 16 and the metal base plate 11b is filled and sealed with an insulating sealing member 15. The case 16 and the metal base plate 11b are fixed together with an adhesive or the like.

[0016] Here, the patterns 12b and 12c of the insulating substrate 12 are made of a material with excellent conductivity. Such a material is, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the patterns 12b and 12c is preferably 0.10 mm or more and 2.00 mm or less, and more preferably 0.20 mm or more and 1.00 mm or less.

[0017] In addition to the semiconductor chip 1, wiring members such as bonding wires, lead frames, and connection terminals, as well as electronic components, can be appropriately arranged on the pattern 12c as required.

[0018] It is also possible to plate such patterns 12c with a material having excellent corrosion resistance. Such materials include, for example, aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of these metals. The number, arrangement, and shape of the patterns 12c can be appropriately selected by design.

[0019] On the other hand, the metal base plate 11b is made of a metal having excellent thermal conductivity. The metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. Examples of such alloys include metal composites such as aluminum-silicon nitride (Al-SiC) or magnesium-silicon nitride (Mg-SiC).

[0020] In order to improve corrosion resistance, a material such as nickel may be formed on the surface of the metal base plate 11b by plating or the like. Specifically, in addition to nickel, nickel-phosphorus alloy, nickel-boron alloy, etc. are available. The thickness of the plating film is preferably 1 μm or more, more preferably 5 μm or more. The cooling body 11 is a heat sink with one or more fins or a water-cooled cooling device, etc.

[0021] On the other hand, the semiconductor chip 1 is a power device made of silicon, silicon carbide, or gallium nitride. The semiconductor chip 1 includes a switching element. The switching element is a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like.

[0022] Such a semiconductor chip 1 includes, for example, a drain electrode (positive electrode, collector electrode in an IGBT) and a source electrode (negative electrode, emitter electrode in an IGBT) as main electrodes, and a gate electrode as a control electrode.

[0023] The semiconductor chip 1 also includes a diode element. The diode element is, for example, a Schottky Barrier Diode (SBD) or a Free Wheeling Diode (FWD) such as a P-intrinsic-N (PiN) diode.

[0024] The thickness of the semiconductor chip 1 is, for example, 80 μm or more and 500 μm or less, with an average thickness of about 200 μm. Note that other electronic components can also be arranged in the pattern 12c as necessary. Examples of the electronic components include a capacitor, a resistor, a thermistor, a current sensor, and a control IC (Integrated Circuit).

[0025] On the other hand, insulating sealing member 15 is filled in the area surrounded by insulating substrate 12 and case 16 to a depth that covers all or part of semiconductor chip 1 from the top surface of insulating substrate 12 and exposes at least a portion of wires 14-1, 14-2, and 14-3.

[0026] Conventionally, for example, the filling height (filling thickness) h2 of insulating sealing member 15 is approximately 15 mm from the upper surface of insulating substrate 12 (the upper surfaces of patterns 12c-1 and 12c-2 in the example of FIG. 1). In contrast, in semiconductor device 10 of the present invention, the filling height h1 of insulating sealing member 15 is 3 mm or less from the upper surface of insulating substrate 12. Note that a gel is used for insulating sealing member 15, and as the gel, for example, a silicone gel or a resin with good conformability can be used.

[0027] In this manner, the semiconductor device 10 has an insulating sealing member 15 that covers the semiconductor chip 1 from the upper surface of the insulating substrate 12 in the region surrounded by the insulating substrate 12 and the case 16, and fills the region to a depth that exposes at least a portion of the wires 14-1 and 14-2. The joint between the semiconductor chip 1 and the wire 14-2 is also covered with the insulating sealing member 15.

[0028] This configuration makes it possible to prevent air bubbles, peeling, and condensation from occurring in the insulating sealing member, thereby improving the insulation reliability in the semiconductor device 10. Note that the semiconductor device 10 to which the above configuration is applied is effective for example for a small capacity, general-purpose voltage-rated semiconductor device.

[0029] On the other hand, for large-capacity, high-voltage rated semiconductor devices, insulation between terminals, etc. must be ensured even if the filling height of the insulating sealing member is 3 mm or less from the top surface of the insulating substrate. For this reason, in large-capacity, high-voltage rated semiconductor devices, not only is the filling height of the insulating sealing member reduced, but insulation is also ensured by covering parts of the terminals and wires exposed from the insulating sealing member with an insulating member. A large-capacity, high-voltage rated semiconductor device having a configuration in which parts of the terminals, wires, etc. are covered with such insulating member will be described later with reference to FIG. 3 and subsequent figures.

[0030] <Insulating sealing material> Silicone gel or resin is used as the insulating sealing material filled inside the semiconductor device, and silicone gel with good conformability is the most commonly used. In recent years, resin sealing structures have been used for applications requiring heat resistance and heat cycle resistance (mainly for automotive applications).

[0031] Insulating sealing materials provide mechanical protection for the internal circuits of semiconductor devices (protection from foreign matter, etc.) and insulation between electrodes (between circuits). Insulating reliability is ensured by covering and filling the circuit surfaces, including the semiconductor element surface, wire surface, and terminal surface, and between electrodes (between circuits) with insulating material.

[0032] For example, if a conductive foreign object adheres between exposed circuits, the circuit may short circuit and cause a breakdown, and even if the foreign object has low conductivity, it may cause a short circuit due to tracking. Therefore, by covering and filling the circuit surface, including the semiconductor element surface, wire surface, and terminal surface, with an insulating sealing material, it is possible to protect the circuit and prevent breakdowns. In addition, by covering and filling the space between electrodes with an insulating sealing material, the insulation distance can be significantly shorter than air insulation, making it possible to miniaturize semiconductor modules through high-density packaging.

[0033] <Problems caused by air bubbles in insulating sealing materials> Silicone gel is soft and has high conformability, so it is less likely to peel off, but it has high moisture absorption (permeability), so it is prone to air bubbles and condensation inside. By making it harder, the generation of air bubbles can be suppressed, but the conformability decreases and it becomes more likely to peel off.

[0034] In addition, resin does not generate bubbles during use because it is highly elastic (hard), but it is more prone to peeling than gel. If bubbles, peeling, or condensation occurs in the insulating material, the reliability of the insulation will decrease.

[0035] Here, insulating sealing materials such as silicone gel and resin have a higher dielectric constant than air, so if a gap occurs between the electrodes due to air bubbles inside the insulating sealing material or peeling of the insulating sealing material, the electric field strength increases in the gap and the insulation reliability decreases. For example, if a gap occurs, the discharge start voltage drops to about 1 / 3. In particular, since the electric field is easily concentrated on the surface of the bonding wire, the discharge start voltage drops to about 1 / 6 compared to other areas, and the thinner the bonding wire, the lower the insulation performance becomes.

[0036] If the maximum rated voltage of a semiconductor chip is around 1.7 kV or less, even if a gap occurs between the electrodes, the insulation distance required for the bonding wire is relatively small, so there are few design (miniaturization) constraints. However, when the maximum rated voltage of a semiconductor chip is a high voltage of 3.3 kV or more, the insulation distance required for a bonding wire with a diameter of around 300 μm becomes larger than the insulation distance required for a bonding wire with a diameter of around 125 μm when the maximum rated voltage is around 1.7 kV or less, which becomes an obstacle to miniaturization. The present invention has been made in view of the above-mentioned points, and aims to prevent the occurrence of bubbles, peeling and condensation in the insulating sealing member, thereby improving the insulation reliability.

[0037] <Depth of insulating sealing material> When silicone gel that has absorbed moisture is heated, air bubbles form inside the silicone gel (especially at the interface between the silicone gel and the component). This occurs when moisture that cannot be completely dissolved by heating increases the internal pressure of the bubble nuclei (tiny spaces / defects), causing foaming.

[0038] This phenomenon competes with the speed at which moisture escapes from the top surface of the gel when the temperature is increased. Therefore, even if a hygroscopic gel is heated, if the moisture concentration in the gel decreases before the pressure inside the bubble nuclei increases sufficiently, no bubbles will be generated.

[0039] On the other hand, when silicone gel that has absorbed moisture is cooled, the absorbed moisture condenses within the gel and condenses. This occurs because the amount of water vapor (gas) that can exist in the gaps within the gel decreases, and this phenomenon also competes with the speed at which moisture escapes from the top surface of the gel. If the moisture concentration within the gel decreases before the relative humidity in the gaps within the gel reaches 100%, condensation will not occur.

[0040] Since moisture transport within the gel follows diffusion transport, the gel dehydration speed is inversely proportional to the square of the thickness (25 times from 15 mm to 3 mm). Therefore, by reducing the depth of the silicone gel, which is an insulating sealing material, to a specified depth, the dehydration speed increases and the generation of air bubbles and condensation can be suppressed.

[0041] FIG. 2 is a diagram showing the relationship between the depth of the insulating sealing member and the generation of air bubbles. The vertical axis shows the density of air bubbles generated (pcs / cm 2 ), with the horizontal axis representing the depth of the insulating sealing member (mm). The graph shows the number of bubbles that were generated after the insulating sealing member was left on a hot plate at 150°C after absorbing moisture at 85°C and 85% for 24 hours. As shown in Figure 2, there is a positive correlation with the depth of the insulating sealing member, and no bubbles were observed when the insulating sealing member was 3 mm deep.

[0042] Therefore, in the present invention, the depth (thickness) of the insulating sealing member is set to 3 mm or less, thereby increasing the drying speed of the insulating sealing member and suppressing the occurrence of air bubbles and condensation even when the moisture-absorbing gel is heated or cooled.

[0043] <Large capacity, high voltage rated semiconductor device> Next, the semiconductor device and the manufacturing method of the semiconductor device of the present invention will be described in detail below. Fig. 3 is a diagram showing an example of the configuration of a semiconductor device. A schematic cross-sectional view is shown to explain the features of the present invention. The semiconductor device 20 is a large-capacity, high-voltage rated semiconductor device, for example, with a current rating of 100A or more and a voltage rating of 1700V or more.

[0044] The semiconductor device 20 has an insulating substrate 22 mounted on one surface of a metal base plate 21, and patterns 22a-1, 22a-2, and 22a-3 laid on the upper surface of the insulating substrate 22. The semiconductor device 20 also has terminals 30a and 30b that are led out to the outside, with the terminal 30a connected to the pattern 22a-1 and the terminal 30b connected to the pattern 22a-2. Furthermore, the patterns 22a-2 and 22a-3 are electrically connected via a wire 24.

[0045] Here, the region surrounded by insulating substrate 22 and a case (not shown) is filled with insulating sealing member 25 to a height of 3 mm or less from the upper surface of insulating substrate 22. Furthermore, the portions of terminals 30a, 30b exposed from insulating sealing member 25 and the portions of wires 24 exposed from insulating sealing member 25 are covered with insulating member 26.

[0046] For example, an adhesive or a resin is applied to the insulating member 26. Examples of the resin include PPS (polyphenylene sulfide), PBT (polybutylene terephthalate), polyamide, LCP (liquid crystal polymer), POM (polyoxymethylene), polyimide, polyamideimide, polyester, epoxy resin, fluororesin, acrylic resin, silicone resin, polyolefin, and polyetherimide.

[0047] In this way, for the semiconductor device 20 with large capacity and high voltage rating, the filling height of the insulating sealing member is set to 3 mm or less from the upper surface of the insulating substrate, and the terminals and parts of the metal wiring exposed from the insulating sealing member are covered with insulating member.

[0048] This makes it possible to suppress the generation of air bubbles in the insulating sealing member and ensure the insulation between terminals, etc. In the example of Fig. 3, a state in which all parts exposed from the insulating sealing member are covered with the insulating member is shown, but the insulating member is only applied to exposed parts that require insulation.

[0049] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device will be described with reference to Figures 4 to 8. In the following description, the insulating sealing member may be referred to as gel. When filling with gel, the gel is injected to fill areas where the insulating spatial distance is insufficient in areas where a high voltage of about the rated voltage is applied. Furthermore, the areas covered with the insulating member are areas exposed from the gel and where insulation is required.

[0050] FIG. 4 is a diagram showing an example of a method for manufacturing a semiconductor device. [Step P1] The semiconductor chip and terminals are connected to a wiring pattern on an insulating substrate. [Step P2] Gel is injected into the area surrounded by the insulating substrate and the case with the insulating substrate placed at the bottom, so that the gel fills the area from the top surface of the insulating substrate to a depth of 3 mm or less. [Step P3] After the gel has been filled into the region, the parts exposed from the gel, such as terminals and wires, that need to be insulated, are covered with an insulating material. [Step P4] The gel is hardened by heat treatment.

[0051] Fig. 5 is a diagram showing an example of the covering operation of the insulating material. When covering a predetermined portion with the insulating material, a dispenser ds can be used. By using the dispenser ds, for example, it is possible to cover an area where the insulating space distance is insufficient with the insulating material 26 for a portion to which a high voltage of about the rated voltage is applied.

[0052] FIG. 6 is a diagram showing an example of a method for manufacturing a semiconductor device. [Step P11] The semiconductor chip and terminals are connected to the wiring pattern on the insulating substrate. [Step P12] In the area surrounded by the insulating substrate and the case with the insulating substrate at the bottom, when gel is poured from the top surface of the insulating substrate to a thickness of 3 mm or less, the exposed areas are pre-coated with insulating material. [Step P13] Gel is injected into the area so that it fills the area to a depth of 3 mm or less from the top surface of the insulating substrate. [Step P14] The gel is hardened by heat treatment.

[0053] FIG. 7 is a diagram showing an example of a method for manufacturing a semiconductor device. [Step P21] The semiconductor chip and terminals are connected to a wiring pattern on an insulating substrate. [Step P22] Gel is injected into the area surrounded by the insulating substrate and the case at the bottom of which the insulating substrate is placed, to a position higher than a thickness of 3 mm or less from the top surface of the insulating substrate. [Step P23] The gel is sucked in until it is 3 mm or less thick from the top surface of the insulating substrate. After the gel has been sucked in, the exposed terminals, wires, and other parts that need to be insulated, which are exposed through the gel that has been filled in to a depth of 3 mm or less from the top surface of the insulating substrate, are covered with gel. [Step P24] The gel is hardened by heat treatment.

[0054] 7, the insulating sealing material is injected to a position greater than 3 mm thick, and then sucked down to a thickness of 3 mm or less. This makes it possible to cover the exposed terminals, wires, and other parts that require insulation, exposed from the gel that has been filled to a thickness of 3 mm or less from the top surface of the insulating substrate, with gel without using an insulating material.

[0055] Here, a suction machine (pump) is used to suck up the gel. Either a rotary or positive displacement pump can be used as the suction machine, but a positive displacement pump is preferred because the suction of gel requires a high viscosity, a small flow rate, and a fixed amount (measurement).

[0056] The amount of gel sucked is controlled by a flow meter. In the case of a rotary pump, a flow meter is used to control the amount of discharge, and the gel depth level in the semiconductor device is controlled. In the case of a positive displacement pump, the amount of discharge can be quantified, and the characteristic is used to control the gel depth level in the semiconductor device.

[0057] FIG. 8 is a diagram showing an example of a method for manufacturing a semiconductor device. [Step P31] The semiconductor chip and terminals are connected to a wiring pattern on an insulating substrate. [Step P32] Gel is injected into the area surrounded by the insulating substrate and the case with the insulating substrate at the bottom, to a depth of 3 mm or less from the top surface of the insulating substrate. The gel is then ejected toward the exposed areas. [Step P33] When the gel reaches a thickness of 3 mm or less, the gel is stopped from being discharged and the exposed areas are covered with gel. [Step P34] The gel is hardened by heat treatment.

[0058] In this way, in the manufacturing method of Figure 8, gel is ejected toward the exposed areas when the gel is filled to a thickness of 3 mm or less, and when the gel reaches a thickness of 3 mm or less, ejection is stopped to cover the exposed areas with gel.

[0059] This makes it possible to cover areas where insulation must be ensured, such as terminals and wires that are exposed from the gel that fills the top surface of the insulating substrate to a depth of 3 mm or less, with gel without using insulating materials.

[0060] Next, an example of a portion covered with an insulating member will be described. In the following description, the connection between the terminal and the pattern, or the connection between the wire and the pattern, is performed by, for example, ultrasonic waves or laser.

[0061] <Equivalent circuit of semiconductor device> 9 is a diagram showing an example of an equivalent circuit of a semiconductor device 10. The equivalent circuit of the semiconductor device 10 shows a full-bridge inverter circuit using MOSFETs as semiconductor chips. The terminals 41a, 41b, and 41c that are P terminals and are led out to the outside are electrically connected to the drain electrodes of the upper arm semiconductor chips 31a, 31b, and 31c via wirings 51a, 51b, and 51c, respectively.

[0062] The U terminal 47a, the V terminal 47b, and the W terminal 47c, which are terminals led out to the outside, are electrically connected to connection points in wirings 52a, 52b, and 52c between the source electrodes of each upper arm semiconductor chip 31a, 31b, and 31c and the drain electrodes of each lower arm semiconductor chip 32a, 32b, and 32c, respectively.

[0063] Moreover, terminals 44a, 44b, and 44c which are N terminals and are led out to the outside are electrically connected to the source electrodes of the lower arm semiconductor chips 32a, 32b, and 32c via wirings 53a, 53b, and 53c, respectively.

[0064] Furthermore, auxiliary terminals 49a, 49b, 49c extending to the outside are electrically connected to the source electrodes of the lower arm semiconductor chips 32a, 32b, 32c and the terminals 44a, 44b, 44c via wirings 53a, 53b, 53c, respectively.

[0065] The control electrodes G1, G3, G5 of the upper arm semiconductor chips 31a, 31b, 31c are electrically connected to control terminals Ga, Gc, Ge led out to the outside via wirings 54a, 54b, 54c, and the control electrodes G2, G4, G6 of the lower arm semiconductor chips 32a, 32b, 32c are electrically connected to control terminals Gb, Gd, Gf led out to the outside via wirings 55a, 55b, 55c. The following describes an example in which only one phase (U phase) is arranged in the semiconductor device 10 of this embodiment. Of course, only two phases or all three phases can also be arranged in the semiconductor device 10.

[0066] Fig. 10 is a plan view of a MOSFET. It is a plan view of the MOSFET of the circuit shown in Fig. 9, showing the front surface. The MOSFET shown in Fig. 10 has a semiconductor substrate 35 exposed to the surroundings, a protective film 36 formed on the inside thereof, a source electrode 37, and a control electrode 38 arranged at a distance from the source electrode 37. A drain electrode is formed on the back surface (not shown).

[0067] <Insulation between the metal wiring and the terminals that are electrically connected to the front electrodes and are led out to the outside> Fig. 11 is a diagram showing an example of covering a terminal and a wire that are led out to the outside with an insulating material. Fig. 12 is a diagram showing an example of filling with an insulating sealing material and covering with an insulating material, where (a) shows the filling with the insulating sealing material and the covering state of the terminal that is led out to the outside, and (b) shows the filling with the insulating sealing material and the covering state of the wire.

[0068] In FIG. 11, patterns 4a-1, 4a-2, and 4a-3 are laid on an insulating substrate 4a, and a vertical semiconductor chip 9a is joined to the pattern 4a-2 by soldering or the like. A front surface main electrode (source electrode) of the semiconductor chip 9a is electrically connected to the pattern 4a-1 through a plurality of wires w2, and a terminal 5a extending to the outside is connected to the pattern 4a-1. The wires w1 and w2 are metal wires electrically connected to the semiconductor chip.

[0069] The backside main electrode (drain electrode) of the semiconductor chip 9a is connected to the pattern 4a-2. A plurality of wires w1 are connected to the patterns 4a-2 and 4a-3. The terminal 5a that is led out to the outside and the wires w1 are close to each other, and therefore, insulation must be ensured between them.

[0070] In terms of the correspondence between Figure 11 and the U-phase in Figure 9, for example, terminal 5a corresponds to terminal 44a, semiconductor chip 9a corresponds to the lower arm semiconductor chip 32a, and wire w1 corresponds to wiring 52a between the source electrode of upper arm semiconductor chip 31a and the drain electrode of lower arm semiconductor chip 32a.

[0071] 12(a), the insulating sealing member 7a is filled to a depth of 3 mm or less from the upper surface of the insulating substrate 4a (the upper surface of the pattern 4a-1). Since the terminal 5a is a portion that needs to be insulated from the wire w1, the portion exposed from the insulating sealing member 7a is covered with an insulating member 6a-1.

[0072] 12(b), the insulating sealing member 7a is filled to a depth of 3 mm or less from the upper surface of the insulating substrate 4a (the upper surfaces of the patterns 4a-2 and 4a-3). Since the wire w1 is a portion that needs to be insulated from the terminal 5a, the portion exposed from the insulating sealing member 7a is covered with an insulating member 6a-2.

[0073] In the above, both the terminal 5a and the wire w1 are covered with an insulating material, but only one of them may be covered with an insulating material. If there is a part of the wire w2 exposed from the insulating sealing member 7a, that part may be covered with an insulating material. Furthermore, a lead frame may be used instead of the wires w1 and w2.

[0074] <Insulation between the terminal and wire that is connected to the back electrode and is led out to the outside> Fig. 13 is a diagram showing an example of covering, with an insulating member, terminals and wires that are led out to the outside, and Fig. 14 is a cross-sectional view of the X1-X2 portion shown in Fig. 13. Patterns 4b-1, 4b-2, and 4b-3 are laid on an insulating substrate 4b, a vertical semiconductor chip 9b1 is joined to the pattern 4b-3 by soldering or the like, and a vertical semiconductor chip 9b2 is joined to the pattern 4b-2 by soldering or the like.

[0075] The front surface main electrodes of the semiconductor chip 9b1 are connected to the pattern 4b-2 through a plurality of wires w3. The front surface main electrodes of the semiconductor chip 9b2 are connected to the pattern 4b-1 through a plurality of wires w3a. The wires w3 and w3a are metal wires electrically connected to the semiconductor chips.

[0076] The terminal 5b1 is connected to the pattern 4b-1. The terminal 5b2, which is led out to the outside, is connected to the pattern 4b-3 and is connected to the back main electrode of the semiconductor chip 9b1. The terminals 5b1 and 5b2 are integrated with the mold resin MD while maintaining insulation. The terminal 5b2 and the wire W3 are close to each other and are therefore in a location where insulation must be maintained.

[0077] 9, for example, terminal 5b2 corresponds to terminal 41a, semiconductor chip 9b1 corresponds to upper-arm semiconductor chip 31a, wire w3 and pattern 4b-2 correspond to wiring 52a between the source electrode of upper-arm semiconductor chip 31a and the drain electrode of lower-arm semiconductor chip 32a. Furthermore, semiconductor chip 9b2 corresponds to lower-arm semiconductor chip 32a, and terminal 5b1 corresponds to terminal 44a.

[0078] FIG. 15 is a diagram showing an example of filling with insulating sealing material and covering with insulating material, where (a) shows the filling with insulating sealing material and the covering state of the terminals that are led out to the outside, and (b) shows the filling with insulating sealing material and the covering state of the wires.

[0079] 15(a), insulating sealing member 7b is filled to a depth of 3 mm or less from the upper surface of insulating substrate 4b (upper surface of pattern 4b-3). Since terminal 5b2 is a portion that needs to be insulated from wire w3, the portion exposed from insulating sealing member 7b is covered with insulating member 6b-1.

[0080] 15(b), insulating sealing member 7b is filled to a depth of about 3 mm or less from the upper surface of insulating substrate 4b (upper surfaces of patterns 4b-2 and 4b-3). Since wire w3 is a portion that needs to be insulated from terminal 5b2, the portion exposed from insulating sealing member 7b is covered with insulating member 6b-2.

[0081] In the above, both the terminal 5b2 and the wire w3 are covered with an insulating material, but only one of them may be covered with an insulating material. If the wire w3a has a portion exposed from the insulating sealing member 7b, that portion may be covered with an insulating material. Furthermore, a lead frame may be used instead of the wires w3 and w3a.

[0082] <Insulation between the first and second terminals> Fig. 16 is a diagram showing an example of covering a first terminal and a second terminal with an insulating member. Fig. 17 is a diagram showing an example of filling with an insulating sealing member and covering with an insulating member, where (a) shows the filling with the insulating sealing member and the covering state of the second terminal, and (b) shows the filling with the insulating sealing member and the covering state of the first terminal.

[0083] In FIG. 16, patterns 4c-1, 4c-2, and 4c-3 are provided on an insulating substrate 4c, and a vertical semiconductor chip 9c is joined to the pattern 4c-1 by soldering or the like.

[0084] The front surface main electrodes of the semiconductor chip 9c are electrically connected to the pattern 4c-2 through a plurality of wires w4. The wires w4 and w5 are metal wires electrically connected to the semiconductor chip.

[0085] The first terminal 5c1 that is led out to the outside is connected to the pattern 4c-3 and is electrically connected to the front surface main electrode of the semiconductor chip 9c. The second terminal 5c2 that is led out to the outside is connected to the pattern 4c-1 and is electrically connected to the back surface main electrode of the semiconductor chip 9c. The first terminal 5c1 and the second terminal 5c2 are close to each other and are in a position where insulation should be ensured.

[0086] 9, for example, the second terminal 5c2 corresponds to the terminal 41a, the semiconductor chip 9c corresponds to the upper-arm semiconductor chip 31a, the wire w4, the pattern 4c-2, the wire w5 and the pattern 4c-3 correspond to the wiring 52a connected to the source electrode of the upper-arm semiconductor chip 31a, and the first terminal 5c1 corresponds to the terminal 47a.

[0087] 17(a), insulating sealing member 7c is filled to a depth of 3 mm or less from the upper surface of insulating substrate 4c (upper surface of pattern 4c-3). Since first terminal 5c1 is a portion that needs to be insulated from second terminal 5c2, the portion exposed from insulating sealing member 7c is covered with insulating member 6c-1.

[0088] 17(b), insulating sealing member 7c is filled to a depth of 3 mm or less from the upper surface of insulating substrate 4c (upper surface of pattern 4c-1). Since second terminal 5c2 is a portion that needs to be insulated from first terminal 5c1, the portion exposed from insulating sealing member 7c is covered with insulating member 6c-2.

[0089] In the above, both the first terminal 5c1 and the second terminal 5c2 are covered with an insulating material, but only one of them may be covered with an insulating material. If there are any parts of the wires w4 and w5 exposed from the insulating sealing member 7c, those parts may be covered with an insulating material. Furthermore, a lead frame may be used instead of the wires w4 and w5.

[0090] <Insulation between control electrode wiring and back electrode wiring> 18 is a diagram showing an example of covering the control electrode wiring and the back electrode wiring with an insulating material. Patterns 4d-1, . . . , 4d-4 are provided on an insulating substrate 4d, and a vertical semiconductor chip 9d is joined to the pattern 4d-1 by soldering or the like.

[0091] A control electrode (gate electrode) G1 of the semiconductor chip 9d is electrically connected to a pattern 4d-2 through a wire w63, and the pattern 4d-2 is electrically connected to a pattern 4d-3 through a plurality of wires w61. The pattern 4d-4 is electrically connected to a pattern 4d-1 through a plurality of wires w62. The wires w61, w62, and w63 are metal wires electrically connected to the semiconductor chips.

[0092] In terms of the correspondence between Figure 18 and the U-phase in Figure 9, for example, the semiconductor chip 9d corresponds to the upper arm semiconductor chip 31a, the wire w61 corresponds to the wiring 54a between the control electrode G1 of the upper arm semiconductor chip 31a and the control terminal Ga, and the wire w62 corresponds to the wiring 51a between the upper arm semiconductor chip 31a and the terminal 41a.

[0093] The wires w61 and w62 are adjacent to each other and have portions exposed from the insulating sealing member. In this case, the wire w61 is a portion that needs to be insulated from the wire w62, so the portion exposed from the insulating sealing member is covered with an insulating member 6d-1. The wire w62 is a portion that needs to be insulated from the wire w61, so the portion exposed from the insulating sealing member is covered with an insulating member 6d-2.

[0094] In the above, both the wire w61 corresponding to the control electrode wiring and the wire w62 corresponding to the back electrode wiring are covered with an insulating material, but only one of them may be covered with an insulating material. Also, a lead frame may be used instead of the wires w61 and w62.

[0095] <Insulation between the front surface main electrode wiring and the back surface electrode wiring> 19 is a diagram showing an example of covering the front surface main electrode wiring and the back surface electrode wiring with an insulating material. Patterns 4e-1, . . . , 4e-3 are laid on an insulating substrate 4e, and a vertical semiconductor chip 9e is joined to the pattern 4e-1 by soldering or the like.

[0096] The front surface main electrode of the semiconductor chip 9e is connected to the pattern 4e-3 through multiple wires w71. The pattern 4e-1 is connected to the back surface main electrode of the semiconductor chip 9e, and the pattern 4e-1 is connected to the pattern 4e-2 through multiple wires w72. The wires w71 and w72 are metal wires electrically connected to the semiconductor chip.

[0097] In terms of the correspondence between Figure 19 and the U-phase in Figure 9, for example, semiconductor chip 9e corresponds to the upper arm semiconductor chip 31a, wire w71 corresponds to wiring 52a between the upper arm semiconductor chip 31a and the lower arm semiconductor chip 32a, and wire w72 corresponds to wiring 51a between the upper arm semiconductor chip 31a and terminal 41a.

[0098] The wires w71 and w72 are adjacent to each other and have portions exposed from the insulating sealing member. In this case, the portion of the wire w71 that is exposed from the insulating sealing member is covered with an insulating member 6e-1 since it is assumed that insulation from the wire w72 must be ensured. The portion of the wire w72 that is exposed from the insulating sealing member is covered with an insulating member 6e-2 since it is assumed that insulation from the wire w71 must be ensured.

[0099] In the above, both the wire w71 corresponding to the front main electrode wiring and the wire w72 corresponding to the back electrode wiring are covered with an insulating material, but only one of them may be covered with an insulating material. Also, a lead frame may be used instead of the wires w71 and w72.

[0100] <Semiconductor device equipped with a vertical semiconductor chip> Fig. 20 and Fig. 21 are diagrams showing an example of the configuration of a semiconductor device including a vertical semiconductor chip, Fig. 20 being a schematic plan view and Fig. 21 being a schematic side view. In the semiconductor device 100, three main electrode terminals 121, 122, 123 and four auxiliary electrode terminals 124, 125, 126, 127 are connected as the electrode terminals 120. The main electrode terminals 121, . . . , 123 and the auxiliary electrode terminals 124, . . . , 127 are formed in advance using a metal material such as Al or Cu before being attached to the semiconductor device 100.

[0101] The main electrode terminal 121 is connected to the first main conductor pattern 143a (C1 terminal) of the first DCB substrate 140A. The main electrode terminal 121 has a terminal body 121a and two legs 121b continuing from the terminal body 121a. The two legs 121b of the main electrode terminal 121 are attached onto the first main conductor pattern 143a of the first DCB substrate 140A by soldering or the like.

[0102] The reason why the main electrode terminal 121 has two legs 121b and is connected to the first main conductor pattern 143a of the first DCB substrate 140A is to prevent electrical bias (imbalance in resistance and impedance) from occurring between one set of IGBT 151 and FWD 152 on the first DCB substrate 140A and the other set of IGBT 151 and FWD 152 on the first DCB substrate 140A.

[0103] The main electrode terminal 122 is connected to the second main conductor pattern 143b (E2 terminal) of the second DCB substrate 140B. The main electrode terminal 122 has a terminal body 122a and two legs 122b continuing from the terminal body 122a. The two legs 122b of the main electrode terminal 122 are attached onto the second main conductor pattern 143b of the second DCB substrate 140B by soldering or the like.

[0104] The main electrode terminal 122 is connected at two points in this manner in order to prevent electrical bias from occurring between one set of IGBT 151 and FWD 152 on the second DCB substrate 140B and the other set of IGBT 151 and FWD 152.

[0105] The main electrode terminal 123 is connected to a first main conductor pattern 143a (E1 terminal) of the second DCB substrate 140B, which is connected to a second main conductor pattern 143b of the first DCB substrate 140A by a wire 160. The main electrode terminal 123 has a terminal body 123a and two legs 123b continuing from the terminal body 123a. The two legs 123b of the main electrode terminal 123 are attached onto the first main conductor pattern 143a of the second DCB substrate 140B by soldering or the like.

[0106] The main electrode terminal 123 is connected at two points in this manner in order to prevent electrical bias from occurring between one set of IGBT 151 and FWD 152 on the second DCB substrate 140B and the other set of IGBT 151 and FWD 152. Terminal body portions 121a, . . . , 123a of the main electrode terminals 121, . . . , 123 are each substantially U-shaped with the leg portions 121b, . . . , 123b opening.

[0107] The auxiliary electrode terminal 124 has a terminal body 124a and a leg 124b. The leg 124b of the auxiliary electrode terminal 124 is attached by soldering or the like to an auxiliary conductor pattern electrically connected to the second main conductor pattern 143b of the first DCB substrate 140A via a wire 160.

[0108] The auxiliary electrode terminal 125 has a terminal body 125a and a leg portion 125b. The leg portion 125b of the auxiliary electrode terminal 125 is attached onto the third main conductor pattern 143c (G1 terminal) of the first DCB substrate 140A by soldering or the like.

[0109] Similarly, the auxiliary electrode terminal 126 has a terminal body and a leg portion. The leg portion of the auxiliary electrode terminal 126 is attached by soldering or the like to the auxiliary conductor pattern of the first DCB substrate 140A to which the second main conductor pattern 143b (E2 terminal) of the second DCB substrate 140B is electrically connected via the wire 160.

[0110] The auxiliary electrode terminal 127 has a terminal body and a leg portion. The leg portion of the auxiliary electrode terminal 127 is attached by soldering or the like to the auxiliary conductor pattern of the first DCB substrate 140A to which the third main conductor pattern 143c (G2 terminal) of the second DCB substrate 140B is electrically connected via the wire 160.

[0111] The main electrode terminals 121, ..., 123 and the auxiliary electrode terminals 124, ..., 127 are each formed in advance in a shape that allows each terminal body to be positioned at a predetermined position in the semiconductor device 100 with the legs attached at predetermined locations.

[0112] For example, as shown in the figure, terminal body portions 121a, ..., 123a of the main electrode terminals 121, ..., 123 are pre-formed so as to be arranged side by side at approximately equal intervals in the central portion of the semiconductor device 100, and terminal body portions of the auxiliary electrode terminals 124, ..., 127 are pre-formed so as to be arranged side by side at the ends of the semiconductor device 100.

[0113] In Figures 20 and 21, the height t1 of the insulating sealing member 15 filled between the case (not shown) and the insulating substrate 140 is higher than the height t2 of the insulating sealing member 15 from the top surface of the insulating substrate 140. However, since the planar area of ​​the insulating sealing member 15 arranged above the insulating substrate 140 accounts for the majority of the area, by making the height from the insulating substrate 140 lower than in the conventional case, the effect of suppressing the generation of air bubbles can be obtained.

[0114] As described above, according to the present invention, it is possible to improve insulation reliability by preventing peeling and bubbles that occur when the moisture-absorbing gel is heated. It is also possible to prevent condensation that occurs when the moisture-absorbing gel is cooled, improving moisture resistance. Furthermore, it is possible to shorten the insulation distance, and for example, it is possible to design a compact product with a high voltage rating of 3.3 kV equivalent to a general-purpose rated product of 1.7 kV.

[0115] Furthermore, even with a 3.3kV rating, fine wire diameters (Φ300μm) can be used, minimizing the gate pads used only for signal input on the element surface. In particular, with expensive SiC (silicon carbide) elements, the element size can be reduced, making it possible to reduce costs.

[0116] Although the embodiments have been described above, the configurations of the parts shown in the embodiments can be replaced with other parts having similar functions. Any other components or steps may be added. Furthermore, any two or more configurations (features) of the above-mentioned embodiments may be combined. [Explanation of symbols]

[0117] 1. Semiconductor chip 10 Semiconductor device 11 Cooling body 11a Thermal paste 11b Metal base plate 12 Insulating substrate 12a Ceramic Patterns 12b, 12c-1, and 12c-2 13a, 13b Solder 14-1, 14-2, 14-3 Wire 15 Insulating sealing material 16 cases 16a, 16b external terminal h1 Filling height of insulating sealing material (present invention) h2 Filling height of insulating sealing material (conventional)

Claims

1. An insulating substrate having a plurality of wiring patterns; a semiconductor chip disposed on at least one of the plurality of wiring patterns; Metal wiring electrically connected to the semiconductor chip; a case having the insulating substrate disposed at the bottom thereof; an insulating sealing member that covers the semiconductor chip from the upper surface of the insulating substrate in a region surrounded by the insulating substrate and the case and fills the region to a thickness that exposes at least a portion of the metal wiring; A semiconductor device having the above structure.

2. The semiconductor device according to claim 1 , wherein the insulating sealing member is a gel.

3. the semiconductor chip is a vertical semiconductor chip and includes a front surface main electrode and a back surface main electrode connected to the wiring pattern; a first terminal connected to the wiring pattern electrically connected to the front-surface main electrode and led out to the outside; the first terminal has an exposed portion that is not covered by the insulating sealing member, The metal wiring is electrically connected to the rear surface main electrode, an insulating member that covers at least one of an exposed portion of the metal wiring that is not covered with the insulating sealing member and an exposed portion of the first terminal, the exposed portion being adjacent to the metal wiring and the first terminal; 3. The semiconductor device according to claim 2.

4. the semiconductor chip is a vertical semiconductor chip and includes a front surface main electrode and a back surface main electrode connected to the wiring pattern; a first terminal connected to the wiring pattern electrically connected to the back surface main electrode and led out to the outside; the first terminal has an exposed portion that is not covered by the insulating sealing member, the metal wiring is electrically connected to the front surface main electrode, an insulating member that covers at least one of an exposed portion of the metal wiring that is not covered with the insulating sealing member and an exposed portion of the first terminal, the exposed portion being adjacent to the metal wiring and the first terminal; 3. The semiconductor device according to claim 2.

5. the semiconductor chip is a vertical semiconductor chip and includes a front surface main electrode and a back surface main electrode connected to the wiring pattern; a first terminal connected to the wiring pattern electrically connected to the front surface main electrode and led out to the outside; a second terminal electrically connected to the back surface main electrode, connected to the wiring pattern different from the wiring pattern to which the first terminal is connected, and led out to the outside; the first terminal and the second terminal have exposed portions that are not covered by the insulating sealing member, an insulating member that covers at least one of an exposed portion of the first terminal and an exposed portion of the second terminal; 3. The semiconductor device according to claim 2.

6. the semiconductor chip is a vertical semiconductor chip and includes a back surface main electrode connected to the wiring pattern, a front surface main electrode, and a control electrode provided on the front surface of the semiconductor chip; the metal wiring includes a first metal wiring electrically connected to the control electrode and a second metal wiring electrically connected to the rear surface main electrode, an insulating member is provided to cover at least one of the first metal wiring and the second metal wiring at an exposed portion not covered with the insulating sealing member, the exposed portion being adjacent to the first metal wiring and the second metal wiring; 3. The semiconductor device according to claim 2.

7. the semiconductor chip is a vertical semiconductor chip and includes a back surface main electrode connected to the wiring pattern and a front surface main electrode; the metal wiring includes a first metal wiring electrically connected to the front surface main electrode and a second metal wiring electrically connected to the rear surface main electrode; an insulating member is provided to cover at least one of the first metal wiring and the second metal wiring at an exposed portion not covered with the insulating sealing member, the exposed portion being adjacent to the first metal wiring and the second metal wiring; 3. The semiconductor device according to claim 2.

8. 8. The semiconductor device according to claim 1, having a current rating of 100 A or more and a voltage rating of 1700 V or more.

9. 8. The semiconductor device according to claim 1, wherein the insulating sealing member has a thickness of 3 mm or less from the upper surface of the insulating substrate.

10. 8. The semiconductor device according to claim 3, wherein the insulating member is an adhesive or a resin.

11. 8. The semiconductor device according to claim 3, comprising a plurality of said semiconductor chips.

12. 6. The semiconductor device according to claim 5, comprising a plurality of said semiconductor chips, said semiconductor chip electrically connected to said first terminal being different from said semiconductor chip electrically connected to said second terminal.

13. An insulating substrate having a plurality of wiring patterns; a semiconductor chip disposed on at least one of the plurality of wiring patterns; Metal wiring electrically connected to the semiconductor chip; a case having the insulating substrate disposed at the bottom thereof; an insulating sealing member that covers the semiconductor chip from an upper surface of the insulating substrate in a region surrounded by the insulating substrate and the case; an insulating member covering a portion exposed from the insulating sealing member and for which insulation should be ensured; having A current rating of 100 A or more and a voltage rating of 1700 V or more, and the thickness of the insulating sealing member from the upper surface of the insulating substrate is 3 mm or less. Semiconductor device.

14. In a method for manufacturing a semiconductor device, For an area surrounded by an insulating substrate having a plurality of wiring patterns and a case having the insulating substrate disposed at the bottom thereof, filling the region with an insulating sealing member to a thickness that covers a semiconductor chip arranged on at least one of the plurality of wiring patterns from the upper surface of the insulating substrate and exposes at least a portion of a metal wiring electrically connected to the semiconductor chip; A method for manufacturing a semiconductor device.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the insulating sealing member is a gel.

16. The insulating sealing material is filled to a depth of 3 mm or less from the upper surface of the insulating substrate. The method for manufacturing a semiconductor device according to claim 14.

17. a portion exposed from the insulating sealing member and for which insulation should be ensured is covered with an insulating member; The method for manufacturing a semiconductor device according to claim 15.

18. When the insulating sealing member is filled into the region to the thickness, the exposed portion is covered with the insulating member in advance, and then the insulating sealing member is filled into the region to the thickness. The method for manufacturing a semiconductor device according to claim 17.

19. Injecting the insulating sealing member into the region to a position higher than the thickness, covering the portion with the insulating sealing member, and then suctioning the insulating sealing member until the thickness is reached, and covering the portion exposed from the insulating sealing member filled to the thickness after suction with the insulating sealing member. The method for manufacturing a semiconductor device according to claim 17.

20. the insulating sealing member is discharged toward the portion that would be exposed when the region is filled with the insulating sealing member to the thickness until the thickness is reached, and when the insulating sealing member reaches the thickness, the discharge is stopped to cover the exposed portion with the insulating sealing member. The method for manufacturing a semiconductor device according to claim 17.

21. 19. The method for manufacturing a semiconductor device according to claim 17, wherein the insulating member is an adhesive or a resin.

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