Lead frame, semiconductor device and method of manufacturing lead frame

Abstract

To provide a lead frame that suppresses a lead from deforming while avoiding occurrence of a short-circuit defect, a semiconductor device and a method of manufacturing the lead frame.SOLUTION: A lead frame 100 has a lead 120, a plating layer 125 and a plating film 126. The lead 120 has a top surface 120a and a reverse surface 120b, and the top surface 120a is larger in width than the reverse surface 120b. The plating layer 125 serves as a connection part for a semiconductor element provided on the top surface 120a. The plating film 126 covers the surface of the lead.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a lead frame, a semiconductor device, and a method for manufacturing a lead frame. [Background technology]

[0002] In recent years, semiconductor devices have been known in which a semiconductor element, such as an integrated circuit (IC) chip, is mounted on a metal lead frame. That is, the semiconductor element is mounted on a planar die pad provided in the center of the lead frame, and the semiconductor element is connected to a plurality of leads provided around the die pad by wire bonding, for example. The semiconductor element mounted on the lead frame is then sealed with a resin, such as an epoxy resin, to form a semiconductor device.

[0003] In such semiconductor devices, the number of leads is increasing, and as the number of leads increases, designs are being made to narrow the width of the leads. As the width of the leads becomes narrower, the strength of the leads decreases, and there is a possibility that the leads may become deformed. In response to this, it has been considered to form protrusions on the sides of the leads to improve the strength of the leads. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-159273 A [Patent Document 2] JP 2017-228795 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, when protrusions are formed on the sides of the leads to improve the strength of the leads, the distance between adjacent leads is not sufficiently secured, which may cause short circuits due to contact between adjacent leads. On the other hand, if no structure is provided to improve the strength of the leads, the leads become easily deformed, which reduces the productivity of the lead frame.

[0006] The disclosed technology has been developed in consideration of the above, and aims to provide a lead frame, a semiconductor device, and a method for manufacturing a lead frame that can suppress deformation of the leads while avoiding the occurrence of short circuits. [Means for solving the problem]

[0007] In one embodiment, the lead frame disclosed in the present application has leads, a connection portion, and a plating film. The leads have an upper surface and a lower surface, and the width of the upper surface is greater than the width of the lower surface. The connection portion is provided on the upper surface and is a connection portion with a semiconductor element. The plating film covers the surface of the leads. Effect of the Invention

[0008] According to one aspect of the lead frame disclosed in the present application, it is possible to suppress deformation of the leads while avoiding the occurrence of short circuits. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a specific example of an assembly of lead frames according to an embodiment. [Diagram 2] FIG. 2 is a top view showing the structure of the lead frame according to the embodiment. [Diagram 3] FIG. 3 is a bottom view showing the structure of the lead frame according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a diagram showing a cross section perpendicular to the longitudinal direction of the lead. [Figure 6]FIG. 6 is a diagram showing a specific example of the surface of a plating film. [Figure 7] FIG. 7 is a diagram showing a specific example of the thickness of the plating film. [Figure 8] FIG. 8 is a diagram showing a specific example of the thickness of the plating film. [Figure 9] FIG. 9 is a diagram showing a specific example of the coverage area of ​​the plating film. [Figure 10] FIG. 10 is a diagram showing a specific example of the coverage area of ​​the plating film. [Figure 11] FIG. 11 is a flowchart showing a method for manufacturing a lead frame according to the embodiment. [Figure 12] FIG. 12 is a diagram showing a specific example of the structure of the metal plate. [Figure 13] FIG. 13 is a diagram showing a specific example of the DFR lamination process. [Figure 14] FIG. 14 is a diagram showing a specific example of the exposure and development steps. [Figure 15] FIG. 15 is a diagram showing a specific example of the etching process. [Figure 16] FIG. 16 is a diagram showing a specific example of the DFR peeling step. [Figure 17] FIG. 17 is a diagram showing a specific example of a plating film forming step. [Figure 18] FIG. 18 is a diagram showing a configuration example of a plating apparatus for performing roughening plating of copper. [Figure 19] FIG. 19 is a diagram showing a specific example of a resist coating step. [Figure 20] FIG. 20 is a diagram showing a specific example of the exposure and development steps. [Figure 21] FIG. 21 is a diagram showing a specific example of a plating process. [Figure 22] FIG. 22 is a diagram showing a specific example of a resist stripping step. [Figure 23] FIG. 23 is a flowchart showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 24] FIG. 24 is a diagram showing a specific example of a semiconductor element mounting process. [Diagram 25]FIG. 25 is a diagram showing a specific example of a wire bonding connection process. [Figure 26] FIG. 26 is a diagram showing a specific example of the molding process. [Figure 27] FIG. 27 is a diagram showing a specific example of a plating process. [Figure 28] FIG. 28 is a diagram showing the structure of a semiconductor device. [Figure 29] FIG. 29 is a cross-sectional view of a lead frame according to a modified example of the embodiment. [Diagram 30] FIG. 30 is a diagram showing the structure of a semiconductor device manufactured using the lead frame shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the lead frame, semiconductor device, and method for manufacturing the lead frame disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited to these embodiments.

[0011] Fig. 1 is a diagram showing a specific example of an assembly of lead frames 100 according to an embodiment. As shown in Fig. 1, the lead frames 100 are manufactured as an assembly in which a plurality of lead frames 100 are connected in an area surrounded by a frame body 110. In the example shown in Fig. 1, six lead frames 100 connected in three rows and two columns are manufactured by performing etching, plating, and the like using a metal plate of, for example, copper or a copper alloy as a material.

[0012] By manufacturing an assembly of a plurality of lead frames 100 in this manner, the lead frames 100 can be manufactured efficiently and costs can be reduced. The plurality of lead frames 100 manufactured as an assembly are each separated into individual pieces to obtain lead frames 100 on which electronic components such as semiconductor elements are mounted.

[0013] FIG. 2 is a top view showing the structure of the lead frame 100 according to the embodiment, and FIG. 3 is a bottom view showing the structure of the lead frame 100 according to the embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. In FIGS. 2 to 4, one lead frame 100 in the assembly is illustrated in an enlarged manner. In the following description, when a semiconductor element is mounted on the lead frame 100, the surface facing the semiconductor element is referred to as the "top surface," and the surface facing the opposite side to the semiconductor element is referred to as the "bottom surface," and the up-down direction is defined accordingly. However, the lead frame 100 may be manufactured and used, for example, upside down, or in any position.

[0014] The lead frame 100 includes a frame body 110 , a plurality of leads 120 , a die pad 130 , and a connecting portion 140 .

[0015] The frame 110 defines the outer periphery of one lead frame 100 and supports the leads 120. The upper surface of the frame 110, the upper surfaces 120a of the leads 120, and the upper surface 130a of the die pad 130 are located in the same plane. The multiple leads 120 each extend from the frame 110 toward the die pad 130, and the die pad 130 is connected to the frame 110 by a connecting portion 140. When a semiconductor device is formed using the lead frame 100, the lead frame 100 is cut along the dashed lines in FIGS. 2 and 3, whereby the leads 120 and the connecting portion 140 are separated from the frame 110.

[0016] The leads 120 extend from the frame 110 toward the die pad 130, and when an electronic component such as a semiconductor element is mounted on the lead frame 100, the leads 120 form terminals that electrically connect the electronic component to an external component. A plating layer 125 is formed on the upper surface of the lead frame 100 on which the semiconductor element is mounted. Specifically, the lead 120 has a first portion 121 connected to the frame 110, a second portion 122 that is thicker than the first portion 121, and a third portion 123 that is thinner than the second portion 122, and the plating layer 125 is formed on the tip upper surface of the third portion 123. As the plating layer 125, silver or nickel / palladium / gold (a plating layer in which a nickel layer, a palladium layer, and a gold layer are laminated in this order) can be used. When a semiconductor element is mounted on the lead frame 100, the semiconductor element mounted on the lead frame 100 is connected to the plating layer 125 by wire bonding on the upper surface 120a of the lead 120. That is, the upper surface 120a of the lead 120 becomes a connection surface with the semiconductor element, and the plating layer 125 becomes a connection portion with the semiconductor element. Then, when the semiconductor element mounted on the lead frame 100 is molded with a sealing resin to form a semiconductor device, the lower surface of the second portion 122 of the lead 120 is exposed from the sealing resin and forms a terminal of the semiconductor device.

[0017] The die pad 130 is a plate-like region formed in the center of the lead frame 100, and is connected to the frame body 110 by, for example, four connecting parts 140. A semiconductor element is mounted on the upper surface 130a of the die pad 130. In other words, the upper surface 130a of the die pad 130 becomes the mounting surface for the semiconductor element. A stepped surface is formed on the outer periphery of the lower surface of the die pad 130.

[0018] In this embodiment, as shown in Fig. 4, a plating film 126 is formed on the surface of the lead frame 100. The plating film 126 covers the frame body 110, the leads 120, the die pad 130, and the connecting portion 140 (see Figs. 2 and 3). The plating film 126 may be made of, for example, copper or nickel.

[0019] The shapes of the lead 120 and the plating film 126 will now be described in more detail with reference to Fig. 5. Fig. 5 is a diagram showing a cross section perpendicular to the longitudinal direction of the lead 120. Fig. 5 shows a cross section taken along line VV in Fig. 4.

[0020] The plating film 126 covers all surfaces of the lead 120 including the upper surface 120a, the lower surface 120b, and the side surface 120c. In the plating film 126, the film thickness of the portion covering the upper surface 120a of the lead 120 and the film thickness of the portion covering the lower surface 120b of the lead 120 are the same, for example, about 1 to 5 μm. In addition, in the plating film 126, the film thickness of the portion covering the side surface 120c of the lead 120 is, for example, 0.5 to 2.5 μm. Here, in the plating film 126, the film thickness of the portion covering the side surface 120c may be made smaller than the film thickness of the portions covering the upper surface 120a and the lower surface 120b.

[0021] In this manner, in this embodiment, the periphery of the lead 120 is entirely covered with the plating film 126. This makes it possible to improve the strength of the lead 120 without forming reinforcing protrusions on the side surface 120c of the lead 120, and also ensure a sufficient distance between adjacent leads 120. As a result, it is possible to prevent the occurrence of short circuits between adjacent leads 120 and suppress deformation of the lead 120.

[0022] The lead 120 has a tapered shape in which the width of the upper surface 120a is larger than the width of the lower surface 120b in a cross section perpendicular to the longitudinal direction of the lead 120, and the width of the portion of the plating film 126 covering the upper surface 120a is larger than the width of the portion covering the lower surface 120b. In this way, the upper surface 120a of the lead 120 is covered with the relatively wide plating film 126, so that the width of the upper surface 120a of the lead 120, which is the connection surface with the semiconductor element, can be substantially expanded by the width of the plating film 126. As a result, the surface area of ​​the plating layer 125 formed on the upper surface 120a of the lead 120 can be increased, and the connection reliability between the semiconductor element and the plating layer 125 by wire bonding can be improved.

[0023] FIG. 6 is a diagram showing a specific example of the surface of the plating film 126. The plating film 126 is formed by, for example, roughening plating of copper. Therefore, as shown in FIG. 6, the surface of the plating film 126 is a roughened surface with a large surface roughness. That is, the surface roughness of the plating film 126 is larger than the surface roughness of all surfaces of the lead 120, including the upper surface 120a, the lower surface 120b, and the side surface 120c. Therefore, when the semiconductor element mounted on the lead frame 100 is molded with a sealing resin, the sealing resin fills the roughened portion of the plating film 126, and the adhesion between the lead 120 and the sealing resin via the plating film 126 can be improved by the anchor effect.

[0024] Furthermore, the surface roughness of the plating film 126 in the portion covering the upper surface 120a of the lead 120 is greater than the surface roughness of the portion covering the lower surface 120b of the lead 120. Therefore, when the semiconductor element mounted on the lead frame 100 is molded with a sealing resin, it is possible to improve the adhesion between the upper surface 120a of the lead 120, which has a larger contact area with the sealing resin than the lower surface 120b of the lead 120, and the sealing resin. Note that the surface roughness of the plating film 126 in the portion covering the upper surface 120a of the lead 120 may be greater than the surface roughness of the portion covering the side surface 120c of the lead 120.

[0025] In addition, the thickness of the plating film 126 at the portion covering the upper surface 120a of the lead 120 and the thickness of the portion covering the lower surface 120b of the lead 120 do not necessarily have to be the same. FIGS. 7 and 8 are diagrams showing specific examples of the thickness of the plating film 126. For example, as shown in FIG. 7, the thickness of the plating film 126 at the portion covering the lower surface 120b or the side surface 120c of the lead 120 may be smaller than the thickness of the portion covering the upper surface 120a of the lead 120. In this case, the thickness of the portion covering the upper surface 120a of the lead 120 may be, for example, about 1 to 5 μm, and the thickness of the portion covering the lower surface 120b or the side surface 120c of the lead 120 may be, for example, 0.5 to 2.5 μm. 8, the thickness of the plating film 126 at the portion covering the upper surface 120a of the lead 120 may be smaller than the thickness of the portion covering the lower surface 120b and the side surface 120c of the lead 120. In this case, the thickness of the portion covering the upper surface 120a of the lead 120 may be, for example, 0.5 to 2.5 μm, and the thickness of the portion covering the lower surface 120b and the side surface 120c of the lead 120 may be, for example, about 1 to 5 μm. By locally reducing the thickness of the plating film 126 covering the surface of the lead 120, the strength of the lead 120 can be improved while suppressing an increase in the thickness of the lead 120 including the thickness of the plating film 126.

[0026] The plating film 126 may also partially cover the surface of the lead 120. FIGS. 9 and 10 are diagrams showing a specific example of the coverage area of ​​the plating film 126. For example, as shown in FIG. 9, the plating film 126 may be formed on the upper surface 120a of the lead 120 to cover only the upper surface 120a of the lead 120. In this case, the lower surface 120b and the side surface 120c of the lead 120 are exposed from the plating film 126. For example, as shown in FIG. 10, the plating film 126 may also be formed on the lower surface 120b and the side surface 120c of the lead 120 to cover only the lower surface 120b and the side surface 120c of the lead 120. In this case, the upper surface 120a of the lead 120 is exposed from the plating film 126. By partially covering the surface of the lead 120 with the plating film 126, it is possible to improve the strength of the lead 120 while suppressing an increase in the thickness of the lead 120, including the thickness of the plating film 126.

[0027] Furthermore, the plating film 126 covers all the surfaces of the die pad 130 in addition to all the surfaces of the leads 120. That is, the plating film 126 covers all the surfaces of the die pad 130, including the upper surface 130a, the lower surface, and the side surfaces, which are the mounting surface for the semiconductor element. The film thickness or surface roughness of the plating film 126 covering the surface of the die pad 130 is similar to the film thickness or surface roughness of the plating film 126 covering the surface of the leads 120. The strength of the die pad 130 can be improved by entirely covering the periphery of the die pad 130 with the plating film 126. As a result, deformation of the die pad 130 can be suppressed.

[0028] Next, a method for manufacturing the lead frame 100 configured as above will be described by way of a specific example with reference to Fig. 11. Fig. 11 is a flow chart showing the method for manufacturing the lead frame 100 according to the embodiment. The steps described below are performed on a group of lead frames 100 such as that shown in Fig. 1, but below, a specific example of each step will be described focusing on one lead frame 100.

[0029] First, as shown in Fig. 12, for example, a metal plate 200 that will be the base material of the lead frame 100 is prepared (step S101). Fig. 12 is a diagram showing a specific example of the structure of the metal plate 200. The material of the metal plate 200 may be, for example, a metal such as copper or a copper alloy. The thickness of the metal plate 200 may be, for example, about 0.1 to 0.25 mm.

[0030] Then, a dry film resist (DFR), which is an etching resist, is laminated on the surface of the metal plate 200 (step S102). Specifically, for example, as shown in Fig. 13, a DFR 210 is laminated on the upper and lower surfaces of the metal plate 200. Fig. 13 is a diagram showing a specific example of the DFR lamination process.

[0031] Once the DFR 210 has been laminated, exposure and development are performed (step S103) to form the DFR 210 with a predetermined opening. Specifically, as shown in FIG. 14, for example, exposure and development are performed on the DFR 210 on the upper and lower sides of the metal plate 200 to form the DFR 210 with openings 211-213. FIG. 14 is a diagram showing a specific example of the exposure and development process. On the upper side of the metal plate 200, an opening 211 is formed in a portion where through etching is performed. Also, on the lower side of the metal plate 200, an opening 212 is formed in a portion where through etching and half etching are performed. Also, on the lower side of the metal plate 200, an opening 213 is formed in a portion where half etching is performed.

[0032] Once DFR 210 having openings 211-213 is formed on the upper and lower surfaces of metal plate 200, metal plate 200 is immersed in an etching solution and etched (step S104). Specifically, by immersing metal plate 200 in an etching solution such as sulfuric acid-hydrogen peroxide or persulfate, the surface of metal plate 200 exposed from openings 211-213 of DFR 210 is dissolved and formed into the shape of lead frame 100.

[0033] 15, for example, in a region where the upper and lower surfaces are exposed from the openings 211 and 212, the metal plate 200 melts from the upper and lower surfaces, and the lead 120 and the die pad 130 are separated. In a region where only the lower surface is exposed from the openings 212 and 213, the metal plate 200 melts from the lower surface and is half-etched, forming a first portion 121 and a third portion 123 of the lead 120. FIG. 15 is a diagram showing a specific example of the etching process.

[0034] In this manner, the lead 120 and the die pad 130 are separated by etching, and at the same time, the first portion 121 and the third portion 123 of the lead 120 are formed. Moreover, in the lead 120, etching is not performed between the first portion 121 and the third portion 123, and the second portion 122 that is thicker than the first portion 121 and the third portion 123 remains.

[0035] Once the etching is complete, the DFR 210 is stripped using, for example, an amine-based or non-amine-based stripping solution (step S105), to obtain the lead frame 100 having the leads 120 and the die pad 130. That is, for example, as shown in Fig. 16, the lead frame 100 from which the leads 120 and the die pad 130 are separated is obtained. Fig. 16 is a diagram showing a specific example of the DFR stripping process.

[0036] When the lead frame 100 is formed, a plating film 126 is formed on the entire surface of the lead frame 100 by copper roughening plating (step S106). That is, for example, as shown in FIG. 17, a plating film 126 is formed by copper roughening plating to cover the frame body 110, the leads 120, the die pad 130, and the connecting portion 140 (see FIG. 2 and FIG. 3). FIG. 17 is a diagram showing a specific example of a plating film forming step. The plating film 126 is formed so as to cover all the surfaces of the leads 120, including the upper surface 120a, the lower surface 120b, and the side surface 120c. At this time, by appropriately adjusting the composition of the copper sulfate plating solution used for the copper roughening plating and the electrolytic copper plating conditions, the plating film 126 may be formed with different surface roughness or thickness on the upper surface 120a and the lower surface 120b of the leads 120.

[0037] Specifically, the surface roughness of the plating film 126 covering the upper surface 120a of the lead 120 may be greater than the surface roughness of the plating film 126 covering the lower surface 120b of the lead 120. In this case, for example, the surface area ratio Sratio, which indicates the surface roughness of the portion covering the upper surface 120a of the lead 120, may be, for example, about 1.5 to 2.0, and the surface area ratio Sratio of the portion covering the lower surface 120b of the lead 120 may be, for example, about 1.1 to 1.5. The surface area ratio Sratio is the ratio of the actual surface area S to the area S0 when the actual surface area of ​​the region having an area S0 in a plan view is S, and is expressed as "S / S0". The larger the surface area ratio Sratio, the greater the surface roughness. Note that the surface area ratio Sratio of the portion covering the lower surface 120b of the lead 120 may be set to less than 1.1, so that the surface of the plating film 126 covering the lower surface 120b of the lead 120 may be made smooth.

[0038] Also, in the plating film 126, the film thickness of the portion covering the lower surface 120b of the lead 120 may be smaller than the film thickness of the portion covering the upper surface 120a of the lead 120. In this case, the film thickness of the portion covering the upper surface 120a of the lead 120 may be, for example, about 1 to 5 μm, and the film thickness of the portion covering the lower surface 120b of the lead 120 may be, for example, 0.5 to 2.5 μm. Also, in the plating film 126, the film thickness of the portion covering the upper surface 120a of the lead 120 may be smaller than the film thickness of the portion covering the lower surface 120b of the lead 120. In this case, the film thickness of the portion covering the upper surface 120a of the lead 120 may be, for example, about 0.5 to 2.5 μm, and the film thickness of the portion covering the lower surface 120b of the lead 120 may be, for example, about 1 to 5 μm.

[0039] The composition of the copper sulfate plating solution used for roughening copper plating is, for example, as follows. Copper sulfate: 200g / L Sulfuric acid: 100g / L Chlorine: 50ppm Polymer (inhibitor): 20mL / L Brightener: 2mL / L Leveler: 10mL / L

[0040] The roughening plating of copper using the copper sulfate plating solution as described above is carried out under predetermined electrolytic copper plating conditions, for example, by using a plating apparatus shown in Fig. 18. Fig. 18 is a diagram showing a configuration example of a plating apparatus for carrying out roughening plating of copper. The plating apparatus 300 shown in Fig. 18 has a plating tank 301, a pair of electrodes 303, 304, a polarity reversing power supply 305, and a DC power supply 306.

[0041] The plating tank 301 stores the copper sulfate plating solution 307. The composition of the copper sulfate plating solution 307 stored in the plating tank 301 is, for example, as described above. The formed lead frame 100 is placed in the plating tank 301 when roughening copper plating is performed.

[0042] The electrode 303 is disposed in the plating tank 301 so as to face one main surface 100a of the lead frame 100. The one main surface 100a of the lead frame 100 is located on one of the upper surface 120a and the lower surface 120b of the lead 120. The electrode 304 is disposed in the plating tank 301 so as to face the other main surface 100b of the lead frame 100. The other main surface 100b of the lead frame 100 is located on the other of the upper surface 120a and the lower surface 120b of the lead 120.

[0043] The polarity reversal power supply 305 is connected to the lead frame 100 and the electrodes 303 , and supplies to the lead frame 100 and the electrodes 303 a pulse current whose polarity is periodically reversed.

[0044] A DC power supply 306 is connected to the lead frame 100 and the electrodes 304 and supplies a constant current to the lead frame 100 and the electrodes 304 .

[0045] The electrolytic copper plating conditions used in the plating apparatus 300 described above can be arbitrarily adjusted according to the surface roughness or film thickness of the plating film 126 to be formed. For example, the magnitude of the pulse current supplied from the polarity reversal power supply 305 and the supply times of the positive and negative sides of the pulse current are arbitrarily adjusted according to the surface roughness or film thickness of the plating film 126 to be formed. In addition, for example, the magnitude of the current supplied from the DC power supply 306 is arbitrarily adjusted according to the surface roughness or film thickness of the plating film 126 to be formed. By adjusting the composition of the copper sulfate plating solution used for the copper roughening plating and the electrolytic copper plating conditions, plating films 126 having different surface roughness or film thicknesses can be formed on the upper surface 120a and the lower surface 120b of the lead 120.

[0046] After the plating film 126 is formed on the surface of the lead frame 100, a resist for plating is applied to the upper surface 120a of the lead 120 (step S107). Specifically, as shown in FIG. 19, for example, a resist 220 is applied to the entire surfaces of the frame body 110, the leads 120, and the die pad 130. The resist 220 may be formed by electrodeposition of an electrodeposition resist. FIG. 19 is a diagram showing a specific example of a resist application step. Note that the resist 220 is actually applied to the entire surfaces of the frame body 110, the leads 120, and the die pad 130 via the plating film 126, but in the following, for convenience, a description of the plating film 126 will be omitted as appropriate.

[0047] After the resist 220 is applied, exposure and development are performed (step S108) to form the resist 220 having a predetermined opening. Specifically, as shown in Fig. 20, for example, exposure and development are performed on the resist 220 on the upper surface side of the lead frame 100 to form the resist 220 having an opening 221. Fig. 20 is a diagram showing a specific example of the exposure and development process. In the opening 221, a part (wire bonding portion) of the upper surface 120a of the lead 120, which is the connection surface with the semiconductor element, is exposed.

[0048] The lead frame 100, in which a portion of the upper surface 120a of the lead 120 is exposed from the opening 221 of the resist 220, is immersed in, for example, a plating solution for silver plating and plated (step S109). Specifically, the lead frame 100 is immersed in, for example, a plating solution containing silver cyanide and potassium cyanide as main components, and electrolytic plating is performed, thereby forming a plating layer 125 on the upper surface 120a of the lead 120.

[0049] That is, for example, as shown in Fig. 21, silver contained in the plating solution is precipitated on a part of upper surface 120a of lead 120 exposed from opening 221 of resist 220, forming plating layer 125 having a thickness of, for example, 0.1 to 10 µm. Fig. 21 is a diagram showing a specific example of the plating process.

[0050] Once the plating layer 125 is formed, the resist 220 is stripped using, for example, a stripping solution (step S110), and the lead frame 100 is completed. That is, as shown in Fig. 22, for example, the plating layer 125 is formed on the upper surface 120a of the lead 120, and the lead frame 100 is completed in which the frame 110, the lead 120, and the die pad 130 are covered with the plating film 126. Fig. 22 is a diagram showing a specific example of the resist stripping step.

[0051] In this way, after etching to separate the leads 120 and the die pad 130, the plating film 126 that covers all the surfaces of the leads 120 is formed by roughening plating of copper. Therefore, the strength of the leads 120 can be improved without forming reinforcing protrusions on the side surfaces 120c of the leads 120, and the distance between adjacent leads 120 can be sufficiently secured. As a result, the deformation of the leads 120 can be suppressed while avoiding the occurrence of short-circuit defects between adjacent leads 120. Furthermore, since the plating film 126 covers all the surfaces of the leads 120 as well as all the surfaces of the die pad 130, the strength of the die pad 130 is improved and deformation of the die pad 130 can also be suppressed.

[0052] Next, a process for manufacturing a semiconductor device by mounting a semiconductor element on the lead frame 100 will be described with a specific example with reference to Fig. 23. Fig. 23 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment.

[0053] First, a semiconductor element is mounted on the die pad 130 of the lead frame 100 (step S121). Specifically, for example, as shown in Fig. 24, a semiconductor element 240 is bonded to an upper surface 130a of the die pad 130 by a bonding material 230 such as solder or die attach paste. Fig. 24 is a diagram showing a specific example of the semiconductor element mounting process.

[0054] When the semiconductor element 240 is bonded to the die pad 130, the semiconductor element 240 and the leads 120 are connected by wire bonding (step S122). That is, for example, as shown in Fig. 25, the electrodes of the semiconductor element 240 are electrically connected to the plating layer 125 on the upper surface 120a of the leads 120 by wires 250. Fig. 25 is a diagram showing a specific example of the wire bonding connection step.

[0055] Then, molding is performed to seal the semiconductor element 240 mounted on the lead frame 100 with sealing resin (step S123). Specifically, the lead frame 100 on which the semiconductor element 240 is mounted is accommodated in a mold, and the fluidized sealing resin is poured into the mold. Then, the sealing resin is heated to a predetermined temperature and hardened, so that the sealing resin 260 fills the space around the semiconductor element 240 as shown in FIG. 26, for example, and the semiconductor element 240 mounted on the lead frame 100 is sealed. At this time, since the surface of the plating film 126 covering the entire surface of the lead 120 is a roughened surface, the sealing resin 260 fills the roughened portion of the plating film 126, and the adhesion between the lead 120 and the sealing resin 260 via the plating film 126 can be improved by the anchor effect. This can reduce the possibility that the lead 120 will peel off from the sealing resin 260. FIG. 26 is a diagram showing a specific example of the molding process.

[0056] At the stage where the semiconductor element 240 mounted on the lead frame 100 is sealed with the sealing resin 260, the lower surface of the frame body 110, the lower surface of the second portion 122 of the lead 120, and the lower surface of the die pad 130 are exposed from the lower surface of the sealing resin 260. Thus, plating is performed to cover these exposed surfaces (step S124). Specifically, as shown in FIG. 27, for example, electrolytic plating of tin, solder, or the like is performed to form an exterior plating layer 270 on the lower surface of the frame body 110, the lower surface of the second portion 122 of the lead 120, and the lower surface of the die pad 130 that are exposed from the sealing resin 260. FIG. 27 is a diagram showing a specific example of the plating process.

[0057] When the exterior plating layer 270 is formed on the exposed surface of the lead frame 100 exposed from the sealing resin 260, the sealing resin 260 is cut and the leads 120 and the connecting portion 140 are cut from the frame 110 at the dashed line portion shown in FIG. 27 (step S125). As a result, the frame 110 is separated and removed from the lead frame 100, and a semiconductor device having the leads 120, the die pad 130, the semiconductor element 240, and the sealing resin 260 is completed as shown in FIG. 28, for example. FIG. 28 is a diagram showing the structure of the semiconductor device. In the semiconductor device shown in FIG. 28, the lower surface of the second portion 122 of the lead 120 is exposed from the lower surface of the sealing resin 260 and becomes a terminal connected to the outside. Also, the lower surface of the die pad 130 is exposed from the lower surface of the sealing resin 260.

[0058] As described above, the lead frame according to the embodiment (for example, lead frame 100) has leads (for example, leads 120), a connection portion (for example, plating layer 125), and a plating film (for example, plating film 126). The leads have an upper surface (for example, upper surface 120a) and a lower surface (for example, lower surface 120b), and the width of the upper surface is greater than the width of the lower surface. The connection portion is a connection portion provided on the upper surface for connecting to a semiconductor element. The plating film covers the surface of the leads. This makes it possible to suppress deformation of the leads while avoiding the occurrence of short circuits.

[0059] (Modification) In the lead frame 100 according to the above embodiment, an example in which a semiconductor element is mounted on the upper surface 130a of the die pad 130 has been shown, but if a semiconductor element can be mounted on the upper surface 120a of the lead 120, the die pad 130 may be omitted. That is, as shown in FIG. 29, for example, the lead frame 100 according to the modified example does not have the die pad 130, and the upper surface 120a of the lead 120 serves as a mounting surface for a semiconductor element and a connection surface with the semiconductor element. FIG. 29 is a cross-sectional view of the lead frame 100 according to the modified example of the embodiment. In the lead frame 100 according to the modified example, the plating film 126 also covers all surfaces of the lead 120, including the upper surface 120a, the lower surface 120b, and the side surface 120c.

[0060] Fig. 30 is a diagram showing the structure of a semiconductor device manufactured using the lead frame 100 shown in Fig. 29. In the semiconductor device shown in Fig. 30, a semiconductor element 240 is flip-chip connected to an upper surface 120a of a lead 120. That is, an electrode of the semiconductor element 240 is electrically connected to a plating layer 125 on an upper surface 120a of the lead 120 by a solder 245. [Explanation of symbols]

[0061] 100 Leadframe 110 Frame 120 Leads 120a top 120b Bottom side 120c side 121 Part 1 122 Part 2 123 Part 3 130 Die pad 130a top side 140 Connection part 240 Semiconductor Devices 260 Sealing resin

Claims

1. a lead having an upper surface and a lower surface, the width of the upper surface being greater than the width of the lower surface; a connection portion for connecting to a semiconductor element provided on the upper surface; A plating film that covers the surface of the lead; A lead frame comprising:

2. The plating film is The thickness of the portion covering the lower surface is smaller than the thickness of the portion covering the upper surface.

2. The lead frame according to claim 1.

3. The plating film is The thickness of the portion covering the upper surface is smaller than the thickness of the portion covering the lower surface.

2. The lead frame according to claim 1.

4. The lead is a side surface between the upper surface and the lower surface; The plating film is The thickness of the portion covering the side surface is smaller than the thickness of the portion covering the upper surface or the lower surface.

2. The lead frame according to claim 1.

5. The surface of the plating film is a roughened surface, The surface roughness of the plating film is greater than the surface roughness of the lead.

2. The lead frame according to claim 1.

6. The plating film is The surface roughness of the portion covering the upper surface is greater than the surface roughness of the portion covering the lower surface.

2. The lead frame according to claim 1.

7. The connection portion is a plating layer formed on the plating film covering the upper surface and made of a different material from the plating film; 2. The lead frame according to claim 1.

8. The lead is In a cross section perpendicular to the longitudinal direction of the lead, the lead has a tapered shape in which the width of the upper surface is greater than the width of the lower surface.

2. The lead frame according to claim 1.

9. A die pad having a mounting surface for the semiconductor element and The plating film is The surface of the die pad is coated.

2. The lead frame according to claim 1.

10. A lead frame; A semiconductor element mounted on the lead frame; A sealing resin that seals the semiconductor element; having The lead frame is a lead having an upper surface and a lower surface, the width of the upper surface being greater than the width of the lower surface; a connection portion for connecting to the semiconductor element, the connection portion being provided on the upper surface; A plating film that covers the surface of the lead; A semiconductor device comprising:

11. forming a lead from a metal plate having an upper surface and a lower surface, the width of the upper surface being greater than the width of the lower surface; forming a plating film covering a surface of the lead; 2. A method for manufacturing a lead frame comprising the steps of:

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