Semiconductor device

Abstract

To provide a semiconductor device that can easily dissipate heat generated from a semiconductor chip mounted on a substrate.SOLUTION: A semiconductor device 10 includes: a first substrate 11 which has a first mounting surface 111 which is a surface intersecting the thickness direction DT; a first semiconductor chip 31 which is mounted on the first substrate by being connected to the first mounting surface 111; a case 60 which stores the first substrate 11 and the first semiconductor chip 31; and a heat transfer part 70 which is connected to the first substrate 11 and the case 60, and conducts heat generated from the first semiconductor chip 31 through the first substrate 11 to the case 60 to dissipate heat.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Conventionally, as described in Patent Document 1, a semiconductor package that reduces heat transfer from a lower chip to an upper chip in a stacked semiconductor package is known. This semiconductor package has a first circuit board, a first semiconductor package, a second circuit board, a second semiconductor package, a first sealing resin, a second sealing resin, a conductive layer, and a thermal via. In the first semiconductor package, a first semiconductor chip is mounted on the first circuit board. In the second semiconductor package, a second semiconductor chip is mounted on the second circuit board and stacked on the first semiconductor package. The first sealing resin seals the first semiconductor chip. The second sealing resin seals the second semiconductor. The conductive layer is arranged in contact with the first sealing resin. The thermal via is connected to the conductive layer and arranged on the first circuit board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-195368 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor package described in Patent Document 1, a conductive layer and a thermal via are formed, but the first semiconductor chip is covered with a first sealing resin and a first circuit board. In addition, the thermal resistance of the first sealing resin and the first circuit board is relatively large. Therefore, the heat generated by the operation of the first semiconductor chip is difficult to dissipate. Therefore, the junction temperature of the first semiconductor chip is easily increased, and the first semiconductor chip is easily deteriorated. Similarly, the second semiconductor chip is covered with a second sealing resin and a second circuit board. In addition, the thermal resistance of the second sealing resin and the second circuit board is relatively large. Therefore, the heat generated by the operation of the second semiconductor chip is difficult to dissipate. Therefore, the junction temperature of the second semiconductor chip is easily increased, and the second semiconductor chip is easily deteriorated.

[0005] An object of the present disclosure is to provide a semiconductor device that facilitates dissipation of heat generated by a semiconductor chip mounted on a substrate. [Means for solving the problem]

[0006] The invention described in claim 1 is a semiconductor device comprising: a substrate (11) having a mounting surface (111) that is a surface that intersects with a thickness direction (DT); a semiconductor chip (31) mounted on the substrate by being connected to the mounting surface; a case (60) that houses the substrate and the semiconductor chip; and a heat transfer section (70) that is connected to the substrate and the case and that transfers heat transferred from the semiconductor chip through the substrate to the case and dissipates the heat.

[0007] As a result, heat generated in the semiconductor chip is more easily transferred to the case than in a case where no heat transfer portion is formed, and heat generated in the semiconductor chip is more easily dissipated.

[0008] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view showing a path of heat generated in a first semiconductor chip of the semiconductor device. [Diagram 3] FIG. 4 is a schematic cross-sectional view showing a path of heat generated in a second semiconductor chip of the semiconductor device. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Diagram 5] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 6] FIG. 13 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals, and the description thereof will be omitted.

[0011] (First embodiment) In the semiconductor device of this embodiment, heat generated by the semiconductor chip mounted on the substrate is easily dissipated.

[0012] 1, the semiconductor device 10 includes a first substrate 11, a first chip first connection portion 21, a first semiconductor chip 31, and a first chip second connection portion 41. The semiconductor device 10 also includes a second chip first connection portion 22, a second semiconductor chip 32, a second chip second connection portion 42, a second substrate 12, electronic components 50, inter-substrate wiring 55, a case 60, and a heat transfer portion 70.

[0013] The first substrate 11 is a printed circuit board. The thickness of the first substrate 11 is, for example, 0.4 mm. Furthermore, the first substrate 11 has a first mounting surface 111, a second mounting surface 112, and a first substrate side surface 113. In the following, the thickness direction of the first substrate 11 will be simply referred to as a thickness direction DT.

[0014] The first mounting surface 111 is a surface perpendicular to the thickness direction DT. The second mounting surface 112 is a surface perpendicular to the thickness direction DT and is the surface opposite to the first mounting surface 111. The first board side surface 113 is connected to the first mounting surface 111 and the second mounting surface 112 and is a surface that intersects with the first mounting surface 111 and the second mounting surface 112.

[0015] The first chip first connection portion 21 is formed of a pad, solder, TIM, etc. The first chip first connection portion 21 is connected to the first mounting surface 111 in the thickness direction DT. The length of the first chip first connection portion 21 in the thickness direction DT is, for example, 0.3 mm. TIM is an abbreviation for Thermal Interface Material.

[0016] The first semiconductor chip 31 is a packaged semiconductor integrated circuit. The length of the first semiconductor chip 31 in the thickness direction DT is, for example, 0.7 mm. The length of the first semiconductor chip 31 in the direction perpendicular to the thickness direction DT is, for example, 10 mm. The first semiconductor chip 31 is connected to the side of the first chip first connection portion 21 opposite to the first substrate 11 in the thickness direction DT. Therefore, the first semiconductor chip 31 is connected to the first mounting surface 111 via the first chip first connection portion 21. Thus, the first semiconductor chip 31 is mounted on the first substrate 11. The first semiconductor chip 31 may be mounted face-down or face-up. The first semiconductor chip 31 is preferably mounted face-down rather than face-up.

[0017] The first chip second connection portion 41 is formed of TIM or the like. Furthermore, the first chip second connection portion 41 is connected to the side of the first semiconductor chip 31 opposite to the first chip first connection portion 21 in the thickness direction DT. Furthermore, the length of the first chip second connection portion 41 in the thickness direction DT is, for example, 1.0 mm.

[0018] The first connecting portion 22 for the second chip is formed of a pad, a solder, a TIM, etc. Furthermore, the first connecting portion 22 for the second chip is connected to the second mounting surface 112 in the thickness direction DT. Moreover, the length of the first connecting portion 22 for the second chip in the thickness direction DT is set to, for example, 0.3 mm.

[0019] The second semiconductor chip 32 is a packaged semiconductor integrated circuit, similar to the first semiconductor chip 31. Furthermore, the length of the second semiconductor chip 32 in the thickness direction DT is, for example, 0.7 mm. Furthermore, the length of the second semiconductor chip 32 in the direction perpendicular to the thickness direction DT is, for example, 10 mm. Furthermore, the second semiconductor chip 32 is connected to the side of the first connection part 22 for the second chip opposite to the first substrate 11 in the thickness direction DT. Therefore, the second semiconductor chip 32 is connected to the second mounting surface 112 via the first connection part 22 for the second chip. Thereby, the second semiconductor chip 32 is mounted on the side of the first substrate 11 opposite to the first semiconductor chip 31. The second semiconductor chip 32 may be mounted face-down or face-up. Furthermore, the second semiconductor chip 32 is preferably mounted face-up rather than face-down.

[0020] The second chip second connection portion 42 is formed of TIM or the like. Furthermore, the second chip second connection portion 42 is connected to the side of the second semiconductor chip 32 opposite to the second chip first connection portion 22 in the thickness direction DT. Furthermore, the length of the second chip second connection portion 42 in the thickness direction DT is, for example, 1.0 mm.

[0021] The second substrate 12 is a printed circuit board. The length of the second substrate 12 in the thickness direction DT is, for example, 1.6 mm, which is longer than the length of the first substrate 11 in the thickness direction DT. Furthermore, the second substrate 12 has a third mounting surface 121, a fourth mounting surface 122, and a second substrate side surface 123.

[0022] The third mounting surface 121 is a surface orthogonal to the thickness direction DT. The third mounting surface 121 is connected to the side of the second chip second connection portion 42 opposite to the second semiconductor chip 32 in the thickness direction DT. The fourth mounting surface 122 is a surface orthogonal to the thickness direction DT and is the surface opposite to the third mounting surface 121. The second substrate side surface 123 is connected to the third mounting surface 121 and the fourth mounting surface 122, and is a surface that intersects with the third mounting surface 121 and the fourth mounting surface 122.

[0023] A plurality of electronic components 50 are mounted on second substrate 12, and are connected to third mounting surface 121 and fourth mounting surface 122. For example, electronic components 50 are components that constitute an ECU. ECU is an abbreviation for Electronic Control Unit.

[0024] The inter-board wiring 55 is made of a metal such as copper and extends in the thickness direction DT. As a result, the inter-board wiring 55 is connected to the second mounting surface 112 and the third mounting surface 121 in the thickness direction DT. For this reason, communication between the first semiconductor chip 31 and the second substrate 12 is performed via the inter-board wiring 55, the first substrate 11, and the first chip first connecting portion 21. Therefore, the communication between the first semiconductor chip 31 and the second substrate 12 has fewer relay parts than the communication performed via the second chip second connecting portion 42, the second semiconductor chip 32, the second chip first connecting portion 22, the first substrate 11, and the first chip first connecting portion 21. Therefore, the communication delay time between the first semiconductor chip 31 and the second substrate 12 is relatively short.

[0025] The case 60 is formed in a hollow or cylindrical shape from a metal having a relatively high thermal conductivity, such as aluminum or copper. As a result, the case 60 accommodates the first substrate 11, the first chip first connection portion 21, the first semiconductor chip 31, and the first chip second connection portion 41. Furthermore, the case 60 accommodates the second chip first connection portion 22, the second semiconductor chip 32, the second chip second connection portion 42, the second substrate 12, the electronic components 50, the inter-substrate wiring 55, and a heat transfer portion 70 described below.

[0026] Here, the distance from the first mounting surface 111 to the case 60 in the thickness direction DT is defined as a first distance L1. The distance from the first board side surface 113 to the case 60 in a direction perpendicular to the thickness direction DT is defined as a second distance L2.

[0027] The first distance L1 is shorter than the second distance L2, i.e., L1 <L2とされている。

[0028] Moreover, here, the case 60 is connected to the side of the first chip second connecting portion 41 opposite to the first semiconductor chip 31 in the thickness direction DT. Therefore, the case 60 is connected to the first semiconductor chip 31 via the first chip second connecting portion 41. Furthermore, the case 60 is connected to the second substrate side surface 123 in a direction perpendicular to the thickness direction DT.

[0029] The heat transfer section 70 is connected to the first substrate 11 and the case 60. As a result, the heat transfer section 70 transfers heat transferred from the first semiconductor chip 31 and the second semiconductor chip 32 via the first substrate 11 to the case 60 and dissipates the heat. Here, the heat transfer section 70 is formed in a cylindrical shape extending in the thickness direction DT. As a result, the heat transfer section 70 surrounds the first chip first connection section 21, the first semiconductor chip 31, and the first chip second connection section 41. Note that the heat transfer section 70 is not limited to being formed in a cylindrical shape, and may be formed in a columnar shape or the like.

[0030] Further, the heat transfer section 70 has an insulating section 701 , a metal section 702 and a heat dissipation connection section 703 .

[0031] The insulating section 701 has electrical insulation properties because it is an insulating sheet or the like using a resin or the like as a base material. The insulating section 701 is also connected to the first mounting surface 111. This prevents electrical conduction between the first substrate 11 and the heat transfer section 70.

[0032] The metal portion 702 is formed of, for example, copper. Furthermore, the metal portion 702 is connected to the insulating portion 701 on the side opposite to the first substrate 11 in the thickness direction DT. Moreover, the metal portion 702 extends from the boundary with the insulating portion 701 in the thickness direction DT.

[0033] The heat dissipation connection part 703 is formed of, for example, TIM or the like. Furthermore, the heat dissipation connection part 703 is connected to the metal part 702 on the opposite side to the insulating part 701 in the thickness direction DT. Furthermore, the heat dissipation connection part 703 extends from the boundary with the metal part 702 in the thickness direction DT. As a result, the heat dissipation connection part 703 is connected to the case 60 in the thickness direction DT. Therefore, the heat transfer part 70 extends from the first mounting surface 111 in the thickness direction DT, and is thereby connected to the case 60 in the thickness direction DT.

[0034] The semiconductor device 10 of the first embodiment is configured as described above. Next, dissipation of heat generated in the first semiconductor chip 31 and the second semiconductor chip 32 by the semiconductor device 10 will be described.

[0035] For example, the first semiconductor chip 31 generates heat by being driven. At this time, the heat generated in the first semiconductor chip 31 is conducted to the case 60 via the second connection part for the first chip 41 as shown in FIG. 2. Furthermore, the heat generated in the first semiconductor chip 31 is conducted to the case 60 via the first connection part for the first chip 21, the first substrate 11, the first connection part for the second chip 22, the second semiconductor chip 32, the second connection part for the second chip 42, and the second substrate 12. Moreover, the heat generated in the first semiconductor chip 31 is conducted to the case 60 via the first connection part for the first chip 21, the first substrate 11, and the heat transfer part 70. Then, the heat conducted to the case 60 by these is dissipated from the case 60. In FIG. 2, the path of the heat generated in the first semiconductor chip 31 is typically shown by white arrows.

[0036] Here, the thermal resistance when the heat generated in the first semiconductor chip 31 is conducted to the case 60 via the second connection portion for first chip 41 is R1_1. The thermal resistance when the heat generated in the first semiconductor chip 31 is conducted to the first substrate 11 via the first connection portion for first chip 21 is R1_2. The thermal resistance when the heat is conducted from the first substrate 11 to the case 60 via the first connection portion for second chip 22, the second semiconductor chip 32, the second connection portion for second chip 42, and the second substrate 12 is R1_3. The thermal resistance when the heat is conducted from the first substrate 11 to the case 60 via the heat transfer portion 70 is R1_4. The combined resistance of these is Rc_1.

[0037] R1_1 is adjusted by the size and material of the first chip second connecting portion 41. R1_2 is adjusted by the size and material of the first chip first connecting portion 21. R1_3 is adjusted by the sizes and materials of the first substrate 11, the second chip first connecting portion 22, the second semiconductor chip 32, the second chip second connecting portion 42, and the second substrate 12. R1_4 is adjusted by the sizes and materials of the first substrate 11 and the heat transfer portion 70.

[0038] Rc_1 is expressed by the following relational expression (1) using R1_1, R1_2, R1_3, and R1_4. For example, R1_1 is set to 3.38 K / W. R1_2 is set to 0.11 K / W. R1_3 is set to 298 K / W. R1_4 is set to 41.12 K / W. In this case, Rc_1 is 3.09 K / W. Furthermore, Rc_1 in the case where the heat transfer section 70 is not formed is 3.34 K / W. Therefore, in the semiconductor device 10, the combined resistance related to the heat generated in the first semiconductor chip 31 is reduced by 7.49% compared to the case where the heat transfer section 70 is not formed. Therefore, the heat transfer section 70 makes it easier for the heat generated in the first semiconductor chip 31 to be transferred to the case 60.

[0039]

number

[0040] Similarly to the first semiconductor chip 31, the second semiconductor chip 32 generates heat when driven. At this time, the heat generated in the second semiconductor chip 32 is conducted to the case 60 via the second chip second connection section 42 and the second substrate 12 as shown in FIG. 3. Furthermore, the heat generated in the second semiconductor chip 32 is conducted to the case 60 via the second chip first connection section 22, the first substrate 11, the first chip first connection section 21, the first semiconductor chip 31, and the first chip second connection section 41. Furthermore, the heat generated in the second semiconductor chip 32 is conducted to the case 60 via the second chip first connection section 22, the first substrate 11, and the heat transfer section 70. Then, the heat conducted to the case 60 by these is dissipated from the case 60. In FIG. 3, the path of the heat generated in the second semiconductor chip 32 is typically indicated by white arrows.

[0041] Furthermore, here, the thermal resistance when the heat generated in the second semiconductor chip 32 is conducted to the case 60 via the second chip second connection portion 42 and the second substrate 12 is R2_1. The thermal resistance when the heat generated in the second semiconductor chip 32 is conducted to the first substrate 11 via the second chip first connection portion 22 is R2_2. The thermal resistance when the heat is conducted from the first substrate 11 to the case 60 via the first chip first connection portion 21, the first semiconductor chip 31, and the first chip second connection portion 41 is R2_3. The thermal resistance when the heat is conducted from the first substrate 11 to the case 60 via the heat transfer portion 70 is R2_4. The combined resistance of these is Rc_2.

[0042] R2_1 is adjusted by the size and material of the second chip second connecting portion 42 and the second substrate 12. R2_2 is adjusted by the size and material of the second chip first connecting portion 22. R2_3 is adjusted by the size and material of the first substrate 11, the first chip first connecting portion 21, the first semiconductor chip 31, and the first chip second connecting portion 41. R2_4 is adjusted by the size and material of the first substrate 11 and the heat transfer portion 70.

[0043] Rc_2 is expressed by the following relational expression (2) using R2_1, R2_2, R2_3, and R2_4. For example, R2_1 is set to 291 K / W. R2_2 is set to 0.11 K / W. R2_3 is set to 3.49 K / W. R2_4 is set to 41.12 K / W. In this case, Rc_2 is 3.29 K / W. Furthermore, Rc_2 in the case where the heat transfer section 70 is not formed is 3.55 K / W. Therefore, in the semiconductor device 10, the combined resistance related to the heat generated in the second semiconductor chip 32 is reduced by 7.50% compared to the case where the heat transfer section 70 is not formed. Therefore, the heat transfer section 70 makes it easier for the heat generated in the second semiconductor chip 32 to be transferred to the case 60.

[0044]

number

[0045] As described above, in semiconductor device 10, heat generated in first semiconductor chip 31 and second semiconductor chip 32 is dissipated. Next, it will be described how heat generated by the semiconductor chips mounted on the substrate is easily dissipated in semiconductor device 10.

[0046] Here, in the semiconductor package described in Patent Document 1, a conductive layer and a thermal via are formed, but the first semiconductor chip is covered with a first sealing resin and a first circuit board. In addition, the thermal resistance of the first sealing resin and the first circuit board is relatively large. Therefore, the heat generated by the operation of the first semiconductor chip is difficult to dissipate. Furthermore, the second semiconductor chip is covered with a second sealing resin and a second circuit board. In addition, the thermal resistance of the second sealing resin and the second circuit board is relatively large. Therefore, the heat generated by the operation of the second semiconductor chip is difficult to dissipate.

[0047] In addition, in the electronic device described in JP 2011-129844 A, a dummy conductive connection member is formed to be connected to a via of a multilayer wiring board, but the electronic components are covered with a sealing resin and a multilayer wiring board. Furthermore, the thermal resistance of the sealing resin and the multilayer wiring board is relatively large. Therefore, the heat generated by the operation of the electronic components is difficult to dissipate.

[0048] In contrast, in the semiconductor device 10 of this embodiment, the heat transfer section 70 is connected to the first substrate 11 and the case 60, so that the heat transferred from the first semiconductor chip 31 via the first substrate 11 is conducted to the case 60 and dissipated.

[0049] As a result, compared to a case in which the heat transfer section 70 is not formed, heat generated in the first semiconductor chip 31 is more easily transferred to the case 60. Therefore, the heat generated in the first semiconductor chip 31 is more easily dissipated.

[0050] Furthermore, the semiconductor device 10 of the first embodiment also provides the following advantages.

[0051] [1] The first distance L1 is shorter than the second distance L2, that is, L1 < L2. Further, since the heat transfer portion 70 extends in the thickness direction DT from the first mounting surface 111, it is connected to the case 60 in the thickness direction DT.

[0052] As a result, compared with the case where the heat transfer portion 70 extends from the first substrate side surface 113, the length of the heat transfer portion 70 becomes shorter. For this reason, the thermal resistance of the heat transfer portion 70 becomes smaller. Therefore, the heat generated in the first semiconductor chip 31 is likely to be transmitted to the heat transfer portion 70, and thus is likely to be transmitted to the case 60. Therefore, the heat generated in the first semiconductor chip 31 is easily radiated.

[0053] [2] The semiconductor device 10 further includes a second semiconductor chip 32. The second semiconductor chip 32 is mounted on the opposite side of the first semiconductor chip 31 on the first substrate 11 by being connected to the second mounting surface 112. Further, the heat transfer portion 70 conducts the heat transmitted from the second semiconductor chip 32 through the first substrate 11 to the case 60 and dissipates it.

[0054] As a result, compared with the case where the heat transfer portion 70 is not formed, the heat generated in the second semiconductor chip 32 is likely to be transmitted to the case 60. For this reason, the heat generated in the second semiconductor chip 32 is easily radiated.

[0055] [3] Here, the thermal resistances of the first substrate 11 and the second substrate 12 are relatively large. For this reason, when the second semiconductor chip 32 is disposed between the first substrate 11 and the second substrate 12, the heat generated in the second semiconductor chip 32 is difficult to be radiated.

[0056] However, due to the heat transfer portion 70, the heat transmitted from the second semiconductor chip 32 through the first substrate 11 is conducted to the case 60. For this reason, even when the second semiconductor chip 32 is disposed between the first substrate 11 and the second substrate 12, the heat generated in the second semiconductor chip 32 is easily radiated.

[0057] [4] Semiconductor device 10 further includes inter-substrate wiring 55. Inter-substrate wiring 55 is connected to first substrate 11 and second substrate 12.

[0058] As a result, communication between first semiconductor chip 31 and second substrate 12 is performed via inter-substrate wiring 55 and first substrate 11. As a result, communication delay time between first semiconductor chip 31 and second substrate 12 becomes relatively short.

[0059] [5] Case 60 is connected to first semiconductor chip 31. This makes it easier for heat generated in first semiconductor chip 31 to be transferred to case 60. This makes it easier for heat generated in first semiconductor chip 31 to be dissipated.

[0060] Second embodiment In the second embodiment, the semiconductor device 10 includes a first substrate 11, a first chip first connection portion 21, a first semiconductor chip 31, and a plurality of, for example, two, first chip second connection portions 41. The semiconductor device 10 further includes a second chip first connection portion 22, a second semiconductor chip 32, a second chip second connection portion 42, inter-substrate wiring 55, and a plurality of, for example, two, heat transfer portions 70. The rest is the same as in the first embodiment.

[0061] 4, the other first substrate 11, the first chip first connection portion 21, the first semiconductor chip 31, and the first chip second connection portion 41 are arranged on the fourth mounting surface 122 side. In addition, the other second chip first connection portion 22, the second semiconductor chip 32, the second chip second connection portion 42, the inter-substrate wiring 55, and the heat transfer portion 70 are arranged on the fourth mounting surface 122 side.

[0062] Therefore, the other first chip second connection portion 41 is connected to the fourth mounting surface 122 side of the case 60. Also, the other second chip second connection portion 42 is connected to the fourth mounting surface 122 in the thickness direction DT. Furthermore, the other inter-substrate wiring 55 is connected to the second mounting surface 112 and the fourth mounting surface 122 of the other first substrate 11 in the thickness direction DT. Also, the other heat transfer portion 70 is connected to the other first substrate 11 and the fourth mounting surface 122 side of the case 60 in the thickness direction DT.

[0063] The semiconductor device 10 of the second embodiment is configured as described above. The second embodiment also provides the same effects as the first embodiment.

[0064] Third embodiment The third embodiment differs from the first embodiment in the form of the heat transfer section 70. The rest is similar to the first embodiment.

[0065] 5, instead of being connected to the first mounting surface 111, the heat transfer section 70 is connected to the first substrate side surface 113 in a direction perpendicular to the thickness direction DT. Therefore, the insulating section 701 is connected to the first substrate side surface 113 in a direction perpendicular to the thickness direction DT. Also, the metal section 702 is connected to the insulating section 701 in a direction perpendicular to the thickness direction DT. Furthermore, the heat dissipation connection section 703 is connected to the metal section 702 and the case 60 in a direction perpendicular to the thickness direction DT. Therefore, the heat transfer section 70 extends from the first substrate side surface 113 in a direction perpendicular to the thickness direction DT, and is therefore connected to the case 60 in a direction perpendicular to the thickness direction DT.

[0066] The semiconductor device 10 of the third embodiment is configured as described above. The third embodiment also provides the same effects as the first embodiment.

[0067] (Fourth embodiment) In the fourth embodiment, the semiconductor device 10 includes a plurality of, for example, two, first chip first connecting portions 21, a first semiconductor chip 31, a first chip second connecting portion 41, a second chip first connecting portion 22, a second semiconductor chip 32, and a second chip second connecting portion 42. The rest is the same as in the first embodiment.

[0068] Specifically, as shown in FIG. 6, the first chip first connection portion 21, the first semiconductor chip 31, and the first chip second connection portion 41 are arranged in a direction perpendicular to the thickness direction DT. The second chip first connection portion 22, the second semiconductor chip 32, and the second chip second connection portion 42 are arranged in a direction perpendicular to the thickness direction DT. Here, the heat transfer portion 70 may be disposed between the first semiconductor chips 31 adjacent to each other when the heat transfer portion 70 surrounds the first semiconductor chips 31 adjacent to each other. The inter-board wiring 55 may be disposed between the second semiconductor chips 32 adjacent to each other when the inter-board wiring 55 surrounds the second semiconductor chips 32 adjacent to each other.

[0069] The semiconductor device 10 of the fourth embodiment is configured as described above. The fourth embodiment also provides the same effects as the first embodiment.

[0070] Fifth embodiment In the fifth embodiment, the semiconductor device 10 further includes a third semiconductor chip 33 and a fourth semiconductor chip 34. Other than this, it is similar to the first embodiment.

[0071] Specifically, the third semiconductor chip 33 is a packaged semiconductor integrated circuit, similar to the first semiconductor chip 31 and the second semiconductor chip 32. As shown in FIG. 7, the third semiconductor chip 33 is disposed between the first chip first connection portion 21 and the first semiconductor chip 31. Furthermore, the third semiconductor chip 33 is connected to the first chip first connection portion 21 in the thickness direction DT. Furthermore, the third semiconductor chip 33 is connected to the first semiconductor chip 31 in the thickness direction DT by three-dimensional mounting. The third semiconductor chip 33 may be disposed between the first semiconductor chip 31 and the first chip second connection portion 41.

[0072] The fourth semiconductor chip 34 is a packaged semiconductor integrated circuit, similar to the first semiconductor chip 31, the second semiconductor chip 32, and the third semiconductor chip 33. Furthermore, the fourth semiconductor chip 34 is disposed between the second chip first connecting portion 22 and the second semiconductor chip 32. Furthermore, the fourth semiconductor chip 34 is connected to the second chip first connecting portion 22 in the thickness direction DT. Furthermore, the fourth semiconductor chip 34 is connected to the second semiconductor chip 32 in the thickness direction DT by three-dimensional mounting. Note that the fourth semiconductor chip 34 may be disposed between the second semiconductor chip 32 and the second chip second connecting portion 42.

[0073] The semiconductor device 10 of the fifth embodiment is configured as described above. The fifth embodiment also provides the same effects as the first embodiment.

[0074] (Other embodiments) The present disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. Furthermore, in each of the above-described embodiments, it goes without saying that the elements constituting the embodiments are not necessarily essential, except in cases where they are particularly clearly stated as essential or where they are clearly considered essential in principle.

[0075] In each of the above embodiments, the first mounting surface 111, the second mounting surface 112, the third mounting surface 121, and the fourth mounting surface 122 are surfaces that are perpendicular to the thickness direction DT. In contrast, the term "perpendicular" includes the manufacturing error range. In addition, the first mounting surface 111, the second mounting surface 112, the third mounting surface 121, and the fourth mounting surface 122 may be surfaces that intersect with the thickness direction DT.

[0076] In each of the above embodiments, the semiconductor device 10 includes the first semiconductor chip 31 and the second semiconductor chip 32, but the semiconductor device 10 may include only the first semiconductor chip 31. The semiconductor device 10 may include only the second semiconductor chip 32.

[0077] In each of the above embodiments, inter-board wiring 55 is used for communication between first semiconductor chip 31 and second substrate 12. In contrast, inter-board wiring 55 may be used as a conduction path for heat generated from first semiconductor chip 31 and second semiconductor chip 32, in addition to the above communication. [Explanation of symbols]

[0078] 10 Semiconductor device 11 First board 12 Second board 31 First semiconductor chip 32 Second semiconductor chip 55 Board-to-board wiring 60 cases 70 Heat transfer section 111 First mounting surface 112 Second mounting surface

Claims

1. A substrate (11) having a mounting surface (111) that is a surface intersecting a thickness direction (DT); a semiconductor chip (31) mounted on the substrate by being connected to the mounting surface; a case (60) housing the substrate and the semiconductor chip; a heat transfer section (70) connected to the substrate and the case, which transfers heat transferred from the semiconductor chip via the substrate to the case and dissipates the heat; A semiconductor device comprising:

2. the substrate has a side surface (113) that is connected to the mounting surface and intersects with the mounting surface, the side surface facing the case in a direction perpendicular to the thickness direction, a distance (L1) from the mounting surface to the case in the thickness direction is shorter than a distance (L2) from the side surface to the case in a direction perpendicular to the thickness direction, The semiconductor device according to claim 1 , wherein the heat transfer portion extends from the mounting surface in the thickness direction, and is thereby connected to the case in the thickness direction.

3. The mounting surface is a first mounting surface, The semiconductor chip is a first semiconductor chip, The substrate has a second mounting surface (112) that is the surface opposite to the first mounting surface, The semiconductor device further includes a second semiconductor chip (32) that is connected to the second mounting surface and thereby mounted on the substrate on the opposite side to the first semiconductor chip, The semiconductor device according to claim 1 , wherein the heat transfer portion transfers heat transferred from the second semiconductor chip through the substrate to the case and dissipates the heat.

4. The substrate is a first substrate, The semiconductor device further includes a second substrate (12) connected to the second semiconductor chip on the opposite side to the first substrate, The semiconductor device according to claim 3 , wherein the second semiconductor chip is disposed between the first substrate and the second substrate in the thickness direction.

5. The semiconductor device according to claim 4 , further comprising an inter-substrate wiring (55) connected to the first substrate and the second substrate.

6. The semiconductor device according to claim 1 , wherein the case is connected to the semiconductor chip.

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