Optical semiconductor element and manufacturing method thereof

Abstract

To improve the characteristics of an optical semiconductor element.SOLUTION: An optical semiconductor element according to the present invention includes a first active layer having an emission and reception wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission and reception wavelength of a second wavelength, and the first and second active layers include Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an optical semiconductor device and a method for manufacturing the same. [Background technology]

[0002] There is known an optical semiconductor device having two or more vertically stacked active layers with a tunnel junction layer sandwiched between them. Such an optical semiconductor device is used as a light emitting device for the purpose of improving the optical output when the wavelengths of the stacked active layers are close, and emitting different wavelengths when the wavelengths of the stacked active layers are separated. Similarly, it is also used as a light receiving device for the purpose of improving the light receiving efficiency when the wavelengths of the stacked active layers are close, and having sensitivity to different wavelength bands when the wavelengths of the stacked active layers are separated.

[0003] In such optical semiconductor devices, multiple active layers are stacked vertically, so that the active layers are connected in series. In light-emitting devices, when a forward current flows through them, each of the multiple active layers can emit light. In this case, the active layers are generally pn junctions.

[0004] The tunnel junction layer is formed from a highly doped p-type semiconductor layer and an n-type semiconductor layer, and when a forward voltage is applied to the active layer, a reverse voltage is applied. Normally, when the junctions are made in the order of p-type, n-type, p-type (or n-type, p-type, n-type), a thyristor is formed and no current flows, but because the tunnel junction layer sandwiched between the active layers is highly doped, a tunnel effect occurs within the tunnel junction layer, allowing current to flow. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2009-522755 [Patent Document 2] Patent Publication No. 2018-201009 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 describes that only Al, Ga, In, and P are preferable as basic constituent materials of the crystal lattice that constitutes the optical semiconductor element, but these materials alone cannot be expected to emit light with a long wavelength of more than 3000 nm. Also, as described in Patent Document 2, conventionally, the concentration of n-type dopant is 1.0×10 19 atoms / cm 3 A high concentration of dopant or more is considered preferable, however, if an n-type semiconductor layer and a p-type semiconductor layer containing a high concentration of dopant are present between vertically stacked active layers, the dopant may diffuse into the active layer, which may result in reduced reliability or increased leakage current.

[0007] The present invention has been made in view of the above circumstances, and has an object to improve the characteristics of optical semiconductor elements. [Means for solving the problem]

[0008] The present inventors have intensively studied ways to solve the above problems, and have found an optical semiconductor device in which the first and second active layers contain Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer, and have completed the present invention. It has been found that the tunnel junction layer of the present invention exhibits a tunnel effect at a dopant concentration lower than that previously considered necessary. That is, the gist of the present invention is as follows.

[0009] (1) An optical semiconductor device having a first active layer having an emission and reception wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission and reception wavelength of a second wavelength, the first active layer and the second active layer contain Sb; The tunnel junction layer includes a p-type InAs layer and an n-type InAs layer. Optical semiconductor element.

[0010] (2) The tunnel junction layer has a dopant concentration of 1.0×10 18 atoms / cm 3 Above 1.0×10 19 atoms / cm 3 The optical semiconductor element according to (1) above,

[0011] (3) the first active layer and the second active layer have a quantum well structure; The optical semiconductor element according to (1) or (2), wherein the first wavelength and the second wavelength are 3000 nm or longer.

[0012] (4) The optical semiconductor element according to any one of (1) to (3), wherein the first wavelength and the second wavelength are the same as each other.

[0013] (5) the p-type InAs layer is located on the first active layer side of the tunnel junction layer, a p-type electron blocking layer between the first active layer and the tunnel junction layer; The optical semiconductor element according to any one of (1) to (4) above, wherein the thickness between the first active layer and the tunnel junction layer is 100 nm or less.

[0014] (6) the n-type InAs layer is located on the second active layer side of the tunnel junction layer, a spacer layer between the tunnel junction layer and the second active layer; The optical semiconductor element according to any one of (1) to (5) above, wherein the thickness between the tunnel junction layer and the second active layer is 100 nm or less.

[0015] (7) forming a first active layer having a first wavelength for receiving and emitting light on the substrate; forming a tunnel junction layer on the first active layer; forming a second active layer having a second wavelength for receiving and emitting light on the tunnel junction layer; Including, the first active layer and the second active layer contain Sb; The step of forming the tunnel junction layer includes the steps of forming an n-type InAs layer and forming a p-type InAs layer on the n-type InAs layer. A method for manufacturing an optical semiconductor element.

[0016] (8) The tunnel junction layer has a dopant concentration of 1.0×10 18 atoms / cm 3 Above 1.0×10 19 atoms / cm 3 The method for producing an optical semiconductor element according to (7) above, Effect of the Invention

[0017] It is possible to provide an optical semiconductor element with improved characteristics and a method for manufacturing the same. For example, when used as a light-emitting element, it is possible to provide an optical semiconductor element with high light-emitting output and forward voltage and a central wavelength of 3000 nm or more, and a method for manufacturing the same. Furthermore, since the leakage current is reduced in the light-emitting element, it is also possible to provide an optical semiconductor element with low dark current and high shunt resistance when used as a light-receiving element, and a method for manufacturing the same. [Brief description of the drawings]

[0018] [Figure 1] 1 is a schematic cross-sectional view illustrating a first embodiment of an optical semiconductor element according to the present invention. [Diagram 2] 4 is a schematic cross-sectional view illustrating a second embodiment of the optical semiconductor element according to the present invention. FIG. [Diagram 3] 5A to 5C are schematic cross-sectional views illustrating an example of a manufacturing method for the second embodiment of the optical semiconductor element according to the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating an example of a manufacturing method subsequent to FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view illustrating an example of a manufacturing method subsequent to FIG. 4. [Figure 6] 5 is a schematic cross-sectional view illustrating a third embodiment of an optical semiconductor element according to the present invention. FIG. [Figure 7]It is a graph showing the result of measuring the diffusion state of Te ions in Example 1 by secondary ion mass spectrometry (SIMS). [Figure 8] It is a graph showing the result of measuring the diffusion state of Zn ions in Example 1 by secondary ion mass spectrometry (SIMS).

Embodiments for Carrying Out the Invention

[0019] Prior to the description of the embodiments according to the present invention, the following points will be explained in advance.

[0020] The active layer containing Sb in the present embodiment means a compound represented as InAs x Sb 1-x (0 < x < 1). When expressed as an InAs layer, an AlInAs layer, or an InAsP layer, it means that Sb is not included in the composition ratio, but it is only necessary not to use an Sb source gas during the growth of the layer, and it is allowed for Sb to be included as an inevitable dopant element due to the residual Sb in the chamber or diffusion from an adjacent Sb-containing layer. Also, when simply expressed as "AlInAsSb" without specifying the composition ratio in this specification, it means an arbitrary compound in which the chemical composition ratio of group III elements (total of Al and In) to group V elements (total of As and Sb) is 1:1, and the ratio of Al and In as group III elements and the ratio of As and Sb as group V elements are each indefinite. In this case, it includes the case where either one of Al and In is not included in the group III elements, and also includes the case where either one of As and Sb is not included in the group V elements. The component composition ratios of each III-V group element of AlInAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, etc.

[0021] Also, in this specification, the case where specific dopants such as Zn, Te, and Si are not intentionally added is referred to as "undoped". An undoped layer may have inevitable dopant contamination during the manufacturing process. Also, the values of dopant concentrations such as Zn, Te, and Si are based on SIMS analysis.

[0022] The III-V compound semiconductor in this embodiment contains at least one of Al, Ga, and In as a group III element, and at least P, As, and Sb as a group V element.

[0023] The thickness of each layer formed by epitaxial growth can be calculated from cross-sectional observation of the grown layer by SEM (scanning electron microscope) or TEM (transmission electron microscope). It is preferable to use SEM when the film thickness is 10 nm or more, and TEM when the film thickness is less than 10 nm.

[0024] In this specification, the central wavelengths of the emission wavelengths are compared for different active layers, and the emission wavelengths are described as being the same, but this is not limited thereto. The central wavelengths of the emission wavelengths may be separated or may be close to each other. When the central wavelengths are separated from each other, different roles can be given to the respective central wavelengths. In this specification, the central wavelengths of the emission wavelengths being close to each other means that the central wavelengths are positioned so that the ranges of the full width at half maximum in the emission spectrum overlap, for example, meaning that the wavelength difference is within the value of the full width at half maximum (for example, within 100 nm), and when the central wavelengths are the same or close to each other, the emission spectrum is synthesized, which is effective in improving the emission intensity. The above description was given in the case of a light-emitting element, but the same applies to the case of a light-receiving element.

[0025] An optical semiconductor device according to the present invention has a first active layer having an emitting and receiving wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emitting and receiving wavelength of a second wavelength, the first active layer and the second active layer containing Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.

[0026] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each drawing, for the sake of convenience, the aspect ratio of the substrate and each layer is shown exaggerated from the actual ratio. In addition, in the following, for III-V compound semiconductors composed of three or more elements, the composition ratio of each element may be omitted (for example, "InAsSb").

[0027] (First embodiment) With reference to Fig. 1, an example of an optical semiconductor element 100 which is a first embodiment of an optical semiconductor element according to the present invention will be described together with a manufacturing method. The optical semiconductor element 100 includes a growth substrate 105 and a semiconductor laminate 140 which is made of a plurality of semiconductor layers laminated on the growth substrate 105 and emits light when electricity is passed through it. Note that, as will be described in detail later, this semiconductor laminate 140 functions as a so-called double-stack type light-emitting diode in which a plurality of active layers made of pn junctions are stacked and a tunnel junction layer through which a current flows in the reverse direction (from the n-type layer to the p-type layer) due to the tunnel effect is sandwiched between these active layers.

[0028] The first embodiment is an embodiment of a semiconductor light emitting element in which an n-type contact layer 141, an n-type window layer 142, a first spacer layer 143, a first active layer 144, a p-type intermediate layer (a first p-type electron blocking layer 145 and a first p-type window layer 146), a tunnel junction layer 147 (a p-type tunnel junction layer 1471 and an n-type tunnel junction layer 1472), an n-type intermediate layer (a second spacer layer 148), a second active layer 149, a second p-type electron blocking layer 150, a second p-type window layer 151, and a p-type contact layer 152 are sequentially formed on a growth substrate 105, and the growth substrate is used as it is as a substrate.

[0029] <Substrate> A description will be given of a substrate applicable to the optical semiconductor element 100. The substrate used in the present invention may be any substrate having a thickness sufficient to mechanically maintain the shape of the semiconductor laminate 140 including the first active layer 144, the tunnel junction layer 147, and the second active layer 149, and may be the growth substrate 105 used for epitaxial growth when forming the semiconductor laminate 140 of the optical semiconductor element 100.

[0030] <<Substrate for growth>> As the growth substrate 105, compound substrates such as GaAs, InP, InAs, GaSb, and InSb can be used. To form an active layer containing Sb, it is ideal to use substrates of InAs, GaSb, and InSb. However, since these substrates are expensive, it is preferable to use a GaAs substrate in terms of cost. The GaAs substrate is preferably Si-doped and is an n-type substrate, and the semiconductor laminate 140 is preferably laminated on the (100) plane of the GaAs substrate. Also, the film thickness of the GaAs substrate is preferably 200 μm or more and 900 μm or less.

[0031] Also, when using a GaAs substrate or an InP substrate, it is also preferable to provide a buffer layer for relaxing the lattice mismatch between the growth substrate 105 and the n-type contact layer 141, and the buffer layer can include an InAs buffer layer grown at a low temperature. The buffer layer can be a buffer layer using a composition gradient or superlattice structure in which each composition α and β of the In α Ga 1-α As β Sb 1-β layer is changed in the range of 0 to 1.

[0032] <<n-type contact layer>> An n-type contact layer 141 made of a group III-V compound semiconductor layer may be provided on the growth substrate 105. The n-type contact layer 141 has high conductivity and is advantageous in electrode formation. The film thickness is preferably 20 nm or more and 500 nm or less. Dopants that can be used here include Si, Te, S, Ge, Sn, Se, etc. Also, the dopant concentration is preferably higher than the dopant concentration of the n-type window layer 142 described below, and is more preferably 8.0×10 18 / cm 3 or more and 3.0×10 19 / cm 3 or less.

[0033] <<n-type window layer>> An n-type window layer 142 made of a III-V compound semiconductor layer may be provided on the n-type contact layer 141, and the thickness is preferably 500 nm to 6000 nm. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se. When the growth substrate 105 and the first active layer 144 have different lattice constants, defects propagate to the first active layer 144 if the thickness of the n-type window layer 142 is thinner than 500 nm. In addition, if the thickness of the n-type window layer 142 is thinner than 500 nm, a sufficient amount of carriers is not supplied to the first active layer 144, resulting in a small light emission output, which is not preferable. On the other hand, even if the thickness of the n-type window layer 142 is thicker than 6000 nm, significant improvement in characteristics cannot be expected, and the growth time becomes long and the cost of raw materials increases, which is not preferable because of problems with productivity.

[0034] The dopant concentration is preferably lower than that of the n-type contact layer 141, and is 1.0×10 18 / cm 3 Above 8.0×10 18 / cm 3 It is preferable that:

[0035] Furthermore, the composition of n-type window layer 142 is preferably a composition that is lattice-matched with the composition of first active layer 144. The composition of n-type window layer 142 is preferably AlInAs, which has a smaller Al composition ratio (i.e., a smaller band gap) than first p-type electron block layer 145 described below, and is more preferably InAs.

[0036] <First spacer layer> A first spacer layer 143 made of an undoped III-V compound semiconductor layer may be provided on the n-type window layer 142, and the thickness of the first spacer layer 143 is preferably 1 nm or more and 100 nm or less. The first spacer layer 143 preferably has the same composition as the barrier layer of the first active layer 144 or the n-type window layer 142, and is preferably a layer that is not doped with an n-type dopant. The first spacer layer 143 reduces the amount of n-type dopant diffusing from the n-type window layer 142 to the first active layer 144.

[0037] <1st active layer> A first active layer 144 containing Sb is provided on the first spacer layer 143. The first active layer 144 is InAs which serves as a light-emitting layer x1 Sb 1-x1 layer (0 < x1 < 1). In FIG. 1, the first active layer 144 is InAs y1 P 1-y1 layer (0 < y1 < 1) and further has, and InAs x1 Sb 1-x1 layer is used as the well layer 144w of the first active layer, and InAs y1 P 1-y1 layer is used as the barrier layer 144b of the first active layer, and a quantum well structure is exemplarily illustrated. However, the first active layer 144 may be a single layer structure of InAs x1 Sb 1-x1 layer. Also, the composition other than Sb is not limited to In and As, and another III-V compound semiconductor may be used. Further, it is also preferable to adjust the composition difference between the well layer 144w of the first active layer and the barrier layer 144b of the first active layer to apply strain to the well layer. The first active layer 144 preferably has a multiple quantum well (MQW) structure as shown in FIG. 1 in order to improve the light output by suppressing crystal defects. This multiple quantum well structure can be formed by a structure in which the above well layer and barrier layer are alternately repeated. When using a multiple quantum well structure, the combination of the well layer and the barrier layer is preferably 3 or more sets and 40 or less sets. That is, including the first barrier layer, it is preferably 3.5 or more sets and 40.5 or less sets. Further, the film thickness of each well layer is preferably 5 nm or more and 40 nm or less, and the film thickness of each barrier layer is preferably 10 nm or more and 50 nm or less. Also, the first active layer 144 is preferably undoped. The first active layer 144 has a wavelength range with an emission center wavelength of 3000 nm or more. As the barrier layer, AlInAs etc. can also be used in addition to InAsP.

[0038] <p-type intermediate layer between the first active layer and the tunnel junction layer> There is a p-type intermediate layer between the first active layer and the tunnel junction layer. The film thickness between the first active layer 144 and the tunnel junction layer 147 described later is preferably 100 nm or less. And this p-type intermediate layer preferably includes a p-type electron blocking layer.

[0039] <First p-type electron blocking layer> A first p-type electron blocking layer 145 made of a III-V group compound semiconductor layer may be provided on the first active layer 144, and the thickness is preferably 5 nm to 60 nm. Dopants that can be used here include Mg, Zn, C, and Be. The p-type dopant concentration is 1.0×10 18 / cm 3 Above 5.0×10 18 / cm 3 It is preferable that the first p-type electron blocking layer 145 has a thickness of 100 nm or less. The first p-type electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. The first p-type electron blocking layer 145 also has the effect of reducing the diffusion of p-type dopants from the tunnel junction layer 147 to be described later to the first active layer 144.

[0040] The composition of the first p-type electron blocking layer 145 is Al z1 In 1-z1 As (0.05≦z1≦0.40) is preferable, and Al z1 In 1-z1 It is more preferable that the Al composition z1 is As (0.10≦z1≦0.35). By making the Al composition z1 0.05 or more, the light emission efficiency of the first p-type electron blocking layer 145 can be improved, and by making it 0.40 or less, it is possible to suppress a decrease in the light emission efficiency due to an increase in the forward voltage. In addition, it is preferable that the p-type dopant concentration of the first p-type electron blocking layer 145 is smaller than the p-type dopant concentration doped in the p-type tunnel junction layer 1471 described later.

[0041] A first p-type window layer 146 may be further provided on the first p-type electron blocking layer 145. The composition of the first p-type window layer 146 is preferably smaller in Al composition than the composition z1 of the first p-type electron blocking layer 145, and is, for example, InAs. The p-type dopant concentration is 1.0×10 18 / cm 3 Above 5.0×10 18 / cm 3 It is preferable that:

[0042] The p-type intermediate layer between the first active layer 144 and the tunnel junction layer 147 may include a layer other than the above-mentioned first p-type electron block layer 145 or the first p-type window layer 146. Even in this case, in the present invention, since the dopant concentration in the tunnel junction layer 147 can be kept low, even if the p-type dopant diffuses from the p-type tunnel junction layer 1471, the p-type dopant concentration in the p-type intermediate layer can be kept at, for example, 5.0×10 18 / cm 3 or less, and the total film thickness between the first active layer 144 and the tunnel junction layer 147 can be suppressed to 100 nm or less. By making the film thin in this manner while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire device can be reduced.

[0043] <Tunnel junction layer> A tunnel junction layer 147 consisting of a p-type tunnel junction layer 1471 and an n-type tunnel junction layer 1472 made of InAs is provided on the first p-type window layer 146. The thickness of the tunnel junction layer 147 is preferably 10 nm to 200 nm. Dopants that can be used for the p-type tunnel junction layer 1471 include Mg, Zn, C, Be, etc., and dopants that can be used for the n-type tunnel junction layer 1472 include Si, Te, S, Ge, Sn, Se, etc. The p-type tunnel junction layer 1471 faces the first active layer 144, and the n-type tunnel junction layer 1472 faces the second active layer 149. The thicknesses and dopant concentrations of the p-type tunnel junction layer 1471 and the n-type tunnel junction layer 1472 may be the same or different. Furthermore, the dopant concentrations of p-type tunnel junction layer 1471 and n-type tunnel junction layer 1472 do not need to be uniform within the layers, and may have a concentration gradient.

[0044] Normally, to form a tunnel junction, the doping rate of the semiconductor must be extremely high, and the depletion layer at the junction between the n-type and p-type semiconductor layers must be thin enough for quantum tunneling to occur. In compound semiconductors, this requires a doping rate of at least 1.0 × 10 19 / cm 3 or more (preferably 1.0×10 20 / cm 3) of dopant concentration is required. However, in the present invention, the dopant concentration is 1.0×10 18 / cm 3 or more and less than 1.0×10 19 / cm 3 Even so, tunnel junction could be realized. The tunnel junction layer preferably has a dopant concentration of 5.0×10 18 / cm 3 or more and 9.0×10 18 / cm 3 or less. Since less diffusion of dopants into the first active layer 144 and the second active layer 149 leads to improvement in characteristics such as reliability, if quantum tunneling can be caused, a lower dopant concentration in the tunnel junction layer 147 is preferable.

[0045] <<p-type tunnel junction layer>> The p-type dopant concentration in the p-type tunnel junction layer 1471 is preferably 1.0×10 18 atoms / cm 3 or more and less than 1.0×10 19 atoms / cm 3 and more preferably 9.0×10 18 atoms / cm 3 or less. The film thickness is preferably 5 nm or more and 100 nm or less.

[0046] <<n-type tunnel junction layer>> The n-type dopant concentration in the n-type tunnel junction layer 1472 is preferably 1.0×10 18 atoms / cm 3 or more and less than 1.0×10 19 atoms / cm 3 and more preferably 9.0×10 18 atoms / cm 3 or less. The film thickness is preferably 5 nm or more and 100 nm or less.

[0047] <n-type intermediate layer between the tunnel junction layer and the second active layer> There is an n-type intermediate layer between the tunnel junction layer and the second active layer. The n-type intermediate layer may be an undoped layer. The film thickness between the tunnel junction layer 147 and the second active layer 149 described below is preferably 100 nm or less. And this n-type intermediate layer preferably includes a spacer layer.

[0048] <Second Spacer Layer> A second spacer layer 148 may be provided on the tunnel junction layer 147, and the film thickness is preferably 1 nm or more and 100 nm or less. The second spacer layer 148 may have the same composition as the n-type tunnel junction layer 1472 of the tunnel junction layer 147 or the barrier layer of the second active layer 149, or may have a composition with a larger bandgap than the barrier layer. It is preferably a layer (undoped layer) in which the raw material gas of the n-type dopant is not flowed during growth and intentional doping is not performed. This second spacer layer 148 reduces the diffusion of the n-type dopant from the n-type tunnel junction layer 1472 of the tunnel junction layer 147 to the second active layer 149.

[0049] A layer other than the above-described second spacer layer 148 may be included between the second active layer 149 and the tunnel junction layer 147. Even in that case, in the present invention, since the dopant concentration in the tunnel junction layer 147 can be kept low, even if diffusion of the n-type dopant occurs from the n-type tunnel junction layer 1472, the n-type dopant concentration in the n-type intermediate layer can be, for example, 5.0×10 18 / cm 3 or less, and it is also possible to suppress the total film thickness between the second active layer 149 and the tunnel junction layer 147 to 100 nm or less. By making it thin in this way while suppressing the diffusion amount of the dopant, it can be expected to reduce the forward voltage of the entire device.

[0050] <Second Active Layer> A second active layer 149 containing Sb is provided on the second spacer layer 148. The second active layer 149 preferably has the same configuration as the first active layer 144. For example, in FIG. 1, the second active layer 149 is a well layer InAs that becomes a light-emitting layer x2 Sb 1-x2 layer (0 <x2 <1) and a barrier layer InAs y2P 1-y2 Although a quantum well structure composed of layers (0 < y2 < 1) is illustrated, it is preferable that the well layer 149w of the second active layer and the well layer 144w of the first active layer, and the barrier layer 149b of the second active layer and the barrier layer 144b of the first active layer have the same configuration respectively. Further, the first active layer 144 and the second active layer 149 have the same emission wavelength and have a wavelength range where the emission center wavelength is 3000 nm or more.

[0051] <Second p-type electron blocking layer> A second p-type electron blocking layer 150 made of a III-V compound semiconductor layer may be provided on the second active layer 149, and the film thickness is preferably 5 nm or more and 60 nm or less. Dopants that can be used here include Mg, Zn, C, Be, etc. Also, the dopant concentration is 1.0×10 18 / cm 3 or more and 5.0×10 18 / cm 3 or less. This second p-type electron blocking layer 150 is a layer that injects and confines carriers into the second active layer 149. Also, the second p-type electron blocking layer 150 has the effect of reducing the diffusion of dopants from the second p-type window layer 151 to the second active layer 149.

[0052] The composition of the second p-type electron blocking layer 150 is preferably Al z2 In 1-z2 As (0.05 ≤ z2 ≤ 0.4), and more preferably Al z2 In 1-z2 As (0.10 ≤ z2 ≤ 0.35). By setting the Al composition z2 to 0.05 or more, the luminous efficiency by the second p-type electron blocking layer 150 can be improved, and by setting it to 0.40 or less, it is possible to suppress the increase in the forward voltage and the decrease in the luminous efficiency. Also, the p-type dopant concentration of the second p-type electron blocking layer 150 is preferably smaller than the p-type dopant concentration doped in the p-type tunnel junction layer 1471.

[0053] <Second p-type window layer> A second p-type window layer 151 made of a group III-V compound semiconductor layer may be provided on the second p-type electron blocking layer 150, and the film thickness is preferably 500 nm or more and 2000 nm or less. If the second p-type window layer 151 is thicker than this, the current spreads to the ends of the LED chip and surface recombination increases, and in addition, the ohmic resistance of the element increases, resulting in a decrease in luminous efficiency, which is not preferable. On the other hand, if the second p-type window layer 151 is thinner than this, light emission occurs directly under the electrode, which hinders light extraction, which is not preferable. Dopants that can be used here include Mg, Zn, C, Be, etc. The dopant concentration of the second p-type window layer 151 is 1.0×10 18 atoms / cm 3 or more and 5.0×10 18 atoms / cm 3 or less, which is preferable.

[0054] <p-type contact layer> A p-type contact layer 152 made of a group III-V compound semiconductor layer may be provided on the second p-type window layer 151, and the film thickness is preferably 20 nm or more and 300 nm or less. The dopant concentration of the p-type contact layer 152 is higher than that of the second p-type window layer 151, and is 8.0×10 18 atoms / cm 3 or more and 3.0×10 19 atoms / cm 3 or less, which is preferable.

[0055] An example of an embodiment of the manufacturing method of the optical semiconductor element 100 described above will be described below. When the growth substrate 105 is n-type or undoped, the optical semiconductor element 100 is manufactured through a process of epitaxially growing the first active layer 144, the tunnel junction layer 147 made of InAs, and the second active layer 149 in order. Here, the first active layer 144 and the second active layer 149 contain Sb, and the tunnel junction layer 147 is formed by vertically stacking a p-type tunnel junction layer 1471 formed of a p-type InAs layer and an n-type tunnel junction layer 1472 formed of an n-type InAs layer. The first active layer 144 and the p-type tunnel junction layer 1471 face each other, and the n-type tunnel junction layer 1472 and the second active layer 149 face each other. The dopant concentration of the tunnel junction layer 147 is 1.0×10 18 atoms / cm 3 Above 1.0×10 19 atoms / cm 3 is less than.

[0056] A first p-type electron blocking layer 145 or a first p-type window layer 146 having a total thickness of 100 nm or less may be formed between the first active layer 144 and the tunnel junction layer 147, and a second undoped spacer layer 148 having a thickness of 100 nm or less may be formed between the tunnel junction layer 147 and the second active layer 149.

[0057] Furthermore, one or more layers selected from the group consisting of an n-type contact layer 141, an n-type window layer 142, and a first spacer layer 143 may be formed between the growth substrate 105 and the first active layer 144, and one or more layers selected from the group consisting of a second p-type electron block layer 150, a second p-type window layer 151, and a p-type contact layer 152 may be formed on the second active layer.

[0058] On the other hand, if the growth substrate 105 for epitaxially growing each semiconductor layer of the semiconductor laminate 140 is a p-type, the second active layer 149, the tunnel junction layer 147, and the first active layer 144 are formed in this order on the growth substrate 105. At this time, the second active layer 149 and the n-type tunnel junction layer 1472 face each other, and the p-type tunnel junction layer 1471 and the first active layer 144 face each other.

[0059] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, arsine (AsH3) or tertiarybutylarsine (TBAs) as an As source, trimethylantimony (TMSb), triethylantimony (TESb), or trisdimethylaminoantimony (TDMASb) as an Sb source, and phosphine (PH3) or tertiarybutylphosphine (TBP) as a P source are used in a predetermined mixture ratio, and these raw material gases are vapor-phase grown using a carrier gas, thereby forming a desired thickness according to the growth time. When doping each layer to p-type or n-type, a dopant source gas may be used as desired. For example, when doping with Zn, DEZn (diethylzinc) gas may be used. Note that InAs is also n-type even when undoped.

[0060] In FIG. 1, a lower electrode 195 is provided on the back surface of the growth substrate 105. Furthermore, an upper electrode 191 is provided on a part of the p-type contact layer 152. The upper electrode 191 may include a wiring portion and a pad portion of an ohmic electrode, and although not shown, the pad portion may have a metal layer or solder for bonding. The metal materials and formation methods used for the upper electrode 191 and the lower electrode 195 can be publicly known. Examples of metal materials that can be used include Ti, Pt, Au, Ag, Al, Zn, and Ni.

[0061] When a forward voltage is applied from the upper electrode 191 to the lower electrode 195, the forward voltage is applied to the first active layer 144 and the second active layer 149, and both the first active layer 144 and the second active layer 149 emit light. At this time, a reverse voltage is applied to the tunnel junction (pn junction) in the tunnel junction layer 147. As a result, a current flows in the tunnel junction layer 147 due to the tunnel effect.

[0062] Second embodiment With reference to FIG. 2, an optical semiconductor element 200 according to a second embodiment of the present invention will be described. The optical semiconductor element 200 is a junction-type optical semiconductor element obtained by bonding a support substrate and then removing a growth substrate. In principle, the same components as those of the optical semiconductor element 100 are given the same reference numbers with the last two digits of the three-digit number, and duplicated explanations will be omitted. This optical semiconductor element 200 includes at least a support substrate 280, a metal bonding layer 279 and a metal reflective layer 271 provided on the surface of the support substrate 280, a transparent insulating layer 261 with a through hole on the metal reflective layer 271, a power distribution section 260 having an ohmic electrode section 265 provided in the through hole, and a semiconductor laminate 240 provided on the power distribution section 260.

[0063] 2 has, in order from the side opposite to supporting substrate 280, n-type contact layer 241, n-type window layer 242, first spacer layer 243, first active layer 244, first p-type electron blocking layer 245, first p-type window layer 246, tunnel junction layer 247, second spacer layer 248, second active layer 249, second p-type electron blocking layer 250, second p-type window layer 251, and p-type contact layer 252.

[0064] The support substrate 280, which is different from the growth substrate, is preferably cheaper and has higher thermal conductivity than the growth substrate, and may be, for example, a compound substrate such as Si, Ge, or GaAs, or a metal substrate using a metal capable of suppressing the thermal expansion coefficient such as copper alloy, molybdenum, tungsten, or Kovar, or a submount substrate in which a metal is attached to a ceramic substrate such as AlN. It is also preferable to use a Si substrate for the support substrate 280 in terms of processability and cost.

[0065] An example of an embodiment of the optical semiconductor element 200 and a manufacturing method thereof will be described in more detail below with reference to Figs. 3 to 5. First, a growth substrate 205 is prepared. Then, with reference to Fig. 3, a semiconductor laminate 240 is formed. At this time, an etching stop layer (not shown) may be formed on the growth substrate 205. The semiconductor laminate 240 is similar to the semiconductor laminate 140 described above.

[0066] <Formation of power distribution section> A power distribution section 260 including a transparent insulating layer 261 with a through hole and an ohmic electrode section 265 provided in the through hole is formed on the p-type contact layer 252. Any specific method may be used to form the power distribution section 260, but an example of a specific embodiment for forming the power distribution section 260 will be described below with reference to Figs. 4 and 5.

[0067] First, the transparent insulating layer 261 is formed on the semiconductor laminate 240. As the film formation method, a known method such as a plasma CVD method or a sputtering method can be applied. After that, a resist pattern of the power distribution section is formed on the transparent insulating layer 261 using a photomask. Next, a part of the transparent insulating layer 261 is removed by etching using the resist pattern to form a through hole. By providing the through hole, a part of the outermost surface of the semiconductor laminate 240 is exposed. After that, the ohmic electrode section 265 is formed, and then lifted off using the resist pattern, so that the power distribution section 260 can be formed. In the power distribution section 260, the transparent insulating layer 261 and the ohmic electrode section 265 are arranged in parallel. Note that, for simplification in the drawing, the ohmic electrode section 265 is illustrated to fill the through hole, but is not limited to this, and a gap may be formed between the transparent insulating layer 261 and the ohmic electrode section 265.

[0068] The ohmic electrode portion 265 can be formed by dispersing it in an island shape in a predetermined pattern. For example, Au, AuZn, AuBe, AuTi, etc. can be used as the ohmic electrode portion 265, and it is also preferable to use a laminated structure of these. For example, Ti / Au can be used as the ohmic electrode portion 265. The film thickness (or total film thickness) of the ohmic electrode portion 265 is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

[0069] <Formation of metal reflective layer> As shown in FIG. 4, it is also preferable to form a metal reflective layer 271 on the power distribution unit 260. The metal reflective layer 271 may include a plurality of metal layers, and the metal constituting the metal reflective layer 271 may be Al, Pt, Ti, Ag, or the like in addition to Au. For example, the metal reflective layer 271 may be a single layer made of Au only, or the metal reflective layer 271 may include two or more Au metal layers. It is preferable that the composition of the metal reflective layer 271 contains 50 mass % or more of Au. In order to ensure bonding with the metal bonding layer 279 in the subsequent process, it is preferable that the outermost layer of the metal reflective layer 271 (the surface opposite to the semiconductor laminate 240) is an Au metal layer.

[0070] For example, metals may be deposited in the order of Al, Au, Pt, and Au on the power distribution section 260 (including the gap if the gap is provided) to form the metal reflective layer 271. The thickness of the Au1 layer in the metal reflective layer 271 may be, for example, 400 nm to 2000 nm, and the thickness of the metal layers made of metals other than Au may be, for example, 5 nm to 200 nm. The metal reflective layer 271 may be deposited by using a general method such as a vapor deposition method.

[0071] <Joining with supporting substrate> The bonding to the support substrate will be described with reference to Fig. 4. The semiconductor laminate 240 and the power distribution section 260 are bonded to the support substrate 280 via at least the metal bonding layer 279. The metal reflective layer 271 may be provided to bond the metal reflective layer 271 and the metal bonding layer 279. The metal bonding layer 279 and the metal reflective layer 271 are placed opposite each other and bonded together, and heated and compressed to bond at a temperature of about 250°C to 500°C, whereby the two can be bonded to each other.

[0072] <Metal bonding layer> The metal bonding layer 279 can be formed using metals such as Ti, Pt, Au, or a metal (such as Sn) that forms a eutectic alloy with Au, or solder, and it is preferable to laminate these to form the metal bonding layer 279. For example, the metal bonding layer 279 can be formed by laminating, in order from the surface of the support substrate 280, Ti having a thickness of 400 nm to 800 nm, Pt having a thickness of 5 nm to 20 nm, and Au having a thickness of 700 nm to 1200 nm. For example, when bonding the metal reflective layer 271 and the metal bonding layer 279, the outermost layer of the metal bonding layer 279 can be made of Au metal, and the outermost layer of the metal reflective layer 271 can also be made of Au, and bonding between Au can be performed by Au-Au diffusion.

[0073] <Support substrate> The support substrate 280 may be a substrate of a different type from the growth substrate 205, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Since the above-mentioned bonding method is used, the support substrate 280 may be lattice-mismatched with each semiconductor layer formed in this embodiment. The support substrate 280 may be an insulating substrate depending on the application, but is preferably a conductive substrate. From the viewpoints of processability and cost, it is preferable to use a Si substrate for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to the conventional method, and it is also suitable for mounting in combination with various semiconductor devices. In addition, the Si substrate is also advantageous in terms of heat dissipation compared to the InAs substrate.

[0074] <Removal of growth substrate> The removal of the growth substrate will be described with reference to FIG. 5. After bonding the support substrate 280, the growth substrate 205 is removed. When the growth substrate 205 is a GaAs substrate, the growth substrate 205 can be wet-etched using, for example, an ammonia-hydrogen peroxide mixture. When an etching stop layer is used, the etching stop layer may be sequentially removed following the removal of the growth substrate 205. In addition, by leaving a part of the etching stop layer, it may be used as an n-type contact layer that reduces the contact resistance with the upper electrode 291.

[0075] Furthermore, as shown in FIG. 2, an upper electrode 291 may be formed on the semiconductor laminate 240, and a back electrode 295 may be formed on the back surface of the support substrate 280. The upper electrode 291 may include a wiring portion and a pad portion. The upper electrode 291 and the back electrode 295 may be formed by a known method, such as a sputtering method, an electron beam deposition method (also referred to as a deposition method), or a resistance heating method. The patterning of the electrodes may be formed by a method using a metal mask, or by a method using a combination of a photolithography method, a lift-off method, and metal etching.

[0076] By the above manufacturing method, it is possible to obtain the optical semiconductor element 200 shown in Fig. 2. These embodiments are merely examples and are not limiting, and suitable modifications are possible, such as providing a slope on the side surface of the element in mesa etching, or the electrode shape may be two electrodes on the upper surface or a flip chip.

[0077] Third embodiment Next, an optical semiconductor device 300 according to a third embodiment of the present invention will be described with reference to Fig. 6. The third embodiment is an embodiment in which a tunnel junction layer and an active layer are further formed on the second p-type window layer of the first embodiment. Specifically, the semiconductor light emitting device in Fig. 6 has a second tunnel junction layer 352, a third active layer 354, a third tunnel junction layer 357, and a fourth active layer 359, successively, on the second p-type window layer. Each component will be described in detail below.

[0078] The second tunnel junction layer 352 has a p-type InAs layer 3521 and an n-type InAs layer 3522, similar to the tunnel junction layer 147 of the first embodiment. Also, the p-type InAs layer 3521 faces the second active layer, and the n-type InAs layer 3521 faces the third active layer 354. Here, the second tunnel junction layer 352 may have the same composition and film thickness as the first tunnel junction layer, or may be different.

[0079] The third active layer 354 is an InAs light-emitting layer, similar to the first active layer. x3 Sb 1-x3 layer (0 < x3 < 1), and has the same emission wavelength as the first active layer. Also, the third active layer 354 may have the same composition and film thickness as the first active layer, or may be different.

[0080] The third tunnel junction layer 357 has a p-type InAs layer 3571 and an n-type InAs layer 3572, similar to the tunnel junction layer of the first embodiment. Also, the p-type InAs layer 3571 faces the third active layer 354, and the n-type InAs layer 3572 faces the fourth active layer 359. Here, the third tunnel junction layer 357 may have the same composition and film thickness as the first tunnel junction layer, or may be different.

[0081] The fourth active layer 359 is an InAs light-emitting layer, similar to the first active layer. x4 Sb 1-x4 layer (0 < x4 < 1), and has the same emission wavelength as the first active layer. Also, the fourth active layer 359 may have the same composition and film thickness as the first active layer, or may be different.

[0082] The layer above the fourth active layer 359 has the same configuration as the layer above the second active layer in the first embodiment.

[0083] In the above-described third embodiment, the second tunnel junction layer 352, the third active layer 354, the third tunnel junction layer 357, and the fourth active layer 359 are formed on the second electron blocking layer to form a total of three tunnel junction layers and a total of four active layers. In this embodiment, instead of the embodiment in FIG. 6, a total of N tunnel junction layers (N is an integer equal to or greater than N3) may be formed, and a total of (N+1) active layers may be formed. For example, a total of two tunnel junction layers may be formed, and a total of three active layers may be formed, or a total of four tunnel junction layers may be formed, and a total of five active layers may be formed. The embodiment in FIG. 6 is a specific example in which N is 3. Even in this case, the dopant concentration of each tunnel junction layer is 1×10 18 atoms / cm 3 More than 1×10 19 atoms / cm 3 The wavelengths of the active layers are equal to or less than 3000 nm and have central wavelengths equal to each other.

[0084] (Fourth embodiment: light receiving element) A semiconductor optical detector according to a fourth embodiment of the present invention will be described. For example, by replacing the first active layer and the second active layer in the first embodiment with a first InAsSb optical absorption layer and a second InAsSb optical absorption layer, the semiconductor optical detector according to the present invention can be used as a semiconductor optical detector. Since the semiconductor optical detector according to the present invention has two absorption layers via a tunnel junction layer, the dark current is reduced compared to the case where there is only one absorption layer, and a semiconductor optical detector with a large shunt resistance and good characteristics can be realized. EXAMPLES

[0085] [Experimental Example 1] Example 1 First, a high dopant concentration (Te concentration 1.0×10) was grown on the (100) surface of a Si-doped n-type GaAs growth substrate (substrate thickness: 350 μm) using the MOCVD method. 19 / cm 3 ) n-type InAs contact layer (thickness: 0.3 μm), Te-doped n-type InAs window layer (thickness: 4.9 μm, Te concentration: 3.0×10 18 / cm 3), and an undoped InAs spacer layer (thickness: 75 nm). Next, a first active layer (total thickness: 430 nm) with a quantum well structure having a central emission wavelength of 4300 nm was formed. The active layer with the quantum well structure is made of undoped InAs 0.90 P 0.10 Barrier layer (thickness: 30 nm) and InAs 0.87 Sb 0.13 After stacking 10 well layers (10 nm after film formation) in sequence, InAs 0.90 P 0.10 The barrier layers were grown to form 10.5 pairs, including the last barrier layer. Zn-doped p-type Al was grown on the first active layer. 0.32 In 0.68 As electron blocking layer (film thickness: 15 nm, Zn concentration: 2.5×10 18 / cm 3 ) and a Zn-doped p-type InAs window layer (thickness: 50 nm, Zn concentration: 2.5×10 18 / cm 3 ) was formed, and a tunnel junction layer was formed thereon.

[0086] The tunnel junction layer is a Zn-doped InAs layer (thickness: 50 nm, Zn concentration at growth: 8 × 10 18 / cm 3 ) on which a Te-doped InAs layer (thickness: 50 nm, Te concentration at time of growth: 8 × 10 18 / cm 3 The tunnel junction layer was grown at a pressure of 50 Torr, with the ratio of group V elements to group III elements (VIII ratio) in the source gas being 50.

[0087] Next, an undoped InAs spacer layer (thickness: 75 nm) was formed on the tunnel junction layer, and a second active layer (total thickness: 430 nm) was formed on the spacer layer, which was the same as the first active layer. Zn-doped p-type Al 0.32 In 0.68 As electron blocking layer (film thickness: 15 nm, Zn concentration: 2.5×10 18 / cm 3) was formed. In addition, a Zn-doped p-type InAs window layer (thickness: 900 nm, Zn concentration: 2.5 × 10 18 / cm 3 ) and then a high dopant concentration (Zn concentration 1.0×10 19 / cm 3 ) a p-type InAs contact layer (thickness: 100 nm) was formed. Table 1 below shows the composition and thickness of each layer, the type of dopant, the (designed) dopant concentration during growth, and the dopant concentration by SIMS analysis including the diffusion of the dopant after all epitaxial growth was completed and the device was removed from the MOCVD device. The source gases selected for the formation of each layer were trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, arsine (AsH3) as the As source, triethylantimony (TESb) as the Sb source, and phosphine (PH3) as the P source. DEZn (diethylzinc) and DETe (diethyltellurium) were used as dopant gases.

[0088] The composition of each layer was measured using a BRUKER JV-QC3 XRD instrument. The composition of each layer was calculated by fitting using analytical software (Jordan Valley RADS). The thickness of each layer was calculated from cross-sectional observation of the growth layer using a SEM (scanning electron microscope) or TEM (transmission electron microscope).

[0089] [Table 1]

[0090] Next, a transparent insulating layer (film thickness: 550 nm) made of SiO2 was formed on the entire surface of the p-type InAs contact layer by plasma CVD. A power distribution pattern was formed on the transparent insulating layer using resist, and the SiO2 in the area not covered by the resist was removed by etching to expose the Zn-doped p-type InAs contact layer. Next, Ti (film thickness: 10 nm) and Au (film thickness: 530 nm) were formed as ohmic metal parts using deposition, and the resist of the power distribution pattern was removed together with the metal film formed thereon, leaving only the ohmic metal parts formed on the exposed Zn-doped p-type InAs contact layer, forming a power distribution part in which the ohmic metal parts and the transparent insulating film are arranged in parallel. Next, a metal reflective layer (Al (film thickness: 10 nm / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm))) was formed on the power distribution part by deposition.

[0091] Next, a metal bonding layer (Ti (film thickness: 650 nm) / Pt (film thickness: 20 nm) / Au (film thickness: 900 nm)) was formed on the support substrate (Si substrate) by deposition. Next, the metal reflective layer and the metal bonding layer were arranged facing each other and heated and compressed at 300 ° C. Next, the growth substrate was removed by wet etching using an ammonia-hydrogen peroxide solution mixture to expose the n-type contact layer. Next, Ti (film thickness: 150 nm) / Au (film thickness: 1250 nm) was formed on the n-type contact layer by deposition to form an n-type ohmic electrode. Next, a pad electrode (Ti (film thickness: 150 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 2500 nm)) was formed on the n-type ohmic electrode by deposition, and the n-type ohmic electrode and the pad electrode were combined to form the upper electrode. The electrode pattern was formed by lift-off using a resist.

[0092] Next, the semiconductor laminate between each element (width: 60 μm) was removed by mesa etching to form a dicing line. Then, a back electrode (Ti (film thickness: 10 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 200 nm)) was formed on the back side of the support substrate by vapor deposition, and alloyed by heat treatment at 300° C. for 1 minute. Next, the entire wafer was immersed in a nitric acid solution kept at 8° C.±1° C. for 5 seconds to roughen the surface of the semiconductor laminate except for the region where the upper electrode was formed. After that, it was immersed in ammonia water for 1 minute and washed with pure water for 1 minute. Finally, chips were separated by dicing to produce the optical semiconductor element according to Example 1. The chip size was 500 μm×500 μm.

[0093] 7 is a graph showing the results of measuring the diffusion state of Te ions in the optical semiconductor element fabricated in Example 1 by secondary ion mass spectrometry (SIMS). In FIG. 7, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of n-type dopants (here, Te, Si, C, H, and O). 3 ), and the vertical axis on the right side is the secondary ion intensity of Sb (counts / sec). In the case of Example 1, the maximum concentration of Te, which is an n-type dopant doped in the semiconductor laminate 140, is 8.0×10 18 atoms / cm 3 The position where the maximum value was reached was the position corresponding to the n-type tunnel junction layer, and diffusion of Te from the n-type tunnel junction layer toward the undoped spacer layer and the first barrier layer was observed. However, even if the Te concentration in the spacer layer and the first barrier layer increased due to diffusion, it was only 4.0 × 10 18 atoms / cm 3 The Te concentration was able to be kept within the preferred range.

[0094] 8 is a graph showing the results of measuring, by SIMS, the diffusion state of Zn ions in the optical semiconductor element fabricated in Example 1. In FIG. 8, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of the p-type dopant (Zn in this case). 3), and the right vertical axis indicates the secondary ion intensity (counts / sec). In the case of Example 1, the maximum concentration of Zn, which is a p-type dopant doped in the semiconductor laminate 140, is 6.0×10 18 atoms / cm 3 The position where the maximum value was reached was the position corresponding to the p-type tunnel junction layer, and Zn diffusion from the p-type tunnel junction layer toward the p-type window layer and the electron block layer was observed. However, the increase in Zn concentration in the p-type window layer and the electron block layer due to diffusion was only 5.0 × 10 18 atoms / cm 3 The Zn concentration was able to be kept within a preferable range.

[0095] Example 2 Similarly to Example 1, each semiconductor layer was epitaxially grown up to the second active layer. Next, the second tunnel junction layer, the third active layer, the third tunnel junction layer, and the fourth active layer were formed in order on the second active layer. On the fourth active layer, an electron block layer, a p-type window layer, and a p-type contact layer were formed in order, similar to the second active layer of Example 1. The third active layer and the fourth active layer have the same film thickness and composition as the first active layer, and the second tunnel junction layer and the third tunnel junction layer have the same film thickness and composition as the first tunnel junction layer. Here, between the second active layer and the second tunnel junction layer, and between the third active layer and the third tunnel junction layer, an electron block layer having the same film thickness and composition as the electron block layer between the first active layer and the first tunnel junction layer was formed. In addition, between the second tunnel junction layer and the third active layer, and between the third tunnel junction layer and the fourth active layer, a spacer layer having the same film thickness and composition as the spacer layer between the first tunnel junction layer and the second active layer was formed. The composition and thickness of each layer, the type of dopant, the dopant concentration during growth, and the dopant concentration by SIMS analysis including dopant diffusion are shown in Table 2. The dopant concentration was diffused in the same manner as in Example 1, and the diffusion amount was kept within the preferred range.

[0096] [Table 2]

[0097] Comparative Example 1 An optical semiconductor device according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the thickness of the second active layer was changed from 430 nm to 0 nm, the thickness of the spacer layer on the tunnel junction layer was changed from 75 nm to 0 nm, the thickness of the Te-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, the thickness of the Zn-doped InAs layer in the tunnel junction layer was changed from 50 nm to 0 nm, and the thickness of the electron blocking layer below the tunnel junction layer was changed from 15 nm to 0 nm, and the number of well layers and barrier layers in the quantum well structure of the first active layer was 20.5 pairs (total thickness: 860 nm).

[0098] <Evaluation: Light output evaluation> A current of 100 mA was applied to the optical semiconductor devices obtained from the above examples and comparative examples using a constant current voltage power supply. The forward voltage Vf (V) and the light output Po (W) using an integrating sphere were measured. In addition, the leakage current (A) was measured when a reverse voltage of -0.1 V was applied. The results are shown in Table 3.

[0099] [Table 3]

[0100] From the above results, it was confirmed that by increasing the number of PN junctions (number of active layers) and the number of tunnel junctions, the light output and forward voltage increase, and furthermore, the leakage current decreases.

[0101] According to the present invention, it is possible to provide an optical semiconductor device comprising two or more active layers containing Sb with a tunnel junction layer made of InAs interposed therebetween, and a method for producing the same. [Explanation of symbols]

[0102] 100 Optical semiconductor element 105 Growth substrate 140 Semiconductor laminate 141 n-type contact layer 142 n-type window layer 143 First spacer layer 144 1st active layer 144b Barrier layer of first active layer 144w First active layer well layer 145 1st p-type electron blocking layer 146 1st p-type window layer 147 Tunnel Junction Layer 1471 p-type tunnel junction layer 1472 n-type tunnel junction layer 148 Second Spacer Layer 149 2nd active layer 149b Barrier layer of second active layer 149w Second active layer well layer 150 2nd p-type electron blocking layer 151 2nd p-type window layer 152 p-type contact layer 191 Upper electrode 195 Lower Electrode 200 Optical semiconductor element 205 Growth substrate 240 Semiconductor laminate 241 n-type contact layer 242 n-type window layer 243 First spacer layer 244 1st active layer 245 1st p-type electron blocking layer 246 1st p-type window layer 247 Tunnel Junction Layer 248 Second Spacer Layer 249 2nd active layer 250 2nd p-type electron blocking layer 251 p-type window layer 252 p-type contact layer 260 Power Distribution Department 261 Transparent insulating layer 265 Ohmic electrode 271 Metal reflective layer 279 Metal bonding layer 280 Support Substrate 291 Upper electrode 295 Back electrode 300 Optical semiconductor element 352 Second tunnel junction layer 3521 p-type InAs layer of the second tunnel junction 3522 n-type InAs layer of the second tunnel junction 354 3rd active layer 357 Third tunnel junction layer 3571 p-type InAs layer of the third tunnel junction 3572 n-type InAs layer of the third tunnel junction 359 4th active layer

Claims

1. An optical semiconductor device having a first active layer having an emission wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission wavelength of a second wavelength, the first active layer and the second active layer contain Sb; The tunnel junction layer includes a p-type InAs layer and an n-type InAs layer. Optical semiconductor element.

2. The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ is less than The optical semiconductor element according to claim 1 .

3. the first active layer and the second active layer have a quantum well structure, The first wavelength and the second wavelength are 3000 nm or longer. The optical semiconductor element according to claim 1 .

4. The first wavelength and the second wavelength are the same. The optical semiconductor element according to claim 1 .

5. the p-type InAs layer is located on the first active layer side of the tunnel junction layer; a p-type electron blocking layer between the first active layer and the tunnel junction layer; a thickness between the first active layer and the tunnel junction layer is 100 nm or less; The optical semiconductor element according to claim 1 .

6. the n-type InAs layer is located on the second active layer side of the tunnel junction layer; a spacer layer between the tunnel junction layer and the second active layer; a thickness between the tunnel junction layer and the second active layer is 100 nm or less; The optical semiconductor element according to claim 1 .

7. forming a first active layer on a substrate, the first active layer having a first wavelength for receiving and emitting light; forming a tunnel junction layer on the first active layer; forming a second active layer on the tunnel junction layer, the second active layer having a second wavelength for receiving and emitting light; Including, the first active layer and the second active layer contain Sb; The step of forming the tunnel junction layer includes the steps of forming an n-type InAs layer and forming a p-type InAs layer on the n-type InAs layer. A method for manufacturing an optical semiconductor element.

8. The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ The method for producing an optical semiconductor device according to claim 7 , wherein the

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