Semiconductor device

Abstract

To provide a semiconductor device with good electrical characteristics, a semiconductor device with high reliability, and a semiconductor device with stable electrical characteristics.SOLUTION: A semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer. The first insulating layer has a stacked structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order. The second insulating layer includes an oxide. The third insulating film has a portion in contact with the semiconductor layer. The first insulating film includes silicon and nitrogen. The second insulating film includes silicon, nitrogen, and oxygen. The third insulating film includes silicon and oxygen. The semiconductor layer includes indium and oxygen.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, and a , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof A semiconductor device functions by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used for transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called the mobility A semiconductor device having improved mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. The company plans to improve some of its production facilities for transistors using polycrystalline silicon and amorphous silicon. This allows the use of metal oxide transistors, which reduces capital investment. The field effect mobility of the transistor is higher than that of amorphous silicon, so the driver circuit It is possible to realize a high-performance display device having the above-mentioned structure. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2014-7399 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device having stable electrical characteristics. An object of the present invention is to provide a highly reliable display device.

[0007] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from descriptions in the specification, drawings, claims, etc. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device having a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor device has a first insulating layer, a semiconductor layer, a second insulating layer, and a first conductive layer. The first insulating layer is made up of a first insulating film, a second insulating film, and a third insulating film. The semiconductor layer has a laminated structure in which the first insulating layer and the second insulating layer are laminated in this order. The third insulating film includes indium and oxygen. The third insulating film has a portion in contact with the semiconductor layer. The first insulating film contains silicon and nitrogen. The third insulating film contains silicon, oxygen, and The second insulating film contains silicon, nitrogen, and oxygen. The amount of oxygen in the second insulating film is greater than that in the first insulating film and less than that in the third insulating film. The nitrogen contained in the film is less than that in the first insulating film and is more than that in the third insulating film.

[0009] In the above, the semiconductor layer is made of M (M is aluminum, gallium, yttrium and tin) and zinc. In this case, it is preferable that the semiconductor layer has a region in which the indium content is higher than the M content. I wish.

[0010] Another aspect of the present invention is a semiconductor device comprising a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor device has a first insulating layer, a semiconductor layer, a second insulating layer, and a first insulating layer. The conductive layers are laminated in this order. The first insulating layer is made up of a first insulating film, a second insulating film, and The semiconductor layer has a laminated structure in which the first metal oxide layer, the second insulating film, and the third insulating film are laminated in this order. The second insulating layer has a laminated structure in which a first insulating film and a second metal oxide film are laminated in this order. The first metal oxide film and the second metal oxide film each contain indium oxide. and oxygen. The second insulating layer has a portion in contact with the second metal oxide film. The insulating film has a portion in contact with the first metal oxide film. The first insulating film is made of silicon and The third insulating film contains silicon and oxygen. The second insulating film contains silicon. The oxygen contained in the second insulating film is more concentrated than that contained in the first insulating film. The nitrogen contained in the second insulating film is greater than that contained in the first insulating film and is less than that contained in the third insulating film. The thickness of the first insulating film is less than that of the second insulating film and is greater than that of the third insulating film.

[0011] In the above, it is preferable that the second conductive layer is provided. In this case, the first insulating layer is located between the second conductive layer and the semiconductor layer. The second conductive layer is located between the semiconductor layer and The first insulating film has a region overlapping the first conductive layer. The first insulating film has a region in contact with the second conductive layer. Yes.

[0012] In the above, the second insulating film is thicker than the first insulating film. It is preferable that the insulating film is thicker than the insulating film of 3.

[0013] In the above, the thickness of the second insulating film is at least twice as thick as the thickness of the first insulating film. It is preferable that the thickness of the second insulating film is 20 times or less than the thickness of the third insulating film. The thickness of the second insulating film is preferably 2 to 20 times that of the first insulating film. It is preferable that the thickness of the insulating layer is 50% or more and 95% or less of the total thickness of the insulating layer.

[0014] In the above, the second insulating layer includes a fourth insulating film, a fifth insulating film, and a sixth insulating film. It is preferable that the fourth insulating film has a laminated structure in which the films are laminated in this order. The fourth insulating film, the fifth insulating film, and the sixth insulating film have a region in contact with the semiconductor layer. Preferably, the films each comprise an oxide.

[0015] In the above, the first metal oxide film contains gallium and zinc, and the second metal oxide film contains The second metal oxide film preferably contains gallium and zinc. The metal oxide film has a higher indium content and a lower gallium content than the first metal oxide film. It is preferable to have areas of low prevalence.

[0016] Alternatively, in the above, the first metal oxide film contains gallium and zinc, and the second The metal oxide film preferably does not contain gallium.

[0017] In the above, a metal oxide layer is provided between the second insulating layer and the first conductive layer. In this case, the metal oxide layer is preferably made of aluminum, hafnium, tin, indium, etc. It is preferable that the alloy contains one or more elements selected from the group consisting of tungsten, gallium, and zinc. Effect of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a semiconductor device having stable electrical characteristics can be provided. Alternatively, a highly reliable display device can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating configuration examples of transistors. [Diagram 2] 2A and 2B are diagrams illustrating configuration examples of transistors. [Diagram 3] 3A and 3B are diagrams illustrating configuration examples of transistors. [Figure 4]4A to 4C are diagrams illustrating configuration examples of transistors. [Diagram 5] 5A to 5C are diagrams illustrating configuration examples of transistors. [Figure 6] 6A to 6C are diagrams illustrating configuration examples of transistors. [Figure 7] 7A to 7C are diagrams illustrating configuration examples of transistors. [Figure 8] 8A to 8D are diagrams illustrating configuration examples of transistors. [Figure 9] 9A to 9D are diagrams illustrating configuration examples of transistors. [Figure 10] 10A to 10D are diagrams illustrating configuration examples of transistors. [Figure 11] 11A to 11E illustrate a method for manufacturing a transistor. [Figure 12] 12A to 12D illustrate a method for manufacturing a transistor. [Figure 13] 13A and 13B illustrate a method for manufacturing a transistor. [Figure 14] 14A to 14D illustrate a method for manufacturing a transistor. [Figure 15] 15(A) to 15(C) are top views of the display device. [Figure 16] FIG. 16 is a cross-sectional view of the display device. [Figure 17] FIG. 17 is a cross-sectional view of the display device. [Figure 18] FIG. 18 is a cross-sectional view of the display device. [Figure 19] FIG. 19 is a cross-sectional view of the display device. [Figure 20] Fig. 20(A) is a block diagram of a display device, and Fig. 20(B) and Fig. 20(C) are circuit diagrams of the display device. [Figure 21]21A, 21C, and 21D are circuit diagrams of a display device, and FIG 21B is a timing chart. [Figure 22] 22(A) and 22(B) are diagrams showing configuration examples of a display module. [Figure 23] 23(A) and 23(B) are diagrams showing configuration examples of electronic devices. [Figure 24] 24A to 24E are diagrams showing configuration examples of electronic devices. [Diagram 25] 25A to 25G are diagrams showing configuration examples of electronic devices. [Figure 26] 26A to 26D are diagrams illustrating configuration examples of electronic devices. [Figure 27] 27(A) to 27(F) show the results of TDS analysis. [Figure 28] 28A to 28D are diagrams showing the Id-Vg characteristics of transistors. [Figure 29] FIG. 29 shows the reliability test results of the transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the drawings. The present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily understood by those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] In addition, in each figure described in this specification, the size, layer thickness, or area of ​​each component may be different. may be exaggerated for clarity.

[0023] In addition, the ordinal numbers "first," "second," and "third" used in this specification indicate components. This is added to avoid confusion and is not intended to limit the number.

[0024] In addition, in this specification, the words "above" and "below" indicating the arrangement are used to refer to the same components. The positional relationship of the components is used for convenience in explaining the drawings. The relative positions of the characters change depending on the direction in which each component is depicted. The words and phrases described in the book are not limited to those used in the text, but can be rephrased appropriately according to the situation.

[0025] In this specification, the functions of the source and drain of a transistor are different. When using polarity transistors, or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are often used interchangeably. It is possible to do so.

[0026] In this specification, the channel length direction of a transistor is the direction between the source region and the drain region. This refers to one of the directions parallel to the line that connects the channel area with the shortest distance. The length direction of the transistor is one of the directions of current flow through the semiconductor layer when the transistor is in the on-state. The channel width direction corresponds to the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction may be one. It may not be fixed.

[0027] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0028] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and The term "insulating film" may sometimes be used interchangeably.

[0029] In this specification and the like, unless otherwise specified, the off-state current refers to the current that occurs when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also called a cut-off state). Unless otherwise specified, for n-channel transistors, V is the voltage between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state of being.

[0030] In this specification, a display panel, which is one aspect of a display device, displays (outputs) images on a display surface. Therefore, the display panel is one aspect of an output device.

[0031] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). inted Circuit) or TCP (Tape Carrier Packa ge) or COG (Chip On Gauge) connectors attached to the board. IC (Integrated Circuit) was implemented using the Glass method, etc. When referring to a display panel module, display module, or simply display panel, etc. There is.

[0032] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images, etc. on a display surface. The function of displaying information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. The touch panel also functions as a touch sensor that detects the touch of the touch panel. A card is one form of input / output device.

[0033] The touch panel is, for example, a display panel (or display device) with a touch sensor, The touch panel can also be called a display panel (or display device) with touch function. A display panel and a touch sensor panel may be used. It may also be configured to have a touch sensor function inside or on the surface.

[0034] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. It may be called a touch panel module, a display module, or simply a touch panel. be.

[0035] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. In particular, in this embodiment, as an example of a semiconductor device, a semiconductor layer in which a channel is formed is A transistor including an oxide semiconductor will be described.

[0036] [Configuration example 1] [Configuration Example 1-1] FIG. 1A is a schematic cross-sectional view of a transistor 10 taken in the channel length direction.

[0037] The transistor 10 includes an insulating layer 103, a semiconductor layer 108, an insulating layer 110, and a metal oxide semiconductor layer 114. The semiconductor device includes a material layer 114 and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode.

[0038] When a conductive film containing a metal or an alloy is used as the conductive layer 112, the electrical resistance can be suppressed. Note that the conductive layer 112 may be a conductive film containing an oxide.

[0039] The metal oxide layer 114 has a function of supplying oxygen to the insulating layer 110. When a conductive film containing a metal or alloy that is easily oxidized is used as 112, the metal oxide Layer 114 is a barrier layer that prevents the conductive layer 112 from being oxidized by oxygen in the insulating layer 110. The metal oxide layer 114 may be removed before the conductive layer 112 is formed. By removing the metal oxide, the conductive layer 112 and the insulating layer 110 may be in contact with each other. The oxide layer 114 may be omitted if unnecessary.

[0040] The insulating layer 110 in contact with the semiconductor layer 108 preferably includes an oxide insulating film. It is more preferable that the insulating layer 110 has a region that contains oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film capable of releasing oxygen. For example, it is preferable to form the insulating layer 110 in an oxygen atmosphere and to form the insulating layer 1 10 is subjected to a heat treatment, a plasma treatment, or the like in an oxygen atmosphere, or the insulating layer 11 By forming an oxide film on the insulating layer 110 in an oxygen atmosphere, oxygen is supplied to the insulating layer 110. It is also possible.

[0041] The insulating layer 110 is formed by, for example, a sputtering method, a chemical vapor deposition (CVD) method, or the like. Vapor Deposition method, vacuum evaporation method, pulsed laser deposition (PLD) :Pulsed Laser Deposition) method, Atomic Layer Deposition (ALD) method The thin-film transistor can be formed by using a method such as a Micro Layer Deposition (MLC) method. As a CVD method, plasma enhanced chemical vapor deposition (PECVD) is used. CVD) method and thermal CVD method.

[0042] In particular, it is preferable that the insulating layer 110 be formed by the PECVD method.

[0043] The semiconductor layer 108 contains a metal oxide (hereinafter, also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. The semiconductor layer 108 preferably contains at least indium and oxygen. By including indium oxide in 108, carrier mobility can be increased. For example, a transistor that can pass a larger current than one that uses amorphous silicon. This can be achieved.

[0044] A region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. The semiconductor layer 108 also has a pair of low-resistance regions 108n sandwiching a channel formation region. It is preferable that the low-resistance region 108n is a region having a higher carrier concentration than the channel formation region. These regions function as a source region and a drain region.

[0045] The low-resistance region 108n is a region having a lower resistance and a higher carrier concentration than the channel formation region. The region may be a region with a large amount of oxygen vacancies, a region with a high hydrogen concentration, or a region with a high impurity concentration. I can say that.

[0046] The insulating layer 103 is a laminate of an insulating film 103a, an insulating film 103b, and an insulating film 103c. The insulating film 103c is in contact with the semiconductor layer 108.

[0047] The insulating layer 103 suppresses the diffusion of impurities from the surface on which the insulating layer 103 is formed into the semiconductor layer 108 and the like. The insulating layer 103 preferably functions as a barrier layer. Satisfy one or more of the following: difficult to release hydrogen or water; difficult to diffuse hydrogen or water It is preferable that all of these conditions are satisfied.

[0048] Among the three insulating films that the insulating layer 103 has, the insulating film 103a located closest to the surface to be formed is On the other hand, an insulating film containing nitrogen is preferably used for the insulating film in contact with the semiconductor layer 108. It is preferable to use an insulating film containing oxygen for the insulating layer 103c. The three insulating films were each deposited in succession using a plasma CVD apparatus without exposure to the atmosphere. It is preferable to form a film.

[0049] The insulating film 103a is a dense film that can prevent the diffusion of impurities from below. It is preferable that the insulating film 103a is formed on a member (such as a substrate) on the side on which the insulating film 103a is to be formed. It is preferable that the film is capable of blocking metal elements, hydrogen, water, etc. contained in the electrolyte. Therefore, the insulating film 103a is formed at a lower film-forming rate than the insulating film 103b. can be applied.

[0050] The insulating film 103a may be, for example, a silicon nitride film, a silicon oxynitride film, or an aluminum nitride film. In particular, an insulating film containing nitrogen, such as a hafnium film or a hafnium nitride film, can be used. A dense silicon nitride film formed using a plasma CVD apparatus is used as 103a. By using such an insulating film containing nitrogen, it is possible to prevent the insulating film from being damaged even if it is thin. In addition, the diffusion of impurities from the formation surface side can be effectively suppressed.

[0051] In this specification, an oxynitride is a compound having a higher oxygen content than nitrogen. Nitrogen oxide refers to a material that contains more nitrogen than oxygen in its composition. For example, when it is written as silicon oxynitride, it means that the composition contains more oxygen than nitrogen. It refers to a material with a high content of oxygen. When it is described as silicon nitride oxide, it means that the composition contains more oxygen than oxygen. This indicates a material that has a higher nitrogen content than other materials.

[0052] In addition, in this specification, oxynitrides and oxynitrides each containing the same element are described. When the oxide nitride is used, the oxygen content is higher than that of the nitride oxide, and The materials include those that meet either one or both of the following criteria: In addition, the oxygen content of the oxynitride is smaller than that of the oxynitride, and the nitrogen content is The materials that satisfy either one or both of the above are included. For example, oxynitride When silicon and silicon oxynitride are mentioned, silicon oxynitride includes silicon oxynitride. The material includes a material that has a higher oxygen content and a lower nitrogen content than silicon. Silicon nitride oxide has a lower oxygen content than silicon oxynitride and a lower nitrogen content. Contains high content materials.

[0053] The insulating film 103c in contact with the semiconductor layer 108 is formed of an insulating film containing an oxide. In particular, it is preferable to use an oxide film for the insulating film 103c. In addition, the insulating film 103c is a dense insulating film whose surface is resistant to adsorption of impurities such as water. It is preferable to use a material that has as few defects as possible and has reduced impurities such as water and hydrogen. It is preferable to use an insulating film having such a structure.

[0054] The insulating film 103c preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating film 103c is an insulating material capable of releasing oxygen when heated. For example, the insulating film 103c is formed in an oxygen atmosphere. The insulating film 103c thus formed is subjected to a heat treatment, a plasma treatment, or the like in an oxygen atmosphere; Alternatively, an oxide film may be formed on the insulating film 103c in an oxygen atmosphere. Oxygen can be supplied into the insulating film 103c. Alternatively, oxygen can be supplied to the insulating film 103c by heating. By forming an insulating film capable of releasing the radiation and then performing a heat treatment, the insulating film is Oxygen may be supplied into the insulating film 103c.

[0055] In addition, a metal oxide film that will become the semiconductor layer 108 is formed by sputtering in an atmosphere containing oxygen. When the insulating film 103c is formed by the above method, oxygen can be supplied to the insulating film 103c. After the metal oxide film that becomes the insulating film 103c is formed, heat treatment is performed to remove oxygen from the insulating film 103c. to the metal oxide film, oxygen vacancies in the metal oxide film can be reduced.

[0056] The insulating film 103c may be, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. Silicon film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film tantalum oxide film, magnesium oxide film, lanthanum oxide film, oxide The insulating layer may include one or more of a cerium film and a neodymium oxide film. It is preferable to use a silicon oxide film or a silicon oxynitride film as the insulating film 103c. .

[0057] The insulating film 103b located between the insulating film 103a and the insulating film 103c has a small stress. It is preferable to use an insulating film formed under conditions of high film formation speed. For example, the insulating film 10 It is preferable that the insulating film 3b has a smaller stress than the insulating film 103a and the insulating film 103c. The insulating film 103b is formed under conditions with a higher film formation rate than the insulating films 103a and 103c. It is preferable that the film is formed under the above-mentioned conditions.

[0058] It is preferable to use an insulating film that releases as little hydrogen and water as possible as the insulating film 103b. By using such an insulating film, the insulation is prevented from being damaged by heat during heating treatment or manufacturing process. The insulating film 103b is formed on the semiconductor layer 108. In this case, the carrier concentration in the channel formation region of the semiconductor layer 108 can be reduced.

[0059] Furthermore, it is preferable to use an insulating film that does not easily absorb oxygen as the insulating film 103b. In other words, it is preferable to use an insulating film through which oxygen does not easily diffuse. Oxygen is supplied from 3c to the semiconductor layer 108 (or the metal oxide film that will become the semiconductor layer 108). When a heat treatment is performed for this purpose, oxygen diffuses from the insulating film 103c to the insulating film 103b. Therefore, the amount of oxygen supplied to the semiconductor layer 108 can be prevented from decreasing.

[0060] The insulating film 103b may be, for example, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, or the like. Insulation containing one or more of aluminum film, hafnium oxide film, aluminum nitride film, and hafnium nitride film In particular, a silicon nitride oxide film or a nitride film can be used as the insulating film 103b. It is preferable to use a silicon membrane.

[0061] Among the insulating films 103a, 103b, and 103c constituting the insulating layer 103, It is preferable that the thickness of the insulating film 103b is the thickest. The thickness of the insulating layer 103 is determined by the relative dielectric constant required for the insulating layer 103 and the dielectric strength required for the insulating layer 103. The dielectric constant and thickness of each insulating film should be determined based on the performance of the insulating film. In other words, the thicknesses of the insulating films can be adjusted to each other within a range that satisfies the above requirements. can.

[0062] In particular, it is preferable that the insulating film 103b is thicker than the insulating film 103a. By making the insulating film 103 thicker than the insulating film 103a, hydrogen is released by heating as the insulating film 103a. Even if a film that is easily oxidized is used, the amount of hydrogen that can reach the insulating film 103c can be reduced. In addition, by making the insulating film 103a thinner than the insulating film 103b, the insulating film 103 Since the volume of a can be made relatively small, the amount of hydrogen that the insulating film 103a can release is reduced. It is possible.

[0063] In addition, the insulating film 103b is preferably thicker than the insulating film 103c. If the insulating film 103c is too thick, the insulating film 103c may become insulated by heating when a process for supplying oxygen into the insulating film 103c is performed. The amount of oxygen remaining in the insulating film 103c without being released increases, resulting in a decrease in the amount of oxygen in the semiconductor layer 1 The amount of oxygen that can be supplied to the metal oxide film that will become the semiconductor layer 108 is reduced. Therefore, the insulating film 103c is made thinner than the insulating film 103b (to reduce the volume). By performing the above-mentioned step, the amount of oxygen remaining in the insulating film 103c after heating can be reduced. The ratio of oxygen supplied to the semiconductor layer 108 out of the oxygen supplied to the insulating film 103c is increased. This allows the amount of oxygen supplied to the semiconductor layer 108 to be effectively increased.

[0064] In addition, the thickest insulating film 103b is formed under conditions of high film formation speed, and a thinner insulating film The insulating film 103a and the insulating film 103c are formed to be dense films under conditions of low film formation rate. As a result, the time required for forming the insulating layer 103 can be shortened without impairing reliability, and productivity can be improved. This can be done.

[0065] Here, the insulating film 103a is an insulating film containing at least silicon and nitrogen. It is preferable to use a silicon nitride film or a silicon nitride oxide film for the insulating film. The insulating film 103b contains at least silicon, nitrogen, and oxygen. Typically, the insulating film is a nitride film. It is preferable to use a silicon oxide film or a silicon oxynitride film. c) is an insulating film containing at least silicon and oxygen, typically a silicon oxide film, It is preferable to use a silicon oxynitride film or a silicon oxide nitride film. The amount of oxygen is preferably greater than that of the insulating film 103a and less than that of the insulating film 103c. Furthermore, the amount of nitrogen contained in the insulating film 103b is less than that of the insulating film 103a. In addition, it is preferable that the thickness is larger than that of the insulating film 103c.

[0066] The oxygen and nitrogen content in the insulating films 103a, 103b, and 103c The amount is determined by secondary ion mass spectrometry (SIMS). ectrometry and X-ray Photoelectron Spectroscopy (XPS) It can be analyzed by analytical methods such as electron spectroscopy. The concentration of the target element is high (e.g. 0.5 atoms / cm 3 or more, or 1 atom s / cm 3 On the other hand, when the content of the target element in the film is low, XPS is suitable. (e.g. 0.5 atoms / cm 3 or less than 1atoms / cm 3 In the following cases When comparing the content of elements in a film, both SIMS and XPS are suitable. It is more preferable to perform a combined analysis using both analytical methods.

[0067] The thickness of the insulating film 103b is at least twice, preferably three times, the thickness of the insulating film 103a. More preferably, it is 5 times or more, and 20 times or less, preferably 15 times or less. It is preferable that the thickness of the insulating film 103b is at least twice as thick as the thickness of the insulating film 103c. , preferably 3 times or more, more preferably 5 times or more, and 20 times or less, preferably 15 times or less It is preferable that the above upper and lower limits are combined in any manner. It is possible.

[0068] The thickness of the insulating film 103b is 100% of the total thickness of the insulating layer 103. When the ratio is 34% or more, preferably 40% or more, more preferably 50% or more, Preferably, it is 60% or more, more preferably, 70% or more, and even more preferably, 80% or more. Therefore, the thickness of the insulating layer 103 can be 95% or less, or 90% or less. The higher the ratio of the thickness of the insulating film 103b, the higher the productivity can be.

[0069] It is preferable that the insulating film 103a is as thin as possible, for example, 5 nm or more, and preferably 8 nm or more. m or more, more preferably 10 nm or more, and even more preferably 15 nm or more. m or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 The above upper and lower limits can be arbitrarily combined. Typically, the thickness is 15 nm to 50 nm, or 15 nm to 20 nm. The lower film thickness is preferable.

[0070] It is also preferable that the insulating film 103c is as thin as possible, for example, 5 nm or more, and preferably 8 nm or more. m or more, more preferably 10 nm or more, and even more preferably 15 nm or more. m or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 The above upper and lower limits can be arbitrarily combined. Typically, the thickness is 15 nm to 50 nm, or 15 nm to 20 nm. The lower film thickness is preferable.

[0071] It is preferable that both the insulating film 103a and the insulating film 103c are as thin as possible. It is extremely important that the film can be formed under conditions with little variation according to the performance of the device. Therefore, the insulating film 103a and the insulating film 103c are each formed so that the variations are sufficiently small. It is therefore preferable to select a minimum thickness.

[0072] The insulating film 103b is determined so as to satisfy the required physical properties such as the relative dielectric constant and the withstand voltage. The total thickness of the insulating layer 103 is calculated by subtracting the thickness of the insulating film 103a and the insulating film 103c. For example, the insulating film 103b may be 20 nm or more, 50 nm or more, or 100 nm or more. or more, 150nm or more, or 200nm or more, and 500nm or less, 400nm or less It is preferable that the thickness is 350 nm or less. Any combination of values ​​can be used.

[0073] Among the insulating films 103a, 103b, and 103c, the insulating film 103b However, the film density of the insulating layer 103 may be smaller than that of the other two insulating films. Cross-sectional Transmission Electron Microscope (TEM) In the microscopy images, etc., the insulating film 103a, The insulating film 103b and the insulating film 103c are observed as different in contrast, and are distinguished from each other. In particular, the insulating film 103a and the insulating film 103b may be subjected to plasma CV Even when a silicon nitride film or a silicon oxynitride film formed by the D method is used, In some cases, it may be possible to confirm the boundary between these two. In addition, when the composition and density are similar, The boundaries between these may be unclear.

[0074] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited. , single crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors Either a single crystal semiconductor or a semiconductor having a crystalline region in part may be used. It is preferable to use a semiconductor having crystallinity because this can suppress deterioration of the transistor characteristics. .

[0075] The semiconductor layer of the transistor preferably contains a metal oxide (also called an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may include silicon. For this purpose, amorphous silicon, crystalline silicon (low-temperature polysilicon, single crystal silicon, etc.) etc.)

[0076] When a metal oxide is used as the semiconductor layer 108, for example, indium and M (M is Gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, Lithium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum , cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. It is preferable that M is aluminum or zinc. It is preferable that the metal is one or more selected from the group consisting of aluminum, gallium, yttrium, and tin. I wish.

[0077] In particular, indium (In), gallium (Ga), and zinc (Zn) are used as the semiconductor layer. It is preferable to use an oxide containing IGZO (also referred to as IGZO).

[0078] In addition to indium, gallium, and zinc, aluminum, silicon, and the like can be used as semiconductor layers. Silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel Kel, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium Oxides containing one or more of nium, tantalum, tungsten, or magnesium In particular, in addition to indium, gallium, and zinc, Using oxides containing tin, aluminum, or silicon, high field effect mobility can be achieved. This is preferable because it can be used as a realized transistor.

[0079] When the semiconductor layer is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The sputtering target preferably has an atomic ratio of In to M of 1 or more. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn. =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In: M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1 , In:M:Zn=5:1:3, In:M:Zn=10:1:3, In:M:Zn=5: 1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn= 6:1:6, In:M:Zn=5:2:5, etc. When two or more elements are contained as the atomic ratio, the ratio of M in the above atomic ratio is It corresponds to the sum of the numbers of atoms of the group elements.

[0080] When a sputtering target containing a polycrystalline oxide is used, This is preferable because it is easy to form a semiconductor layer having crystallinity. The atomic ratio is the plus or minus of the atomic ratio of the metal elements contained in the sputtering target. For example, the composition of the sputtering target used for the semiconductor layer is When the atomic ratio of In:M:Zn is 4:2:4.1, the composition of the semiconductor layer is I The atomic ratio may be close to n:M:Zn=4:2:3.

[0081] In addition, when the atomic ratio is described as In:M:Zn=4:2:3 or close to that, In is 4, M is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When describing that the atomic ratio is In:M:Zn=5:1:6 or close to that, In this case, M is greater than 0.1 and is equal to or less than 2, and Zn is equal to or greater than 5 and is equal to or less than 7. In addition, when describing that the atomic ratio is In:M:Zn=1:1:1 or close to that, When In is 1, M is greater than 0.1 and is equal to or less than 2, and Zn is greater than 0.1. Including cases where it is 2 or less.

[0082] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 is made of at least insulator. It is preferable that the semiconductor layer 108 contains a metal oxide containing sodium and oxygen. In addition, the semiconductor layer 108 may contain zinc. stomach.

[0083] Here, the composition of the semiconductor layer 108 has a significant effect on the electrical characteristics and reliability of the transistor 10. For example, increasing the indium content in the semiconductor layer 108 affects the carrier The mobility is improved, and a transistor with high field effect mobility can be realized.

[0084] Here, as one of the indicators for evaluating the reliability of a transistor, Gate Bias Stress Test (GBT) Among them, the gate potential is determined by the source potential and the drain potential. A test in which a positive potential is applied and the material is held at high temperature is called PBTS (Positive Bias Test). s Temperature Stress test, with a negative potential applied to the gate, The test to hold the material at high temperatures is called NBTS (Negative Bias Temperature Test). It is called the PB Stress test, which is performed under the irradiation of white LED light, etc. The TS test and the NBTS test are respectively PBTIS (Positive Bias Test Insulation Specification) mperature Illumination Stress) test, NBTIS(N egative Bias Temperature Illumination St This is called the ress test.

[0085] In particular, in an n-type transistor using an oxide semiconductor, Since a positive potential is applied to the gate when the device is placed in a state where current flows, The amount of variation in threshold voltage is one of the important indicators of transistor reliability. It becomes.

[0086] Here, the composition of the semiconductor layer 108 does not contain gallium or has a gallium content of By using a metal oxide film with low resistance, the variation in threshold voltage during PBTS testing is reduced. In addition, when gallium is contained, the composition of the semiconductor layer 108 may be indium. It is preferable to have a lower gallium content than the tungsten content. Therefore, a highly reliable transistor can be realized.

[0087] One factor that causes the threshold voltage fluctuation in the PBTS test is the difference between the semiconductor layer and the gate insulating layer. The defect level at or near the interface is one of the causes. The higher the defect level density, the higher the PB Degradation in the TS test becomes evident. By reducing the content of arsenic, the generation of the defect levels can be suppressed.

[0088] No gallium or low gallium content suppresses PBTS degradation The reason why this can be achieved is considered to be, for example, as follows. Gallium attracts oxygen more easily than other metallic elements (such as indium and zinc). Therefore, the metal oxide film containing a large amount of gallium and the insulating layer 11 containing oxide are At the interface with 0, gallium combines with excess oxygen in the insulating layer 110, and the carriers It is assumed that this makes it easier to create (electron) trap sites. When a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer. This may cause the threshold voltage to fluctuate.

[0089] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, the In atoms A metal oxide film having a larger atomic ratio than that of Ga can be applied to the semiconductor layer 108. In addition, by using a metal oxide film in which the atomic ratio of Zn is larger than the atomic ratio of Ga, In other words, the atomic ratio of the metal elements is more preferably In>Ga and Zn>G. It is preferable to use a metal oxide film that satisfies a for the semiconductor layer 108.

[0090] For example, the atomic ratio of metal elements in the semiconductor layer 108 is In:Ga:Zn=2:1: 3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn =4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5 :1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5:2:5, or A metal oxide film, which is in the vicinity of the above, can be used.

[0091] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, The ratio of the number of gallium atoms to the number of atoms of the metal element contained in the metal oxide (atomic ratio) is , greater than 0 and less than 50%, preferably 0.05% or more and 30% or less, more preferably 0. The content can be set to 1% or more and 15% or less, and more preferably, 0.1% or more and 5% or less. By including gallium in the semiconductor layer 108, oxygen deficiency is less likely to occur. It plays a key role.

[0092] Alternatively, a metal oxide film not containing gallium may be used for the semiconductor layer 108. For example, In this case, In-Zn oxide can be applied to the semiconductor layer 108. By increasing the ratio of the number of In atoms to the number of metal element atoms in On the other hand, the number of atoms of the metal element contained in the metal oxide is By increasing the atomic ratio of Zn to Tn, a metal oxide film with high crystallinity is obtained. Fluctuations in the electrical characteristics of the transistor are suppressed, and the reliability can be improved. For 8, a metal oxide film that does not contain gallium or zinc, such as indium oxide, may be applied. By using a metal oxide film that does not contain gallium, the The variation in threshold voltage can be made extremely small.

[0093] For example, the semiconductor layer 108 can be made of an oxide containing indium and zinc. In this case, the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or Alternatively, a metal oxide film in the vicinity of these can be used.

[0094] In the transistor 10 according to one embodiment of the present invention, the semiconductor layer 108 is made of a gold material having a low content of gallium. A gallium-containing metal oxide film or a gallium-free metal oxide film is applied, and a semiconductor layer 10 is further applied. The insulating layer 110 in contact with the upper surface of the semiconductor layer 108 is a layer having a structure that reduces damage to the semiconductor layer 108. The film formed by the film forming method is used. Therefore, the interface between the semiconductor layer 108 and the insulating layer 110 Therefore, the defect state density in the semiconductor device is reduced, and the transistor 10 can have high reliability. Cut.

[0095] Although gallium has been described as a representative example here, element M (M is , Aluminum, Silicon, Boron, Yttrium, Tin, Copper, Vanadium, Beryllium , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium selected from the group consisting of aluminum, neodymium, hafnium, tantalum, tungsten, and magnesium In particular, M is gallium, aluminum, It is preferable that the metal oxide is one or more selected from the group consisting of tin, yttrium, and tin.

[0096] In particular, the semiconductor layer 108 contains a metal oxide in which the atomic ratio of In is higher than the atomic ratio of the element M. It is preferable to apply a film of the metal in which the atomic ratio of Zn is higher than the atomic ratio of the element M. It is preferred to apply an oxide film.

[0097] It is preferable to use a metal oxide film having crystallinity for the semiconductor layer 108. For example, CAAC (c-axis aligned crystal) structure, nc (na A metal oxide film having a (no crystal) structure, a polycrystalline structure, a microcrystalline structure, etc. is used. By using a crystalline metal oxide film for the semiconductor layer 108, The defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0098] As the semiconductor layer 108 has a higher crystallinity, the density of defect states in the film can be reduced. A transistor that can pass a large current by using a metal oxide film with low crystallinity It is possible to achieve this.

[0099] When forming a metal oxide film by sputtering, the substrate temperature (stage temperature) during film formation is The higher the concentration of the metal oxide, the higher the crystallinity of the metal oxide film. The higher the ratio of the flow rate of oxygen gas to the total deposition gas (also called the oxygen flow rate ratio), the better the deposition efficiency. It is possible to form a metal oxide film having high crystallinity. The crystallinity of the film can be controlled by the substrate temperature and the oxygen flow rate ratio in the deposition gas.

[0100] [Configuration Example 1-2] FIG. 1B is a schematic cross-sectional view of the transistor 10A. The main difference compared to transistor 10 is that it has a conductive layer 106 .

[0101] The conductive layer 106 is connected to the insulating layer 103 via the semiconductor layer 108, the insulating layer 110, and the metal oxide layer 111. The conductive layer 106 has a region overlapping with the first gate electrode 114 and the conductive layer 112. The insulating layer 103 functions as a first gate insulating film (also referred to as a back gate electrode). At this time, the conductive layer 112 functions as a second gate electrode (also called a top gate electrode). ), and insulating layer 110 functions as a second gate insulating layer.

[0102] For example, transistor 10A is configured such that conductive layer 112 and conductive layer 106 are applied with the same potential. This allows a larger current to flow when the transistor is on. The transistor 10A has a threshold voltage control layer for one of the conductive layers 112 and 106. a potential for controlling the on / off state of the transistor 10A is applied to the other side. In addition, one of the conductive layer 112 and the conductive layer 106 and the source may be electrically connected to the By connecting it to the transistor 10A, it is possible to stabilize the electrical characteristics of the transistor 10A.

[0103] The insulating layer 103 is made up of an insulating film 103a, an insulating film 103b, and an insulating film 103c from the conductive layer 106 side. The insulating film 103a is in contact with the conductive layer 106. The insulating film 103c is in contact with the semiconductor layer .

[0104] The insulating layer 103 functioning as the first gate insulating layer has a high withstand voltage and a small film stress. The conductive layer 106 is preferably made of a material having a low resistance to hydrogen and water release, has few defects in the film, and is preferably made of a material having a low resistance to hydrogen and water release. It is preferable to satisfy at least one of the above requirements. It is most preferable to satisfy all of the above.

[0105] The insulating film 103a is a dense film that can prevent the diffusion of impurities from below. It is preferable that the insulating film 103a be capable of blocking a metal element contained in the conductive layer 106. Therefore, the insulating film 103a is preferably a film having an insulating film 103b or an insulating film. Applying an insulating film formed under conditions with a lower film formation rate than either one or both of 103c. It is possible.

[0106] [Configuration Example 1-3] FIG. 2A is a schematic cross-sectional view of a transistor 10B. The main difference compared to the transistor 10 is that the configuration of the semiconductor layer 108 is different.

[0107] The semiconductor layer 108 of the transistor 10B is formed by stacking the semiconductor layer 108 from the insulating layer 103 side. The semiconductor layer 108a and the semiconductor layer 108b are stacked together. It is preferable that metal oxide films are used for the layers 108a and 108b.

[0108] For the sake of simplicity, the low resistance region of the semiconductor layer 108a and the semiconductor layer 10 The low resistance region of the first and second electrodes 8b is collectively referred to as a low resistance region 108n, and is indicated by the same hatching pattern. In reality, the composition of the semiconductor layer 108a and the composition of the semiconductor layer 108b are different. Since the electrical resistivity, carrier concentration, oxygen vacancy amount, hydrogen concentration, Or, the impurity concentration may be different.

[0109] The semiconductor layer 108b is in contact with the upper surface of the semiconductor layer 108a and the lower surface of the insulating layer 110. The semiconductor layer 108b is made of the same material as that used for the semiconductor layer 108 in the above configuration example 1-1. A metal oxide film capable of being bonded to the substrate can be applied.

[0110] On the other hand, the semiconductor layer 108a is a metal oxide film having a higher atomic ratio of M than the semiconductor layer 108b. In particular, indium, gallium, and zinc can be used for the semiconductor layer 108a. It is preferable to use a metal oxide film containing gallium and having a higher atomic ratio of gallium than the semiconductor layer 108b. I wish.

[0111] Gallium has a stronger bond with oxygen than indium, so the high atomic ratio of gallium By using a thin metal oxide film for the semiconductor layer 108a, oxygen vacancies are less likely to be formed. If there are many oxygen vacancies in the conductor layer 108a, the electrical characteristics and reliability of the transistor are deteriorated. Therefore, the semiconductor layer 108a contains more gallium atoms than the semiconductor layer 108b. By using a metal oxide film with a high molecular weight ratio, it is possible to produce a transistor with good electrical properties and high reliability. It is possible to realize Zister 10B.

[0112] More specifically, the semiconductor layer 108a is a gold layer containing indium, gallium, and zinc. The atomic ratio of gallium is higher than that of the semiconductor layer 108b. The metal oxide film preferably has a region in which the atomic ratio of sodium is lower than that of the semiconductor layer 108b. In other words, the semiconductor layer 108b can be made of a material having a higher conductivity than the semiconductor layer 108a. In comparison, the atomic ratio of indium is high and the atomic ratio of gallium is low. A metal oxide film can be used.

[0113] In addition, the semiconductor layer 108a may have a region in which the atomic ratio of zinc is equal to that of the semiconductor layer 108b. or a metal oxide film having a region in which the atomic ratio of zinc is lower than that of the semiconductor layer 108b. It is preferred.

[0114] The semiconductor layer 108a may have an atomic ratio of metal elements of, for example, In:Ga:Zn=1: 1:1, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga: Zn=1:3:6, In:Ga:Zn=2:2:1, or a metal oxide having a ratio of about 1:3:6, In:Ga:Zn=2:2:1, or ... A nitride film can be used.

[0115] Typically, the atomic ratio of metal elements in the semiconductor layer 108a is In:Ga:Zn=1:1: The semiconductor layer 108b is formed of a metal oxide film having an atomic ratio of I n:Ga:Zn=4:2:3, In:Ga:Zn=5:1:6, or gold in the vicinity of these It is preferable to use a metal oxide film.

[0116] Alternatively, it is preferable to use a metal oxide film that does not contain gallium for the semiconductor layer 108b. For example, it is preferable to use an oxide containing indium and zinc for the semiconductor layer 108b. In this case, the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1. , or a metal oxide film in the vicinity thereof can be used.

[0117] In addition, by using a metal oxide film in which oxygen vacancies are unlikely to occur as the semiconductor layer 108a, This can reduce the degradation in the NBTIS test described above.

[0118] The transistor 10B shown in FIG. 2A includes a semiconductor layer 108a located on the insulating layer 103 side. By using a metal oxide film having a relatively high gallium content, Furthermore, the semiconductor layer 108b located on the insulating layer 110 side is provided with gallium. By using a metal oxide film with a low gallium content or without gallium, the semiconductor layer 1 The interface defect density between the GaN layer 08 and the insulating layer 110 is reduced. Thus, the transistor 10B This transistor has both extremely high electrical characteristics and extremely high reliability.

[0119] Here, it is preferable that the semiconductor layer 108b is formed thinner than the semiconductor layer 108a. Even if the semiconductor layer 108b is an extremely thin film, for example, having a thickness of 0.5 nm or more and 10 nm or less, The density of defects at the interface with the insulating layer 110 can be reduced. By making the layer 108a relatively thick, a more reliable transistor can be realized. can be done.

[0120] For example, the thickness of the semiconductor layer 108a is set to 1.5 times or more and 2 times or more as thick as the semiconductor layer 108b. 0 times or less, preferably 2 times or more and 15 times or less, and more preferably 3 times or more and 10 times or less. The thickness of the semiconductor layer 108b is preferably 0.5 nm or more and 30 nm or less. The thickness is preferably 1 nm or more and 20 nm or less, and more preferably 2 nm or more and 10 nm or less. stomach.

[0121] The semiconductor layer 108a and the semiconductor layer 108b are formed of the above-mentioned metal oxide film having crystallinity. It is preferable to use a highly crystalline gold film for both the semiconductor layer 108a and the semiconductor layer 108b. Alternatively, a metal oxide film having low crystallinity may be used. The semiconductor layer 108a and the semiconductor layer 108b may have different crystallinity. The semiconductor layer 108a may be a film having a higher crystallinity than the semiconductor layer 108b. The semiconductor layer 108a and the semiconductor layer b may be a film having higher crystallinity than the semiconductor layer 108a. The crystallinity of the metal oxide film used for 108b is important to ensure the required electrical characteristics and reliability of the transistor. The thickness can be determined based on the properties of the material and the specifications of the deposition apparatus.

[0122] [Configuration Example 1-4] FIG. 2B is a schematic cross-sectional view of the transistor 10C. The transistor 10B illustrated in the configuration example 1-3 (FIG. 2A) is This is an example in which the conductive layer 106 of the transistor 10A illustrated in (B) is used. .

[0123] By adopting such a configuration, a transistor having good electrical characteristics and extremely high reliability can be obtained. This makes it possible to realize

[0124] [Configuration Example 1-5] FIG. 3A is a schematic cross-sectional view of a transistor 10D. The main difference compared to transistor 10 is that the insulating layer 110 has a different configuration.

[0125] The insulating layer 110 is made up of an insulating film 110a, an insulating film 110b, and an insulating film 110c from the insulating layer 103 side. The insulating film 110a has a layered structure in which the semiconductor layer 108 and the insulating film 110b are stacked in this order. The insulating film 110c has a region in contact with the channel forming region. The insulating film 110b is located between the insulating film 110a and the insulating film 110c.

[0126] The insulating films 110a, 110b, and 110c are each an insulating film containing an oxide. In this case, the insulating film 110a, the insulating film 110b and the insulating film 110 It is preferable that the layers c and c are successively formed in the same film forming apparatus.

[0127] The insulating films 110a, 110b, and 110c are, for example, silicon oxide. silicon oxide film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, oxide Contains one or more of magnesium oxide, lanthanum oxide, cerium oxide, and neodymium oxide films An insulating layer may be used.

[0128] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a stacked structure of oxide insulating films. In addition, the insulating layer 110 may have a region that contains oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is preferably an insulating film capable of releasing oxygen. For example, the insulating layer 110 is formed in an oxygen atmosphere. After the insulating layer 110 is formed, a heat treatment is performed in an oxygen atmosphere. Alternatively, an oxide film may be formed on the insulating layer 110 in an oxygen atmosphere. By using the above-mentioned oxygen supplying method, oxygen can be supplied into the insulating layer 110. In the process, instead of or in addition to oxygen, an oxidizing gas (e.g., nitrous oxide or , ozone, etc.) may also be used.

[0129] The insulating films 110a, 110b, and 110c are formed by, for example, a sputtering method. It can be formed by using a CVD method, a vacuum deposition method, a PLD method, an ALD method, etc. The VD method includes a plasma CVD method and a thermal CVD method.

[0130] In particular, the insulating films 110a, 110b, and 110c are formed by plasma CVD. It is preferable to form the

[0131] Since the insulating film 110a is formed on the semiconductor layer 108, it is necessary to form the insulating film 110a so as to be as close to the semiconductor layer 108 as possible. It is preferable that the film is formed under conditions that do not cause damage. For example, the film formation speed ( The deposition rate (also called deposition rate) can be sufficiently low.

[0132] For example, a silicon oxynitride film is formed as the insulating film 110a by a plasma CVD method. In this case, the damage to the semiconductor layer 108 can be minimized by forming the semiconductor layer 108 under low power conditions. It can be made smaller.

[0133] The deposition gas used in the deposition of the silicon oxynitride film is, for example, silane, disilane, or other silane gas. Deposition gases including oxynitride and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. In addition to the source gas, argon, helium, Alternatively, a diluent gas such as nitrogen may be included.

[0134] For example, the ratio of the flow rate of the deposition gas to the total flow rate of the deposition gas (hereinafter, simply referred to as the flow rate ratio) By reducing the thickness, the deposition rate can be reduced, and a dense film with fewer defects can be formed. can.

[0135] The insulating film 110b is a film formed under conditions of a higher film formation rate than the insulating film 110a. This makes it possible to improve productivity.

[0136] For example, the insulating film 110b is formed under the condition that the flow rate ratio of the deposition gas is higher than that of the insulating film 110a. This allows the film to be formed under conditions with an increased film formation rate.

[0137] The insulating film 110c has reduced surface defects and is resistant to impurities such as water contained in the air. For example, similar to the insulating film 110a, The film can be formed under conditions where the film formation rate is sufficiently low.

[0138] In addition, since the insulating film 110c is formed on the insulating film 110b, it is The insulating film 110c has little effect on the semiconductor layer 108 when it is formed. The insulating film 110c can be deposited under higher power conditions than the insulating film 110a. By reducing the amount of ZnO and depositing the film at a relatively high power, a dense film with reduced surface defects can be obtained. It is possible.

[0139] That is, the deposition rate of the insulating film 110b is the highest, and the deposition rate of the insulating film 110a and the insulating film 110c is the highest. The insulating layer 110 can be formed using stacked films formed under conditions in which the temperature is lower than that of the insulating layer 110 . In addition, the insulating layer 110 is etched under the same conditions in wet etching or dry etching. The etching rate at 100° C. is the highest for the insulating film 110b, and the etching rates at 100° C. are the highest for the insulating film 110a and the insulating film 110c. The order goes down.

[0140] The insulating film 110b is formed thicker than the insulating films 110a and 110c. It is preferable to form the insulating film 110b having the fastest film formation rate thicker. The time required for the film formation process can be shortened.

[0141] Here, the boundary between the insulating film 110a and the insulating film 110b and the boundary between the insulating film 110b and the insulating film 110 Since the boundaries of c may be unclear, these boundaries are indicated by dashed lines in Figure 3(A) and elsewhere. Since the insulating film 110a and the insulating film 110b have different film densities, In a transmission electron microscope image of a cross section of 0, these boundaries are distinguished by differences in contrast. Similarly, the boundary between the insulating film 110b and the insulating film 110c may be observed as In some cases, the field can also be observed as a difference in contrast.

[0142] The transistor 10D of one embodiment of the present invention has a semiconductor layer 108 containing a small amount of gallium. It is preferable to use a metal oxide film or a metal oxide film that does not contain gallium. Further, as the insulating film 110a in contact with the upper surface of the semiconductor layer 108, a diaphragm provided to the semiconductor layer 108 is It is preferable to use a film formed by a film formation method in which image damage is reduced. The defect level density at the interface between the layer 108 and the insulating layer 110 is reduced, resulting in a highly reliable transistor. The transistor may be 10D.

[0143] [Configuration Example 1-6] FIG. 3B is a schematic cross-sectional view of the transistor 10E. The transistor 10D illustrated in the configuration example 1-5 (FIG. 3A) was This is an example in which the conductive layer 106 of the transistor 10A illustrated in (B) is used. .

[0144] By adopting such a configuration, a transistor having good electrical characteristics and extremely high reliability can be obtained. This makes it possible to realize

[0145] In addition, the transistor 10D illustrated in the configuration example 1-5 and the transistor 10E illustrated in the configuration example 1-6 The transistor 10E has a laminated structure applied to the transistor 10B illustrated in the configuration example 1-3. It is also possible to use the semiconductor layer 108 having a structure having a good electrical property. It is possible to realize a highly reliable transistor.

[0146] [Configuration example 2] A more specific example of the configuration of a transistor will be described below.

[0147] [Configuration Example 2-1] FIG. 4A is a top view of a transistor 100, and FIG. 4B is a top view of the transistor 100 shown in FIG. FIG. 4(C) corresponds to a cross-sectional view taken along the dashed line A1-A2 shown in FIG. It corresponds to a cross-sectional view taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as a gate insulating layer) are omitted in the figure. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B2 direction is the channel width direction. In addition, the top view of the transistor is the same as that of FIG. Similarly, some of the components are omitted in the drawings.

[0148] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating The semiconductor device includes an edge layer 110, a metal oxide layer 114, a conductive layer 112, and an insulating layer 118. The dielectric layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided on the upper surface of the insulating layer 103, The metal oxide layer 114 and the conductive layer 115 are provided in contact with the upper surface and the side surface of the semiconductor layer 108. The layer 112 is stacked in this order on the insulating layer 110, and a portion overlapping with the semiconductor layer 108 is The insulating layer 118 is formed on the top surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the conductive layer. The conductive layer 112 is disposed on the upper surface of the conductive layer 112 .

[0149] The insulating layer 103 is made up of an insulating film 103a, an insulating film 103b, and an insulating film 103c from the substrate 102 side. The insulating layer 110 is insulated from the semiconductor layer 108 side. The insulating film 110a, the insulating film 110b, and the insulating film 110c are laminated to form a laminate structure.

[0150] As shown in FIGS. 4A and 4B, the transistor 100 includes an insulating layer 118. The conductive layer 120a and the conductive layer 120b may be disposed on the conductive layer 120a. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The openings 141a and 120b are provided in the insulating layer 118 and the insulating layer 110, respectively. is electrically connected to the low resistance region 108n through the opening 141b.

[0151] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 includes a gate electrode provided on the semiconductor layer 108. In other words, it is a so-called top-gate transistor.

[0152] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes are roughly the same as each other. It has been done.

[0153] In this specification, the term "approximately coincident upper surface shapes" means that there is at least a slight difference between the layers. For example, the upper and lower layers have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where a part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0154] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing into the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, It is preferable to use a material that is less permeable to oxygen and hydrogen than zero.

[0155] The metal oxide layer 114 makes it easier for the conductive layer 112 to absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 can be prevented from Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 through the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0156] The metal oxide layer 114 can be made of an insulating material or a conductive material. When the metal oxide layer 114 has insulating properties, the metal oxide layer 114 is a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has electrical conductivity, the metal oxide layer 1 14 functions as a part of the gate electrode.

[0157] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a gate film or the like since the driving voltage can be reduced.

[0158] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). Conductive oxides such as silicon-doped indium tin oxide (ITSO) In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0159] The metal oxide layer 114 may be made of an oxide material containing at least one of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same structure as the semiconductor layer 108 as the metal oxide layer 114. By applying metal oxide films formed using sputtering targets, equipment can be standardized This is preferable because it allows

[0160] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0161] A metal oxide film that can be used for the metal oxide layer 114 is formed, and the insulating layer 110 is Alternatively, oxygen may be supplied to the semiconductor layer 108, and then the metal oxide film may be removed. In addition, the metal oxide layer 114 or a metal oxide film that can be used for the metal oxide layer 114 If not required, it need not be provided.

[0162] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions sandwiching the region. A region of the semiconductor layer 108 overlapping with the conductive layer 112 corresponds to the transistor 1 On the other hand, the pair of low resistance regions 108n function as a channel forming region of the transistor. The gate electrodes 102 function as the source and drain regions of the MOSFET 100 .

[0163] The low-resistance region 108n is a region having a lower resistance and a carrier concentration than the channel formation region. These regions are also called high-density regions, high-density oxygen vacancies regions, high-density impurity regions, or n-type regions. It can be said.

[0164] The low resistance region 108n of the semiconductor layer 108 may be a region containing an impurity element. The impurity elements include, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and a Examples of rare gases include aluminum and rare gases. A typical example of a rare gas is helium. , neon, argon, krypton, and xenon. In particular, those containing boron or phosphorus It is preferable that the composition contains two or more of these elements.

[0165] As described later, the process of doping the low resistance region 108n with impurities is performed by masking the conductive layer 112. As a result, the insulating layer 110 can be interposed therebetween.

[0166] The low resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×1 0 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 That's it, 5x 10 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 End , 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0167] The concentration of impurities contained in the low resistance region 108n can be measured by, for example, secondary ion mass spectrometry (SIM S: Secondary Ion Mass Spectrometry, X-ray photoelectron XPS: X-ray Photoelectron Spectroscop When XPS analysis is used, the surface side or By combining ion sputtering from the backside and XPS analysis, You can see the degree distribution.

[0168] In addition, in the low resistance region 108n, the impurity element is present in an oxidized state. For example, boron, phosphorus, magnesium, aluminum, and silicon are used as impurity elements. It is preferable to use an element that is easily oxidized, such as silicon. Such an element that is easily oxidized is Since the oxidized state of the fluorine-containing oxide can be stably present by bonding with oxygen in the semiconductor layer 108, the fluorine-containing oxide can be stably present in the subsequent process. When exposed to high temperatures (e.g., 400°C or higher, 600°C or higher, or 800°C or higher) Even if an impurity element is present, the desorption is suppressed. As a result, many oxygen vacancies are generated in the low resistance region 108n. The low resistance region 108n has an extremely low resistance because the hydrogen atoms bond with the low resistance region 108n to become a carrier supply source. It becomes an resistant state.

[0169] For example, when boron is used as an impurity element, the boron contained in the low resistance region 108n can exist in a state of being bound to oxygen. This is confirmed by the XPS analysis. 2 O 3 To join This can be confirmed by observing the spectrum peaks caused by the above phenomenon. Spectral peaks due to the existence of elemental boron are not observed or are not observed. The peak intensity is so low that it is buried in the background noise observed near the lower limit of the and becomes smaller.

[0170] The insulating layer 110 is a region that contacts the channel formation region of the semiconductor layer 108, i.e., the conductive layer 1 The insulating layer 110 has a region overlapping with the low resistance region 10 of the semiconductor layer 108. The conductive layer 8n has a region that does not overlap with the conductive layer 112.

[0171] The region of the insulating layer 110 overlapping with the low resistance region 108n contains the above-mentioned impurity element. At this time, the impurity elements in the insulating layer 110 may be removed, similarly to the low resistance region 108n. It is preferable that such easily oxidized elements exist in a state of being bonded to oxygen. Since it can bond with oxygen in the layer 110 and remain stable in an oxidized state, it can be used at high temperatures in subsequent processes. In particular, the insulating layer 110 is prevented from being desorbed even when the insulating layer 110 is heated. In the case where oxygen that can be separated (also called excess oxygen) is contained, the excess oxygen and the impurity element are Oxygen is supplied from the insulating layer 110 to the low resistance region 108n to bond and stabilize it. In addition, the part of the insulating layer 110 containing the impurity element in an oxidized state can be suppressed. Since oxygen is less likely to diffuse into the insulating layer 110, the insulating layer 11 0, the supply of oxygen to the low resistance region 108n is suppressed, and the low resistance region 108n It is also possible to prevent the resistance of the capacitor from increasing.

[0172] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon oxide, silicon oxynitride, silicon nitride, and silicon nitride oxide. , aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, haf For example, an inorganic insulating material such as tungsten aluminate can be used.

[0173] [Configuration Example 2-2] FIG. 5A is a top view of a transistor 100A, and FIG. 5B is a top view of a transistor 100B. 5(A) is a cross-sectional view of the channel length direction of the transistor 100A, and FIG. 5(B) is a cross-sectional view of the channel width direction of the transistor 100A. 1 is a cross-sectional view in the direction.

[0174] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. The main difference from the configuration example 2-1 is that the conductive layer 106 is made of the semiconductor layer 108 and the conductive layer 112. It has an overlapping area with.

[0175] In the transistor 100A, the conductive layer 112 is a second gate electrode (a top gate electrode). The conductive layer 106 functions as a first gate electrode (also called a bottom gate electrode). A part of the insulating layer 110 functions as a second gate insulating layer. and a part of the insulating layer 103 functions as a first gate insulating layer.

[0176] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 is It will function as a channel formation region. In the following, for ease of explanation, the semiconductor layer 108 The portion overlapping with the conductive layer 112 is sometimes called a channel formation region. The portion that does not overlap with the conductive layer 102 but overlaps with the conductive layer 106 (the portion including the low resistance region 108n) is also A channel can be formed.

[0177] As shown in FIG. 5C, the conductive layer 106 is formed by a metal oxide layer 114 and an insulating layer 110. and is electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 103. In this way, the conductive layer 106 and the conductive layer 112 can be given the same potential. can be done.

[0178] The conductive layer 106 may be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. This is preferable because

[0179] As shown in FIGS. 5A and 5C, the conductive layer 11 2 and the conductive layer 106 preferably protrude outward beyond the end of the semiconductor layer 108. At this time, as shown in FIG. 5C, the entire semiconductor layer 108 in the channel width direction is insulated. The layer 110 and the insulating layer 103 are interposed between the conductive layer 112 and the conductive layer 106 .

[0180] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by a pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108 in order to induce a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0181] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. At this time, the potential applied to one of the gate electrodes of the transistor 100 It is also possible to control the threshold voltage when A is driven by the other gate electrode.

[0182] In addition, the conductive layer 106 is electrically connected to the conductive layer 120a or the conductive layer 120b. At this time, the openings in the insulating layer 118, the insulating layer 110, and the insulating layer 103 may be The conductive layer 120a or the conductive layer 120b is electrically connected to the conductive layer 106 via the portion. It is sufficient to adopt such a configuration.

[0183] [Configuration Example 2-3] FIG. 6A is a top view of a transistor 100B, and FIG. 6B is a top view of a transistor 100C. 6(C) is a cross-sectional view of the channel length direction of the transistor 100B, and FIG. 6(D) is a cross-sectional view of the channel width direction of the transistor 100B. 1 is a cross-sectional view in the direction.

[0184] The transistor 100B has an insulating property different from that of the transistor 100 illustrated in the configuration example 2-1. The main differences are the different composition of the edge layer 110 and the inclusion of an insulating layer 116 .

[0185] The insulating layer 110 is formed so that the top surface shape is approximately the same as that of the conductive layer 112 and the metal oxide layer 114. The insulating layer 110 is processed, for example, by processing a conductive layer 112 and a metal oxide layer 114. The insulating film can be formed by processing the insulating film using a resist mask.

[0186] The insulating layer 116 is formed by bonding the conductive layer 112, the metal oxide layer 114, and the insulating layer 116 of the semiconductor layer 108. The insulating layer 116 is provided in contact with the upper surface and the side surface that are not covered by the insulating film 10. The top surface of layer 103, the side surface of insulating layer 110, the side surface of metal oxide layer 114, and the bottom surface of conductive layer 112 It is provided covering the top and sides.

[0187] The insulating layer 116 has a function of lowering the resistance of the low-resistance region 108n. The insulating layer 116 is formed by heating during or after the formation of the insulating layer 116. An insulating film capable of supplying impurities into the region 108n can be used. By heating the insulating layer 116 during or after its formation, an oxide is formed in the low resistance region 108n. An insulating film capable of generating elemental defects can be used.

[0188] For example, the insulating layer 116 may function as a source of impurities to the low resistance region 108n. In this case, the insulating layer 116 can be formed of an insulating film capable of releasing hydrogen by heating. It is preferable that such an insulating layer 116 is formed in contact with the semiconductor layer 108. By this, impurities such as hydrogen are supplied to the low resistance region 108n, and the low resistance region 108n is made to have a low resistance. It can be made resistant.

[0189] The insulating layer 116 is formed by using a deposition gas containing an impurity element such as a hydrogen element. In addition, the lower the deposition temperature of the insulating layer 116, the It is possible to effectively supply a large amount of impurity elements to the semiconductor layer 108. The film temperature is, for example, 200° C. or higher and 500° C. or lower, preferably 220° C. or higher and 450° C. or lower. and more preferably, 230° C. or higher and 400° C. or lower.

[0190] In addition, the insulating layer 116 is formed under reduced pressure and by heating. This can promote the desorption of oxygen from the region that will become the low-resistance region 108n. By supplying impurities such as hydrogen to the semiconductor layer 108, the low resistance region 108 The carrier density in n is increased, and the resistance of the low-resistance region 108n can be reduced more effectively. can.

[0191] The insulating layer 116 may be made of, for example, silicon nitride, silicon nitride oxide, or silicon oxide nitride. An insulating film containing a nitride, such as aluminum nitride or aluminum nitride oxide, is preferably used. In particular, silicon nitride has blocking properties against hydrogen and oxygen, Prevent both the diffusion of hydrogen from the outside into the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside. This makes it possible to realize a highly reliable transistor.

[0192] In addition, the insulating layer 116 has a function of absorbing oxygen in the semiconductor layer 108 and generating oxygen vacancies. In particular, the insulating layer 116 may be made of a metal such as aluminum nitride. It is particularly preferable to use metal nitrides.

[0193] In addition, when metal nitrides are used, aluminum, titanium, tantalum, tungsten, quartz, etc. It is preferable to use nitrides of chromium or ruthenium. In particular, nitrides of aluminum or titanium are used. For example, aluminum is used as the sputtering target, Aluminum nitride formed by reactive sputtering using nitrogen-containing gas as deposition gas The nitrogen gas flow rate relative to the total flow rate of the deposition gas is appropriately controlled to produce an extremely thin film. The film has both high insulation and extremely high blocking properties against hydrogen and oxygen. For this reason, an insulating film containing such a metal nitride is provided in contact with a semiconductor layer. This not only reduces the resistance of the semiconductor layer, but also causes oxygen to be released from the semiconductor layer. This can effectively prevent hydrogen from diffusing into the semiconductor layer.

[0194] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the thickness of the layer is 5 nm or more. Even with such a thin film, hydrogen and oxygen This allows the compound to have both high blocking properties against elements and a function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be any thickness, but in consideration of productivity, it is preferably 500 nm or less. It is preferable that the thickness is 200 nm or less, and more preferably 50 nm or less.

[0195] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0 A membrane is used that satisfies the following: x is a real number less than or equal to 2, preferably, x is a real number greater than 0.5 and less than or equal to 1.5. This makes it possible to obtain a film having excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the dissipation of heat generated when the transistor 100B is driven. Cut.

[0196] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like is used as the insulating layer 116. It is possible.

[0197] By providing such an insulating layer 116 in contact with the low resistance region 108n, the insulating layer 116 Oxygen in the low resistance region 108n is absorbed, and oxygen vacancies are formed in the low resistance region 108n. In addition, after forming such an insulating layer 116, a heat treatment can be performed to obtain a low resistance. It is possible to form many oxygen vacancies in the resistive region 108n, and this can promote the reduction of the resistance. In addition, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 can be a semiconductor. As a result of absorbing oxygen from the layer 108, an insulating layer is formed between the insulating layer 116 and the low resistance region 108n. In some cases, a layer containing an oxide of the metal element (e.g., aluminum) contained in 116 is formed. be.

[0198] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, the semiconductor layer 108 has a low resistance. A region in which indium oxide is precipitated near the interface of the region 108n on the insulating layer 116 side, or In some cases, regions with high indium concentration are formed. This results in extremely low resistance A resistive region 108n can be formed. The presence of such a region can be used to detect, for example, X-ray photodetection. XPS: X-ray Photoelectron Spectroscop This may be possible using analytical methods such as y).

[0199] In this embodiment, the insulating layer 116 is used as a film for reducing the resistance of a part of the semiconductor layer 108. However, by providing the insulating layer 118 in contact with a part of the semiconductor layer 108, Alternatively, a part of the semiconductor layer 108 may be made to have a low resistance. In this case, the insulating layer 118 in contact with a part of the semiconductor layer 108 may be formed of An insulating film containing an oxide, such as a silicon oxide film or a silicon oxynitride film, can also be used.

[0200] [Configuration Example 2-4] FIG. 7A is a top view of a transistor 100C, and FIG. 7(C) is a cross-sectional view of the channel length direction of the transistor 100C, and FIG. 7(D) is a cross-sectional view of the channel width direction of the transistor 100C. 1 is a cross-sectional view in the direction.

[0201] The transistor 100C is a transistor 100B illustrated in the configuration example 2-3. This is an example of the case where a conductive layer 106 functioning as a first gate electrode is provided, as illustrated in FIG. .

[0202] With such a structure, a transistor with high on-state current can be obtained. may be a transistor whose threshold voltage can be controlled.

[0203] [Variation 1 of Configuration Example 2] In the above configuration examples 2-1 to 2-4, the semiconductor layer 108 is shown as a single layer. The layer 108 preferably has a laminated structure in which a semiconductor layer 108a and a semiconductor layer 108b are laminated. I wish.

[0204] The transistor 100_a shown in FIG. 8A is the same as the transistor 100 illustrated in the configuration example 2-1. 8A is an example of the semiconductor layer 108 of FIG. 8A having a laminated structure. The left side shows a cross section in the channel length direction, and the right side shows a cross section in the channel width direction. do.

[0205] Similarly, the transistor 100A_a shown in FIG. 8B and the transistor 100A_b shown in FIG. The transistors 100B_a and 100C_a shown in FIG. The semiconductor layer 108 of the transistor 100A, the transistor 100B, or the transistor 100C is This is an example of a laminated structure.

[0206] [Modification 2 of Configuration Example 2] As described above, the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is After oxygen is supplied to the insulating layer 110, it can be removed. It is also possible to configure the device without using 4.

[0207] The transistor 100_b shown in FIG. 9A is the same as the transistor 100 illustrated in FIG. In the case of 0_a, when the metal oxide layer 114 is removed or when the metal oxide layer 114 is not used, This is an example where this is not the case.

[0208] Similarly, the transistor 100A_b shown in FIG. 9B and the transistor 100A_b shown in FIG. The transistors 100B_b and 100C_b shown in FIG. In the transistor 100A_a, the transistor 100B_a, or the transistor 100C_a In the case where the metal oxide layer 114 is removed or where the metal oxide layer 114 is not used, be.

[0209] [Variation 3 of Configuration Example 2] As described above, in the transistor 100B and the transistor 100C, the insulating layer 11 Alternatively, the insulating layer 118 may be in contact with part of the semiconductor layer 108 without providing the insulating layer 6 .

[0210] The transistor 100B_c shown in FIG. 10A and the transistor 10 0C_c are the insulating layers 100B and 100C, respectively. In addition, the transistor 100B_d shown in FIG. The transistor 100C_d shown in FIG. 10D includes an insulating layer 116 and a metal oxide This is an example without layer 114.

[0211] [Production method example 1] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100A illustrated in configuration example 2-2 will be described as an example.

[0212] The thin films (insulating film, semiconductor film, conductive film, etc.) constituting the semiconductor device are formed by sputtering. The film can be formed by using a method such as CVD, vacuum deposition, PLD, or ALD. D methods include PECVD and thermal CVD. One of the thermal CVD methods is There is a method called metal organic chemical vapor deposition (MOCVD: Metal Organic CVD).

[0213] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coat, roll coat, curtain coat, knife coat It can be formed by the above method.

[0214] In addition, when processing the thin films that constitute the semiconductor device, photolithography and other methods are used. In addition, nanoimprinting, sandblasting, lift-off, The thin film may be processed by a method such as a masking method using a metal mask. The island-shaped thin film may be directly formed by the film method.

[0215] There are two typical photolithography methods. A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the mask after forming a photosensitive thin film. Then, development is performed to process the thin film into a desired shape.

[0216] In the photolithography method, the light used for exposure is, for example, i-line (wavelength 365 nm), Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may be performed by immersion lithography. Using extreme ultraviolet (EUV) light and X-rays, Also, instead of light for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferable because it allows extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is not necessary.

[0217] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as the above can be used.

[0218] 11A to 13B show steps in the manufacturing process of the transistor 100A. 4 shows cross sections in the channel length direction and the channel width direction.

[0219] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a gate electrode. A functional conductive layer 106 is formed (FIG. 11(A)).

[0220] At this time, as shown in FIG. 11(A), the end of the conductive layer 106 is tapered. This is preferable in order to improve the step coverage of the insulating layer 103 to be formed next. It is possible.

[0221] In addition, by using a conductive film containing copper as the conductive film to be the conductive layer 106, the wiring resistance can be reduced. For example, when applied to a large display device or a high-resolution display device, In the case of using the conductive layer 106 as a conductive layer, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used, the insulating layer 103 prevents copper from diffusing to the semiconductor layer 108 side. Since this suppresses the occurrence of the problem, a highly reliable transistor can be realized.

[0222] [Formation of insulating layer 103] Next, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 11(B) The insulating layer 103 is formed by using a PECVD method, an ALD method, a sputtering method, or the like. It is possible.

[0223] Here, the insulating layer 103 includes an insulating film 103a, an insulating film 103b, and an insulating film 103c. c is laminated to form a

[0224] In particular, each insulating film constituting the insulating layer 103 is preferably formed by the PECVD method. As for the method for forming the insulating layer 103, the description of the above-mentioned configuration example 1 can be cited.

[0225] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, a plasma treatment or a heat treatment can be performed in an oxygen atmosphere. Alternatively, oxygen is supplied to the insulating layer 103 by plasma ion doping or ion implantation. This is also fine.

[0226] [Formation of Semiconductor Layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 11(C)).

[0227] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0228] It is preferable that the metal oxide film 108f be a dense film with as few defects as possible. In addition, the metal oxide film 108f is a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable that the metal oxide film 108f is a metal oxide having crystallinity. It is preferred to use a membrane.

[0229] In addition, when forming a metal oxide film, oxygen gas and an inert gas (e.g., helium gas) are used. In addition, the metal oxide film may be formed by mixing the gas with the nitrogen gas. The higher the ratio of oxygen gas to the total deposition gas (hereinafter referred to as the oxygen flow ratio), This makes it possible to improve the crystallinity of the metal oxide film, thereby achieving a highly reliable transistor. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. It may be a transistor.

[0230] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and the denser the metal oxide film. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal. It may be an oxide film.

[0231] The conditions for forming the metal oxide film are a substrate temperature of room temperature or higher and 250° C. or lower, preferably room temperature. The substrate temperature may be set to a temperature between room temperature and 140° C., for example. For example, it is preferable to set the substrate temperature to room temperature or higher and lower than 140° C., since this increases productivity. The metal oxide film is formed at room temperature or without any intentional heating. This allows the crystallinity to be reduced.

[0232] In addition, before the metal oxide film 108f is formed, water and hydrogen adsorbed on the surface of the insulating layer 103 are removed. Among the treatment for removing organic substances and the like and the treatment for supplying oxygen into the insulating layer 103, It is preferable to carry out at least one of the following: Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, nitrous oxide (N 2In an atmosphere containing oxidizing gases such as O Oxygen may be supplied to the insulating layer 103 by plasma treatment at 2000.degree. By performing a plasma treatment containing oxygen, organic substances on the surface of the insulating layer 103 can be suitably removed. After such a treatment, the surface of the insulating layer 103 is exposed to the atmosphere. It is preferable to deposit the metal oxide film 108f continuously without depositing the metal oxide film 108c.

[0233] In addition, when the semiconductor layer 108 has a laminated structure in which a plurality of semiconductor layers are laminated, After forming the metal oxide film on the surface, the next It is preferable to deposit a metal oxide film.

[0234] Next, a part of the metal oxide film 108f is etched to form an island-shaped semiconductor layer 1 Form 08 (Figure 11(D)).

[0235] The metal oxide film 108f is processed by a wet etching method or a dry etching method. In this case, the insulating layer 106 that does not overlap with the semiconductor layer 108 may be used. A part of the insulating layer 103 may be etched and thinned. In some cases, the insulating film 103c is removed by etching, and the surface of the insulating film 103b is exposed. .

[0236] Here, after the metal oxide film 108f is formed, or after the metal oxide film 108f is It is preferable to perform a heat treatment after processing into the metal oxide film 8. 8f or removing hydrogen or water contained in the semiconductor layer 108 or adsorbed on the surface. In addition, the metal oxide film 108f or the semiconductor layer 108 can be heated. The quality may be improved (e.g., fewer defects, improved crystallinity, etc.).

[0237] In addition, the metal oxide film 108f or the semiconductor layer 103 is removed by the heat treatment. In this case, a heat treatment is performed before processing into the semiconductor layer 108. It is more preferable to do so.

[0238] The temperature of the heat treatment is typically 150°C or higher and lower than the distortion point of the substrate, or 200°C or higher and lower than 5 00℃ or less, or 250℃ to 450℃ or 300℃ to 450℃ It is possible.

[0239] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, the material may be heated in a dry air atmosphere and then heated in an oxygen-containing atmosphere. It is preferable that the atmosphere for the heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is preferably performed in an electric furnace or a rapid thermal annealing (RTA) furnace. By using an RTA device, the heating time can be shortened. It is possible.

[0240] If the heat treatment is unnecessary, it is not necessary to perform the heat treatment. It may be used in combination with the heat treatment to be performed in a later step. In some cases, the heat treatment may be performed in a step similar to that described above, for example, a film formation step.

[0241] [Formation of insulating layer 110] Next, the insulating layer 110 is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 11). (E)).

[0242] Here, the insulating layer 110 includes an insulating film 110a, an insulating film 110b, and an insulating film 110c. c is laminated to form a

[0243] In particular, each insulating film constituting the insulating layer 110 is preferably formed by the PECVD method. As for the method of forming each layer constituting the insulating layer 110, the description of the above-mentioned configuration example 1 can be used. This can be done.

[0244] In addition, before the insulating layer 110 is formed, a plasma treatment is performed on the surface of the semiconductor layer 108. By the plasma treatment, it is preferable that inclusions such as water adsorbed on the surface of the semiconductor layer 108 are removed. Therefore, the impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced. Since the impurities in the semiconductor layer 1 can be reduced, a highly reliable transistor can be realized. The surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. In some cases, it is preferable to use plasma treatment with oxygen, ozone, nitrogen, or nitrous oxide. The plasma treatment and the formation of the insulating layer 110 can be performed under an atmosphere of argon or the like. The film is preferably formed continuously without exposure to the atmosphere.

[0245] Here, after the insulating layer 110 is formed, heat treatment is preferably performed. This makes it possible to remove hydrogen or water contained in the insulating layer 110 or adsorbed on the surface. In addition, defects in the insulating layer 110 can be reduced.

[0246] The heat treatment conditions may be as described above.

[0247] If the heat treatment is unnecessary, it is not necessary to perform the heat treatment. It may be used in combination with the heat treatment to be performed in a later step. In some cases, the heat treatment may be performed in a step similar to that described above, for example, a film formation step.

[0248] [Formation of Metal Oxide Film 114f] Next, a metal oxide film 114f is formed on the insulating layer 110 (FIG. 12(A)).

[0249] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the insulating film by sputtering in an atmosphere containing oxygen. When the metal oxide film 114f is formed, oxygen can be supplied to the insulating layer 110. Oxygen may be supplied to the semiconductor layer 108 when the metal oxide film 114f is formed.

[0250] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. In the case of forming the film by a sputtering method using a target, the above description is incorporated herein. can be done.

[0251] For example, the deposition conditions for the metal oxide film 114f are as follows: oxygen is used as the deposition gas; The metal oxide film may be formed by reactive sputtering using a metal target. When aluminum is used as the base, an aluminum oxide film is formed. can be done.

[0252] When the metal oxide film 114f is formed, the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating layer 1 The oxygen supplied during the experiment can be increased by, for example, 5 0% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or less, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure in the film formation chamber as close to 100% as possible.

[0253] In this manner, the metal oxide film 114f is formed by the sputtering method in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating layer 110 during the formation of the metal oxide film 114f. In addition, it is possible to prevent oxygen from being released from the insulating layer 110. 10, which can trap an extremely large amount of oxygen.

[0254] After the metal oxide film 114f is formed, it is preferable to perform heat treatment. The oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. By heating the insulating layer 110 with the insulating layer 114f covering it, the oxide is released from the insulating layer 110 to the outside. This prevents the desorption of oxygen and allows a large amount of oxygen to be supplied to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0255] The heat treatment conditions may be as described above.

[0256] If the heat treatment is unnecessary, it is not necessary to perform the heat treatment. It may be used in combination with the heat treatment to be performed in a later step. In some cases, the heat treatment may be performed in a step similar to that described above, for example, a film formation step.

[0257] After the formation of the metal oxide film 114f or after the heat treatment, the metal oxide film 114 f may be removed.

[0258] [Formation of opening 142] Next, the metal oxide film 114f, the insulating layer 110, and a part of the insulating layer 103 are etched. As a result, an opening 142 reaching the conductive layer 106 is formed (FIG. 12(B)). The conductive layer 106 is electrically connected to a conductive layer 112 to be formed later through the opening 142. It can continue.

[0259] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Next, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f ( Figure 12(C)).

[0260] The conductive film 112f is preferably made of a low-resistance metal or alloy material. The conductive film 112f is made of a material that does not easily release hydrogen and does not easily diffuse hydrogen. It is preferable to use a material that is not easily oxidized as the conductive film 112f. is preferred.

[0261] For example, the conductive film 112f is formed by sputtering using a sputtering target containing a metal or an alloy. It is preferable to form the film by a sputtering method.

[0262] For example, the conductive film 112f may be a conductive film that is resistant to oxidation and hydrogen diffusion and has a low resistance. It is preferable to form a laminated film by laminating a conductive film having a conductive layer.

[0263] Next, a part of the conductive film 112f and the metal oxide film 114f is etched to form a conductive The conductive layer 112 and the metal oxide layer 114 are formed. It is preferable to process each of the layers f using the same resist mask. The conductive layer 112 after etching is used as a hard mask to etch the metal oxide film 114f. This is also fine.

[0264] The conductive film 112f and the metal oxide film 114f are etched by wet etching. It is preferable to use the rubbing method.

[0265] This forms the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same. It is possible.

[0266] In this manner, the upper and side surfaces of the semiconductor layer 108 and the By using a structure in which the insulating layer 103 covers the semiconductor layer 112f, etc. This can prevent the body layer 108 and the insulating layer 103 from being partially etched and thinned. .

[0267] [Supply of impurity elements] Next, impurities are implanted into the semiconductor layer 108 through the insulating layer 110 using the conductive layer 112 as a mask. A process of supplying (adding or injecting) the element 140 is performed (FIG. 12(D)). As a result, a low resistance region 108n is formed in the region of the semiconductor layer 108 that is not covered by the conductive layer 112. At this time, the impurity source can be added to the region of the semiconductor layer 108 that overlaps with the conductive layer 112. In order to minimize the supply of the element 140, the material and thickness of the conductive layer 112 serving as the mask are selected. It is preferable to determine the conditions for the supply process of the impurity element 140 taking into consideration the above. A channel having a sufficiently reduced impurity concentration is formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112. A forming region can be formed.

[0268] The impurity element 140 is preferably supplied by a plasma ion doping method or an ion implantation method. These methods can be used to measure the concentration profile in the depth direction by ion acceleration. It is possible to control the voltage and dose with high precision. Plasma ion doping By using this method, productivity can be increased. In addition, ion implantation using mass separation is also used. By using this, the purity of the impurity element supplied can be increased.

[0269] In the supplying process of the impurity element 140, the interface between the semiconductor layer 108 and the insulating layer 110, indicates a portion of the semiconductor layer 108 close to the interface, or a portion of the insulating layer 110 close to the interface. It is preferable to control the treatment conditions so that the concentration of The process supplies the optimum concentration of impurity elements 140 to both the semiconductor layer 108 and the insulating layer 110. It is possible.

[0270] The impurity elements 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples of the material include aluminum, magnesium, silicon, and rare gases. Representative examples include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon. It is.

[0271] As a source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically B 2 H 6 Gas and BF 3 Gas can be used. In addition, when phosphorus is supplied, the typical 3 Gas can be used. Alternatively, a mixed gas in which these source gases are diluted with a rare gas may be used.

[0272] Other raw gases include CH 4 , N 2 , N.H. 3 , AlH 3 , AlCl 3 , SiH 4 , S 2 H 6 , F 2 , H.F., H. 2 , (C 5 H 5 ) 2 Mg and rare gases can be used. In addition, the ion source is not limited to gas, and a solid or liquid vaporized by heating can also be used. good.

[0273] The addition of the impurity element 140 affects the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108. This can be controlled by setting conditions such as acceleration voltage and dose amount taking into consideration the above.

[0274] For example, when boron is added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV to 100 kV, preferably 7 kV to 70 kV, more preferably The voltage can be preferably in the range of 10 kV to 50 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 ×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 More preferably, 1 ×10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following range should be met: can be done.

[0275] In addition, when phosphorus ions are added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less. More preferably, the voltage can be in the range of 40 kV to 80 kV. For example, 1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 The following are the preferred Or 1×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 The following is more preferred: Or 1×10 15 ions / cm 2 More than 3×10 16 ions / cm 2 The range is as follows: It is possible.

[0276] The method of supplying the impurity element 140 is not limited to this. For example, plasma processing, A treatment utilizing thermal diffusion by heating may be used. In the case of the plasma treatment method, the added By generating plasma in a gas atmosphere containing impurity elements and performing plasma processing, The impurity element can be added by the plasma generation device. Etching equipment, Ashing equipment, Plasma CVD equipment, High density plasma CVD equipment, etc. can be used.

[0277] In one embodiment of the present invention, the impurity element 140 is supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, impurities can be The damage to the semiconductor layer 108 during the supply of the element 140 is reduced, and the crystallinity is not impaired. Therefore, the increase in electrical resistance due to the decrease in crystallinity can be prevented. This is preferable in such cases.

[0278] [Formation of insulating layer 118] Next, the insulating layer 11 is formed over the insulating layer 110, the metal oxide layer 114, and the conductive layer 112. 8 is formed (Figure 13(A)).

[0279] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, the low resistance The impurities contained in the region 108n etc. are introduced into the peripheral region including the channel formation region of the semiconductor layer 108. There is a risk of diffusion, and the electrical resistance of the low resistance region 108n may increase. The deposition temperature of the insulating layer 118 can be determined taking these factors into consideration.

[0280] For example, the deposition temperature of the insulating layer 118 is preferably 150° C. or more and 400° C. or less. The temperature is preferably 180°C or higher and 360°C or lower, and more preferably 200°C or higher and 250°C or lower. By forming the insulating layer 118 at a low temperature, a transistor with a short channel length can be formed. Even if there is a problem, good electrical properties can be imparted.

[0281] After the insulating layer 118 is formed, heat treatment may be performed. In some cases, the region 108n can be made more stable and have a lower resistance. By carrying out the heat treatment, the impurity element 140 is appropriately diffused and locally uniformed, and thus the In this case, the low resistance region 108n having a concentration gradient of the impurity element can be formed. If the temperature is too high (for example, 500° C. or higher), the impurity element 140 may enter the channel formation region. This can lead to deterioration in the electrical characteristics and reliability of the transistor.

[0282] The heat treatment conditions may be as described above.

[0283] If the heat treatment is unnecessary, it is not necessary to perform the heat treatment. It may be used in combination with the heat treatment to be performed in a later step. In the case where a process such as a film formation process is performed, the process may be performed together with the heat treatment.

[0284] [Formation of Openings 141a and 141b] Next, the insulating layer 118 and the insulating layer 110 are partially etched to form a low resistance region 1 08n.

[0285] [Formation of Conductive Layer 120a and Conductive Layer 120b] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (FIG. 13(B)).

[0286] Through the above steps, the transistor 100A can be manufactured. When the sta 100A is applied to a pixel of a display device, a protective insulating layer, a planarizing layer, A step of forming at least one of the pixel electrodes and the wiring may be added.

[0287] This concludes the description of Preparation Method 1.

[0288] In addition, when the transistor 100 illustrated in the configuration example 2-1 is manufactured, the above manufacturing method The steps of forming the conductive layer 106 and the opening 142 in Example 1 may be omitted. In addition, the transistor 100 and the transistor 100A are formed on the same substrate through the same process. It can be achieved.

[0289] [Production method example 2] Hereinafter, an example in which some steps are different from the above-mentioned manufacturing method example 1 will be described. The transistor 100C illustrated in Example 2-4 will be described as an example.

[0290] In the following, explanations of the parts that overlap with the above-mentioned Preparation Method Example 1 will be omitted, and only the different parts will be explained. This section will now be explained in detail.

[0291] First, in the same manner as in the above-mentioned Example 1 of Manufacturing Method, the conductive layer 106, the insulating layer 103, the semiconductor layer 108, and the insulating The edge layer 110, the metal oxide film 114f, and the conductive film 112f are formed in this order. A cross-sectional view of the above is shown in FIG.

[0292] Next, the conductive film 112f and a part of the metal oxide film 114f are etched to form the conductive layer 1 12 and a metal oxide layer 114 are formed, and then a portion of the insulating layer 110 is etched to form a semiconductor layer. A part of the conductor layer 108 is exposed (FIG. 14(B)). This allows the upper surface shapes to roughly match. A conductive layer 112, a metal oxide layer 114, and an insulating layer 110 may be formed.

[0293] The insulating layer 110 is etched using a resist mask for etching the conductive film 112f. The etching of the insulating layer 110 is preferably performed using the conductive film 112f and the gold film. This may be performed in the same step as the etching of the conductive film 112f and the metal oxide film 114f. After etching the oxide film 114f, etching is performed by a different etching method. You may also use the

[0294] For example, the conductive film 112f and the metal oxide film 114f are etched on a wafer using the same etchant. After etching by hot etching, the insulating layer 110 is etched by dry etching. In particular, the conductive film 112f and the metal oxide film 114f can be dry etched. When the semiconductor layer 10 is processed by the etching method, a reaction product containing a metal is generated, and the semiconductor layer 10 8 and the insulating layer 110. Therefore, before etching the insulating layer 110, The conductive film 112f and the metal oxide film 114f are processed by a wet etching method. is preferred.

[0295] Depending on the etching conditions, the conductive layer 112, the metal oxide layer 114, and the insulating layer 115 may be etched. For example, the ends of the conductive layer 112 may be closer than the ends of the insulating layer 110. At least one end of the metal oxide layer 114 is located on the inside or the outside. There may be cases where this occurs.

[0296] Furthermore, when the insulating layer 110 is etched, a part of the exposed semiconductor layer 108 is also etched. At this time, the semiconductor layer 108 may be thinned by being heated to a temperature of 1000. , it may have a shape thinner than the thickness of the channel forming region.

[0297] In addition, when the insulating layer 110 is etched, a part of the insulating layer 103 that is not covered with the semiconductor layer 108 For example, the insulating film 103c of the insulating layer 103 may be etched and thinned. There may also be losses.

[0298] Next, an insulating layer 116 is formed on the exposed portion of the semiconductor layer 108, followed by an insulating By forming the insulating layer 116, the exposed portion of the semiconductor layer 108 is removed. The exposed portion has a low resistance, forming a low resistance region 108n.

[0299] The insulating layer 116 is formed by emitting an impurity element having a function of reducing the resistance of the semiconductor layer 108. In particular, a silicon nitride film capable of releasing hydrogen can be used. It is preferable to use an inorganic insulating film such as a silicon nitride oxide film or a silicon oxynitride film. At this time, the insulating layer 11 is formed by using a plasma CVD method using a deposition gas containing hydrogen. This is preferable because hydrogen can be supplied to the semiconductor layer 108 during the formation of the film 6 .

[0300] For example, when silicon nitride is used as the insulating layer 116, silicon such as silane is used. The mixed gas containing nitrogen such as ammonia and nitrous oxide is used as the deposition gas. It is preferable to form the silicon nitride film by the PECVD method used in the above. It is preferable that hydrogen is contained in the insulating layer 116. This allows the hydrogen in the insulating layer 116 to Diffusion into the layer 108 makes it easier to reduce the resistance of a portion of the semiconductor layer 108 .

[0301] Alternatively, an insulating film having a function of generating oxygen vacancies in the semiconductor layer 108 may be used. In particular, it is preferable to use an insulating film containing a metal nitride. A sputtering target is used to form a mixture of nitrogen gas and a diluent gas such as a rare gas. It is preferable to form the film by a reactive sputtering method using a film gas as the film gas. By controlling the flow rate ratio of the deposition gas, it becomes easy to control the film quality of the insulating layer 116. .

[0302] For example, the insulating layer 116 is formed by reactive sputtering using an aluminum target. When using an aluminum nitride film formed by the above method, the flow rate of nitrogen gas relative to the total flow rate of the deposition gas is The amount is 30% or more and 100% or less, preferably 40% or more and 100% or less, more preferably 50 It is preferable that the ratio is 100% or more and 100% or less.

[0303] Here, the insulating layer 116 and the insulating layer 118 are formed successively without being exposed to the air. is preferred.

[0304] In the case where the insulating layer 118 is provided in contact with the semiconductor layer 108, the shape of the insulating layer 116 is The forming step can be omitted.

[0305] After the insulating layer 116 or the insulating layer 118 is formed, heat treatment may be performed. The heat treatment can promote the reduction in resistance of the low-resistance region 108n.

[0306] The heat treatment conditions may be as described above.

[0307] If the heat treatment is unnecessary, it is not necessary to perform the heat treatment. It may be used in combination with the heat treatment to be performed in a later step. In some cases, the heat treatment may be performed in a step similar to that described above, for example, a film formation step.

[0308] Next, an opening 141 is formed in the insulating layer 118 and the insulating layer 116, reaching the low resistance region 108n. a and an opening 141b are formed.

[0309] Subsequently, the conductive layer 120a and the conductive layer 120b are formed on the insulating layer 118 in the same manner as in the first manufacturing method. b is formed (Figure 14(D)).

[0310] Through the above steps, the transistor 100C can be manufactured.

[0311] In addition, when the transistor 100B illustrated in the configuration example 2-3 is manufactured, the above manufacturing method is used. The steps of forming the conductive layer 106 and the opening 142 in Example 2 can be omitted. The transistors 100B and 100C are also fabricated on the same substrate through the same process. It can be formed into.

[0312] [Components of Semiconductor Devices] The components included in the semiconductor device of this embodiment will be described below.

[0313] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates A plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. are used as the substrate 102. In addition, the substrate 102 may be a substrate on which a semiconductor element is provided. It may be used.

[0314] In addition, a flexible substrate is used as the substrate 102, and a semiconductor device is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the semiconductor device. After a semiconductor device is partially or entirely completed thereon, it is separated from the substrate 102 and then mounted on another substrate. In this case, the semiconductor device is mounted on a substrate having poor heat resistance or a flexible substrate. It can also be printed on other circuit boards.

[0315] [Conductive Film] The conductive layer 112 and the conductive layer 106 function as a gate electrode, and a source electrode or drain electrode. A conductive layer 120a serving as one of the drain electrodes and a conductive layer 120b serving as the other drain electrode are provided. b is chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tin A metal element selected from the group consisting of zinc, manganese, nickel, iron, and cobalt, or the above-mentioned gold. The alloys are made of metal elements or alloys combining the above-mentioned metal elements. It can be achieved.

[0316] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. Alternatively, oxide conductors or metal oxides may be used.

[0317] Here, we will explain about oxide conductors (OC). For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. Then, a donor level is formed near the conduction band. As a result, the metal oxide has high electrical conductivity. The metal oxide that has been made conductive can be called an oxide conductor.

[0318] In addition, as the conductive layer 112, etc., a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating film that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0319] The conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is preferable to use one or more of the above. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and high barrier properties against copper, oxygen, and hydrogen. Since the conductive film in contact with the semiconductor layer 108 has a low hydrogen emission property and emits little hydrogen from itself, Alternatively, the conductive film can be suitably used as a conductive film in the vicinity of the semiconductor layer 108 .

[0320] [Semiconductor Layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The atomic ratio of the metal elements in the sputtering target used is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Z n=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M :Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In :M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=10:1 :3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5 :1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, etc. In the above, when the element M contains two or more elements, the atomic ratio The ratio of M corresponds to the sum of the numbers of atoms of the two or more metal elements.

[0321] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 having crystallinity can be easily formed. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering used for the semiconductor layer 108 may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], the film is formed. The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. There may be cases where this occurs.

[0322] In addition, when the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, When Ga is 4, this includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when describing that the atomic ratio is In:Ga:Zn=5:1:6 or close to that, When n is 5, Ga is greater than 0.1 and is equal to or less than 2, and Zn is equal to or greater than 5 and is equal to or less than 7. Also, the atomic ratio is In:Ga:Zn=1:1:1 or in the vicinity. When mounting, when In is 1, Ga is greater than 0.1 and less than 2, and Zn is 0. Includes cases greater than 1 and less than or equal to 2.

[0323] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0324] In addition, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure is, for example, This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure described below. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0325] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0326] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystal structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which the film is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0327] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since no clear crystal grain boundaries can be seen in CAAC-OS, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. The crystallinity can be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). The physical properties of an oxide semiconductor having an OS are stable. The oxide semiconductor used is heat resistant and highly reliable.

[0328] In crystallography, the three axes that make up a unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the lattice. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis that intersects the layers is the Generally, the c-axis is taken as the c-axis. A typical example of a crystal with such a layered structure is Graphite is classified as a hexagonal crystal, and the a- and b-axes of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure YbFe 2 O 4 Crystal structure of the type InGaZnO 4 The crystal of this system can be classified as a hexagonal system, and the a-axis and The a- and b-axes are parallel to the plane of the layer, and the c-axis is perpendicular to the layers (i.e., the a- and b-axes).

[0329] An oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film) is shown in the TEM image. In some cases, it may not be possible to clearly identify the crystal parts in the microcrystalline oxide semiconductor film. The crystal part has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, microcrystals with sizes between 1 nm and 10 nm or between 1 nm and 3 nm are often An oxide semiconductor film having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) film In addition, the grain boundaries of the nc-OS film can be clearly seen in the TEM images. There may be cases where this is not possible.

[0330] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that in the crystalline region. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam of 50 nm or more (for example) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using the electron beam shown below, a circle is drawn. A bright ring-shaped area was observed, and multiple spots were observed within the ring-shaped area. may be observed.

[0331] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S-film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film has The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to OS films, the carrier density and electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0332] The nc-OS film is formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a low temperature compared to the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is relatively low (for example, below 130°C) or the board is not heated. Since it can form films even on large glass substrates, it is suitable for use with large glass substrates or resin substrates. This allows for increased productivity.

[0333] An example of the crystal structure of a metal oxide will be described. The atomic ratio of In:Ga:Zn=4:2:4.1 was used, and the substrate temperature was kept at 100°C or higher for 1 The metal oxide formed by sputtering is nc (nano c Either the CAAC structure or the crystalline structure, or a mixture of these On the other hand, metal oxides formed at room temperature (RT) tend to have a structure similar to that shown in Fig. The nc crystal structure is easily obtained. Includes temperatures without heating.

[0334] [Metal oxide composition] The following describes a CAC (C This paper explains the configuration of the Multicloud Aligned Composite Operating System (MSO).

[0335] CAAC (c-axis aligned crystal) is an example of a crystal structure. CAC (Cloud-Aligned Composite) stands for function or material. An example of the fee structure is shown below.

[0336] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has a function of insulating in part and a function of semiconductor in the whole material. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a layer, the conductive function is to allow the flow of electrons (or holes) that serve as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the function of the material and the function of the material complement each other, the material can be switched (On / Off). The function of ff can be given to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the functions are separated. By combining them, the functions of both can be maximized.

[0337] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a gap in the material. In addition, the conductive regions are observed as connected clouds with blurred edges. This may be the case.

[0338] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than one millimeter.

[0339] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide gap component due to the insulating region and a conductive region. In this configuration, when the carrier flows, In addition, carriers mainly flow in the narrow gap component. The component with a gap acts complementary to the component with a wide gap to produce a narrow gap. Carriers also flow to the wide gap component in conjunction with the component with a large gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field effect mobility can be obtained.

[0340] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a composite matrix.

[0341] The above is an explanation of the configuration of the metal oxide.

[0342] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0343] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0344] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain about this.

[0345] [Configuration example] 15A shows a top view of a display device 700. The display device 700 includes a sealant 712. The first substrate 701 and the second substrate 705 are bonded together by a bonding agent. 1, the second substrate 705, and the area sealed by the sealant 712. 1, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0346] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. Through the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 Various signals are supplied to each of these.

[0347] A plurality of gate driver circuit sections 706 may be provided. The path portion 706 and the source driver circuit portion 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip may be mounted on the first substrate 70. 1, or can be mounted on FPC716.

[0348] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0349] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light emitting element. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, etc. are used. The light emitting element can be LED (Light Emitting Diode). Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs and semiconductor lasers. MEMS (Micro Electro Mechanical Systems) using the optical interferometry or optical interference method l Systems) elements, microcapsule type, electrophoretic type, electrowet type Display elements using the electronic powder method or the like can be used. It is also possible.

[0350] The display device 700A shown in FIG. 15B has a flexible substrate instead of the first substrate 701. A display device to which a resin layer 743 is applied and which can be used as a flexible display This is an example.

[0351] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in the region P1 in FIG. 15B, the pixel section 702 and the resin layer 743 The pair of gate driver circuit sections 706 are connected to the pixel section 7 The gate driver circuit section 706 is provided on both sides of the pixel section 702. The recess is provided along a circular arc-shaped contour at the recess.

[0352] The resin layer 743 has a protruding shape at the portion where the FPC terminal portion 708 is provided. In addition, a part of the resin layer 743 including the FPC terminal portion 708 is disposed on the back side in the region P2 in FIG. By folding back a part of the resin layer 743, the FPC 716 can be attached to the pixel area. With the display device 700A placed behind the display device 702, the display device 700A can be mounted on the electronic device. This allows for space saving for electronic devices.

[0353] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. The source driver circuit section 704 in 00A includes a protection circuit, a buffer circuit, a demultiplexer, The configuration may include at least one of a crosstalk circuit, etc.

[0354] The display device 700B shown in FIG. 15(C) is suitable for use in electronic devices having a large screen. For example, television sets, monitors, personal computers, etc. Computers (including notebooks and desktops), tablets, digital signage It can be suitably used in the following cases:

[0355] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuits. The sensor 722 has a first section 722.

[0356] The source driver ICs 721 are each attached to an FPC 723. In addition, the plurality of FPCs 723 are arranged such that one terminal is connected to the first board 701 and the other terminal is connected to the printed board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things.

[0357] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0358] With this configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It is possible to realize a display device with a resolution of 4K2K or 8K4K. It is possible to realize a display device with extremely high resolution.

[0359] [Cross-section example] The following describes a configuration in which a liquid crystal element is used as a display element, and a configuration in which an EL element is used. 16 to 19. Note that FIGS. 16 to 18 are the same as FIG. 15(A 19 is a cross-sectional view of the display device 700 taken along the dashed line QR shown in FIG. 5(B) is a cross-sectional view of the display device 700A taken along dashed line ST in FIG. FIG. 17 shows a configuration using a liquid crystal element as a display element, and FIGS. 18 and 19 show a configuration using an EL element. This is a configuration using the above.

[0360] [Description of common parts of the display device] The display device shown in FIG. 16 to FIG. 19 includes a wiring portion 711, a pixel portion 702, and a The wiring section 711 includes a driver circuit section 704 and an FPC terminal section 708. 7 and a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752. The absence of element 790 is shown.

[0361] The transistor 750 and the transistor 752 are the transistors exemplified in the first embodiment. can be applied.

[0362] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The retention time of the image signal can be extended, and the interval between writing the image signal can be set to be longer. Since the frequency of refresh operations can be reduced, this has the effect of reducing power consumption.

[0363] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in a device, the switching transistor in the pixel section and the driver circuit section In other words, the transistors can be formed on the same substrate, such as a silicon wafer. It is also possible to adopt a configuration that does not use a driving circuit formed by the above-mentioned method, and the number of parts of the display device can be reduced. In addition, by using a transistor capable of high speed operation in the pixel portion, It is possible to provide high quality images.

[0364] The capacitor 790 shown in FIG. 16, FIG. 18, and FIG. 19 is a third capacitor included in the transistor 750. The lower electrode is formed by processing the same film as the gate electrode in 1, and the same metal oxide as the semiconductor layer is and an upper electrode formed by processing a material. The upper electrode is a source electrode of the transistor 750. The resistance of the gate electrode is reduced in the same manner as the source and drain regions. A part of an insulating film that functions as a first gate insulating layer of the transistor 750 is provided on the That is, the capacitor 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. The upper electrode is a layered structure in which the source electrode and drain electrode of the transistor are formed. The electrodes are connected to wiring obtained by processing the same film as the electrodes.

[0365] In addition, a planarization insulating layer is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0366] A transistor 750 included in the pixel portion 702 and a transistor 751 included in the source driver circuit portion 704 A transistor having a different structure from the transistor 752 may be used. For example, A top-gate transistor is applied to one side and a bottom-gate transistor is applied to the other side. The gate driver circuit section 706 may also be configured using a source driver. As in the driver circuit section 704, a transistor having the same structure as the transistor 750 may be used. Alternatively, transistors having different structures may be used.

[0367] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. It is made of the same conductive film as the electrodes. At this time, a low-resistance material such as a material containing copper is used. This is preferable because it reduces signal delays caused by wiring resistance and enables large-screen displays. I wish.

[0368] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, and an anisotropic conductive film 78. The wiring 760 is connected to the FPC 710 via an anisotropic conductive film 780. In this example, the wiring 760 is electrically connected to a terminal of the transistor 750 or The source electrode and the drain electrode of the transistor 752 are formed using the same conductive film.

[0369] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used as the first substrate 701. When using a substrate that can be used for the first substrate 701, water or water may be provided between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer having a barrier property against elements.

[0370] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and insulating films in contact with these are provided. A border membrane 734 is provided.

[0371] [Example of the configuration of a display device using a liquid crystal element] The display device 700 shown in FIG. 16 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 772 is provided on the substrate 705 side and functions as a common electrode. The conductive layer is electrically connected to a source electrode or a drain electrode of the transistor 750. A pixel electrode 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0372] The conductive layer 772 can be formed using a material that transmits or reflects visible light. The transparent material may be, for example, an oxide material containing indium, zinc, tin, etc. As the reflective material, for example, a material containing aluminum, silver, etc. is used. It is good.

[0373] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the display device becomes a transmissive type. In the case of a liquid crystal display device of the transmission type, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0374] The display device 700 shown in FIG. 17 includes a liquid crystal element 77 of a horizontal electric field type (for example, an FFS mode). 5 is formed on a conductive layer 772 with an insulating layer 773 interposed therebetween, the insulating layer 773 serving as a common electrode. A conductive layer 774 is provided. An electric field is generated between the conductive layer 772 and the conductive layer 774, The alignment state of the liquid crystal layer 776 can be controlled.

[0375] In FIG. 17, a holding container is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0376] Although not shown in FIGS. 16 and 17, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as a backlight and a sidelight can be provided as appropriate.

[0377] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, etc. Crystal (PDLC: Polymer Dispersed Liquid Crystal) , Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the lateral electric field mode is adopted, liquid crystal exhibiting a blue phase without using an alignment film may be used.

[0378] The liquid crystal element modes are Twisted Nematic (TN) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optically Compensated Biref ringence mode, ECB (Electrically Controlled Birefringence mode, guest host mode, etc. .

[0379] In addition, the liquid crystal layer 776 is made of a polymer dispersed liquid crystal or a polymer network liquid crystal. A scattering type liquid crystal can also be used. In this case, a black and white display is performed without providing the color film 736. Alternatively, a colored film 736 may be used to perform color display.

[0380] In addition, as a driving method for liquid crystal elements, a time-series additive color mixing method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the color film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors R (red), G (green), and B (blue). This has the advantage of improving the pixel aperture ratio and increasing the resolution. do.

[0381] [Display device using light-emitting element] The display device 700 shown in FIG. 18 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound, The light-emitting element includes a light-emitting material such as an inorganic compound.

[0382] The luminescent materials include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (TFA). ctivated delayed fluorescence (TADF) materials, inorganic Compounds (such as quantum dot materials) can be used.

[0383] In the display device 700 shown in FIG. 18, a conductive layer 772 is provided on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. Note that the light-emitting element 782 emits light toward the conductive layer 772. A bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788 can be used. It may also be a dual emission structure.

[0384] The colored film 736 is provided at a position overlapping the light emitting element 782. 8 indicates a position overlapping with the insulating film 730, the lead wiring section 711, and the source driver circuit section 70 The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. The EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by coloring. In this case, the colored film 736 may not be provided.

[0385] FIG. 19 shows a configuration of a display device that can be suitably applied to a flexible display. FIG. 19 is a cross-sectional view taken along dashed line ST in the display device 700A shown in FIG. 15(B). FIG.

[0386] A display device 700A shown in FIG. 19 includes a support substrate instead of the first substrate 701 shown in FIG. It has a laminated structure of a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744. The transistor 750, the capacitor 790, and the like are formed on an insulating layer 744 provided on a resin layer 743. It is provided in.

[0387] The support substrate 745 is a substrate that contains organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The resin layer 74 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferably thinner than the supporting substrate 745 .

[0388] In addition, the display device 700A shown in FIG. 19 has a support substrate 705 instead of the second substrate 705 shown in FIG. The protective layer 740 is attached to the sealing film 732. The protective layer 740 may be a glass substrate or a resin film. Examples of the optical components include polarizing plates and scattering plates, and input devices include touch sensor panels. A configuration in which two or more of these are stacked may also be applied.

[0389] In addition, the EL layer 786 of the light-emitting element 782 is an island on the insulating film 730 and the conductive layer 772. The EL layer 786 is formed so that each subpixel emits a different light. In this way, color display can be achieved without using the color film 736. A protective layer 741 is provided to cover the light emitting element 782. The protective layer 741 protects the light emitting element 782 from inclusions such as water. The protective layer 741 has a function of preventing diffusion of impurities. It is also preferable to use a laminated structure including at least one inorganic insulating film and at least one organic insulating film. preferable.

[0390] 19 shows a bendable region P2. In the region P2, the support substrate 7 45, in addition to the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. The bendable region P2 is provided with as little inorganic insulating film as possible, and is provided with a conductive material containing a metal or an alloy. By laminating only layers containing organic materials, cracks do not occur when the material is bent. In addition, by not providing the support substrate 745 in the region P2, A portion of the display device 700A can be bent with a small radius of curvature.

[0391] [Example of configuration in which an input device is provided on a display device] In addition, an input device is provided to the display device 700 or the display device 700A shown in FIG. An example of the input device is a touch sensor.

[0392] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, infrared type, etc. Various methods can be used, such as a pressure-sensitive, optical, or pressure-sensitive method. Or, two or more of these can be used. may be used in combination.

[0393] The touch panel is of the so-called in-cell type, in which the input device is formed between a pair of substrates. The touch panel and the input device are formed on the display device 700, that is, a so-called on-cell type touch panel. A so-called out-cell type touch panel, in which an input device is attached to the display device 700, is used. There are panels etc.

[0394] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0395] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0396] (Embodiment 3) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. The following description will be given with reference to Figures 20(A) to 20(C).

[0397] The display device shown in FIG. 20A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 505. 6 and a terminal portion 507. Note that the protection circuit 506 may be omitted. .

[0398] The transistors in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also use the transistor of one embodiment of the present invention. may be applied.

[0399] The pixel section 502 is a multi-layered pixel array arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 501 has a circuit for driving a display element. Yes.

[0400] The driver circuit unit 504 is a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. A data driver 504a supplies data signals to the data lines DL_1 through DL_Y. The gate driver 504a includes at least one driver circuit such as a source driver 504b. The source driver 504b may also have a shift register. It is composed of a number of analog switches. It is also possible to use a shift register to A switch driver 504b may be configured.

[0401] The terminal unit 507 is a terminal for inputting power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals are provided for connecting the power supply to the power source.

[0402] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit The protection circuit 506 shown in FIG. For example, the gate line GL, which is a wiring between the gate driver 504a and the pixel circuit 501, indicates various wirings such as the data line DL which is the wiring between the source driver 504b and the pixel circuit 501. In FIG. 20A, in order to distinguish the protection circuit 506 from the pixel circuit 501, Therefore, the protection circuit 506 is hatched.

[0403] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) Plates) are bonded to the drawing board by COG or TAB (Tape Automated Bonding). It may be configured to be mounted on a substrate on which element portion 502 is provided.

[0404] 20B and 20C show pixel circuit configurations that can be applied to the pixel circuit 501. An example of the configuration is shown below.

[0405] The pixel circuit 501 shown in FIG. 20B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a gate line GL _m, a potential supply line VL, etc. are connected.

[0406] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0407] The pixel circuit 501 shown in FIG. 20C includes a transistor 552 and a transistor The pixel circuit 501 includes a pixel electrode 54, a capacitor 562, and a light-emitting element 572. The data line DL_n, the gate line GL_m, the potential supply line VL_a, and the potential supply line VL_b are is connected.

[0408] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. A low power supply potential VSS is applied to the gate of the transistor 554. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0409] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0410] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0411] (Embodiment 4) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0412] [Circuit configuration] FIG. 21A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0413] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, The other end is connected to one electrode of the capacitor C1. The gate of the transistor M2 is G2, one of the source and drain is the wiring S2, and the other is the other electrode of the capacitance C1, and 401 and 402, respectively.

[0414] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) ems) elements, etc. can be applied.

[0415] The node connecting the transistor M1 and the capacitor C1 is a node N1, and the transistor M2 is a The node connecting to the path 401 is node N2.

[0416] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via transistor M1, capacitive coupling via capacitor C1 This makes it possible to change the potential of the node N2 in response to a change in the potential of the node N1.

[0417] Here, in one or both of the transistors M1 and M2, The transistor using an oxide semiconductor, which is exemplified in 1, can be used. Therefore, the potential of the node N1 or node N2 is maintained for a long period of time due to the extremely low off-current. In addition, when the period for which the potential of each node is held is short (specifically, when In cases where the frequency is 30 Hz or more, transistors using semiconductors such as silicon A star may also be used.

[0418] [Driving method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. 4B is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, we have not included various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The effects of the transistor threshold voltage, etc. are not taken into account.

[0419] In the operation shown in FIG. 21B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0420] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the line S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supplies.

[0421] The node N1 is connected to a potential V ref is given. The node N2 is supplied with a first data potential V w Given Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0422] [Period T2] In the next period T2, a potential is applied to the wiring G1 to turn on the transistor M1. A potential for turning off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. The state may be a locking state.

[0423] The node N1 receives a second data potential V data but At this time, the second data potential V data In response In other words, the potential of the node N2 changes by a potential dV. Potential V w The potential obtained by adding the potential dV to the potential is input. Although dV is shown as a positive value, it may be a negative value. Potential V data is the potential V ref It may be lower.

[0424] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes the second Data potential V data The potential becomes close to

[0425] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the line 401 can be generated, the gray scale correction can be performed within the pixel circuit 400. It will be possible to do so.

[0426] In addition, the pixel circuit 400 can supply a source driver connected to the wiring S1 and the wiring S2. For example, when a light emitting element is used, a potential exceeding the maximum potential can be generated. This allows high dynamic range (HDR) display, etc. In this case, overdrive driving or the like can be realized.

[0427] [Example of application] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 21C includes a circuit 401LC. has a liquid crystal element LC and a capacitance C2.

[0428] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the Potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0429] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0430] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Achieving high-speed display through overdrive operation and using liquid crystal materials with high drive voltage In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0431] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 21D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0432] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the One of the rains is at potential V H The other is one electrode of the light-emitting element EL. The capacitor C2 is connected to the other electrode at potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0433] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0434] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value of can be changed appropriately.

[0435] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or wiring S2, the transistor M3 or It is also possible to correct the variation in the electrical characteristics of the light-emitting element EL.

[0436] In addition, the present invention is not limited to the circuits illustrated in FIG. 21C and FIG. 21D, and may be implemented by using additional transistors or A configuration in which a capacity or the like is added may also be used.

[0437] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0438] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. I will explain it below.

[0439] The display module 6000 shown in FIG. 22(A) includes an upper cover 6001 and a lower cover 6002. A display device 6006, a frame 6009, and a printer 6002 are connected to the FPC 6005. The semiconductor device has a support substrate 6010 and a battery 6011.

[0440] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0441] The upper cover 6001 and the lower cover 6002 are adapted to the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0442] The display device 6006 may have a function as a touch panel.

[0443] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0444] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0445] FIG. 22(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. It is.

[0446] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guiding portions (light guiding portion 6017a, light guiding portion 6017b).

[0447] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are disposed on top of the light guide unit 6011. 017a and fixed to light guiding portion 6017b.

[0448] Light 6018 emitted from the light emitting portion 6015 is guided to the display device 600 by the light guiding portion 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0449] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information on the position where the touch operation was performed.

[0450] The light emitting unit 6015 may be a light source such as an LED element, and in particular, may be a light source that emits infrared rays. It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that can receive light and convert it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0451] The light guiding portion 6017a and the light guiding portion 6017b transmit light 6018. The light receiving unit 6016 can be disposed under the display device 6006, and external light is received by the light receiving unit 601. 6, which prevents the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively prevented.

[0452] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0453] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Reveal.

[0454] The electronic device 6500 shown in FIG. 23(A) is a mobile device that can be used as a smartphone. It is a portable information terminal.

[0455] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, and a button 6 504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0456] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0457] FIG. 23B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0458] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. In the space surrounded by the protective member 6510, a display panel 6511, an optical member 6512, and a The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. There are.

[0459] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The panel 6513 is fixed by an adhesive layer (not shown).

[0460] In addition, in an area outside the display portion 6502, a part of the display panel 6511 is folded back. The folded part is connected to the FPC6515. The 6515 is equipped with IC 6516. The FPC 6515 is a printed circuit board 6 517.

[0461] A flexible display panel according to one embodiment of the present invention is applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. 1 is extremely thin, so it can accommodate a large-capacity battery 6518 while keeping the thickness of the electronic device to a minimum. Also, a part of the display panel 6511 can be folded back and an FPC can be attached to the back side of the pixel area. By arranging the connection part with 6515, it is possible to realize electronic devices with narrow bezels.

[0462] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0463] (Embodiment 7) In this embodiment, an electronic device including a display device manufactured according to one embodiment of the present invention will be described. I will explain it below.

[0464] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0465] The display unit of the electronic device according to one embodiment of the present invention may be a display device that supports, for example, full high definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0466] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices that can be used for electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, etc. Examples of the portable electronic device include mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0467] An electronic device to which one aspect of the present invention is applied is installed on the inner or outer wall of a house or building, the interior of a car, etc. The sensor can be installed along a flat or curved surface of a housing or exterior.

[0468] FIG. 24A shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0469] The camera 8000 includes a housing 8001, a display unit 8002, an operation button 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0470] In addition, the camera 8000 may have the lens 8006 and the housing integrated together.

[0471] The camera 8000 can be operated by pressing the shutter button 8004 or by using a touch panel. By touching the display portion 8002, an image can be captured.

[0472] The housing 8001 has a mount having electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as a

[0473] The finder 8100 includes a housing 8101, a display unit 8102, a button 8103, and the like. .

[0474] The housing 8101 is attached to the camera 8000 via a mount that engages with the mount of the camera 8000. The Finder 8100 is attached to the Camera 8000. The information can be displayed on the display unit 8102 .

[0475] The button 8103 has a function such as a power button.

[0476] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied to a camera having a built-in viewfinder. It may be La 8000.

[0477] FIG. 24B is a diagram showing the external appearance of the head mounted display 8200.

[0478] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0479] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0480] In addition, the attachment part 8201 is provided with a flow sensor that flows in accordance with the movement of the user's eyeball at a position where the attachment part 8201 touches the user. A plurality of electrodes capable of detecting a current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse rate of the user by measuring the current flowing through the electrodes. In addition, the mounting part 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function for displaying the user's biological information, and the head of the user may have a function for displaying the user's biological information. The display portion 8204 may have a function of changing an image displayed on the display portion 8204 in accordance with the user's movement.

[0481] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0482] 24(C), 24(D), and 24(E) show a head mounted display 83. 83 is a diagram showing the external appearance of the head mounted display 8300. The head mounted display 8300 includes a housing 8301 and It has a display portion 8302 , a band-shaped fixture 8304 , and a pair of lenses 8305 .

[0483] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but may be configured in such a way that two display units 8302 are provided and one of the display units is One display unit may be arranged for each eye.

[0484] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of the present invention has extremely high definition. Even if the image is magnified using the lens 8305, the pixels are not visible to the user, and the image is more This makes it possible to display images with a higher sense of reality.

[0485] The electronic device shown in FIG. 25A to FIG. 25G includes a housing 9000, a display portion 9001, a switch A speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared rays), 9008, etc.

[0486] The electronic devices shown in FIGS. 25A to 25G have various functions. Function to display various information (still images, videos, text images, etc.) on the display unit, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by a wireless communication function, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data, etc. The electronic device may have a variety of functions, but is not limited to these. Also, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external It has the functions of storing the captured image on a memory card (built into the camera or the internal memory) and displaying the captured image on the display. It is okay to do so.

[0487] The electronic devices shown in FIGS. 25A to 25G will be described in detail below.

[0488] FIG. 25A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more or 100 inches or more It is possible to incorporate.

[0489] FIG. 25B is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. In the example shown in FIG. 9, three icons 9050 are displayed. 051 can be displayed on another surface of the display unit 9001. , notifications of incoming e-mails, SNS, phone calls, etc., subject of e-mails and SNS, sender Name, date, time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0490] FIG. 25C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example in which information 9053 and information 9054 are displayed on different sides is shown. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check information 9053 displayed in a position that can be observed from above 2. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0491] FIG. 25D is a perspective view showing a wristwatch-type portable information terminal 9200. The display surface of the display device 9001 is curved, and the display can be performed along the curved display surface. In addition, the portable information terminal 9200 can communicate with, for example, a wireless headset. By doing so, it is possible to make a call hands-free. A connection terminal 9006 is used to transmit data to and from other information terminals and to charge the device. The charging operation may be performed by wireless power supply.

[0492] 25(E), 25(F), and 25(G) show a foldable portable information terminal 92. FIG. 25(E) shows the mobile information terminal 9201 in an unfolded state. Figure 25(G) shows the folded state, and Figure 25(F) shows the folded state from either Figure 25(E) or Figure 25(G). The portable information terminal 9201 is in a folded state. The is highly portable, and when unfolded, the seamless, wide display area makes it easy to see what is displayed. The display unit 9001 of the portable information terminal 9201 is connected by a hinge 9055. For example, the display unit 9001 has a curvature radius of 1 mm or less. It can be bent up to 150mm.

[0493] FIG. 26A shows an example of a television device. A television device 7100 includes a housing 7 A display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0494] The television device 7100 shown in FIG. 26A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75 A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control operation device 7111 may have a display unit in addition to the operation buttons.

[0495] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0496] FIG. 26B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, The display unit 7500 is assembled in the housing 7211. It is embedded in the

[0497] FIG. 26(C) and FIG. 26(D) show a digital signage. An example of a digital signboard is shown below.

[0498] The digital signage 7300 shown in FIG. 26C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0499] FIG. 26(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0500] The larger the display 7500, the more information can be provided at once, and the closer it is to the human eye. Since it is easy to attach to the skin, it has the effect of increasing the effectiveness of advertising, for example.

[0501] It is preferable that a touch panel be applied to the display unit 7500 so that a user can operate it. This will enable the use of the information not only for advertising purposes, but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide users with information they are looking for.

[0502] Also, as shown in FIG. 26(C) and FIG. 26(D), the digital signage 7300 The digital signage 7400 is a display that is displayed on an information terminal device 7 such as a smartphone carried by a user. It is preferable that the display unit 7500 can wirelessly communicate with the display unit 311. The information on the advertisement to be displayed can be displayed on the screen of the information terminal 7311, and the information terminal 7311 can be used to By operating the buttons, the display on the display unit 7500 can be switched.

[0503] In addition, the Digital Signage 7300 or Digital Signage 7400 can be equipped with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0504] The display portion 7500 in FIG. 26A to FIG. 26D shows a display device according to one embodiment of the present invention. can be applied.

[0505] Although the electronic device of the present embodiment has a display unit, the present invention can be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above-mentioned semiconductor device.

[0506] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. EXAMPLES

[0507] In the following, a sample in which an insulating film applicable to a transistor of one embodiment of the present invention is formed is prepared. , Thermal Desorption Spectroscopy (TDS) The amount of hydrogen released from the insulating film and the oxygen permeability of the insulating film were evaluated by the ion beam spectrometry. The results will be explained below.

[0508] [Example 1-1] [Sample Preparation] First, a 100 nm thick nitride film was deposited on a glass substrate as an insulating film by plasma CVD. Here, three samples (tests) were prepared with different conditions for forming the insulating film. Materials A1 to A3) were prepared.

[0509] The silicon oxynitride film of sample A1 was formed by evaporating silane gas, nitrogen gas, ammonia gas, and monoacid gas. The flow rates of dinitrogen chloride gas were set at 150sccm, 5000sccm, 100sccm, and and 100sccm, pressure 200Pa, deposition power 2000W, substrate temperature 350℃ The film was formed.

[0510] The silicon nitride oxide films of the samples A2 and A3 were formed under the same conditions as those of the sample A1. The film was formed under the conditions of nitrogen dioxide gas flow rate of 500sccm and 1000sccm, respectively. Ta.

[0511] In this manner, Samples A1 to A3 in which an insulating film was formed on a glass substrate were manufactured.

[0512] [TDS analysis] The above samples A1 to A3 were subjected to TDS analysis. The heating rate was 100 / min.

[0513] 27(A) to 27(C) show samples A1 to A3, respectively. The results of TDS analysis are shown in Fig. 27(A) to Fig. 27(C). The horizontal axis shows the mass-to-charge ratio (M / z) of the substrate. emp.), and the vertical axis is the detection intensity. The quantitative values ​​of the amount of desorption per unit volume are also shown.

[0514] It was confirmed that the amount of hydrogen molecules desorbed from the insulating film was small for each sample. It was confirmed that the greater the flow rate of nitrous oxide gas during the membrane process, the smaller the amount of hydrogen molecules desorbed. Ta.

[0515] [Example 1-2] In the following, a silicon nitride oxide film is formed on a silicon oxynitride film that releases oxygen when heated. The formed sample was prepared and the oxygen permeability of the silicon nitride oxide film was examined by TDS analysis. Evaluated.

[0516] [Sample Preparation] First, a silicon oxynitride film with a thickness of about 100 nm was formed on a glass substrate by plasma CVD. A film was formed.

[0517] Next, a metal oxide film is formed on the silicon oxynitride film by sputtering. Then, oxygen radical treatment was performed to supply oxygen into the silicon oxynitride film. The metal oxide film was removed by etching.

[0518] Next, a nitride film having a thickness of about 100 nm is formed on the silicon oxynitride film by plasma CVD. Here, we have three different conditions for forming the silicon oxide nitride film. The following samples (samples B1 to B3) were prepared.

[0519] The silicon oxynitride films of the samples B1, B2, and B3 are the same as those of the samples A1 and A2, respectively. A2 and A3 were deposited under the same conditions.

[0520] As a result, a silicon nitride oxide film is formed on the silicon oxynitride film which releases oxygen by heating. A sample was prepared in which the above were laminated.

[0521] [TDS analysis] FIG. 27(D) to FIG. 27(F) show the TDS analyses of samples B1 to B3, respectively. The results are shown in Fig. 27(D) to (F). The results are shown in the figures. Each figure also shows the quantitative value of the amount of desorption per unit volume. In addition, each figure shows the T of the silicon oxynitride film when the silicon nitride oxide film is not formed. The DS analysis results are shown by the dashed line.

[0522] In each sample, the formation of a silicon oxynitride film suppresses the desorption of oxygen molecules. In other words, it can be seen that the silicon nitride oxide film has an oxygen blocking property. In particular, sample B1, which had the lowest flow rate of nitrous oxide gas during film formation, showed extremely It was confirmed that the film exhibited high oxygen blocking properties.

[0523] From the above, the silicon nitride oxide film produced in this embodiment has an extremely small amount of hydrogen desorption. It was also confirmed that the film had oxygen blocking properties. By applying the same to the insulating layer 103 shown in the first embodiment, particularly to the insulating film 103a, This makes it possible to realize extremely reliable transistors. EXAMPLES

[0524] In the following, transistors having different configurations of insulating layers that form the surface on which the semiconductor layer is formed will be fabricated. The electrical characteristics and reliability of these devices were evaluated and the results are described below.

[0525] [Sample preparation] The structure of the manufactured transistor is the same as that of the transistor 100C described in the first embodiment. can.

[0526] First, a tungsten film with a thickness of about 100 nm was formed on a glass substrate by sputtering. This was processed to obtain the first gate electrode.

[0527] Next, a first gate insulating layer was formed. Four samples (samples C1 to C4) were prepared by applying the above-mentioned method.

[0528] The first gate insulating layer of each of the samples C1 to C3 is a silicon nitride layer having a thickness of about 30 nm. A silicon oxide nitride film having a thickness of about 280 nm and a silicon oxynitride film having a thickness of about 20 nm were used. The film has a laminated structure.

[0529] The silicon nitride film was formed by heating the silane gas, nitrogen gas, and ammonia gas at flow rates of 290 s ccm, 2000sccm, 2000sccm, pressure 200Pa, deposition power 3000 The film was formed under the conditions of W and substrate temperature of 350°C.

[0530] The silicon oxynitride film was formed by setting the flow rates of silane gas and nitrous oxide gas to 100 scc. m, 4000sccm, pressure 200Pa, deposition power 2000W, substrate temperature 350℃ The film was formed under the conditions.

[0531] The silicon oxynitride film of the sample C1 was grown under the same conditions as the sample A1 described in the above Example 1-1. The silicon oxynitride film of sample C2 was formed under the same conditions as those of sample A2. The silicon oxynitride film of C3 was formed under the same conditions as those of the sample A3.

[0532] The first gate insulating layer of the sample C4 is a first silicon nitride film having a thickness of about 200 nm and a A laminated structure of a second silicon nitride film of about 100 nm and a silicon oxynitride film of about 20 nm in thickness. It was constructed as follows.

[0533] The first silicon nitride film was formed under the same conditions as those for the silicon nitride film in the above-mentioned sample C1. did.

[0534] The second silicon nitride film was formed by increasing the flow rate of silane gas, nitrogen gas, and ammonia gas to 1 The flow rates were 50sccm, 5000sccm, and 100sccm, the pressure was 200Pa, and the deposition power was 20 The film was formed under conditions of 300 W and a substrate temperature of 350°C.

[0535] The silicon oxynitride film was formed under the same conditions as the silicon oxynitride film in the above sample C1. The membrane was

[0536] Next, a metal oxide film having a thickness of about 30 nm is formed on the first gate insulating layer, and then heated. The metal oxide film had an atomic ratio of metal elements of In:Ga:Zn=1: The film was formed by sputtering using a sputtering target with a ratio of 1:1. Then, heat treatment was carried out at 370° C. for 1 hour.

[0537] Next, a silicon oxynitride film with a thickness of about 140 nm, which will be the second gate insulating layer, is plasma-etched. The film was formed by the chemical vapor deposition method.

[0538] Next, a conductive film of indium zinc oxide with a thickness of about 20 nm is applied as the second gate electrode. A metal film, a copper film having a thickness of about 100 nm, and an indium zinc oxide film having a thickness of about 30 nm were then Each of the conductive films and the silicon oxynitride film was then deposited by sputtering. After processing, a second gate electrode and a second gate insulating layer were obtained.

[0539] Next, a silicon oxynitride layer about 300 nm thick is applied as a protective insulating layer to cover the transistor. The protective insulating layer was then partially opened by etching. After forming a molybdenum film by sputtering, it was processed to form a source electrode and Then, an acrylic film with a thickness of about 1.5 μm was formed as a flat film. The heat treatment was carried out under a nitrogen atmosphere at a temperature of 250° C. for one hour.

[0540] Through the above steps, sample C, each having a transistor formed on a glass substrate, was obtained. 1 to C4 were obtained.

[0541] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistors of Samples C1 to C4 fabricated above were measured. Sex was measured.

[0542] The measurement conditions for the Id-Vg characteristics of a transistor are the voltage applied to the gate electrode (hereafter referred to as Apply a gate voltage (VG) from -15V to +20V in 0.25V increments. In addition, the voltage applied to the source electrode (hereinafter referred to as source voltage (VS)) was set to 0 V (c omm), and the voltage applied to the drain electrode (hereinafter referred to as drain voltage (VD)) is , 0.1V and 10V.

[0543] Here, the case where the same gate voltage is applied to the first gate electrode and the second gate electrode is The Id-Vg characteristics were measured.

[0544] The measured transistor had a design value of 2 μm channel length and 3 μm channel width. The transistors had a dual-gate structure, and 20 measurements were taken for each sample.

[0545] 28(A) to 28(D) show the Id-Vg characteristics of samples C1 to C4, respectively. In each figure, two Id-V curves are shown for drain voltages of 0.1 V and 10 V. The g characteristics are also shown.

[0546] As shown in Figures 28(A) to 28(D), there was little variation in any of the samples. It can be seen that good electrical properties are obtained without any defects.

[0547] [Reliability assessment] Next, a GBT test was performed to evaluate the reliability of the transistor. The substrate on which the transistor is formed is kept at 60°C, and the source and drain of the transistor are A voltage of 0 V was applied to the input and 20 V or -20 V was applied to the gate, and this state was maintained for one hour. Here, we will focus on PBTS testing.

[0548] FIG. 29 shows the variation in threshold voltage ( In FIG. 29, the first gate electrode and the second gate electrode are connected in series. When the same stress is applied to the first gate electrode (Dual Stress), When only the first gate electrode is stressed (Top Stress), and when only the first gate electrode is stressed (Top Stress), The figures show the results for the case where a stress is applied (Bottom Stress).

[0549] As shown in FIG. 29, the samples C1, C2, and C3 have a lower threshold voltage than the sample C4. It can be seen that the amount of change is small. This indicates that the first gate insulating layer is made of a silicon oxynitride film. It was confirmed that by applying this technique, highly reliable transistors can be realized.

[0550] In addition, the results of the Bottom Stress of samples C1, C2, and C3 were compared. As a result, the amount of variation in the threshold voltage tends to become smaller in this order. From the results of Example 1-1, it is considered that a silicon nitride oxide film that releases less hydrogen is preferable. It is presumed that this can suppress the fluctuation of the threshold voltage.

[0551] From the above, it is considered that the first gate insulating layer is formed of a material that is difficult to release hydrogen and has a high oxygen diffusion property. By using a silicon oxynitride film that is difficult to break down, the characteristics variation is small and the electrical characteristics are good. It was confirmed that a highly reliable transistor could be realized. [Explanation of symbols]

[0552] 10, 10A-10E: transistor, 100, 100A-100C: transistor, 1 02: substrate, 103: insulating layer, 103a to 103c: insulating films, 106: conductive layer, 108, 108a, 108b: semiconductor layer, 108f: metal oxide film, 108n: low resistance region, 11 0, 110a to 110c: insulating film, 112: conductive layer, 112f: conductive film, 114: metal oxide oxide layer, 114f: metal oxide film, 116, 118: insulating layers, 120a, 120b: conductive layers Layer, 140: impurity element, 141a, 141b, 142: opening

Claims

1. a first conductive layer on a substrate; first to third insulating films each having a region located on the first conductive layer; a semiconductor layer each having a region located on the third insulating film; fourth to sixth insulating films each having a region located on the semiconductor layer; a second conductive layer each having a region in contact with an upper surface of the semiconductor layer; and a third conductive layer each having a region located on the sixth insulating film; the second insulating film is located between the first insulating film and the third insulating film; the fifth insulating film is located between the fourth insulating film and the sixth insulating film, the second conductive layer is electrically connected to the semiconductor layer through openings provided in the fourth to sixth insulating films; the semiconductor layer is a metal oxide containing indium, gallium, and zinc; The sixth insulating film has fewer defects than the fourth insulating film and the fifth insulating film.

2. In claim 1, the first insulating film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; The second insulating film contains silicon, nitrogen, and oxygen.

3. In claim 1 or 2, the semiconductor layer includes a first layer and a second layer located on an upper surface of the first layer; The first layer has a higher atomic ratio of gallium than the second layer.

Images