Semiconductor device

Abstract

To provide a semiconductor device with excellent bonding properties, in which the bonding strength between an insulating circuit board, a semiconductor chip, etc., and a printed circuit board is increased.SOLUTION: The semiconductor device comprises: an insulating circuit board 1 that includes conductive layers 12a, 12b; semiconductor chips 3a, 3b; a printed circuit board 6; pin terminals 5a to 5f; external terminals 76, 77 that include supporting portions 76a, 77a arranged on the conductive layers 12a, 12b and terminal portions 76b, 77b connected to the supporting portions 76a, 77a and extending outward in parallel to the conductive layers 12a, 12b, and have an L-shaped bent shape in cross section; and a sealing member 8 that seals the insulating circuit board 1, the semiconductor chips 3a, 3b, the pin terminals 5a to 5f, the printed circuit board 6, and the external terminals 76, 77, and exposes portions of the external terminals 76, 77 from their sides. The height from the top surface of the insulating circuit board 1 to the top surfaces of the supporting portions 76a, 77a is greater than the height from the top surface of the insulating circuit board 1 to the top surfaces of the semiconductor chips 3a, 3b.SELECTED DRAWING: Figure 24

Description

[Technical field]

[0001] The present invention relates to a semiconductor device (semiconductor module) equipped with a power semiconductor chip. [Background technology]

[0002] Semiconductor devices equipped with power semiconductor chips (hereinafter simply referred to as "semiconductor chips") are mainly used for variable speed drive applications such as motors and inverters, and for power conversion applications. The functions and performance required of the semiconductor device vary depending on the application in which the semiconductor device is used, and semiconductor devices with various configurations, structures, and shapes are provided according to the required quality.

[0003] Patent Document 1 describes a heat dissipation structure in which a bead core is arranged between conductive plate materials and a conductive pin is inserted into the hole of the bead core. Patent Document 2 describes a semiconductor module in which a block with a hole is soldered onto an insulating circuit board, a cylindrical slide support member is inserted into the hole, and a pin is inserted into the hole of the slide support member. Patent Document 3 describes a semiconductor device in which a cylindrical contact member is arranged on a conductive plate of an insulating board, an external electrode terminal is fitted into the cylindrical contact member, and an upper end of the external electrode terminal is inserted into a printed circuit board.

[0004] Patent Document 4 describes a direct bonding technique using a bonding material such as solder as a method for connecting an insulating circuit board and a semiconductor element, a semiconductor element and a pin terminal press-fitted into a printed circuit board, and an insulating circuit board and a pin terminal press-fitted into a printed circuit board inside a semiconductor device. It also describes a technique for controlling the bonding distance between the pin terminal and the semiconductor element and the insulating circuit board by changing the depth to which the pin terminal is pressed into a via hole in the printed circuit board.

[0005] Patent Document 5 describes a technique in which a recess is formed in an insulating circuit board and an external terminal is inserted into the printed board to adjust in a self-aligning manner the electrical connection and the relative position between a semiconductor element and a pin terminal press-fitted into the printed board. It also describes a technique in which the connection distance between the pin terminal and the semiconductor element and the insulating circuit board is controlled by the position at which the external terminal is supported in the via hole of the printed board and the press-fit depth of the pin terminal. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2010-109236 A [Patent Document 2] JP 2019-110284 A [Patent Document 3] WO 2017 / 159505 (Figure 9) [Patent Document 4] JP 2013-125804 A [Patent Document 5] JP 2019-161174 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the technology described in Patent Document 4, the heat treatment during bonding of a bonding material such as solder causes deformation of the insulating circuit board and the printed circuit board, and it may not be possible to obtain a predetermined distance between the pin terminals press-fitted into the printed circuit board and the semiconductor element and the insulating circuit board. Also, depending on the degree of deformation of the insulating circuit board and the printed circuit board, electrical connection may not be maintained.

[0008] The technology described in Patent Document 5 was developed in consideration of the above problems, but in a large-capacity semiconductor device, the number of semiconductor elements mounted increases, which increases the dimensions of the insulating circuit board and printed circuit board used, which in turn causes greater deformation of the insulating circuit board and printed circuit board due to the heat treatment during bonding of bonding materials such as solder, and there is a risk that a predetermined distance cannot be maintained between the pin terminals pressed into the printed circuit board and the semiconductor elements and insulating circuit board.

[0009] In view of the above problems, an object of the present invention is to provide a semiconductor device having excellent bonding strength between an insulating circuit board and a printed circuit board, and between a semiconductor chip or the like and a printed circuit board. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device comprising: an insulating circuit board having a conductor layer, a semiconductor chip mounted on the insulating circuit board, a printed board arranged above the semiconductor chip, a pin terminal inserted into the printed board and joined to an upper surface of the semiconductor chip via a bonding material, a support part arranged on a conductive layer of the insulating circuit board, a terminal part connected to the support part and extending outward in parallel to the conductive layer of the insulating circuit board, and an external terminal having an L-shaped bent shape in cross section, and a sealing member that seals the insulating circuit board, the semiconductor chip, the pin terminal, the printed board, and the external terminal and exposes a part of the external terminal from a side, wherein the height from a top surface of the insulating circuit board to a top surface of the support part is greater than the height from the top surface of the insulating circuit board to a top surface of the semiconductor chip.

[0011] The semiconductor device may have a distance between an upper surface of the support and a lower surface of the printed circuit board of 0 to 0.2 mm. The support may be disposed closer to the periphery of the insulating circuit board than the semiconductor chip. The semiconductor device may have a plurality of external terminals, and terminal portions of the external terminals may extend outward from opposing side surfaces of the sealing resin. The semiconductor device may further include other pin terminals that penetrate the printed circuit board and are bonded to the upper surface of the insulating circuit board via a bonding material. Effect of the Invention

[0012] According to the present invention, the bonding strength between the insulating circuit board and the printed circuit board, the semiconductor chip, etc., is increased, and a semiconductor device with excellent bonding properties can be provided. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view of region A in FIG. [Diagram 3] FIG. 2 is an enlarged cross-sectional view of region B in FIG. [Figure 4] FIG. 2 is an enlarged cross-sectional view of a region C in FIG. [Diagram 5] FIG. 2 is an enlarged cross-sectional view of a region D in FIG. [Figure 6] 1A to 1C are cross-sectional views of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 7] 7 is a cross-sectional view continuing from FIG. 6 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8 is a cross-sectional view continuing from FIG. 7 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9 is a cross-sectional view continuing from FIG. 8 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 10 is a cross-sectional view continuing from FIG. 9 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 11 is a cross-sectional view continuing from FIG. 10 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 11 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 13] FIG. 11 is another cross-sectional view of the semiconductor device according to the comparative example. [Figure 14] FIG. 4 is a cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. [Figure 15] FIG. 11 is a cross-sectional view of a portion of a semiconductor device according to a second modified example of the first embodiment. [Figure 16] FIG. 11 is a perspective view of a portion of a semiconductor device according to a second modified example of the first embodiment. [Figure 17] FIG. 11 is a cross-sectional view of a semiconductor device according to a third modified example of the first embodiment. [Figure 18] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth modified example of the first embodiment. [Figure 19] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 20] FIG. 11 is a cross-sectional view of a semiconductor device according to a first modified example of the second embodiment. [Figure 21] FIG. 11 is a cross-sectional view of a semiconductor device according to a second modified example of the second embodiment. [Figure 22] FIG. 11 is a cross-sectional view of a semiconductor device according to a third modified example of the second embodiment. [Diagram 23] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 24] FIG. 13 is a cross-sectional view of a semiconductor device according to a modified example of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the first to third embodiments will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, the drawings may include parts with different dimensional relationships and ratios. In addition, the first to third embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0015] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are reversed and read.

[0016] (First embodiment) <Configuration of Semiconductor Device> 1, the semiconductor device according to the first embodiment includes an insulating circuit board 1, semiconductor chips (semiconductor elements) 3a, 3b mounted on the insulating circuit board 1 via bonding materials 2a, 2b, and a printed circuit board 6 arranged above the semiconductor chips 3a, 3b and spaced apart from the semiconductor chips 3a, 3b. The periphery of the semiconductor chips 3a, 3b and the printed circuit board 6 are sealed with a sealing member 8 and are electrically insulated from the surroundings.

[0017] The insulating circuit board 1 comprises an insulating substrate 11, upper conductor layers 12a and 12b arranged on the upper surface of the insulating substrate 11, which is the circuit side, and a lower conductor layer 13 arranged on the lower surface of the insulating substrate 11, which is the cooling side.

[0018] The insulating circuit board 1 may be, for example, a direct copper bonding (DBC) board or an active metal bonding (AMD) board. The insulating board 11 is composed of a ceramic board made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or a resin insulating board using a polymer material. The upper conductor layers 12a, 12b and the lower conductor layer 13 are composed of conductor foils made of, for example, copper (Cu), aluminum (Al), or the like. The upper conductor layers 12a, 12b form a predetermined circuit pattern.

[0019] The semiconductor chips 3a and 3b are bonded onto the upper conductor layer 12a via bonding materials 2a and 2b. The bonding materials 2a and 2b are made of, for example, solder or a sintered material. For example, tin-antimony (SnSb)-based or tin-silver (SnAg)-based solder can be used as the solder. For example, silver (Ag)-based or copper (Cu)-based metal particle paste (conductive paste) can be used as the sintered material.

[0020] The semiconductor chips 3a and 3b are of different types depending on the application, but may be, for example, power semiconductor elements such as insulated gate bipolar transistors (IGBTs), field effect transistors (FETs), static induction (SI) thyristors, gate turn-off (GTO) thyristors, rectifier elements such as free wheel diodes (FWDs), etc. The semiconductor chips 3a and 3b may be, for example, made of a silicon (Si) substrate, or may be made of a compound semiconductor substrate made of a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3).

[0021] In Fig. 1, two semiconductor chips 3a and 3b are illustrated, but the number of semiconductor chips is not particularly limited. For example, only one semiconductor chip may be included, or three or more semiconductor chips may be included. In Fig. 1, the thicknesses of the semiconductor chips 3a and 3b are different, but the thicknesses of the semiconductor chips 3a and 3b may be the same.

[0022] A printed circuit board 6 is disposed above the semiconductor chips 3a and 3b. The printed circuit board 6 includes an insulating layer 61, an upper wiring layer 62 disposed on the upper surface of the insulating layer 61, and a lower wiring layer 63 disposed on the lower surface of the insulating layer 61. The upper wiring layer 62 and the lower wiring layer 63 form a predetermined circuit pattern.

[0023] The insulating layer 61 is made of an insulating material such as ceramics or resin mainly composed of alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. The insulating layer 61 may be a resin substrate made of a combination of glass fiber and epoxy resin, etc. The upper wiring layer 62 and the lower wiring layer 63 are made of conductive foils made of copper (Cu), aluminum (Al), etc.

[0024] The printed circuit board 6 is provided with a plurality of through holes (via holes) 6x penetrating the insulating layer 61, the upper wiring layer 62, and the lower wiring layer 63. A plurality of pin terminals (post electrodes) 5a to 5h are inserted (press-fitted) and fixed into the plurality of through holes 6x of the printed circuit board 6. The printed circuit board 6 and the pin terminals 5a to 5h constitute an implant substrate (6, 5a to 5h). A conductive layer (not shown) that electrically connects the upper wiring layer 62 and the lower wiring layer 63 may be formed on the inner surface of the plurality of through holes 6x of the printed circuit board 6, and the upper wiring layer 62 and the lower wiring layer 63 may be at the same potential by the conductive layer on the inner surface being electrically connected to the pin terminals 5a to 5h.

[0025] The pin terminals 5a to 5h are, for example, rod-shaped (pin-shaped) or columnar, and specifically may be polygonal prisms such as circular cylinders, elliptical cylinders, triangular prisms, or quadrangular prisms. The pin terminals 5a to 5h may be made of a conductive material such as copper (Cu). Although eight pin terminals 5a to 5h are shown in FIG. 1, the number of pin terminals is not particularly limited.

[0026] The lower ends of pin terminals 5a-5c are bonded to the upper surface of semiconductor chip 3a via bonding materials 4a-4c, respectively. The lower ends of pin terminals 5d-5f are bonded to the upper surface of semiconductor chip 3b via bonding materials 4d-4f, respectively. The lower ends of pin terminals 5g and 5h are bonded to the upper surfaces of upper conductor layers 12a and 12b of insulating circuit board 1 via bonding materials 4g and 4h, respectively.

[0027] For example, when the semiconductor chips 3a and 3b are IGBTs, the semiconductor chips 3a and 3b each have a first main electrode (collector electrode) on the lower surface side, and a control electrode (gate electrode) and a second main electrode (emitter electrode) on the upper surface side. In this case, the first main electrode (collector electrode) on the lower surface side of the semiconductor chips 3a and 3b is bonded to the upper conductor layer 12a of the insulating circuit board 1 via the bonding materials 2a and 2b. The control electrodes (gate electrodes) of the semiconductor chips 3a and 3b are bonded to the pin terminals 5a and 5d, etc. The second main electrodes (emitter electrodes) of the semiconductor chips 3a and 3b are bonded to the pin terminals 5b, 5c, 5e, 5f, etc. that are not bonded to the control electrodes (gate electrodes).

[0028] FIG. 2 shows an enlarged view of the area A including the pin terminals 5a to 5c, which is surrounded by a dashed line in FIG. 1. As shown in FIG. 2, the height H1 from the upper surface of the upper wiring layer 62 of the printed circuit board 6 to the upper surface of the semiconductor chip 3a is, for example, about 100 μm or more and 300 μm or less, but is not limited thereto. The press-fit depth L1 of the pin terminals 5a to 5c into the through-holes 6x is defined as the distance from the upper surface of the upper wiring layer 62 of the printed circuit board 6 to the lower ends of the pin terminals 5a to 5c. The press-fit depth L1 is adjusted to fit the distance L2 from the upper surface of the upper conductor layer 12a of the insulating circuit board 1 to the upper ends of the bonding materials 4a to 4c. In other words, the distance (gap) G11 between the lower ends of the pin terminals 5a to 5c and the upper surface of the semiconductor chip 3a is adjusted to be a predetermined distance. As the distance L2 increases, the press-fit depth L1 of the pin terminals 5a to 5c is made deeper (shorter) and the length of the pin terminals 5a to 5c protruding from the upper surface side of the upper wiring layer 62 of the printed circuit board 6 is made longer.

[0029] FIG. 3 shows an enlarged view of the region B including the pin terminals 5fd-5f, which is surrounded by a dashed line in FIG. 1. As shown in FIG. 3, the height H2 from the upper surface of the upper wiring layer 62 of the printed circuit board 6 to the upper surface of the semiconductor chip 3b is lower than the height H1 shown in FIG. 2. The press-fit depth L3 of the pin terminals 5d-5f into the through-holes 6x is defined as the distance from the upper surface of the upper wiring layer 62 of the printed circuit board 6 to the lower ends of the pin terminals 5d-5f. The press-fit depth L3 is adjusted to fit the distance L4 from the upper surface of the upper conductor layer 12a of the insulating circuit board 1 to the upper ends of the bonding materials 4d-4f. In other words, the distance (gap) G12 between the lower ends of the pin terminals 5d-5f and the upper surface of the semiconductor chip 3b is adjusted to be a predetermined distance.

[0030] Fig. 4 shows an enlarged view of the area C including the pin terminals 5g, 5h, surrounded by a dashed line in Fig. 1. As shown in Fig. 4, the press-fit depth L5 of the pin terminals 5g, 5h into the through-holes 6x is defined as the distance from the upper surface of the upper wiring layer 62 of the printed circuit board 6 to the lower ends of the pin terminals 5g, 5h. The press-fit depth L5 is adjusted to match the distance L6 from the upper surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1 to the upper ends of the bonding materials 4g, 4h. In other words, the distance (gap) L6 between the lower ends of the pin terminals 5g, 5h and the upper surface of the upper wiring layer 62 is adjusted to be a predetermined distance.

[0031] External terminals 71, 72 are bonded onto the upper conductor layers 12a, 12b of the insulating circuit board 1 shown in Fig. 1 via a bonding material (not shown) such as solder or a sintered material. The external terminals 71, 72 may be made of a conductive material such as copper (Cu). The external terminals 71, 72 protrude from the sealing member 8 and are connected to an external circuit.

[0032] For example, if the semiconductor chips 3a and 3b are IGBTs, the external terminal 71 may supply a current to the collector electrodes of the semiconductor chips 3a and 3b via the upper conductor layer 12a. The external terminal 72 may supply a control signal for controlling the on / off of the semiconductor chips 3a and 3b to the gate electrodes of the semiconductor chips 3a and 3b via the upper wiring layer 62 and lower wiring layer 63 of the printed circuit board 6, pin terminals 5c and 5f, etc. The external terminal 72 may output a main current or a measurement current from the emitter electrodes of the semiconductor chips 3a and 3b to an external circuit via the pin terminals 5a, 5b, 5d, and 5e, the upper wiring layer 62 and lower wiring layer 63 of the printed circuit board 6, etc.

[0033] The external terminal 71 includes a support portion (support block) 71a and a terminal portion 71b arranged on the support portion 71a. The external terminal 72 includes a support portion (support block) 72a and a terminal portion 72b arranged on the support portion 72a. The support portions 71a and 72a are integrally formed with the terminal portions 71b and 72b, and form part of the external terminals 71 and 72.

[0034] The shape of the support parts 71a, 72a is, for example, rod-like (pin-like) or column-like, and specifically may be a polygonal prism such as a circular cylinder, an elliptical cylinder, a triangular prism or a quadrangular prism, a plate-like shape, etc. In FIG. 1, the upper surfaces of the support parts 71a, 72a are separated from the lower surface of the lower wiring layer 63 of the printed circuit board 6, but the upper surfaces of the support parts 71a, 72a may be in contact with the lower wiring layer 63 of the printed circuit board 6.

[0035] The supporting portions 71a, 72a have the function of suppressing deformation of the insulating circuit board 1 and the printed circuit board 6 by abutting the lower surface of the printed circuit board 6 against the upper surfaces of the supporting portions 71a, 72a when deformation of the insulating circuit board 1 and the printed circuit board 6 occurs due to a heating process performed when joining the lower ends of the pin terminals 5a-5h to the semiconductor chips 3a, 3b and the upper surface of the insulating circuit board 1 with the bonding materials 4a-4h.

[0036] For example, when the printed circuit board 6 is about to deform convexly upward, it is possible to prevent the lower end of the pin terminal 5a on the peripheral side (left side) of the insulating circuit board 1 from approaching the upper surface of the semiconductor chip 3a and pushing out the bonding material 4a. It is also possible to prevent the lower end of the pin terminal 5h on the peripheral side (right side) of the insulating circuit board 1 from approaching the upper surface of the insulating circuit board 1 and pushing out the bonding material 4h. It is also possible to prevent the lower ends of the pin terminals 5d to 5f on the central side of the insulating circuit board 1 from moving away from the upper surface of the semiconductor chip 3b and causing an open failure with the bonding materials 4d to 4f.

[0037] The shape of the terminal portions 71b, 72b is, for example, rod-like (pin-like) or column-like, and specifically may be a polygonal prism such as a circular cylinder, an elliptical cylinder, a triangular prism or a rectangular prism, a plate-like shape, etc. The terminal portions 71b, 72b are inserted into the multiple through holes 6a, 6b of the printed circuit board 6, respectively. The upper ends of the terminal portions 71b, 72b protrude from the upper surface of the sealing member 8 and are connected to an external circuit.

[0038] 5 shows an enlarged view of an area D including the external terminal 71, surrounded by a dashed line in FIG. 1. The external terminal 72 shown in FIG. 1 has a similar configuration to the external terminal 71. As shown in FIG. 5, the height H0 from the upper surface of the upper conductor layer 12a to the upper surface of the support portion 71a is higher than the heights H1 and H2 from the upper surface of the upper conductor layer 12a to the upper surfaces of the semiconductor chips 3a and 3b shown in FIG. 2 and FIG. 3. In order to suppress deformation of the printed circuit board 6 and the insulating circuit board 1, the distance G1 between the upper surface of the support portion 71a and the lower surface of the lower wiring layer 63 of the printed circuit board 6 is preferably, for example, 0 mm or more and 0.20 mm or less.

[0039] The diameter (width) D1 of the terminal portion 71b is set to be equal to or smaller than the diameter (width) D0 of the through holes 6a and 6b so that the terminal portion 71b can be inserted into the through holes 6a and 6b. The diameter (width) D1 of the support portion 71a is set to be larger (wider) than the diameter (width) D1 of the terminal portion 71b and larger (wider) than the diameter (width) D0 of the through holes 6a and 6b so as to prevent the support portion 71a from being inserted into the through holes 6a and 6b.

[0040] In addition, although two external terminals 71, 72 are illustrated in Fig. 1, the number of external terminals is not limited, and for example, three or more external terminals may be provided. In addition, although a case where the external terminals 71, 72 are arranged on the peripheral side of the insulating circuit board 1 is illustrated in Fig. 1, the arrangement positions of the external terminals 71, 72 are not limited. For example, by arranging the external terminals 71, 72 on the central side of the insulating circuit board 1, it becomes easier to suppress the deformation of the printed circuit board 6 in a convex shape on the lower side. In addition to the external terminals 71, 72 having the support portions 71a, 72a, rod-shaped (pin-shaped) or column-shaped external terminals having no support portions and consisting only of terminal portions may be provided.

[0041] The sealing member 8 constitutes the housing of the semiconductor device according to the first embodiment and has a substantially rectangular parallelepiped shape. The insulating circuit board 1 is exposed from the lower surface of the sealing member 8. As the sealing member 8, for example, a resin material such as a hard thermosetting resin having high heat resistance can be used, and specifically, an epoxy resin, a maleimide resin, a cyanate resin, etc. can be used.

[0042] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing (assembling) the semiconductor device according to the first embodiment will be described mainly with reference to FIGS.

[0043] First, an insulating circuit board 1 is prepared as shown in Fig. 6. The insulating circuit board 1 includes an insulating substrate 11, upper conductor layers 12a and 12b arranged on the upper surface of the insulating substrate 11, and a lower conductor layer 13 arranged on the lower surface of the insulating substrate 11. Next, bonding materials 2a and 2b made of solder, sintered material, or the like are placed (applied) on the upper conductor layers 12a and 12b of the insulating circuit board 1 using a dispenser or the like. Next, as shown in Fig. 7, semiconductor chips 3a and 3b are mounted on the bonding materials 2a and 2b using a conveyor or the like.

[0044] When the bonding materials 2a, 2b are made of solder, the bonding materials 2a, 2b are bonded together with other bonding materials by a heating process described later. However, when the bonding materials 2a, 2b are made of a sintered material, the semiconductor chips 3a, 3b may be bonded to the insulating circuit board 1 via the bonding materials 2a, 2b by mounting the semiconductor chips 3a, 3b and then heating the chips while applying pressure from the upper surfaces of the semiconductor chips 3a, 3b.

[0045] 8, a dispenser or the like is used to place (apply) bonding materials 4a-4h made of solder, sintered material, or the like on the semiconductor chips 3a, 3b and the upper conductor layers 12a, 12b of the insulating circuit board 1. Next, as shown in Fig. 9, external terminals 71, 72 are bonded to the upper conductor layers 12a, 12b of the insulating circuit board 1 via bonding materials (not shown) made of solder, sintered material, or the like.

[0046] Meanwhile, an implant substrate (6, 5a-5h) consisting of a printed circuit board 6 and pin terminals 5a-5h is prepared as shown in Fig. 10. Next, the lower surface of the implant substrate (6, 5a-5h) shown in Fig. 10, i.e., the lower surface of the lower wiring layer 63 of the printed circuit board 6 into which the pin terminals 5a-5h are inserted, is placed opposite the upper surfaces of the semiconductor chips 3a, 3b of the insulating circuit board 1 shown in Fig. 9.

[0047] Next, as shown in Fig. 11, the external terminals 71, 72 are inserted into the through holes 6a, 6b of the printed circuit board 6, while the lower ends of the pin terminals 5a-5h are mounted on the bonding materials 4a-4h and brought into contact with the bonding materials 4a-4h. In Fig. 11, the upper surfaces of the supporting parts 71a, 72a are spaced apart from the lower surface of the lower wiring layer 63 of the printed circuit board 6, but they may be in contact with the lower surface of the lower wiring layer 63 of the printed circuit board 6. It is preferable that the distance G2 from the upper surfaces of the supporting parts 71a, 72a to the lower surface of the lower wiring layer 63 of the printed circuit board 6 when the implant substrate (6, 5a-5h) is mounted is set to be 0 or more and 0.20 mm or less.

[0048] In addition, instead of joining the external terminals 71, 72 onto the insulating circuit board 1 before mounting the implant board (6, 5a to 5h) composed of the printed circuit board 6 and the pin terminals 5a to 5h, the external terminals 71, 72 may be inserted into the implant board (6, 5a to 5h) in advance, and the implant board (6, 5a to 5h) with the external terminals 71, 72 inserted may be mounted on the insulating circuit board 1.

[0049] Next, by heat treatment using a heating furnace, the lower ends of the pin terminals 5a-5h are bonded with the semiconductor chips 3a, 3b and the upper surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1 by bonding materials 4a-4h. Also, the lower surfaces of the semiconductor chips 3a, 3b are bonded with the upper surface of the upper conductor layer 12a of the insulating circuit board 1 by bonding materials 2a, 2b. At this time, the support portions 71a, 72a may be bonded with the upper surface of the upper conductor layer 12a of the insulating circuit board 1 by bonding materials.

[0050] This heat treatment causes deformation of the insulating circuit board 1 and the printed circuit board 6, and when, for example, the distance between the lower ends of the pin terminals 5a-5h press-fitted into the printed circuit board 6 and the upper surface of the semiconductor chips 3a, 3b and the insulating circuit board 1 is about to change, the upper surfaces of the supporting portions 71a, 72a abut against and support the lower surface of the printed circuit board 6, thereby suppressing deformation of the insulating circuit board 1 and the printed circuit board 6. As a result, the lower ends of the pin terminals 5a-5h press-fitted into the printed circuit board 6 and the upper surface of the semiconductor chips 3a, 3b and the insulating circuit board 1 can be maintained at a predetermined distance for good bonding.

[0051] Next, the printed circuit board 6 and the semiconductor chips 3a, 3b are sealed with a sealing member 8. As a result, the semiconductor device shown in FIG. 1 is completed. If no deformation occurs in the insulating circuit board 1 and the printed circuit board 6, the distance G1 from the upper surface of the supporting portion 71a shown in FIG. 5 to the lower surface of the lower wiring layer 63 of the printed circuit board 6 can be equal to the distance G2 before the heat treatment shown in FIG. 11. On the other hand, if deformation occurs in the insulating circuit board 1 and the printed circuit board 6, the distance G1 from the upper surfaces of the supporting portions 71a, 72a shown in FIG. 1 to the lower surface of the lower wiring layer 63 of the printed circuit board 6 can be larger or smaller than the distance G2 before the heat treatment shown in FIG. 11.

[0052] <Comparative Example> Here, a semiconductor device according to a comparative example will be described. As shown in Fig. 12, the semiconductor device according to the comparative example differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the external terminals 7a and 7b are rod-shaped and no support portion is provided.

[0053] In the manufacturing method of the semiconductor device according to the comparative example, the pin terminals 5a-5h press-fitted into the printed circuit board 6 are bonded to the insulating circuit board 1 and the semiconductor chips 3a, 3b via the bonding materials 4a-4h during the heat treatment, which may cause deformation of the insulating circuit board 1 and the printed circuit board 6.

[0054] 13, if the printed circuit board 6 is deformed so as to be convex upward, the distance between the lower ends of the pin terminals 5d-5f at the center of the printed circuit board 6 and the upper surface of the semiconductor chip 3b increases, which may result in an open failure. Also, the distance between the lower ends of the pin terminals 5a-5c, 5g, 5h at the periphery of the printed circuit board 6 and the upper surfaces of the semiconductor chip 3a and the insulating circuit board 1 decreases, which may result in the pin terminals 5a-5c, 5g, 5h pushing out the bonding materials 4a-4c, 4g, 4h, which may result in a bonding failure.

[0055] In contrast, the method for manufacturing a semiconductor device according to the first embodiment can suppress deformation of the insulating circuit board 1 and the printed board 6 due to heat treatment when bonding the pin terminals 5a-5h press-fitted into the printed board 6 to the insulating circuit board 1 and the semiconductor chips 3a, 3b via the bonding materials 4a-4h. This makes it possible to maintain a predetermined distance between the lower ends of the pin terminals 5a-5h press-fitted into the printed board 6 and the upper surfaces of the semiconductor chips 3a, 3b and the insulating circuit board 1, thereby achieving bonding quality with excellent reliability.

[0056] <First Modification of First Embodiment> 14, the semiconductor device according to the first modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the upper surfaces of the support portions 71a, 72a of the external terminals 71, 72 are in contact with the lower surface of the lower wiring layer 63 of the printed circuit board 6. Other configurations of the semiconductor device according to the first modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0057] According to the semiconductor device of the first modified example of the first embodiment, when the upper surfaces of the support portions 71a, 72a of the external terminals 71, 72 need to be electrically connected to the lower wiring layer 63 of the printed circuit board 6, the upper surfaces of the support portions 71a, 72a of the external terminals 71, 72 can be brought into contact with the lower surface of the lower wiring layer 63 of the printed circuit board 6.

[0058] 11, when the implant substrate (6, 5a to 5h) is mounted on the insulating circuit substrate 1 and the semiconductor chips 3a and 3b, the upper surfaces of the supporting portions 71a and 72a may come into contact with the lower surface of the lower wiring layer 63 of the printed circuit board 6. Alternatively, when the implant substrate (6, 5a to 5h) is mounted on the insulating circuit substrate 1 and the semiconductor chips 3a and 3b, the upper surfaces of the supporting portions 71a and 72a are spaced apart from the lower surface of the lower wiring layer 63 of the printed circuit board 6, but as a result of deformation of the printed circuit board 6 due to a subsequent heat treatment, the upper surfaces of the supporting portions 71a and 72a may come into contact with the lower surface of the lower wiring layer 63 of the printed circuit board 6.

[0059] <Second Modification of First Embodiment> As shown in Fig. 15, the semiconductor device according to the second modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the support portions 71a, 72a of the external terminals 71, 72 are separate from the terminal portions 71b, 72b. The support portions 71a, 72a are cylindrical, and the terminal portions 71b, 72b are inserted inside the support portions 71a, 72a.

[0060] In this case, the support portions 71a and 72a may be made of a material different from that of the terminal portions 71b and 72b. For example, the support portions 71a and 72a may be made of an insulating material other than a conductive material such as copper (Cu). The other configurations of the semiconductor device according to the second modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore, repeated explanations will be omitted.

[0061] 16, in the method for manufacturing a semiconductor device according to the second modification of the first embodiment, terminal portion 71b may be press-fitted and inserted inside supporting portion 71a, and then bonded onto insulating circuit board 1. Alternatively, terminal portion 71b may be press-fitted and inserted inside supporting portion 71a after only supporting portion 71a is bonded onto insulating circuit board 1.

[0062] Although the support portions 71a, 72a of the external terminals 71, 72 are similarly structured to be separate from the terminal portions 71b, 72b, the structure may also be such that rod-shaped or column-shaped terminal portions 71b, 72b that are thinner than the support portions 71a, 72a are arranged on the upper surfaces of the rod-shaped or column-shaped support portions 71a, 72a.

[0063] <Third Modification of First Embodiment> As shown in Fig. 17, the semiconductor device according to the third modification of the first embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that recesses 1a, 1b are provided in the upper conductor layers 12a, 12b of the insulating circuit board 1. The lower ends of the support portions 71a, 72a of the external terminals 71, 72 are provided inside the recesses 1a, 1b of the upper conductor layers 12a, 12b. Other configurations of the semiconductor device according to the third modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, so duplicated explanations will be omitted.

[0064] In the method for manufacturing a semiconductor device according to the third modified example of the first embodiment, recesses 1a, 1b are formed by, for example, etching in the upper conductor layers 12a, 12b of the insulating circuit board 1. Next, the lower ends of the support portions 71a, 72a of the external terminals 71, 72 are press-fitted into the recesses 1a, 1b to make them stand on their own.

[0065] <Fourth Modification of First Embodiment> As shown in Fig. 18, the semiconductor device according to the fourth modification of the first embodiment is common to the semiconductor device according to the third modification of the first embodiment shown in Fig. 17 in that recesses 1a, 1b are provided in upper conductor layers 12a, 12b of an insulating circuit substrate 1. However, the semiconductor device according to the fourth modification of the first embodiment differs from the semiconductor device according to the third modification of the first embodiment shown in Fig. 17 in that the diameter (width) of the recesses 1a, 1b is smaller than the diameter (width) of the support portions 71a, 72a of the external terminals 71, 72.

[0066] The external terminals 71, 72 further include protrusions 71c, 72c provided on the lower surfaces of the supports 71a, 72a. The protrusions 71c, 72c of the external terminals 71, 72 are provided inside the recesses 1a, 1b of the upper conductor layers 12a, 12b. Other configurations of the semiconductor device according to the fourth modification of the first embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0067] In the method for manufacturing a semiconductor device according to the fourth modification of the first embodiment, recesses 1a, 1b are formed by, for example, etching or the like in the upper conductor layers 12a, 12b of the insulating circuit board 1. Next, protrusions 71c, 72c of external terminals 71, 72 are press-fitted into the recesses 1a, 1b to make the external terminals 71, 72 self-supporting.

[0068] Second embodiment In the semiconductor device according to the first embodiment, as shown in Fig. 1, the support portions 71a, 72a are integral with the terminal portions 71b, 72b and form part of the external terminals 71, 72. In contrast, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the support portions 73a, 73b are provided separately from the external terminals 9a, 9b, as shown in Fig. 19.

[0069] The shape of the support parts 73a, 73b is, for example, rod-like (pin-like) or column-like, and specifically may be a polygonal prism such as a circular cylinder, an elliptical cylinder, a triangular prism or a square prism, or a plate-like shape. The support parts 73a, 73b may be made of a conductive material such as copper (Cu), or may be made of an insulating material having heat resistance. The support parts 73a, 73b are disposed, for example, directly below the external terminals 9a, 9b, but the positions of the support parts 73a, 73b are not particularly limited.

[0070] A height H0 from the top surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1 to the top surfaces of the supporting portions 73a, 73b is higher than heights H1, H2 from the top surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1 to the semiconductor chips 3a, 3b. The top surfaces of the supporting portions 73a, 73b are spaced apart from the bottom surface of the lower wiring layer 63 of the printed circuit board 6. The top surfaces of the supporting portions 73a, 73b may be in contact with the bottom surface of the lower wiring layer 63 of the printed circuit board 6.

[0071] The external terminals 9a, 9b have, for example, an L-shaped bent shape in a cross-sectional view. The external terminals 9a, 9b may be I-shaped, and the lower ends of the external terminals 9a, 9b may be joined to the printed circuit board 6. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore repeated explanations will be omitted.

[0072] In the method for manufacturing the semiconductor device according to the second embodiment, before the implant substrate (6, 5a to 5h) is mounted on the insulating circuit substrate 1 and the semiconductor chips 3a and 3b, the support portions 73a and 73b are mounted on the upper conductor layers 12a and 12b of the insulating circuit substrate 1 via a bonding material such as solder or a sintered material. Next, the implant substrate (6, 5a to 5h) is mounted on the insulating circuit substrate 1 and the semiconductor chips 3a and 3b, and the lower ends of the pin terminals 5a to 5h of the implant substrate (6, 5a to 5h) are brought into contact with the bonding materials 4a to 4h. Next, the external terminals 9a and 9b are mounted on the printed circuit substrate 6 via a bonding material such as solder or a sintered material.

[0073] Next, a heat treatment is performed to collectively bond the pin terminals 5a-5h to the insulating circuit board 1 and the semiconductor chips 3a, 3b. At this time, if the insulating circuit board 1 and the printed circuit board 6 are about to deform, the lower surface of the insulating circuit board 1 abuts against the upper surfaces of the supporting portions 73a, 73b and is supported, so that the deformation of the insulating circuit board 1 and the printed circuit board 6 can be suppressed.

[0074] The external terminals 9a, 9b may be previously joined to the implant substrates (6, 5a to 5h) before the implant substrates (6, 5a to 5h) are mounted on the insulating circuit substrate 1 and the semiconductor chips 3a, 3b. The other steps of the method for manufacturing a semiconductor device according to the second embodiment are similar to those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore will not be described again.

[0075] According to the manufacturing method of the semiconductor device according to the second embodiment, by providing the support portions 73a and 73b, it is possible to suppress deformation of the insulating circuit board 1 and the printed board 6 due to a heat treatment when bonding the pin terminals 5a-5h press-fitted into the printed board 6 to the insulating circuit board 1 and the semiconductor chips 3a, 3b via the bonding materials 4a-4h. Therefore, it is possible to maintain a predetermined distance between the lower ends of the pin terminals 5a-5h press-fitted into the printed board 6 and the semiconductor chips 3a, 3b and the insulating circuit board 1, and it is possible to obtain bonding quality with excellent reliability.

[0076] <First Modification of Second Embodiment> As shown in Fig. 20, the semiconductor device according to the first modification of the second embodiment differs from the semiconductor device according to the second embodiment shown in Fig. 19 in that recesses 1a, 1b are provided in the upper conductor layers 12a, 12b of the insulating circuit substrate 1. The lower ends of the support portions 73a, 73b are provided inside the recesses 1a, 1b of the upper conductor layers 12a, 12b. Other configurations of the semiconductor device according to the first modification of the second embodiment are similar to those of the semiconductor device according to the second embodiment shown in Fig. 19, and therefore repeated explanations will be omitted.

[0077] In the method for manufacturing a semiconductor device according to the first modified example of the second embodiment, for example, by etching or the like, recesses 1a, 1b are formed in upper conductor layers 12a, 12b of the insulating circuit board 1. Next, the lower ends of supporting portions 73a, 73b are press-fitted into the recesses 1a, 1b to make the supporting portions 73a, 73b self-supporting.

[0078] 18, the width of the recesses 1a, 1b may be narrower than the width of the supporting portions 73a, 73b. In this case, protrusions may be provided on the lower surfaces of the supporting portions 73a, 73b and the protrusions may be disposed in the recesses 1a, 1b.

[0079] <Second Modification of Second Embodiment> As shown in Fig. 21, the semiconductor device according to the second modification of the second embodiment differs from the semiconductor device according to the second embodiment shown in Fig. 19 in that external terminals 9a, 9b are joined onto upper conductor layers 12a, 12b of the insulating circuit board 1. The external terminals 9a, 9b are arranged so as to be sandwiched between the insulating circuit board 1 and the printed circuit board 6. The external terminals 9a, 9b are arranged closer to the periphery of the insulating circuit board 1 than the support portions 73a, 73b.

[0080] The external terminals 9a, 9b have an L-shaped bent shape in a cross-sectional view. One end of each of the external terminals 9a, 9b is joined onto the upper conductor layers 12a, 12b of the insulating circuit board 1 via a joining material (not shown) such as solder. The other end of each of the external terminals 9a, 9b protrudes from the side surface of the sealing member 8 and is connected to an external circuit. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the second embodiment shown in FIG. 19, and therefore repeated explanations will be omitted.

[0081] In the manufacturing method of a semiconductor device according to the second modified example of the second embodiment, external terminals 9a, 9b may be mounted on upper conductor layers 12a, 12b of the insulating circuit board 1 before, simultaneously with, or after the step of mounting supporting portions 73a, 73b on upper conductor layers 12a, 12b of the insulating circuit board 1.

[0082] <Third Modification of Second Embodiment> As shown in Fig. 22, the semiconductor device according to the third modification of the second embodiment is common to the semiconductor device according to the second modification of the second embodiment shown in Fig. 21 in that the external terminals 9a, 9b are joined onto the upper conductor layers 12a, 12b of the insulating circuit board 1. However, the semiconductor device according to the third modification of the second embodiment is different from the semiconductor device according to the second modification of the second embodiment shown in Fig. 21 in that the external terminals 9a, 9b are I-shaped in cross-sectional view.

[0083] The I-shaped external terminals 9a, 9b may extend in the vertical direction and penetrate the printed circuit board 6. In this case, the lower ends of the external terminals 9a, 9b are joined onto the upper conductor layers 12a, 12b of the insulating circuit board 1, and the upper ends of the external terminals 9a, 9b protrude from the upper surface of the sealing member 8. The other configuration of the semiconductor device according to the third modified example of the second embodiment is similar to that of the semiconductor device according to the second embodiment shown in FIG. 19, so duplicated explanations will be omitted.

[0084] In the manufacturing method of a semiconductor device according to the third modified example of the second embodiment, external terminals 9a, 9b may be mounted on upper conductor layers 12a, 12b of the insulating circuit board 1 before, simultaneously with, or after the step of mounting supporting portions 73a, 73b on upper conductor layers 12a, 12b of the insulating circuit board 1.

[0085] Third embodiment 23, the semiconductor device according to the third embodiment is common to the semiconductor device according to the first embodiment shown in Fig. 1 in that the support portions 74a, 75a are integral with the terminal portions 74c, 75c and form part of the external terminals 74, 75. However, the semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment shown in Fig. 1 in that the lower sides of the support portions 74a, 75a are connected to the terminal portions 74c, 75c.

[0086] The external terminals 74, 75 have a U-shaped bent shape in a cross-sectional view. The external terminals 74, 75 are shaped like a column (rod) such as a cylinder or a rectangular column, or like a plate. The external terminal 74 includes a support portion 74a, a joint portion 74b connected to the support portion 74a, and a terminal portion 74c connected to the joint portion 74b. The external terminal 75 includes a support portion 75a, a joint portion 75b connected to the support portion 75a, and a terminal portion 75c connected to the joint portion 75b.

[0087] A height H0 from the top surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1 to the top surfaces of the supporting portions 74a, 75a is greater than heights H1, H2 of the semiconductor chips 3a, 3b from the top surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1. In FIG. 23 , the top surfaces of the supporting portions 74a, 75a are spaced apart from the bottom surface of the lower wiring layer 63 of the printed circuit board 6. However, the top surfaces of the supporting portions 74a, 75a may be in contact with the bottom surface of the lower wiring layer 63 of the printed circuit board 6.

[0088] The joint portions 74b, 75b are joined to the upper surfaces of the upper conductor layers 12a, 12b of the insulating circuit board 1 via a joint material (not shown) such as solder or a sintered material. The terminal portions 74c, 75c penetrate the through holes 6a, 6b of the printed circuit board 6 and protrude from the upper surface of the sealing member 8. Other configurations of the semiconductor device according to the third embodiment are similar to those of the semiconductor device according to the first embodiment shown in FIG. 1, and therefore repeated explanations will be omitted.

[0089] In the manufacturing method of the semiconductor device according to the third embodiment, external terminals 74, 75 are mounted on the upper conductor layers 12a, 12b of the insulating circuit board 1 via bonding materials (not shown) before, simultaneously with, or after mounting the semiconductor chips 3a, 3b via bonding materials 2a, 2b on the upper conductor layers 12a, 12b of the insulating circuit board 1. Next, implant substrates (6, 5a to 5h) are mounted on the insulating circuit board 1 and the semiconductor chips 3a, 3b.

[0090] Next, a heat treatment is performed to collectively bond the pin terminals 5a-5h to the insulating circuit board 1 and the semiconductor chips 3a, 3b. At this time, if the insulating circuit board 1 and the printed circuit board 6 are about to deform, the lower surface of the insulating circuit board 1 abuts against the upper surfaces of the supports 74a, 75a and is supported, so that the deformation of the insulating circuit board 1 and the printed circuit board 6 can be suppressed.

[0091] The external terminals 9a, 9b may be previously joined to the implant substrates (6, 5a to 5h) before the implant substrates (6, 5a to 5h) are mounted on the insulating circuit substrate 1 and the semiconductor chips 3a, 3b. The other steps of the method for manufacturing a semiconductor device according to the third embodiment are similar to those of the method for manufacturing a semiconductor device according to the first embodiment, and therefore will not be described again.

[0092] According to the manufacturing method of the semiconductor device in the third embodiment, as in the manufacturing method of the semiconductor device in the first embodiment, it is possible to suppress deformation of the insulating circuit board 1 and the printed board 6 due to heat treatment when bonding the pin terminals 5a-5h press-fitted into the printed board 6 to the insulating circuit board 1 and the semiconductor chips 3a, 3b via the bonding materials 4a-4h. Therefore, a predetermined distance can be maintained between the pin terminals 5a-5h press-fitted into the printed board 6 and the semiconductor chips 3a, 3b and the insulating circuit board 1, and highly reliable bonding quality can be obtained.

[0093] <Modification of the third embodiment> As shown in FIG. 24, a semiconductor device according to a modified example of the third embodiment differs from the semiconductor device according to the third embodiment shown in FIG. 23 in that the external terminals 76, 77 have an L-shaped bent shape in cross-sectional view.

[0094] The external terminal 76 includes a support portion 76a and a terminal portion 76b connected to the support portion 76a. The external terminal 77 includes a support portion 77a and a terminal portion 77b connected to the support portion 77a. The support portions 76a and 77a are similar to the support portions 74a and 75a of the third embodiment shown in FIG. 23. The upper surfaces of the support portions 76a and 77a are separated from the lower surface of the lower wiring layer 63 of the printed circuit board 6, but may be in contact with the lower surface of the lower wiring layer 63 of the printed circuit board 6.

[0095] The terminal portions 76b, 77b protrude from the side surface of the sealing member 8 without penetrating the printed circuit board 6. Other configurations of the semiconductor device according to the second embodiment are similar to those of the semiconductor device according to the first embodiment, and therefore redundant explanations will be omitted. The method for manufacturing the semiconductor device according to the modified example of the third embodiment is similar to the method for manufacturing the semiconductor device according to the third embodiment.

[0096] (Other embodiments) As described above, the present invention has been described by the first to third embodiments, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0097] For example, the configurations disclosed in the first to third embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is determined only by the invention-specifying matters related to the claims that are appropriate from the above description. [Explanation of symbols]

[0098] 1...Insulated circuit board 1a, 1b...Concave 2a,2b,4a~4h…Joining material 5a~5h...Pin terminals (post electrodes) 6...Printed circuit board 6a,6b,6x…Through hole 7a,7b…External terminal 8...Sealing member 9...Printed circuit board 9a,9b…External terminal 11...Insulating substrate 12a, 12b...Upper conductor layer 13...Lower conductor layer 61...Insulating layer 62...Upper wiring layer 63...Lower wiring layer 71, 72, 74, 75, 76, 77...External terminals 71a, 72a, 73a, 73b, 74a, 75a, 76a, 77a...Support part 71b,72b,74c,75c,76b,77b...Terminal section 71c, 72c…Convex 74b,75b…Joint part

Claims

1. an insulating circuit board having a conductor layer; a semiconductor chip mounted on the insulating circuit board; a printed circuit board disposed above the semiconductor chip; a pin terminal that is inserted into the printed circuit board and bonded to an upper surface of the semiconductor chip via a bonding material; an external terminal including a support portion disposed on the conductive layer of the insulating circuit board and a terminal portion connected to the support portion and extending outward in parallel with the conductive layer of the insulating circuit board, the external terminal having an L-shaped bent shape in a cross-sectional view; a sealing member that seals the insulating circuit board, the semiconductor chip, the pin terminals, the printed circuit board, and the external terminals and exposes parts of the external terminals from side surfaces; Equipped with 4. The semiconductor device according to claim 1, wherein a height from an upper surface of the insulating circuit board to an upper surface of the support portion is greater than a height from the upper surface of the insulating circuit board to an upper surface of the semiconductor chip.

2. 2. The semiconductor device according to claim 1, wherein a distance between an upper surface of the support portion and a lower surface of the printed circuit board is 0 to 0.2 mm.

3. 3. The semiconductor device according to claim 1, wherein the support portion is disposed closer to the periphery of the insulating circuit board than the semiconductor chip.

4. A plurality of the external terminals are provided, 4. The semiconductor device according to claim 3, wherein the terminal portions of the external terminals extend outward from opposing side surfaces of the sealing resin.

5. 4. The semiconductor device according to claim 3, further comprising another pin terminal which penetrates said printed circuit board and is joined to the upper surface of said insulating circuit board via a joining material.

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