Power supply circuit
Patent Information
- Application Number
- JP2024204854
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-02-26
- Estimated Expiration
- Not applicable · inactive patent
Smart Images

Figure 2025027012000001_ABST
Abstract
Description
[Technical field]
[0001] The present embodiment relates to a power supply circuit. [Background technology]
[0002] Conventionally, a power supply circuit technology has been disclosed that adjusts the on-duty of an output transistor using a control loop, and controls the charging of a smoothing capacitor to adjust the output voltage. The load response changes depending on the capacitance value of the smoothing capacitor. When the capacitance value of the smoothing capacitor is large, the circuit operation is stable but the load response is slow. On the other hand, when the capacitance value of the smoothing capacitor is small, the load response is fast but oscillation problems occur, so a configuration to avoid oscillation is required. A power supply circuit that operates stably without depending on the capacitance value of the smoothing capacitor is desired. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2005-184962 A Summary of the Invention [Problem to be solved by the invention]
[0004] An object of one embodiment is to provide a power supply circuit that operates stably without depending on the capacitance value of a smoothing capacitor. [Means for solving the problem]
[0005] According to one embodiment, a power supply circuit comprises a smoothing capacitor that is charged with a charging current from an output transistor and outputs a voltage generated by the charging as an output voltage, and a control loop that controls the conductive state of the output transistor in accordance with a difference value between the output voltage and a reference voltage, the control loop comprising an error amplifier that compares the output voltage with the reference voltage and outputs a control signal to the output transistor in accordance with the difference output, a current detection circuit that outputs a detection signal in accordance with the value of the charging current, and a gain adjustment circuit that adjusts the gain of the error amplifier in accordance with the detection signal. [Brief description of the drawings]
[0006] [Figure 1] FIG. 1 is a diagram showing a configuration of a power supply circuit according to a first embodiment. [Diagram 2] FIG. 2 is a diagram for explaining a method of adjusting the gain of a control loop. [Diagram 3] FIG. 3 is a diagram showing an example of a configuration for adjusting the gain of a control loop. [Figure 4] FIG. 4 is a diagram for explaining the effect of gain adjustment of the control loop. [Diagram 5] FIG. 5 is a diagram showing another example of a configuration for adjusting the gain of a control loop. [Figure 6] FIG. 6 is a diagram for explaining another method of adjusting the gain of the control loop. [Figure 7] FIG. 7 is a diagram showing a configuration of a power supply circuit according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing a configuration of a power supply circuit according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0007] Hereinafter, a power supply circuit according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.
[0008] (First embodiment) FIG. 1 is a diagram showing the configuration of a power supply circuit according to a first embodiment. This embodiment includes a DC voltage source 10. The DC voltage source 10 supplies an input voltage Vin to an input terminal 1. This embodiment includes output transistors Q1 and Q2. The source of the output transistor Q1 is connected to the input terminal 1, and the drain is connected to one end of an inductor L. The drain of the output transistor Q2 is connected to the drain of the output transistor Q1 and one end of the inductor L, and the source is grounded. The output transistors Q1 and Q2 are alternately turned on and off in response to a drive signal from a drive circuit 70, and the conductive state is controlled. The first embodiment constitutes a DC / DC converter of a switching power supply circuit.
[0009] The other end of the inductor L is connected to one end of the smoothing capacitor C. The other end of the smoothing capacitor C is grounded. The smoothing capacitor C is charged by the current supplied from the inductor L. The charging voltage of the smoothing capacitor C, i.e., the voltage at one end of the smoothing capacitor C, is supplied to the output terminal 2 as the output voltage Vout. The output voltage Vout is applied to the load 12.
[0010] This embodiment has a control loop that controls the output voltage Vout to be equal to the reference voltage Vref. The control loop has an error amplifier 40 and a comparison circuit 60. The error amplifier 40 compares the output voltage Vout with the reference voltage Vref, and outputs a control signal control according to the difference between them. When the output voltage Vout becomes higher than the reference voltage Vref, the level of the control signal control becomes higher, and when the output voltage Vout becomes lower than the reference voltage Vref, the level of the control signal control becomes lower.
[0011] The comparator circuit 60 compares the control signal control with the triangular wave from the triangular wave generator circuit 50, generates a PWM (Pulse Width Modulation) signal PWM whose on-duty varies according to the level of the control signal control, and supplies it to the driver circuit 70. The driver circuit 70 supplies a drive signal to the output transistors Q1 and Q2 in response to the PWM signal PWM. In order to avoid a shoot-through current that occurs when the output transistors Q1 and Q2 are simultaneously turned on, the driver circuit 70 provides a dead time for the drive signal before supplying it to the gates of the output transistors Q1 and Q2.
[0012] This embodiment includes a current sensor 11, a current detection circuit 20, and a gain adjustment circuit 30. The current sensor 11 senses the input current Iin output by the output transistor Q1, and supplies a signal corresponding to the input current Iin to the current detection circuit 20. Hereinafter, for convenience, the description will be given assuming that the value of the input current Iin detected by the current sensor 11 is supplied directly to the current detection circuit 20. Also, for convenience, the input current Iin may be referred to as a charging current for the smoothing capacitor C.
[0013] The current detection circuit 20 supplies a detection signal Det corresponding to the input current Iin to the gain adjustment circuit 30. The gain adjustment circuit 30 generates a gain adjustment signal Gn for adjusting the gain of the error amplifier 40 according to the detection signal Det from the current detection circuit 20, and supplies the gain adjustment signal Gn to the error amplifier 40. For example, the gain adjustment circuit 30 selects the gain adjustment signal Gn corresponding to the input current Iin from a data table (not shown) and outputs it. The gain of the error amplifier 40 is adjusted according to the gain adjustment signal Gn.
[0014] The method of adjusting the control loop gain will be explained using Figure 2. In Figure 2, the horizontal axis represents time, and the vertical axis represents the input current Iin. When the power supply circuit starts up, the charging voltage of the smoothing capacitor C, and therefore the output voltage Vout, is zero. When the power supply circuit starts up and the output transistor Q1 turns on, charging of the smoothing capacitor C begins. The input current Iin at this time has a value that corresponds to the difference voltage between the input voltage Vin and the output voltage Vout, which is the charging voltage of the smoothing capacitor C.
[0015] When the value of the smoothing capacitor C is large, it takes time to charge the smoothing capacitor C, and the rise of the output voltage Vout becomes slow. For this reason, at start-up, the larger the capacitance value of the smoothing capacitor C, the larger the input current Iin becomes. Therefore, as the capacitance value of the smoothing capacitor C changes from a small value to a large value, it increases as shown by solid lines 111 to 112 and 113 in FIG. 2. In other words, the larger the capacitance value of the smoothing capacitor C, the longer the detection time T C The input current Iin at the detection time T C By detecting the value of the input current Iin in the input terminal, the magnitude relationship of the capacitance value of the smoothing capacitor C can be detected.
[0016] In this embodiment, the change in the input current Iin caused by the difference in the capacitance value of the smoothing capacitor C is detected, and the gain of the control loop is adjusted. The input current Iin is compared with the threshold values Ith1 and Ith2, and a gain adjustment signal Gn according to the comparison result is supplied to the error amplifier 40 to adjust the gain of the error amplifier 40. When the input current Iin is smaller than the threshold value Ith1, the gain is set to G1, and a gain adjustment signal Gn corresponding to the gain G1 is supplied to the error amplifier 40. Similarly, when the input current Iin is equal to or larger than the threshold value Ith1 and smaller than the threshold value Ith2, the gain is set to G2, and when the input current Iin is equal to or larger than the threshold value Ith2, the gain is set to G3. The gains are set in the order of gain G1 to G3, from smallest to largest. Note that by increasing the number of threshold values Ithn and the number of corresponding gain adjustment signals Gn, the accuracy of detection of the capacitance value of the smoothing capacitor C is improved, and fine-grained gain adjustment of the control loop is possible.
[0017] An example of a configuration for adjusting the gain of the error amplifier 40 will be described with reference to FIG. 3. Configurations corresponding to those in the previously described embodiments are given the same reference numerals, and duplicated descriptions will be given only when necessary. The same applies hereinafter. In this example configuration, the current value of a current source 41 that supplies a bias current to the error amplifier 40 is adjusted by a gain adjustment signal Gn from a gain adjustment circuit 30. By increasing the bias current of the error amplifier 40, the gain of the error amplifier 40 can be increased. By increasing the gain of the error amplifier 40, the gain of the control loop can be increased, and the bandwidth of the control loop can be widened.
[0018] The effect of this embodiment will be described with reference to Fig. 4. The upper part of Fig. 4 shows the bandwidth of the control loop before gain adjustment. The dashed line 100 shows the gain of 0. The dashed line 101 shows the case where the capacitance value of the smoothing capacitor C is the smallest. The dashed line 102 shows the case where the capacitance value of the smoothing capacitor C is the next smallest, and the solid line 103 shows the case where the capacitance value of the smoothing capacitor C is the largest. When the capacitance value of the smoothing capacitor C is the smallest, the load response is fast, the frequency F1 at which the gain becomes 0 is the highest, and the bandwidth of the control loop is the widest. As the capacitance value of the smoothing capacitor C increases, the frequency at which the gain becomes 0 decreases from F2 to F3, and the bandwidth of the control loop narrows.
[0019] The lower part shows the effect of adjusting the gain of the control loop in this embodiment. The gain of the error amplifier 40 is adjusted according to the capacitance value of the smoothing capacitor C. The dashed line 101A corresponds to the dashed line 101 in the upper part, and is the case where the capacitance value of the smoothing capacitor C is the smallest. In this case, the gain of the error amplifier 40 is adjusted by the gain adjustment signal Gn so that it becomes the highest. This adjustment makes it possible to speed up the load response of the control loop and to raise the frequency at which the gain becomes 0 up to F0. In other words, the bandwidth of the control loop can be widened.
[0020] Similarly, the gain of the error amplifier 40 is adjusted according to the capacitance value of the smoothing capacitor C to adjust the bandwidth of the control loop. By such adjustment, for example, it is possible to adjust the frequency indicating the bandwidth to F0 for all the capacitance values of the smoothing capacitor C, regardless of the capacitance value of the smoothing capacitor C. By detecting the input current Iin at the time of startup and automatically adjusting the gain of the control loop, it is possible to adjust the bandwidth of the control loop to be the same, regardless of the capacitance value of the smoothing capacitor C. By such adjustment, it is possible to provide a power supply circuit that performs stable operation independent of the capacitance value of the smoothing capacitor C of the power supply circuit. For example, it is possible to provide a power supply circuit that performs stable operation when the capacitance value of the smoothing capacitor C is changed according to a user's request, or when the capacitance value of the smoothing capacitor C changes due to a change over time.
[0021] 5 is a diagram showing another example of a configuration for adjusting the gain of a control loop. A current detection circuit 20 of this configuration has a comparison circuit 21. The comparison circuit 21 compares an input current Iin with a reference current Ia. When the input current Iin becomes larger than the reference current Ia, the comparison circuit 21 outputs an H-level detection signal Det.
[0022] The gain adjustment circuit 30 of this configuration includes a counter 31, a flip-flop 32, and a setting circuit 33. The counter 31 counts the clock signal CK. The flip-flop 32 responds to the output of the counter 31 and the detection signal Det. The flip-flop 32 supplies the count value of the counter 31 when the detection signal Det becomes H level to the setting circuit 33. That is, the output of the flip-flop 32 becomes a signal indicating the time until the input current Iin reaches the reference current Ia. The setting circuit 33 compares the output of the flip-flop 32 with a threshold value Tthn. The setting circuit 33 outputs a gain adjustment signal Gn according to the comparison result between the output of the flip-flop 32 and the threshold value Tthn.
[0023] The adjustment method by the gain adjustment circuit 30 of this configuration example will be described with reference to Fig. 6. The horizontal axis of Fig. 6 indicates time, and the vertical axis indicates the input current Iin. The comparison circuit 21 detects the timing when the input current Iin reaches the reference current Ia. A signal corresponding to the time it takes for the input current Iin to reach the reference current Ia is output from the flip-flop 32 and compared with a threshold value Tthn in the setting circuit 33. When the capacitance value of the smoothing capacitor C is large, the input current Iin at start-up becomes large, and therefore, as shown by the solid line 123, the time T1 until the input current Iin reaches the reference current Ia is short.
[0024] The smaller the capacitance value of the smoothing capacitor C, the longer the times T2, T3 until the input current Iin reaches the reference current Ia, as shown by solid lines 122, 121. Therefore, by detecting the input current Iin at the start-up of the power supply circuit and detecting the times T1, T2, T3 until the input current Iin reaches the reference current Ia, it is possible to detect the magnitude relationship of the value of the smoothing capacitor C.
[0025] When the time T3 until the input current Iin reaches the reference current Ia is equal to or greater than the threshold value Tth2, the gain G1 with the smallest gain is selected. When the time T2 until the input current Iin reaches the reference current Ia is shorter than the threshold value Tth2 and equal to or greater than the threshold value Tth1, the gain G2 is selected, and when the time T1 until the input current Iin reaches the reference current Ia is shorter than the threshold value Tth1, the gain G3 with the largest gain is selected. The gain of the error amplifier 40 is adjusted according to the gains G1 to G3.
[0026] By this adjustment, when the capacitance value of the smoothing capacitor C is large, the gain of the error amplifier 40 is adjusted to be high, so that the gain of the control loop including the error amplifier 40 becomes high and the load response becomes faster. This makes it possible to widen the bandwidth of the control loop. A power supply circuit is configured in which the gain of the control loop is automatically adjusted according to the magnitude of the capacitance value of the smoothing capacitor C, and the bandwidth of the control loop is automatically adjusted.
[0027] Second embodiment 7 is a diagram showing the configuration of a power supply circuit according to a second embodiment. The control loop of this embodiment has a subtraction circuit 71. The subtraction circuit 71 outputs an output signal according to the difference between the output voltage Vout and the reference voltage Vref. The subtraction circuit 71 is formed of, for example, a differential amplifier circuit. The output signal of the subtraction circuit 71 is supplied to an A / D converter 72. As the A / D converter 72, various A / D converters such as a successive approximation type A / D converter and a flash type A / D converter can be used.
[0028] The A / D converter 72 outputs a digital error value ER[n] in response to the output signal of the subtraction circuit 71. The error value ER[n] is supplied to a digital compensation circuit 73.
[0029] The digital compensation circuit 73 receives the error value ER[n] output by the A / D converter 72, and calculates and outputs a control value CT[n] by PID calculation to perform PID (Proportional Integral Derivative) control so that the output voltage Vout is equal to the reference voltage Vref.
[0030] The control value CT[n] output by the digital compensation circuit 73 is expressed by, for example, the following equation (1). CT[n]=CT[n-1]+K1×ER[n]+K2×ER[n-1] +K3×[n-2]+K4×ER[n-3] ··· (1) Here, ER is an error value, and K1, K2, K3, and K4 are compensation coefficients. [n] is the current value, [n-1] is the value in the previous switching cycle, [n-2] is the value in the switching cycle two cycles ago, and [n-3] is the value in the switching cycle three cycles ago. The control value CT[n] of the digital compensation circuit 73 is supplied to an adder circuit 77.
[0031] This embodiment includes a capacitance calculation circuit 74, a gain adjustment circuit 75, and a duty adjustment circuit 76. The duty adjustment circuit 76 generates an adjustment signal DT that changes the duty of the PWM signal, and supplies the adjustment signal to an adder circuit 77.
[0032] The capacitance calculation circuit 74 generates a calculation signal VC according to the capacitance value of the smoothing capacitor C based on the amount of fluctuation in the error value ER[n]. When the capacitance value of the smoothing capacitor C is large, the amount of change in the output voltage Vout relative to a change in the duty instruction signal duty is small. The capacitance calculation circuit 74 calculates the degree of change in the output voltage Vout when the duty instruction signal duty is changed, and generates and outputs a calculation signal VC according to the capacitance value of the smoothing capacitor C depending on the magnitude of the change. Information indicating that the duty has been adjusted is supplied to the capacitance calculation circuit 74 from the duty adjustment circuit 76.
[0033] The adder circuit 77 adds the control value CT[n] and the adjustment signal DT to generate a duty instruction signal duty, which is then supplied to the digital PWM circuit 78. The digital PWM circuit 78 generates a PWM signal PWM in response to the duty instruction signal duty, and supplies the PWM signal PWM to the drive circuit .
[0034] The on-duty of the PWM signal PWM changes due to the adjustment signal DT from the duty adjustment circuit 76, and the on-time of the output transistors Q1 and Q2 changes. The output voltage Vout changes due to the change in the on-time of the output transistors Q1 and Q2. As a result, the difference between the output voltage Vout and the reference voltage Vref changes, and the error value ER[n] supplied from the A / D converter 72 to the capacitance calculation circuit 74 changes.
[0035] The gain adjustment circuit 75 compares the calculation signal VC from the capacitance calculation circuit 74 with a preset threshold value (not shown), selects a gain adjustment signal Gn according to the comparison result from a data table (not shown), and supplies the selected signal to the digital compensation circuit 73. The compensation coefficients K1, K2, K3, and K4 of the digital compensation circuit 73 are adjusted by the gain adjustment signal Gn.
[0036] When it is detected that the capacitance value of the smoothing capacitor C is small, the compensation coefficients K1, K2, K3, and K4 are adjusted to be smaller, and when it is detected that the capacitance value is large, the compensation coefficients K1, K2, K3, and K4 are adjusted to be larger. The gain of the digital compensation circuit 73 is adjusted by adjusting the compensation coefficients K1, K2, K3, and K4, and the gain of the control loop is adjusted. That is, since the gain of the control loop can be adjusted according to the capacitance value of the smoothing capacitor C, for example, the band of the control loop can be adjusted to be constant regardless of the capacitance value of the smoothing capacitor C. Note that the adjustment of the compensation coefficients of the digital compensation circuit 73 does not have to be made for all the compensation coefficients K1 to K4, and for example, only the compensation coefficient K1 may be adjusted.
[0037] According to this embodiment, the on-duty of the output transistors Q1 and Q2 is intentionally changed, and the magnitude of the capacitance value of the smoothing capacitor C is calculated by detecting the amount of change in the output voltage Vout caused by the change, and the gain of the control loop including the digital compensation circuit 73 is adjusted based on the calculation result. Since the gain of the control loop is adjusted according to the capacitance value of the smoothing capacitor C, a power supply circuit that operates stably regardless of the capacitance value of the smoothing capacitor C is provided. In addition, since the gain of the digital compensation circuit 73 is digitally adjusted, the gain adjustment of the control loop in this embodiment is not easily affected by noise, etc. In addition, since this embodiment is a control based on the amount of change in the output voltage Vout, the current sensor 11 and the current detection circuit 20 of the above-mentioned embodiment can be omitted. The on-duty adjustment by the duty adjustment circuit 76 can be performed when the power supply circuit is in a stable operating state after startup.
[0038] (Third embodiment) FIG. 8 is a diagram showing the configuration of a power supply circuit according to the third embodiment. As in the first embodiment, this embodiment has an error amplifier 40 that compares the output voltage Vout with a reference voltage Vref and outputs a control signal control according to the difference output. The error amplifier 40 forms a control loop that adjusts the conductive state of the output transistor Q1 so that the output voltage Vout is equal to the reference voltage Vref. When the output voltage Vout becomes higher than the reference voltage Vref, the level of the control signal control output by the error amplifier 40 becomes higher, and when the output voltage Vout becomes lower than the reference voltage Vref, the level of the control signal control becomes lower. The gate voltage of the P-channel output transistor Q1 changes according to the level of the control signal control, thereby controlling the conductive state of the output transistor Q1, and controlling the output voltage Vout to be equal to the reference voltage Vref.
[0039] The gain of the error amplifier 40 is adjusted by a gain adjustment signal Gn from the gain adjustment circuit 30. The configuration for comparing the input current Iin at the time of startup with the threshold values Ith1 and Ith2 and generating the gain adjustment signal Gn in accordance with the result of the comparison can be the same as that of the first embodiment.
[0040] In this embodiment, a so-called linear regulator is configured, which controls the conductive state of the output transistor Q1 to make the output voltage Vout equal to the reference voltage Vref. The bandwidth of the control loop can be automatically adjusted by automatically adjusting the gain of the error amplifier 40 that configures the control loop in accordance with the capacitance value of the smoothing capacitor C. This makes it possible to provide a power supply circuit that operates stably and does not depend on the capacitance value of the smoothing capacitor C.
[0041] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]
[0042] 1 input terminal, 2 output terminal, Q1, Q2 output transistors, C smoothing capacitor, 10 DC voltage source, 12 load, 20 current detection circuit, 30 gain adjustment circuit, 40 error amplifier, 50 triangular wave generation circuit, 60 comparison circuit, 70 drive circuit, 73 digital compensation circuit, 74 capacitance calculation circuit, 75 gain adjustment circuit, 76 duty adjustment circuit.
Claims
1. a smoothing capacitor that is charged by a charging current from the output transistor and outputs a voltage generated by the charging as an output voltage; a control loop for controlling a conductive state of the output transistor in response to a difference between the output voltage and a reference voltage; Equipped with The control loop an error amplifier that compares the output voltage with the reference voltage and outputs a control signal to the output transistor in accordance with a difference output between the output voltage and the reference voltage; a current detection circuit that outputs a detection signal corresponding to the value of the charging current; a gain adjustment circuit that adjusts a gain of the error amplifier in response to the detection signal; A power supply circuit comprising:
2. The control loop providing the control signal to a gate of the output transistor; 2. The power supply circuit according to claim 1.
3. an output transistor having a main current path, an input voltage being applied to one end of the main current path and outputting a charging current from the other end; a smoothing capacitor that is charged with the charging current and outputs a voltage generated by the charging as an output voltage; a current detection circuit for detecting the charging current; a control loop having an error amplifier that outputs a difference between the output voltage and a reference voltage; a gain adjustment circuit that adjusts a gain of the error amplifier in response to a change in the charging current after the smoothing capacitor starts to be charged by the charging current; Equipped with The control loop a signal generating circuit for generating a PWM signal whose on-duty is adjusted in response to an output signal of the error amplifier; a drive circuit that generates a drive signal based on the PWM signal and supplies the drive signal to the output transistor. A power supply circuit comprising:
4. The gain adjustment circuit includes:
4. The power supply circuit according to claim 3, wherein the value of the charging current when a predetermined time has elapsed since the charging started is compared with a predetermined threshold value, and a gain corresponding to the comparison result is selected to adjust the gain of the control loop.
5. The gain adjustment circuit includes: comparing a time from the start of the charging until the charging current reaches a predetermined set value with a predetermined threshold value, and selecting a gain corresponding to the comparison result to adjust the gain of the control loop; 4. The power supply circuit according to claim 3.
6. The gain adjustment circuit includes: Adjusting the bias current of the error amplifier to adjust the gain of the error amplifier; 5. The power supply circuit according to claim 4.
7. The gain adjustment circuit includes: Adjusting the bias current of the error amplifier to adjust the gain of the error amplifier; 6. The power supply circuit according to claim 5.
8. The control loop a signal generating circuit for generating a PWM signal whose on-duty is adjusted in response to an output signal of the error amplifier; 4. The power supply circuit according to claim 3.
Citation Information
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