Semiconductor storage device and control method for semiconductor storage device

Abstract

To provide a semiconductor storage device having an OTP memory in which an ECC function with high yield is installed and a control method thereof.SOLUTION: A semiconductor storage device 1 includes: a storage unit 20, which is a one-time programmable memory, having a data memory 21 in which replacement address information of a defective memory cell in a memory cell array 50 detected during a redundancy rescue operation is written, and a check bit memory 22 in which check information added correspondingly to the replacement address information is written; and an error detection and correction unit 30 that performs error detection and correction of the replacement address information based on the check information. The data memory 21 has a unit to which the replacement address information can be written, and the error detection and correction unit is configured not to perform error detection and correction when one of replacement address information and check information corresponding to the replacement address information is written to one unit, and another replacement address information is written to the one unit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device and a method for controlling a semiconductor memory device. [Background technology]

[0002] Large-capacity semiconductor memory devices such as Dynamic Random Access Memories (DRAM) generally employ redundant circuit technology, and when a defective memory cell is detected in a memory cell array, which is a data area, during a rescue test, the defective memory cell is replaced with a redundant memory cell to rescue the defective memory cell and improve the yield. Here, in the semiconductor memory device, address information of a defective memory cell (fail bit) is programmed into an OTP (One Time Programmable) memory that can be written only once. However, defects in the OTP memory itself used to record the address information of the defective memory cell can cause data errors, resulting in a decrease in yield. In order to correct data errors in such OTP memory, there is an OTP memory equipped with an ECC (Error Checking and Correcting) function (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-508658 Summary of the Invention [Problem to be solved by the invention]

[0004] An OTP memory with an ECC function has a data memory and a check bit memory for error correction, and can write data information, which is replacement address information, and check bit information added for error detection / correction corresponding to the data information. In the case of 1-bit error detection / correction, for example, 5 bits of check bit information are added to 16 bits of data information, and 6 bits of check bit information are added to 32 bits of data information. In this way, the larger the unit (ECC unit) for detecting / correcting 1-bit errors, the smaller the ratio of added check bits to data bits can be, but the data bits in the ECC unit are sized to allow multiple sets of replacement address information for defective memory cells in the data area to be input.

[0005] In such a situation, a case where redundancy relief is performed by performing multiple relief test processes (wafer test, post-package test, etc.) after the product is completed will be described. First, when a defective memory cell is detected in the data area in the first relief test process, one set of replacement address information and corresponding check bit information are written in the data memory in the ECC unit. At this time, an area in the data memory where another set of replacement address information can be input remains unwritten. However, even if this second set of replacement address information is to be used in another process, writing to the check bit memory, which is an OTP memory that can be written only once, has already been performed, so writing to the check bit memory is not possible. As a result, when error detection / correction is performed based on the second replacement address information written in the data memory and the check bit information corresponding to the first replacement address information written in the check bit memory, an error occurs, resulting in an overall decrease in yield. On the other hand, the memory that stores the replacement address information needs to be a non-volatile memory. However, adding a dedicated process to the standard CMOS process just for recording the replacement address information is not desirable from a cost standpoint. Therefore, it is desirable to use a non-volatile memory element that can be formed by the standard CMOS process, in particular an OTP memory.

[0006] Therefore, an object of the present invention is to solve the problems of the above-mentioned conventional technology and to provide a semiconductor memory device having an OTP memory equipped with an ECC function with high yield, and a control method for a semiconductor memory device having an OTP memory equipped with an ECC function with high yield. [Means for solving the problem]

[0007] The semiconductor memory device of the present invention has a data memory in which replacement address information of a defective memory cell in a memory cell array detected during a redundancy rescue operation is written, and a check memory in which check information added corresponding to the replacement address information is written, and is equipped with a storage section which is a one-time programmable memory, and an error detection and correction section which performs error detection and correction of the replacement address information based on the check information, wherein the data memory has units into which replacement address information can be written, and the error detection and correction section is configured such that when one of the replacement address information and the check information corresponding to the replacement address information is written to one of the units, the error detection and correction section does not perform the error detection and correction if another replacement address information is further written to one of the units.

[0008] When one of the replacement address information and the check information corresponding to the replacement address information is written in one of the units, if another replacement address information is written in one of the units, and error detection and correction is performed using the other replacement address information and the check information corresponding to the one replacement address information, there is a possibility that an unintended error will be detected. Therefore, in the present invention, by not performing the error detection and correction in such a case, it is possible to suppress the detection of an unintended error and improve the overall yield.

[0009] For this reason, a preferred specific configuration of the present invention is further provided with a control unit, which judges whether or not the check information corresponding to one of the replacement address information is written in one of the units, and when the check information is written, sets a flag to a first logical value, and when the flag is the first logical value, the error detection and correction unit is configured not to perform the error detection and correction. Whether or not to perform error detection and correction can be set by the simple configuration of the control unit setting a flag.

[0010] The control method of a semiconductor memory device of the present invention is a control method of a semiconductor memory device having a data memory into which replacement address information of a defective memory cell in a data area detected during a redundancy rescue operation is written and a check memory into which check information added corresponding to the replacement address information is written, the control method having a storage section which is a one-time programmable memory, the data memory having a unit into which replacement address information can be written, the control method including an error detection and correction step of detecting and correcting errors in the replacement address information based on the check information, and wherein when one of the replacement address information and the check information corresponding to the replacement address information is written to one of the units, the error detection and correction step is not performed when another replacement address information is written to one of the units. Effect of the Invention

[0011] According to the present invention, it is possible to provide a semiconductor memory device having an OTP memory equipped with an ECC function with high yield, and a control method for a semiconductor memory device having an OTP memory equipped with an ECC function with high yield. [Brief description of the drawings]

[0012] [Figure 1] 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] 4 is a diagram illustrating an example of the operation of a storage unit in the semiconductor storage device according to the first embodiment. FIG. [Diagram 3] FIG. 11 is a diagram showing a configuration of a storage unit in a semiconductor storage device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, a semiconductor memory device and a method for controlling the semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiment is merely an example, and the present invention is not limited thereto.

[0014] The semiconductor memory device 1 of the present invention includes a control unit 10, a memory unit 20, an error detection and correction (ECC) unit 30, a replacement address register 40, and a memory cell array 50 which is a data area. The semiconductor memory device 1 of this embodiment is a volatile memory. After the semiconductor memory device 1 is completed, it undergoes a plurality of repair test processes (wafer test, post-package test, etc.) to perform a redundant repair operation for defective memory cells.

[0015] When a defective memory cell is detected by a redundancy relief operation performed on the memory cell array 50, data information dt, which is replacement address information of the defective memory cell, and check bit information cb assigned correspondingly thereto are input to the storage unit 20. Then, an error detection and correction unit 30 provided for this storage unit 20 performs error detection and correction as necessary to obtain replacement address information ss, which is input to the replacement address register 40, and redundancy relief of the memory cell array 50 is performed according to this replacement address information ss. This will be described in detail below.

[0016] When a redundancy rescue operation is started for the memory cell array 50 and a defective memory cell is detected, the control unit 10 generates data information dt which is replacement address information for the defective memory cell and inputs it to the storage unit 20. The control unit 10 also generates check bit information cb corresponding to this data information dt and inputs it to the storage unit 20. The control unit 10 also generates an ECC stop flag fl and inputs it to the storage unit 20. The ECC stop flag fl is a signal indicating a flag for setting the stop / activation of ECC operation by the error detection and correction unit 30, and is at high level "1" when stopped and at low level "0" when ECC operation is performed.

[0017] The storage unit 20 is made of a one-time programmable (OTP) memory. As OTP memories that can be realized by a standard CMOS process, there are fuse elements that are programmed using a laser beam and fuse elements that are programmed electrically, but in this embodiment, fuse elements that are programmed electrically are used. The storage unit 20 includes a data memory 21, a check bit memory (check memory) 22, and an ECC stop memory 23. The data memory 21, the check bit memory 22, and the ECC stop memory 23 of the storage unit 20 are composed of a plurality of memory cells that are two-dimensionally arranged in correspondence with rows and columns. The data memory 21 is a storage area for data information dt that is replacement address information for defective memory cells, the check bit memory 22 is a storage area for check bit information cb that corresponds to the data information dt, and the ECC stop memory 23 is a storage area for an ECC stop flag fl for setting the stop / activation of the ECC operation by the error detection and correction unit 30.

[0018] The data information dt and check bit information cb output from the storage unit 20, and the ECC stop flag fl are input to the error detection and correction unit 30. When the ECC stop flag fl is input as “1” (first logical value), the error detection and correction unit 30 does not perform an error detection and correction operation (error detection and correction step), and generates the data information dt as replacement address information ss as it is. When the ECC stop flag fl is input as “0”, the error detection and correction unit 30 performs error detection and correction from the data information dt and check bit information cb, and corrects any errors, thereby generating correct replacement address information ss. The error detection and correction unit 30 inputs the generated replacement address information ss to the replacement address register 40.

[0019] The replacement address register 40 temporarily records the replacement address information ss input from the error detection and correction unit 30 and outputs it to the memory cell array 50 .

[0020] The memory cell array 50 includes a plurality of memory cells (not shown) that are two-dimensionally arranged in correspondence with rows and columns. The row decoder 51 receives a row address ra that specifies the row direction of the memory cell array and a row replacement address ssr, and decodes them. Then, the row decoder 51 selects a word line according to the decoded result and applies a voltage required for rewriting and reading data. The column decoder 52 receives column address information ca that specifies the column direction of the memory cell array and column replacement address information ssc, and decodes them. Then, the column decoder 52 selects a word line according to the decoded result and applies a voltage required for rewriting and reading data. The row replacement address information ssr of the replacement address information ss input to the replacement address register 40 is input to the row decoder 51, and the column replacement address information ssc is input to the column decoder 52. Note that address information other than the replacement address information is input to each component from a memory controller (not shown in FIG. 1).

[0021] The storage unit 20 will be described in detail with reference to FIG. 2. The data memory 21, check bit memory 22, and ECC stop memory 23 of the storage unit 20 are configured as units. This unit is a unit in which the error detection and correction unit 30 detects / corrects a 1-bit error, and the storage unit 20 is configured from a plurality of units. In this embodiment, the unit does not correspond to a predetermined area of ​​the memory cell array 50, but is not limited to this. Depending on the rescue method of the redundancy rescue operation, the unit may be set to correspond to a predetermined area of ​​the memory cell array 50.

[0022] Each unit of this embodiment will be described in schematic form with reference to Fig. 2. As shown in Fig. 2, the data memory 21 (hereinafter also referred to as data bits) in each unit is composed of 32 bits, the check bit memory 22 (hereinafter also referred to as check bits) is composed of 6 bits, and the ECC stop memory 23 is composed of 1 bit. As described above, the larger the unit that is the unit for detecting / correcting 1-bit errors, the smaller the ratio of the check bits to the data bits to be added, but the size of the data bits is such that multiple sets of replacement address information can be input.

[0023] Specifically, as shown in FIG. 2(1), in this embodiment, for example, the data bits are sized so that one set of replacement address information can be stored in [0]-

[15] , and another set of replacement address information can be stored in

[16] -

[31] . Thus, in this embodiment, the data bits have a size equivalent to two sets of replacement address information, set 1 and set 2. Note that the data bits may be appropriately configured according to the size of the replacement address information and the data bits, for example, one set of replacement address information can be stored in each of [0]-[7], [8]-

[15] ,

[16] -

[23] , and

[24] -

[31] .

[0024] A case will be described in which multiple repair test processes (wafer test, post-package test, etc.) are performed on such a semiconductor memory device 1 after the product is completed, to perform redundancy repair on the memory cell array 50. First, when starting the redundancy repair operation, the control unit 10 judges whether or not the check bits have already been written. If no writing has been performed, the ECC stop flag fl is left at "0."

[0025] Next, when a redundancy rescue operation is started for the memory cell array 50 and a defective memory cell is detected, the control unit 10 inputs replacement address information of the defective memory cell to set 1, i.e., data bits [0] to

[15] , and inputs corresponding check bit information cb to check bits [0] to [5], as shown in Fig. 2(2). Then, this data information dt, check bit information cb, and ECC stop flag fl indicating "0" are input to the error detection and correction unit 30.

[0026] Since the ECC stop flag fl indicating “0” is input, the error detection and correction unit 30 performs error detection and correction based on the data information dt and the check bit information cb. If an error is detected, the error detection and correction unit 30 corrects the error, generates replacement address information, and inputs it to the replacement address register 40.

[0027] Next, when another redundancy rescue operation is started for the memory cell array 50 and a defective memory cell is detected, the control unit 10 inputs replacement address information of the defective memory cell to the data bits

[16] to

[31] as shown in FIG. 2(3). However, since the check bits have already been written with data information corresponding to the data information input to the set 1 by the first redundancy rescue operation, and the storage unit 20 is a one-time programmable memory, it is not possible to input check bit information cb corresponding to the replacement address information input to the set 2. That is, the value input to the check bits remains the check bit information cb corresponding to the replacement address information of the defective memory cell detected in the first redundancy rescue operation. If the data information dt and check bit information cb input to the set 2 are input to the error detection and correction unit 30 as is and an error detection and correction is performed, the expected values ​​of the data bits and the check bits do not match, so that the data bits are detected as an error and the value of the data bits is corrected to an unintended value.

[0028] Therefore, in this embodiment, the control unit 10 performs a flag setting operation (flag setting step) at the timing when this separate redundancy rescue operation is started. In the flag setting operation, the ECC stop flag fl is "0" (second logic value) at the beginning of the operation, and the control unit 10 judges whether or not a check bit has already been written. If the check bit has already been written, the control unit 10 inputs the ECC stop flag fl as "1" (first logic value). Then, when the ECC stop flag fl is input to the error detection and correction unit 30 as "1", the error detection and correction unit 30 does not perform error detection and correction based on the data information dt and the check bit information cb because the ECC stop flag fl indicating "1" has been input. Then, the error detection and correction unit 30 generates the data information dt input to the set 2 as replacement address information ss and inputs it to the replacement address register 40.

[0029] In this manner, in this embodiment, when a plurality of pieces of replacement address information can be written to a data bit, if check information corresponding to this replacement address information is written, the control unit 10 sets the ECC stop flag fl so that the error detection and correction unit 30 does not perform error detection and correction. This makes it possible to prevent unintended errors from being detected in the error detection and correction unit 30, and improves the overall yield.

[0030] In this embodiment, when the ECC stop flag fl is "1" and input to the error detection and correction unit 30, the error detection and correction is not performed. However, when the ECC stop flag fl is "1" and it is confirmed by error evaluation that there is no defective memory cell in the unit, the error detection and correction unit may be configured not to perform the ECC operation. In this case, the error evaluation is performed, for example, by reading the data information dt and the ECC stop flag fl in an accelerated test under conditions such as a voltage outside the range of normal operation conditions, that is, a voltage higher / lower than the voltage value in the normal operation state, and checking whether an error occurs. Preferably, the voltage is lowered below the voltage value in the normal operation state to make the test conditions stricter. The timing of performing this error evaluation may be the timing when the error detection unit detects an error, or may be the timing before all the relief test steps are started, or the timing when each relief test step is started. By performing the error evaluation further in this way, it is possible to increase the reliability of the replacement address information even if the check information corresponding to the second set of replacement address information is not input when the second set of replacement address information is input.

[0031] (Embodiment 2)

[0032] In this embodiment, the above-mentioned ECC stop memory 23 is configured with multiple bits, and is composed of ECC stop data bits and ECC stop check bits, so that even if the ECC stop memory 23 contains a defective memory cell, it is possible to detect and correct it, which is different from embodiment 1.

[0033] 3, in this embodiment, the ECC stop memory 23 constituting the ECC stop flag fl in the unit is composed of a 1-bit ECC stop data bit 31 and a 2-bit ECC stop check bit 32. For example, when the ECC stop data bit 31 is "0" and the ECC stop check bit 32 is "00", the ECC stop flag fl is not set ("0"), and when the ECC stop data bit 31 is "1" and the ECC stop check bit 32 is "11", the ECC stop flag fl is set ("1").

[0034] In this embodiment, the control unit 10 judges whether or not check information has already been written to the check bits at the timing when another redundancy rescue operation is started, and writes to the ECC stop memory according to the result. For example, when check information has already been written to the check bits, the control unit 10 writes "1" to the ECC stop data bit 31 and inputs "11" to the ECC stop check bit 32. Then, before performing the ECC operation, the error detection and correction unit 30 first performs the ECC operation based on the ECC stop data bit 31 and the ECC stop check bit 32 to judge whether the ECC stop flag fl is "1" or "0", and performs the ECC operation according to the result.

[0035] In this manner, in this embodiment, the ECC stop memory 23 of the ECC stop flag fl is constructed from multiple bits, and an error detection bit is added, thereby eliminating the possibility that the ECC stop data bit 31 itself is a defective memory cell, making it possible to more reliably improve yields.

[0036] In each of the above-mentioned embodiments, it is detected that data information dt and check bit information cb have been written in the redundancy rescue operation before the previous time depending on whether check bit information cb has been written in the check bit, but this is not limited to this. For example, it may be detected that data information dt and check bit information cb have been written in the redundancy rescue operation before the previous time depending on whether data information has been written in the data bit. Also, in each of the above-mentioned embodiments, the ECC stop flag fl is set depending on whether check bit information cb has been written in the check bit, but it may be configured not to use the ECC stop flag fl.

[0037] In each of the above-described embodiments, the control unit 10 determines whether or not the check bit information cb has already been written in the check bit memory 22 at the timing when another redundancy rescue operation is started, and inputs "1" to the ECC stop bit, but this is not limited to the above. If the check bit information cb corresponding to the replacement address information is written, the error detection and correction unit 30 may be configured not to perform error detection and correction. For example, the control unit 10 may input "1" as the ECC stop flag fl after performing the first redundancy rescue operation, and the error detection and correction unit 30 may acquire this ECC stop flag fl when performing the next redundancy rescue operation. At any timing, the error detection and correction unit 30 can more preferably activate or stop error detection and correction. [Explanation of symbols]

[0038] 1. Semiconductor memory device 10 Control section 20 Memory section 21 Data Memory 22 Check bit memory 23 ECC stop memory 30 Error detection and correction unit 31 ECC stop data bit 32 ECC stop check bits 40 Replacement Address Register 50 Memory Cell Array 51 Row Decoder 52 Column Decoder fl ECC stop flag ca Column address information cb Check bit information dt Data information ra Row address ss Replacement address information ssc Column replacement address information ssr Row replacement address information

Claims

1. a storage unit which is a one-time programmable memory and which has a data memory in which replacement address information of a defective memory cell of a memory cell array detected during a redundancy relief operation is written, and a check memory in which check information to be added corresponding to the replacement address information is written; an error detection and correction unit that performs error detection and correction of the replacement address information based on the check information; the data memory has a unit in which replacement address information can be written; a plurality of replacement address information units each having ...

2. Further comprising a control unit, The control unit determines whether or not the check information corresponding to one of the replacement address information is written in one of the units; If the check information is written, a flag is set to a first logical value; 2. The semiconductor memory device according to claim 1, wherein the error detection and correction unit is configured not to perform the error detection and correction when the flag is the first logical value.

3. the control unit determines whether the check information corresponding to one of the replacement address information is written in one of the units, and determines whether a defective memory cell is present in the memory cells constituting the unit; 3. The semiconductor memory device according to claim 2, wherein when the check information is written and when the unit does not contain the defective memory cell, the flag is set to the first logic value.

4. The storage unit includes an area for storing flag data information indicating whether or not the check information corresponding to one of the replacement address information is written in one of the units, and flag check bit information to be added to the data information.

3. The semiconductor memory device according to claim 2, wherein the control unit generates the flag data information and the flag check bit information depending on whether the check information corresponding to one of the replacement address information is written in one of the units.

5. The semiconductor memory device according to claim 2, characterized in that the control unit determines whether the check information has been written when starting the redundancy rescue operation, and sets the flag to the first logical value if the check information has been written.

6. 4. The semiconductor memory device according to claim 3, further comprising: applying a voltage at a voltage value outside a voltage range during normal operation to read at least one of the replacement address information and the flag, thereby determining whether or not the memory cells constituting the unit include a defective memory cell.

7. 2. The semiconductor memory device according to claim 1, further comprising a memory cell array which is a data area.

8. 8. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a volatile memory.

9. a data memory in which replacement address information of a defective memory cell of a memory cell array, which is a data area, detected during a redundancy relief operation is written, and a check memory in which check information to be added corresponding to the replacement address information is written, and a storage unit which is a one-time programmable memory; A method for controlling a semiconductor memory device having a unit in which replacement address information can be written, the data memory comprising: an error detection and correction step of detecting and correcting an error in the replacement address information based on the check information; A control method for a semiconductor memory device, characterized in that when one of the replacement address information and the check information corresponding to the replacement address information is written to one of the units, the error detection and correction step is not performed when another replacement address information is written to one of the units.

10. determining whether the check information corresponding to one of the replacement address information is written in one of the units; If the check information is written, a flag setting step of setting a flag to a first logical value is provided; 10. The method for controlling a semiconductor memory device according to claim 9, wherein the error detection and correction step is not performed when the flag is the first logical value.

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