Semiconductor device, method for manufacturing semiconductor device, and electronic device

Abstract

To achieve a semiconductor device having a high withstand voltage.SOLUTION: A semiconductor device 1 includes; a channel layer 10 including a nitride semiconductor and a barrier layer 20 on a surface 10a side of the channel layer; a source electrode 40 and a drain electrode 50 provided on a surface 20a side of the barrier layer 20; and a gate electrode 30 provided between the source electrode 40 and the drain electrode 50. The semiconductor device 1 further includes a polarization layer 60 provided between the gate electrode 30 and the drain electrode 50, on the surface 20a side of the barrier layer 20. The polarization layer 60 includes a nitride semiconductor containing Al, and has an inclined Al composition where an Al composition decreases from a barrier layer 20 side toward a surface 60a side opposite to the barrier layer 20 side. Due to the polarization that occurs in the polarization layer 60, electron concentration in a 2DEG region 80 immediately below the polarization layer is reduced. As a result, electric field concentration of the gate electrode 30 near an end portion on a drain electrode 50 side is alleviated, and a withstand voltage of the semiconductor device 1 can be increased.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. [Background technology]

[0002] A high electron mobility transistor (HEMT) including a barrier layer and a channel layer using a nitride semiconductor is known as one type of semiconductor device. The channel layer is also called an electron transit layer, and the barrier layer is also called an electron supply layer.

[0003] For example, a technique is known in which source, drain and gate contacts are provided on a barrier layer on a channel layer, and a regrowth material is provided between the gate and the source and drain, such as a regrowth material whose Al composition decreases from 1 or a value close to 1 toward the top (Patent Document 1).

[0004] Also, a technology is known in which a cap layer is provided on an electron supply layer on an electron transit layer, the cap layer including a GaN (gallium nitride) layer, an AlN (aluminum nitride) layer, and an AlGaN (aluminum gallium nitride) layer between them, the Al composition of which increases toward the AlN layer (Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Pat. No. 10,553,697 [Patent Document 2] JP 2012-119582 A Summary of the Invention [Problem to be solved by the invention]

[0006] In a semiconductor device such as a HEMT in which a source electrode, a drain electrode, and a gate electrode are provided on a barrier layer on a channel layer, a relatively high voltage may be applied to the drain electrode side during operation. In this case, a relatively high electric field may be applied to the end of the gate electrode on the drain electrode side. If the electric field strength at the end of the gate electrode on the drain electrode side exceeds the limit of the material in the vicinity, the semiconductor device may be destroyed.

[0007] In one aspect, the present invention has an object to provide a semiconductor device with high breakdown voltage. [Means for solving the problem]

[0008] In one aspect, there is provided a semiconductor device comprising: a channel layer including a first nitride semiconductor; a barrier layer including a second nitride semiconductor provided on a first surface side of the channel layer; a source electrode and a drain electrode provided on a second surface side of the barrier layer opposite the channel layer side; a gate electrode provided between the source electrode and the drain electrode on the second surface side of the barrier layer; and a polarization layer including a third nitride semiconductor containing Al provided between the gate electrode and the source electrode and between the gate electrode and the drain electrode on the second surface side of the barrier layer, the polarization layer having an Al composition decreasing from the barrier layer side toward the third surface side opposite the barrier layer side.

[0009] In another aspect, there is provided a method for manufacturing the semiconductor device as described above, and an electronic device including the semiconductor device as described above. Effect of the Invention

[0010] In one aspect, it is possible to realize a semiconductor device with high breakdown voltage. [Brief description of the drawings]

[0011] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Diagram 2]2A to 2C are diagrams illustrating an example of the configuration of a polarization layer of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 2 is a diagram for explaining the relationship between the Al composition and spontaneous polarization of a nitride semiconductor. [Figure 4] 11A and 11B are diagrams illustrating an example of a simulation result of an electron concentration in a semiconductor device. [Diagram 5] FIG. 2 is a diagram illustrating an energy band of an example of a semiconductor device. [Figure 6] 11A and 11B are diagrams illustrating an example of a simulation result of an electric field strength in a semiconductor device. [Figure 7] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to a first embodiment; [Figure 8] FIG. 2 is a second view for explaining an example of the method for manufacturing the semiconductor device according to the first embodiment; [Figure 9] FIG. 11 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 10A to 10C are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 11] 13A to 13C are diagrams illustrating an example of a semiconductor package according to a third embodiment. [Figure 12] FIG. 13 is a diagram illustrating an example of a power factor correction circuit according to a fourth embodiment. [Figure 13] FIG. 13 is a diagram illustrating an example of a power supply device according to a fifth embodiment. [Figure 14] FIG. 13 is a diagram illustrating an example of an amplifier according to a sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] [First embodiment] Fig. 1 is a diagram for explaining an example of a semiconductor device according to the first embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device.

[0013] 1 is an example of a HEMT. The semiconductor device 1 includes a channel layer 10, a barrier layer 20, a gate electrode 30, a source electrode 40, a drain electrode 50, a polarization layer 60, and an insulating film 70.

[0014] The channel layer 10 is made of a nitride semiconductor, for example, GaN. The channel layer 10 may be made of nitride semiconductors such as AlGaN and InGaN (indium gallium nitride) in addition to GaN. The channel layer 10 is formed on a predetermined base substrate (not shown) by, for example, a metal organic chemical vapor deposition (MOCVD) or metal organic vapor phase epitaxy (MOVPE) method, a molecular beam epitaxy (MBE) method, or the like. The base substrate on which the channel layer 10 is formed may be any of various substrates such as SiC (silicon carbide), GaN, Si (silicon), sapphire, diamond, or any of such various substrates on which a nucleation layer or buffer layer such as AlN is formed. The channel layer 10 is formed on a predetermined base substrate such that one surface 10a of the channel layer 10 is a (0001) surface, i.e., a group III polar surface. The channel layer 10 is also called an electron transit layer, or the like.

[0015] The barrier layer 20 is made of a nitride semiconductor, for example, AlGaN. In addition to AlGaN, the barrier layer 20 may be made of nitride semiconductors such as InAlGaN (indium aluminum gallium nitride) and InAlN (indium aluminum nitride). The barrier layer 20 is provided on the face 10a side of the channel layer 10. The barrier layer 20 is formed on the face 10a of the channel layer 10, which is a group III polar face, by using a MOVPE method or the like. The face 20a of the barrier layer 20 opposite to the channel layer 10 side is a (0001) face, that is, a group III polar face. The barrier layer 20 is also called an electron supply layer or the like.

[0016] Here, the channel layer 10 and the barrier layer 20 are made of nitride semiconductors having different band gaps. The barrier layer 20 is made of a nitride semiconductor having a larger band gap than the channel layer 10. A two dimensional electron gas (2DEG) region 80 is generated in the channel layer 10 by spontaneous polarization of the nitride semiconductor of the barrier layer 20 and piezoelectric polarization generated in the barrier layer 20 due to strain caused by a lattice constant difference between the barrier layer 20 and the nitride semiconductor of the channel layer 10. The channel layer 10 and the barrier layer 20 are made of a combination of nitride semiconductors that generates the 2DEG region 80 in the channel layer 10.

[0017] The gate electrode 30 is provided on the surface 20a side of the barrier layer 20. A metal material is used for the gate electrode 30. For example, the gate electrode 30 is a laminate having Ni (nickel) and Au (gold) provided thereon. The gate electrode 30 is formed by using a deposition method or the like. The gate electrode 30 is provided so as to function as, for example, a Schottky electrode. Alternatively, the gate electrode 30 may be provided on the surface 20a side of the barrier layer 20 via a gate insulating film (not shown) and may have a MIS (Metal Insulator Semiconductor) type gate structure.

[0018] The source electrode 40 and the drain electrode 50 are provided on the surface 20a side of the barrier layer 20. The source electrode 40 and the drain electrode 50 are provided on both sides of the gate electrode 30, spaced apart from the gate electrode 30. For example, in order to increase the withstand voltage, the gate electrode 30 may be arranged asymmetrically, that is, closer to the source electrode 40 than the drain electrode 50. A metal material is used for the source electrode 40 and the drain electrode 50. For example, a laminate having Ta (tantalum) or Ti (titanium) and Al (aluminum) provided thereon is provided as the source electrode 40 and the drain electrode 50. The source electrode 40 and the drain electrode 50 are formed by using a deposition method or the like. The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes. If the source electrode 40 and the drain electrode 50 function as ohmic electrodes, they may be connected to the barrier layer 20, or may be connected to the channel layer 10 through the barrier layer 20. A contact layer (regrowth layer) using a nitride semiconductor such as n-type GaN or n-type AlGaN may be provided at a portion of the barrier layer 20 or the channel layer 10 to which the source electrode 40 and the drain electrode 50 are connected.

[0019] The polarization layer 60 is provided between the gate electrode 30 and the drain electrode 50 on the surface 20a side of the barrier layer 20. The polarization layer 60 is provided so as to extend from an end of the gate electrode 30 on the drain electrode 50 side toward the drain electrode 50 side. The polarization layer 60 extends from an end 31 of the gate electrode 30 on the drain electrode 50 side of the bottom surface 30b facing the barrier layer 20 toward the drain electrode 50 side. For example, the polarization layer 60 is provided so as to be separated from the drain electrode 50.

[0020] The polarization layer 60 is made of a nitride semiconductor containing Al. For example, the polarization layer 60 is made of a nitride semiconductor having the general formula In x Al y Ga 1-(x+y) N (0≦x≦1, 0≦y≦1, 0≦x+y≦1) is used. Here, the polarization layer 60 has a structure having a gradient Al composition in which the Al composition decreases from a surface 60b on the barrier layer 20 side toward a surface 60a on the opposite side to the barrier layer 20 side.

[0021] A predetermined polarization occurs in the polarization layer 60 due to its graded Al composition. The polarization occurring in the polarization layer 60 modulates the 2DEG region 80 immediately below the polarization layer 60, reducing the electron concentration in the 2DEG region 80 immediately below the polarization layer 60. Details of the configuration of the polarization layer 60, the polarization occurring therein, and the modulation of the 2DEG region 80 by the polarization will be described later.

[0022] The insulating film 70 is provided on the surface 20a side of the barrier layer 20 so as to cover the gate electrode 30, the source electrode 40, the drain electrode 50 and the polarization layer 60. The insulating film 70 is made of an insulating material such as SiN (silicon nitride).

[0023] Although not shown here, a layer of AlN or the like may be provided between the channel layer 10 and the base substrate on which it is formed as an initial layer, a layer of AlGaN or the like may be provided as a buffer layer, or a layer of GaN or the like doped with Fe (iron) may be provided. In addition, a layer of AlN, AlGaN or the like may be provided between the channel layer 10 and the base substrate as a barrier layer (back barrier layer) for realizing a quantum well (quantum confinement) structure. A layer of AlGaN, InGaN or the like may be provided between the channel layer 10 and the barrier layer 20 as a spacer layer. A layer of GaN or the like may be provided on the surface 20a side of the barrier layer 20 as a cap layer. In addition to the channel layer 10 and the barrier layer 20, the semiconductor device 1 may include one or more of such initial layers, buffer layers, spacer layers, back barrier layers, cap layers, etc.

[0024] The surface 10a of the channel layer 10 is also referred to as the "first surface." The surface 20a of the barrier layer 20 is also referred to as the "second surface." The surface 60a of the polarization layer 60 is also referred to as the "third surface," and the surface 60b is also referred to as the "fourth surface." The nitride semiconductor contained in the channel layer 10 is also referred to as the "first nitride semiconductor." The nitride semiconductor contained in the barrier layer 20 is also referred to as the "second nitride semiconductor." The nitride semiconductor contained in the polarization layer 60 is also referred to as the "third nitride semiconductor."

[0025] When the semiconductor device 1 having the above configuration is in operation, a predetermined voltage is applied between the source electrode 40 and the drain electrode 50, and a predetermined voltage is applied to the gate electrode 30. The amount of charge passing through the 2DEG region 80 immediately below the gate electrode 30 between the source electrode 40 and the drain electrode 50 is controlled by the field effect caused by the voltage applied to the gate electrode 30, thereby controlling the output current. In this manner, the transistor function of the semiconductor device 1 is realized.

[0026] In general, a relatively high voltage may be applied to the drain electrode side during operation of a semiconductor device. In this case, a relatively high electric field may be applied to the end of the gate electrode on the drain electrode side. If the electric field strength at the end of the gate electrode on the drain electrode side exceeds the limit of the material in the vicinity, the semiconductor device may be destroyed.

[0027] In contrast, in the semiconductor device 1 having the above configuration, a polarization layer 60 having a graded Al composition is provided at the end of the gate electrode 30 on the drain electrode 50 side so as to extend from there toward the drain electrode 50 side. The polarization generated in the polarization layer 60 modulates the 2DEG region 80 directly below the polarization layer 60, reducing its electron concentration. This alleviates electric field concentration near the end of the gate electrode 30 on the drain electrode 50 side. As a result, the material near the end is prevented from reaching a breakdown electric field, and the semiconductor device 1 is prevented from being destroyed. By providing the polarization layer 60, a semiconductor device 1 with high breakdown voltage is realized.

[0028] The polarization layer 60 of the semiconductor device 1 will now be described in detail. 2A and 2B are diagrams illustrating an example of the configuration of the polarization layer of the semiconductor device according to the first embodiment, each of which is a schematic cross-sectional view of a main part of an example of the semiconductor device.

[0029] 2(A), the polarization layer 60 is provided on the surface 20a of the barrier layer 20 between the gate electrode 30 and the drain electrode 50. The polarization layer 60 extends from an end 31 of the gate electrode 30 on the drain electrode 50 side of the bottom surface 30b facing the barrier layer 20 toward the drain electrode 50. FIG. 2(A) shows, as an example, a configuration in which the polarization layer 60 extending from the end 31 of the gate electrode 30 does not reach the drain electrode 50, i.e., a configuration in which the polarization layer 60 is separated from the drain electrode 50.

[0030] The gate electrode 30 is shaped so that, for example, a part of the gate electrode 30 is provided on the surface 60a of the polarization layer 60 opposite to the surface 60b of the barrier layer 20 side of the drain electrode 50, that is, so as to ride on the surface 60a. As shown in FIG. 1, the gate electrode 30 is shaped so that an insulating film 70 is interposed between the part of the gate electrode 30 and the barrier layer 20 on the source electrode 40 side. In other words, the gate electrode 30 is so-called T-shaped (FIG. 1). By adopting such a T-shaped shape for the gate electrode 30, it is possible to reduce the gate length while increasing the cross-sectional area and thereby reduce the gate resistance. In addition, by adopting such a T-shaped shape for the gate electrode 30, it is possible to alleviate electric field concentration by the field plate effect and increase the breakdown voltage.

[0031] The polarization layer 60 includes a nitride semiconductor containing Al. The polarization layer 60 has a gradient Al composition in which the Al composition decreases from a surface 60b on the barrier layer 20 side toward a surface 60a on the opposite side to the barrier layer 20 side. A predetermined polarization is generated in the polarization layer 60 due to the gradient Al composition. The polarization generated in the polarization layer 60 modulates a 2DEG region 80 directly below the polarization layer 60, that is, the 2DEG region 80 corresponding to the region AR1 shown in FIG. 2(A), and the electron concentration in the region AR1 is reduced.

[0032] 2B shows an example of the configuration of the polarization layer 60, the barrier layer 20 on which the polarization layer 60 is provided, and the channel layer 10 thereunder. In this example, the Al 0.3 Ga 0.7A barrier layer 20 of N is provided. A polarization layer 60 of Al is provided on the surface 20a side of the barrier layer 20. 0.3 Ga 0.7 The first layer of N is 61, Al 0.1 Ga 0.9 The polarization layer 60 is thus formed with a second layer 62 of N and a third layer 63 of GaN. The polarization layer 60 is thus formed with a Al composition that decreases from the surface 60b to the surface 60a. 0.3 Ga 0.7 N, Al 0.1 Ga 0.9 It can have a three-layer structure of N and GaN.

[0033] For example, the Al composition of the first layer 61 located closest to the barrier layer 20 of the polarization layer 60 can be the same as the Al composition of the barrier layer 20. That is, the Al composition of the surface 60b of the polarization layer 60 on the barrier layer 20 side can be the same as the Al composition of the surface 20a of the barrier layer 20 on the polarization layer 60 side. In the example of FIG. 2(B), the Al composition of the surface 60b of the polarization layer 60 and the Al composition of the surface 20a of the barrier layer 20 are both set to 0.3. The Al composition of the third layer 63 located closest to the barrier layer 20 side of the polarization layer 60 can be set to 0. In the example of FIG. 2(B), GaN is used for the third layer 63. In this way, the polarization layer 60 may include a layer that does not contain Al in a part thereof.

[0034] As shown in FIG. 2B, both the polarization layer 60 and the barrier layer 20 are made of Al. 0.3 Ga 0.7 By using N and making the Al composition on the surface 60b and the surface 20a the same, lattice mismatch between the first layer 61 of the polarization layer 60 and the barrier layer 20 and the occurrence of crystal defects due to this are suppressed. 0.3 Ga 0.7 N, Al 0.1 Ga 0.9 By using N and GaN and adopting a layered structure in which the Al composition decreases from surface 60b to surface 60a, lattice mismatch between the first layer 61 and the second layer 62, and between the second layer 62 and the third layer 63, and the resulting occurrence of crystal defects, are suppressed.

[0035] The Al composition of the barrier layer 20 and the Al compositions of the first layer 61, the second layer 62, and the third layer 63 of the polarization layer 60 are not limited to those shown in FIG. 2(B). For example, the Al composition of the barrier layer 20 (surface 20a) and the Al composition of the first layer 61 (surface 60b) of the polarization layer 60 are not limited to the illustrated 0.3, and do not necessarily have to be the same as long as the occurrence of lattice mismatch and crystal defects between them is suppressed. The Al composition of the second layer 62 of the polarization layer 60 is not limited to the illustrated 0.1 as long as it is lower than the Al composition of the first layer 61, and may be a value smaller than 0.1 or larger than 0.1 depending on the Al composition of the first layer 61. The third layer 63 of the polarization layer 60 may contain Al as long as it is lower than the Al composition of the second layer 62. Furthermore, the number of layers in the polarizing layer 60 is not limited to three, but may be two or four or more layers as long as the Al composition has a gradient in which the Al composition decreases from the surface 60b toward the surface 60a.

[0036] The polarizing layer 60 shown in FIG. 2(A) is made of Al 0.3 Ga 0.7 N, Al 0.1 Ga 0.9 The polarization layer 60 has a structure having a gradient Al composition in which the Al composition decreases from the surface 60b toward the surface 60a, such as a three-layered structure of N and GaN.

[0037] Here, the polarization occurring in the polarizing layer 60 will be described. Figure 3 is a diagram explaining the relationship between the Al composition and spontaneous polarization of a nitride semiconductor. Figure 3(A) is a diagram showing the spontaneous polarization of an AlN layer. Figure 3(B) is a diagram showing the spontaneous polarization of a GaN layer or the like. Figure 3(C) is a diagram showing the spontaneous polarization of an AlGaN layer or the like.

[0038] Nitride semiconductors have a spontaneous polarization along the

[0001] direction (c-axis). As an example, the spontaneous polarization of AlN is -0.081 C / m 2 The spontaneous polarization of GaN is -0.029C / m2 The spontaneous polarization of InN (indium nitride) is -0.032C / m 2 GaN and InN have similar spontaneous polarizations, while AlN has a stronger spontaneous polarization.

[0039] When the (0001) plane is used, for example, as shown in Figures 3(A) and 3(B), negative charges (indicated by "-") are generated on the upper end side of each of the nitride semiconductor layers 100a and 100b, and positive charges (indicated by "+") are generated on the lower end side. Since AlN has a stronger spontaneous polarization than GaN, the amount of charge generated in the AlN layer 100a is greater than the amount of charge generated in the GaN layer 100b. Note that, since InN has the same degree of spontaneous polarization as GaN, the same can be said about InN and InGaN, in which part of GaN is replaced with InN (Figure 3(B)).

[0040] AlGaN in which a part of GaN is replaced by AlN (or AlGaN in which a part of AlN is replaced by GaN) has an intermediate charge between AlN and GaN depending on the Al composition. At this time, when the Al composition of AlGaN is decreased toward the top end of the layer, the relatively large amount of negative charge generated at the top end of the lower layer in the layer is offset by the relatively small amount of positive charge generated at the bottom end of the upper layer stacked directly above it. Therefore, in the entire layer including them, spontaneous polarization occurs as shown in layer 100c shown in FIG. 3(C), and negative charges are generated over a wide range in the layer 100c. AlGaN in which the Al composition is decreased toward the top end of the layer 100c exhibits the properties of a p-type semiconductor (also called "p-type semiconductivity") due to the generation of negative charges over a wide range in the layer 100c, that is, the generation of negative fixed charges spreading throughout the layer 100c. The expression of p-type semiconductivity by changing the Al composition in this way is also called "polarization doping" or "polarization p-doping".

[0041] In addition, since InN and GaN have the same degree of spontaneous polarization, the same can be said about InAlN, in which part of InN is replaced with AlN, and about InAlGaN, in which part of InGaN is replaced with InN, and part of InAlGaN is replaced with AlN.

[0042] In the semiconductor device 1 as shown in Figures 1, 2(A) and 2(B) above, a nitride semiconductor with a gradient Al composition that exhibits p-type semiconducting properties by decreasing the Al composition from surface 60b toward surface 60a is used for the polarization layer 60.

[0043] In the semiconductor device 1, the polarization layer 60 may be made of AlGaN having an Al composition that decreases from the surface 60b to the surface 60a. The polarization layer 60 may be made of InAlN having an Al composition that decreases from the surface 60b to the surface 60a. The polarization layer 60 may be made of InAlGaN having an Al composition that decreases from the surface 60b to the surface 60a. The polarization layer 60 may be made of a combination of two or more of AlGaN, InAlN, and InAlGaN, as long as the Al composition decreases from the surface 60b to the surface 60a. The bottom layer (surface 60b side) of the polarization layer 60 may include an AlN layer, and the top layer (surface 60a side) of the polarization layer 60 may include a GaN, InN, or InGaN layer.

[0044] The polarization layer 60 may be made of a nitride semiconductor containing Al, and may have a structure represented by the general formula In x Al y Ga 1-(x+y) A nitride semiconductor including a layer portion represented by N (0≦x≦1, 0≦y≦1, 0≦x+y≦1) can be used. The polarization layer 60 is formed on the surface 20a side of the barrier layer 20 by using a MOVPE method or the like so that the Al composition decreases from the surface 60b toward the surface 60a.

[0045] 4A and 4B are diagrams for explaining an example of a simulation result of electron concentration in a semiconductor device. Fig. 4A shows an example of a semiconductor device model. Fig. 4B shows an example of an electron concentration distribution.

[0046] The semiconductor device model 1a shown in FIG. 4A is a GaN channel layer 10 and an Al 0.3 Ga 0.7 The semiconductor device includes a barrier layer 20 of N and a gate electrode 30 (G) provided on the surface 20a side of the barrier layer 20. A 2DEG region 80 is generated in the channel layer 10 on which the barrier layer 20 is laminated. A polarization layer 60 is provided at one end of the gate electrode 30 on the surface 20a side of the barrier layer 20. In FIG. 4(A), the polarization layer 60 is shown by a dotted line. The polarization layer 60 is made of Al 0.3 Ga 0.7 The first layer of N is 61, Al 0.1 Ga 0.9 A second layer 62 of N and a third layer 63 of GaN are provided. The gate electrode 30 and the polarizing layer 60 are covered with an insulating layer 70 of SiN.

[0047] In FIG. 4B, the electron concentration distribution in the 2DEG region 80 in the semiconductor device model 1a when the polarization layer 60 is not provided is shown by a solid line, and the electron concentration distribution in the 2DEG region 80 when the polarization layer 60 (shown by a dotted line in FIG. 4A) is provided is shown by a dotted line. In the 2DEG region 80 shown in FIG. 4A, in the regions a and c sandwiching the region b immediately below the end of the gate electrode 30, as shown in FIG. 4B, there is no significant difference in electron concentration between the case where the polarization layer 60 is provided and the case where it is not provided at the end of the gate electrode 30. On the other hand, in the region b immediately below the end of the gate electrode 30 in the 2DEG region 80 shown in FIG. 4A, as shown in FIG. 4B, the electron concentration is lower when the polarization layer 60 is provided (shown by a dotted line as "with polarization layer") than when the polarization layer 60 is not provided at the end of the gate electrode 30 (shown by a solid line as "without polarization layer").

[0048] Fig. 5 is a diagram for explaining the energy band of an example of a semiconductor device. Fig. 5(A) shows an example of a semiconductor device model. Fig. 5(B) to Fig. 5(D) each show an example of a conduction band at a specific portion in the semiconductor device model. Fig. 5(E) shows an example of modulation of the 2DEG region.

[0049] The semiconductor device model 1b shown in FIG. 5A is a GaN channel layer 10 and an Al 0.3 Ga 0.7 The semiconductor device includes a barrier layer 20 of N, a gate electrode 30 (G), a source electrode 40 (S), and a drain electrode 50 (D) provided on the surface 20a side of the barrier layer 20. A 2DEG region 80 is generated in the channel layer 10 on which the barrier layer 20 is laminated. A polarization layer 60 is provided on the end of the gate electrode 30 on the drain electrode 50 side on the surface 20a side of the barrier layer 20. The polarization layer 60 is made of Al 0.3 Ga 0.7 The first layer of N is 61, Al 0.1 Ga 0.9 A second layer 62 of N and a third layer 63 of GaN are provided. The gate electrode 30, the source electrode 40, the drain electrode 50 and the polarizing layer 60 are covered with an insulating film 70 of SiN.

[0050] 5(B) shows an example of the conduction band Ec of a portion d corresponding to the end of the gate electrode 30 on the source electrode 40 side of the semiconductor device model 1b shown in FIG. 5(A). As shown in FIG. 5(A) and FIG. 5(B), in the portion d, the GaN of the channel layer 10, the Al of the barrier layer 20, and the GaN of the barrier layer 20 are arranged in that order from the channel layer 10 side. 0.3 Ga 0.7 A structure in which a SiN insulating film 70 is laminated and reaches the gate electrode 30 is obtained.

[0051] 5(C) shows an example of the conduction band Ec of the portion e corresponding to the gate electrode 30 of the semiconductor device model 1b shown in FIG. 5(A). As shown in FIG. 5(A) and FIG. 5(C), in the portion e, the GaN of the channel layer 10, the Al of the barrier layer 20, and the GaN of the barrier layer 20 are arranged in that order from the channel layer 10 side. 0.3 Ga 0.7 N is laminated to form a structure that reaches the gate electrode 30.

[0052] 5(D) shows an example of the conduction band Ec of a portion f corresponding to the end of the gate electrode 30 on the drain electrode 50 side of the semiconductor device model 1b shown in FIG. 5(A). As shown in FIG. 5(A) and FIG. 5(D), in the portion f, the GaN of the channel layer 10, the Al of the barrier layer 20, and the GaN of the barrier layer 20 are arranged in that order from the channel layer 10 side. 0.3 Ga 0.7 N, Al of the first layer 61 of the polarizing layer 60 0.3 Ga 0.7 N, Al of the second layer 62 of the polarizing layer 60 0.1 Ga 0.9 N, GaN of the third layer 63 of the polarizing layer 60 is laminated, resulting in a structure that reaches the gate electrode 30.

[0053] 5(E) shows the conduction band Ec at the portion f (FIG. 5(D)) where the polarization layer 60 is provided, i.e., the end of the gate electrode 30 on the drain electrode 50 side, by a solid line, and for comparison, shows the conduction band Ec when the polarization layer 60 is not provided at the portion f by a dotted line. In FIG. 5(E), Ef represents the Fermi level. The conduction band Ec at the junction interface between the channel layer 10 and the barrier layer 20 is lower (lower energy side) than the Fermi level Ef, so that a 2DEG region 80 is generated in the channel layer 10 near the junction interface with the barrier layer 20.

[0054] In the polarization layer 60 with a graded Al composition, negative fixed charges are generated in the layer (FIG. 3(C)), and p-type semiconductivity is expressed. Such a polarization layer 60 with a graded Al composition that expresses p-type semiconductivity is provided at the end of the gate electrode 30 on the drain electrode 50 side. As a result, when the polarization layer 60 is provided (solid line in FIG. 5(E)), the conduction band Ec of the channel layer 10 is raised compared to when the polarization layer 60 is not provided at the end of the gate electrode 30 on the drain electrode 50 side (dotted line in FIG. 5(E)).

[0055] That is, when the polarization layer 60 is not provided at the end of the gate electrode 30 on the drain electrode 50 side, the conduction band Ec of the channel layer 10 becomes relatively low, as shown by the dotted line in Fig. 5(E). In contrast, when the polarization layer 60 is provided at the end of the gate electrode 30 on the drain electrode 50 side, the conduction band Ec of the channel layer 10 is raised (schematically shown by the thick arrow in Fig. 5(E)) and becomes relatively high, as shown by the solid line in Fig. 5(E) due to the p-type semiconductivity of the polarization layer 60. By raising the conduction band Ec by the polarization layer 60, the potential below the Fermi level Ef is modulated so as to be raised, and the electron concentration in the 2DEG region 80 is reduced.

[0056] In the semiconductor device 1, a polarization layer 60 is provided at the end of the gate electrode 30 on the drain electrode 50 side, and the polarization of the polarization layer 60 raises the conduction band Ec directly below the polarization layer 60, modulating the 2DEG region 80 and reducing the electron concentration in the 2DEG region 80 directly below the polarization layer 60.

[0057] 6A and 6B are diagrams for explaining an example of a simulation result of an electric field strength in a semiconductor device. Fig. 6A shows an example of a semiconductor device model. Fig. 6B shows an example of an electric field strength distribution.

[0058] Fig. 6(A) shows an enlarged view of the gate electrode 30 and its vicinity of the semiconductor device model 1b. In Fig. 6(A), the polarization layer 60 is shown by a dotted line. In Fig. 6(A), position g corresponds to the end 31 of the gate electrode 30 on the drain electrode 50 side of the bottom surface 30b facing the barrier layer 20. Position h corresponds to the end (side end surface) of the gate electrode 30 on the drain electrode 50 side, and is the end of the portion of the polarization layer 60 that runs up onto the surface 60a. Position i corresponds to the end of the polarization layer 60 on the drain electrode 50 side.

[0059] Fig. 6(B) shows an example of a simulation result of the electric field strength distribution when the voltage (drain voltage) Vd applied to the drain electrode 50 is set to 50V and the voltage (gate voltage) Vg applied to the gate electrode 30 is set to -5V. In Fig. 6(B), the electric field strength distribution when the polarization layer 60 is not provided is shown by a solid line, and the electric field strength distribution when the polarization layer 60 (shown by a dotted line in Fig. 6(A)) is provided is shown by a dotted line. Fig. 6(B) also shows positions corresponding to positions g, h, and i shown in Fig. 6(A).

[0060] As shown in FIG. 6(B), the electric field intensity distribution when the polarization layer 60 is provided (shown by the dotted line "with polarization layer") is such that the electric field concentration position is shifted and the electric field concentration is alleviated compared to the electric field intensity distribution when the polarization layer 60 is not provided (shown by the solid line "without polarization layer").

[0061] From the above results, in the semiconductor device 1, the polarization layer 60 is provided at the end of the gate electrode 30 on the drain electrode 50 side, and the 2DEG region 80 directly below the polarization layer 60 is modulated by the polarization, thereby dispersing the electric field concentration near the end of the gate electrode 30 on the drain electrode 50 side. In the semiconductor device 1, the electric field concentration near the end of the gate electrode 30 on the drain electrode 50 side is dispersed, thereby preventing the electric field strength from exceeding the limit of the material near the end. This prevents the semiconductor device 1 from being destroyed by the electric field concentration. By providing the polarization layer 60, a semiconductor device 1 with high withstand voltage is realized.

[0062] Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described. Figures 7 to 9 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 7(A) to 7(C), 8(A) to 8(C), and 9(A) to 9(C) each show a schematic cross-sectional view of a main part of an example of each step in manufacturing a semiconductor device.

[0063] For example, as shown in FIG. 7(A), a barrier layer 20 is laminated on surface 10a of channel layer 10, and a structure is prepared in which a first layer 61, a second layer 62 and a third layer 63 of a polarization layer 60 are laminated on surface 20a of the barrier layer 20.

[0064] The channel layer 10 is made of, for example, GaN. The channel layer 10 is grown on a predetermined base substrate such as SiC, GaN, Si, etc., by MOVPE or the like. The thickness of the channel layer 10 is set to, for example, 200 nm.

[0065] The barrier layer 20 is made of, for example, AlGaN. 0.3 Ga 0.7 N is used for the barrier layer 20. The barrier layer 20 is grown by MOVPE or the like on the face 10a ((0001) face) of the channel layer 10. The thickness of the barrier layer 20 is set in the range of, for example, 9 nm to 25 nm.

[0066] A barrier layer 20 made of a nitride semiconductor having a band gap different from that of the channel layer 10 is laminated on the channel layer 10 , and a 2DEG region 80 is generated in the vicinity of the junction interface between the channel layer 10 and the barrier layer 20 .

[0067] In this example, the polarizing layer 60 has a three-layer laminate structure including a first layer 61, a second layer 62, and a third layer 63. The first layer 61 includes, for example, AlGaN. The first layer 61 includes AlGaN having the same Al composition as or a similar Al composition to the AlGaN (AlGaN on the surface 20a of the barrier layer 20) used in the barrier layer 20. As an example, AlGaN having the same Al composition as the barrier layer 20 is used. 0.3 Ga 0.7 N is used for the first layer 61. For example, the first layer 61 is grown on the face 20a ((0001) face) of the barrier layer 20 by MOVPE or the like. When the Al composition of the first layer 61 is the same as or close to the Al composition of the barrier layer 20, lattice mismatch between the first layer 61 and the barrier layer 20 and the occurrence of crystal defects in the first layer 61 are suppressed.

[0068] The second layer 62 is made of, for example, AlGaN. The second layer 62 is made of AlGaN having a lower Al composition than the AlGaN used in the first layer 61. As an example, Al 0.1 Ga 0.9 N is used for the second layer 62. The second layer 62 is grown on the first layer 61 ((0001) plane) by MOVPE or the like. When the Al composition of the second layer 62 is lower than but close to the Al composition of the first layer 61, lattice mismatch between the second layer 62 and the first layer 61 and the occurrence of crystal defects in the second layer 62 are suppressed.

[0069] The third layer 63 is made of, for example, GaN. The third layer 63 is made of GaN having a lower Al composition than the AlGaN used in the second layer 62. The third layer 63 may be made of AlGaN having a lower Al composition than the AlGaN used in the second layer 62. The third layer 63 is grown on the second layer 62 ((0001) plane) by MOVPE or the like. When the Al composition (0 in the case of GaN) of the third layer 63 is lower than and close to the Al composition of the second layer 62, lattice mismatch between the third layer 63 and the second layer 62 and the occurrence of crystal defects in the third layer 63 are suppressed.

[0070] A three-layer stacked structure of a first layer 61, a second layer 62 and a third layer 63 forms a polarization layer 60 with a gradient Al composition, in which the Al composition decreases from the surface 60b on the barrier layer 20 side toward the surface 60a opposite the barrier layer 20 side.

[0071] The thickness of the polarization layer 60 including the first layer 61, the second layer 62, and the third layer 63 is set to, for example, 40 nm or less. The thicknesses of the first layer 61, the second layer 62, and the third layer 63 may be different from each other or may be the same as each other. The thicknesses of the first layer 61, the second layer 62, and the third layer 63 may be set based on the Al composition of each layer, lattice relaxation due to the thickness during growth, etc. If the thickness (total thickness) of the polarization layer 60 exceeds 40 nm, the effect of lattice relaxation becomes large, and there is a possibility that the polarization layer 60 will not generate polarization that can sufficiently modulate the 2DEG region 80.

[0072] Furthermore, when the same nitride semiconductor is used for the first layer 61 and the barrier layer 20 (at least the surface portion on the side of face 20a), when growing the barrier layer 20 using a method such as MOVPE, the portion to function as the barrier layer 20 may be grown immediately after the portion to function as the first layer 61.

[0073] Here, a polarization layer 60 having a three-layer stacked structure of a first layer 61, a second layer 62, and a third layer 63 is used as an example, but a polarization layer 60 having a stacked structure of two layers or four or more layers may be provided as long as the Al composition is graded such that the Al composition decreases from surface 60b to surface 60a.

[0074] The polarizing layer 60 formed on the barrier layer 20 as shown in FIG. 7(A) is patterned by etching using a mask 90 as shown in FIGS. 7(B) and 7(C). For example, as shown in Fig. 7(B), a mask 90 is formed in a predetermined region on the polarization layer 60. As an example, the mask 90 is formed of SiN using a CVD (Chemical Vapor Deposition) method or the like. The mask 90 is formed in a region on the polarization layer 60 that is between the gate electrode 30 and the drain electrode 50 that are formed as described below. For example, the mask 90 is formed in a region that is the end of the gate electrode 30 on the drain electrode 50 side.

[0075] Then, as shown in Fig. 7(C), a mask 90 formed on a predetermined region on the polarization layer 60 is used, and the third layer 63, the second layer 62, and the first layer 61 of the polarization layer 60 exposed from the mask 90 are removed by etching. For example, a chlorine-based gas is used, and the third layer 63, the second layer 62, and the first layer 61 of the polarization layer 60 are removed by dry etching. As a result, the polarization layer 60 patterned by etching is formed in a predetermined region on the barrier layer 20 as shown in Fig. 7(C). The polarization layer 60 is formed by patterning so as to remain in a region 103 on the surface 20a side of the barrier layer 20.

[0076] When the same nitride semiconductor is used for the first layer 61 and the barrier layer 20, the surface layer of the nitride semiconductor is etched, and the first layer 61 is formed in the portion that remains after patterning.

[0077] After the polarizing layer 60 is patterned by etching, the mask 90 is removed. For example, the mask 90 is removed by wet etching using hydrofluoric acid or the like. After removing the mask 90, a resist 91 is formed as shown in Fig. 8(A). The resist 91 has openings 91a in regions corresponding to the source electrode 40 and the drain electrode 50 to be formed as described below. The openings 91a are formed in a region 101 on the surface 20a side of the barrier layer 20, in the region 101 where the source electrode 40 and the drain electrode 50 are to be formed.

[0078] After the resist 91 is formed, a metal material is deposited on the resist 91 and in the openings 91a thereof by deposition. As an example, a laminate of Ta or Ti and Al provided thereon is formed by deposition. After deposition, the resist 91 is removed together with the metal material deposited thereon by lift-off technology. As a result, the source electrode 40 and the drain electrode 50 are formed on the barrier layer 20 (region 101 on the surface 20a side of the barrier layer 20) as shown in FIG. 8(B). Thereafter, a predetermined heat treatment is performed to establish ohmic connection between the source electrode 40 and the drain electrode 50. As a result, the source electrode 40 and the drain electrode 50 that function as ohmic electrodes are formed.

[0079] After the source electrode 40 and the drain electrode 50 are formed, a passivation film 71 is formed as shown in Fig. 8(C). For example, the passivation film 71 made of SiN is formed by using a CVD method or the like. The passivation film 71 is formed so as to cover, for example, the barrier layer 20, the polarization layer 60, the source electrode 40, and the drain electrode 50.

[0080] After the passivation film 71 is formed, an opening 71a is formed in a predetermined region of the passivation film 71, as shown in Fig. 9(A). The opening 71a of the passivation film 71 is formed in a region corresponding to the gate electrode 30 to be formed as described below. The opening 71a is formed so that a part of the barrier layer 20 (its surface 20a) and a part of the polarization layer 60 (its surface 60a) are exposed. The opening 71a is formed in a region 102 on the surface 20a side of the barrier layer 20, in the region 102 where the gate electrode 30 is to be formed.

[0081] After the opening 71a is formed in the passivation film 71, as shown in FIG. 9B, the gate electrode 30 is formed in the opening 71a. For example, a metal material of the gate electrode 30 is deposited in the opening 71a using lithography, deposition, and lift-off techniques. As an example, a laminate of Ni and Au provided thereon is deposited, and the gate electrode 30 is formed by lift-off techniques. As a result, the gate electrode 30 functioning as a Schottky electrode is formed in the opening 71a of the passivation film 71 (region 102 on the surface 20a side of the barrier layer 20).

[0082] The gate electrode 30 is formed so as to cover the barrier layer 20 and the polarization layer 60 in the opening 71a. A part of the gate electrode 30 is provided on a surface 60a of the polarization layer 60. The polarization layer 60 extends from an end 31 of the gate electrode 30 on the drain electrode 50 side of a bottom surface 30b facing the barrier layer 20 toward the drain electrode 50 side. This results in a state in which the polarization layer 60 is provided at the end of the gate electrode 30 on the drain electrode 50 side.

[0083] In the above method, it can also be said that the source electrode 40, the drain electrode 50 and the gate electrode 30 are formed so that a polarization layer 60 is provided between the gate electrode 30 and the source electrode 40 and the drain electrode 50, among between the gate electrode 30 and the drain electrode 50.

[0084] Here, the region 101 on the surface 20a side of the barrier layer 20 where the drain electrode 50 is formed is also referred to as the "first region." The region 102 on the surface 20a side of the barrier layer 20 facing the region 101 where the drain electrode 50 is formed and where the gate electrode 30 is formed is also referred to as the "second region." The region 103 on the surface 20a side of the barrier layer 20 between the region 101 where the drain electrode 50 is formed and the region 102 where the gate electrode 30 is formed and where the polarization layer 60 is formed (remains by patterning) is also referred to as the "third region."

[0085] In the above method, the step of removing the polarization layer 60 (FIGS. 7(B) and 7(C)) can be said to remove the polarization layer 60 from the region 101 (first region) where the drain electrode 50 is to be formed and the region 102 (second region) where the gate electrode 30 is to be formed on the surface 20a side of the barrier layer 20. Then, the step of forming the drain electrode 50 (FIGS. 8(A) and 8(B)) can be said to form the drain electrode 50 in the region 101 (first region) from which the polarization layer 60 has been removed. Furthermore, the step of forming the gate electrode 30 (FIGS. 9(A) and 9(B)) can be said to form the gate electrode 30 in the region 102 (second region) from which the polarization layer 60 has been removed.

[0086] After the gate electrode 30 is formed, an interlayer insulating film 72 is formed as shown in FIG. 9C. The interlayer insulating film 72 may be made of various insulating materials such as SiO (silicon oxide) and SiN. For example, the interlayer insulating film 72 may be made of the same insulating material as the passivation film 71. For example, the interlayer insulating film 72 is made of SiN using a CVD method or the like. The interlayer insulating film 72 is formed so as to cover the passivation film 71 and the gate electrode 30. The passivation film 71 and the interlayer insulating film 72 are stacked to form the insulating film 70 as shown in FIG. 1 and the like.

[0087] Through the steps described above, a semiconductor device 1 having a configuration as shown in FIG. 9(C) is manufactured. In the above manufacturing process, a cap layer such as GaN may be formed on the surface 20a of the barrier layer 20. A spacer layer such as AlGaN or InGaN may be formed between the channel layer 10 and the barrier layer 20. Various layers such as an initial layer, a buffer layer, and a back barrier layer may be formed between the channel layer 10 and an underlying substrate (not shown).

[0088] In the above manufacturing process, when the source electrode 40 and the drain electrode 50 are formed, the above-mentioned heat treatment is not necessarily required as long as ohmic contact is realized by forming the metal materials. When the gate electrode 30 is formed, a heat treatment may be further performed after the metal material is formed. The gate electrode 30 may be provided on the surface 20a side of the barrier layer 20 via a gate insulating film (not shown) made of oxide, nitride, oxynitride, or the like, to form an MIS gate structure.

[0089] [Second embodiment] Fig. 10 is a diagram illustrating an example of a semiconductor device according to the second embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device.

[0090] The semiconductor device 1A shown in Fig. 10 is an example of a HEMT. The semiconductor device 1A has a configuration in which a polarization layer 60 extending from an end 31 on the drain electrode 50 side of the bottom surface 30b of the gate electrode 30 toward the drain electrode 50 reaches the drain electrode 50. That is, in the semiconductor device 1A, the polarization layer 60 is provided so as to be in contact with the drain electrode 50. The semiconductor device 1A differs from the semiconductor device 1 (Fig. 1, etc.) described in the first embodiment in that it has such a configuration.

[0091] The polarization layer 60 has a gradient Al composition in which the Al composition decreases from the surface 60a on the barrier layer 20 side toward the opposite surface 60a. In the semiconductor device 1A, the polarization layer 60 having such a gradient Al composition is provided so as to extend from the end of the gate electrode 30 on the drain electrode 50 side to the drain electrode 50.

[0092] The polarization layer 60 is polarized to exhibit p-type semiconductor properties due to its graded Al composition. The polarization generated in the polarization layer 60 raises the conduction band immediately below the polarization layer 60, modulating the 2DEG region 80, and reducing the electron concentration in the 2DEG region 80 immediately below the polarization layer 60. In the semiconductor device 1A, the polarization layer 60 is provided in the region from the gate electrode 30 to the drain electrode 50. Therefore, in the semiconductor device 1A, the electron concentration in the 2DEG region 80 is reduced not only in the end of the gate electrode 30 on the drain electrode 50 side, but also over a wider range from the gate electrode 30 to the drain electrode 50. This relaxes the electric field on the drain electrode 50 side of the gate electrode 30. As a result, the material in the region from the gate electrode 30 to the drain electrode 50 is prevented from reaching a breakdown electric field, and the semiconductor device 1A is prevented from being broken. By providing the polarization layer 60, the semiconductor device 1A with high breakdown voltage is realized.

[0093] Even if the polarization layer 60 is provided in the region from the gate electrode 30 to the drain electrode 50 as in this semiconductor device 1A and the electron concentration in this region is reduced, the deterioration of the operating performance of this semiconductor device 1A compared to the semiconductor device 1 described in the first embodiment is suppressed. For example, the deterioration of the operating performance of the semiconductor device 1A, such as an increase in resistance of the semiconductor device 1 and a decrease in output due to the increase in resistance, is suppressed. This is because, unless the electron concentration directly below the polarization layer 60 provided in the region from the gate electrode 30 to the drain electrode 50 of the semiconductor device 1A is lower than the electron concentration directly below the polarization layer 60 provided at the end of the gate electrode 30 on the drain electrode 50 side of the semiconductor device 1, it will not become a resistance.

[0094] According to the semiconductor device 1A, it is possible to reduce the electric field in a wider area from the gate electrode 30 to the drain electrode 50 while suppressing a decrease in operating performance, thereby preventing the material in that area from reaching a destructive electric field, and thus preventing breakdown of the semiconductor device 1A.

[0095] In the manufacturing of the semiconductor device 1A having the above-mentioned configuration, in the step of removing the polarization layer 60 shown in Fig. 7(B) and Fig. 7(C), the region of the polarization layer 60 to be covered with the mask 90 and the region to be left by etching using the mask 90 are changed. That is, the mask 90 is formed and etched so that the polarization layer 60 extends between the region 101 (Figs. 8(A) and 8(B)) where the drain electrode 50 is formed and the region 102 (Figs. 9(A) and 9(B)) where the gate electrode 30 is formed on the surface 20a side of the barrier layer 20. Except for this change, the semiconductor device 1A can be manufactured according to the example of the manufacturing method described for the semiconductor device 1.

[0096] The first and second embodiments have been described above. The semiconductor devices 1, 1A, etc. described above can be applied to various electronic devices. As an example, the following describes the case where the semiconductor device having the above configuration is applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier.

[0097] [Third embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a semiconductor package will be described as a third embodiment.

[0098] Fig. 11 is a diagram illustrating an example of a semiconductor package according to the third embodiment, which diagrammatically shows a plan view of a main part of the example of the semiconductor package. The semiconductor package 200 shown in Fig. 11 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 1 (Fig. 1, etc.) as described in the first embodiment, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

[0099] The semiconductor device 1 is mounted on a die pad 210a of a lead frame 210 using, for example, a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. The pads 30a, 40a, and 50a are connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using wires 230 made of Au, Al, or the like, respectively. The lead frame 210, the semiconductor device 1 mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that parts of the gate lead 211, the source lead 212, and the drain lead 213 are exposed.

[0100] An external connection electrode connected to the source electrode 40 may be provided on the surface of the semiconductor device 1 opposite to the surface on which the pad 30a connected to the gate electrode 30 and the pad 50a connected to the drain electrode 50 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 by using a conductive bonding material such as solder.

[0101] For example, the semiconductor device 1 as described in the first embodiment is used, and a semiconductor package 200 having such a configuration is obtained. As described above, the semiconductor device 1 is provided with the polarization layer 60 extending from the end of the gate electrode 30 on the drain electrode 50 side toward the drain electrode 50 side. The polarization layer 60 has a gradient Al composition in which the Al composition decreases from the surface 60b on the barrier layer 20 side toward the surface 60a on the opposite side. The polarization generated in the polarization layer 60 reduces the electron concentration in the 2DEG region 80 directly below the polarization layer 60. This suppresses electric field concentration on the drain electrode 50 side of the gate electrode 30 and the resulting breakdown. The polarization layer 60 realizes a semiconductor device 1 with high breakdown voltage. By using such a semiconductor device 1, a high-performance semiconductor package 200 is realized.

[0102] Although the semiconductor device 1 is taken as an example here, it is possible to obtain a semiconductor package in a similar manner using other semiconductor devices such as the semiconductor device 1A. [Fourth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to a power factor correction circuit will be described as a fourth embodiment.

[0103] Fig. 12 is a diagram for explaining an example of a power factor correction circuit according to the fourth embodiment. Fig. 12 shows an equivalent circuit diagram of the example of the power factor correction circuit. The power factor correction (PFC) circuit 300 shown in FIG. 12 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0104] In the PFC circuit 300, a drain electrode of a switch element 310 is connected to an anode terminal of a diode 320 and one terminal of a choke coil 330. A source electrode of the switch element 310 is connected to one terminal of a capacitor 340 and one terminal of a capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to a cathode terminal of the diode 320. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out from between both terminals of the capacitor 350.

[0105] For example, the semiconductor device 1, 1A, or the like is used for the switch element 310 of the PFC circuit 300 having such a configuration. As described above, the semiconductor device 1, 1A, etc. is provided with the polarization layer 60 extending from the end of the gate electrode 30 on the drain electrode 50 side toward the drain electrode 50 side. The polarization layer 60 has a gradient Al composition in which the Al composition decreases from the surface 60b on the barrier layer 20 side toward the surface 60a on the opposite side. The polarization generated in the polarization layer 60 reduces the electron concentration in the 2DEG region 80 directly below the polarization layer 60. This suppresses electric field concentration on the drain electrode 50 side of the gate electrode 30 and the resulting breakdown. The polarization layer 60 realizes the semiconductor device 1, 1A, etc. with a high breakdown voltage. The semiconductor device 1, 1A, etc. with such a configuration is used to realize a high-performance PFC circuit 300.

[0106] [Fifth embodiment] Here, an example in which the semiconductor device having the above-mentioned configuration is applied to a power supply device will be described as the fifth embodiment.

[0107] Fig. 13 is a diagram illustrating an example of a power supply device according to the fifth embodiment. Fig. 13 shows an equivalent circuit diagram of the example of the power supply device. The power supply device 400 shown in FIG. 13 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0108] The primary side circuit 410 includes the PFC circuit 300 as described in the fourth embodiment above, and an inverter circuit, for example, a full-bridge inverter circuit 440, connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of switch elements, four in this example, a switch element 441, a switch element 442, a switch element 443, and a switch element 444.

[0109] The secondary side circuit 420 includes a plurality of switch elements, three of which, as an example here, are a switch element 421, a switch element 422, and a switch element 423. For example, the semiconductor devices 1, 1A, etc. are used for the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 of the power supply device 400 having such a configuration, and for the switch elements 441-444 of the full bridge inverter circuit 440. For example, normal MIS type field effect transistors using Si are used for the switch elements 421-423 of the secondary side circuit 420 of the power supply device 400.

[0110] As described above, the semiconductor device 1, 1A, etc. is provided with the polarization layer 60 extending from the end of the gate electrode 30 on the drain electrode 50 side toward the drain electrode 50 side. The polarization layer 60 has a gradient Al composition in which the Al composition decreases from the surface 60b on the barrier layer 20 side toward the surface 60a on the opposite side. The polarization generated in the polarization layer 60 reduces the electron concentration in the 2DEG region 80 directly below the polarization layer 60. This suppresses electric field concentration on the drain electrode 50 side of the gate electrode 30 and the resulting breakdown. The polarization layer 60 realizes the semiconductor device 1, 1A, etc. with a high breakdown voltage. The semiconductor device 1, 1A, etc. with such a configuration is used to realize a high-performance power supply device 400.

[0111] [Sixth embodiment] Here, an example of application of the semiconductor device having the above-mentioned configuration to an amplifier will be described as a sixth embodiment.

[0112] Fig. 14 is a diagram for explaining an example of an amplifier according to the sixth embodiment, showing an equivalent circuit diagram of the example of the amplifier. The amplifier 500 shown in FIG. 14 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0113] The digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the input signal SI, for which the nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0114] The semiconductor device 1, 1A, or the like is used in the power amplifier 540 of the amplifier 500 having such a configuration. As described above, the semiconductor device 1, 1A, etc. is provided with the polarization layer 60 extending from the end of the gate electrode 30 on the drain electrode 50 side toward the drain electrode 50 side. The polarization layer 60 has a gradient Al composition in which the Al composition decreases from the surface 60b on the barrier layer 20 side toward the surface 60a on the opposite side. The polarization generated in the polarization layer 60 reduces the electron concentration in the 2DEG region 80 directly below the polarization layer 60. This suppresses electric field concentration on the drain electrode 50 side of the gate electrode 30 and the resulting breakdown. The polarization layer 60 realizes the semiconductor device 1, 1A, etc. with a high breakdown voltage. The semiconductor device 1, 1A, etc. with such a configuration is used to realize a high-performance amplifier 500.

[0115] Various electronic devices to which the semiconductor devices 1, 1A, etc. are applied (such as the semiconductor package 200, PFC circuit 300, power supply device 400, and amplifier 500 described in the third to sixth embodiments) can be mounted in various electronic devices or electronic devices. For example, they can be mounted in various electronic devices or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing devices, transmitters, receivers, and radar devices.

[0116] The following supplementary notes are further provided with respect to the embodiment described above. (Supplementary Note 1) A channel layer including a first nitride semiconductor; a barrier layer provided on the first surface side of the channel layer and including a second nitride semiconductor; a source electrode and a drain electrode provided on a second surface side of the barrier layer opposite to the channel layer; a gate electrode provided between the source electrode and the drain electrode on the second surface side of the barrier layer; a polarization layer provided on the second surface side of the barrier layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, the polarization layer including a third nitride semiconductor containing Al, the Al composition decreasing from the barrier layer side toward a third surface side opposite to the barrier layer side; 13. A semiconductor device comprising:

[0117] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the polarization layer extends from an end of the gate electrode on the drain electrode side on a bottom surface of the gate electrode facing the barrier layer toward the drain electrode side.

[0118] (Supplementary Note 3) The semiconductor device according to Supplementary Note 2, wherein the polarization layer is separated from the drain electrode. (Supplementary Note 4) The semiconductor device according to Supplementary Note 2, wherein the polarization layer is in contact with the drain electrode.

[0119] (Supplementary Note 5) The semiconductor device according to Supplementary Note 1, wherein a portion of the gate electrode is provided on the third surface of the polarization layer. (Additional Note 6) The second nitride semiconductor of the barrier layer contains Al, The semiconductor device according to claim 1, wherein the third nitride semiconductor of the polarization layer has an Al composition at a fourth surface of the polarization layer on the barrier layer side, the Al composition being equal to the Al composition at the second surface of the barrier layer.

[0120] (Supplementary Note 7) The semiconductor device according to Supplementary Note 1, wherein the third nitride semiconductor of the polarization layer has an Al composition of 0.3 in a fourth surface of the polarization layer on the barrier layer side. (Supplementary Note 8) The semiconductor device according to Supplementary Note 1, wherein the third nitride semiconductor of the polarization layer has an Al composition of 0 at the third surface.

[0121] (Supplementary Note 9) The semiconductor device according to Supplementary Note 1, wherein the thickness of the polarization layer from a fourth surface on the barrier layer side to the third surface opposite the barrier layer side is 40 nm or less. (Additional Note 10) A step of forming a barrier layer including a second nitride semiconductor on a first surface side of a channel layer including a first nitride semiconductor; forming a polarization layer including a third nitride semiconductor containing Al on a second surface side of the barrier layer opposite to the channel layer side, the polarization layer having an Al composition decreasing from the barrier layer side toward a third surface side opposite to the barrier layer side; forming a source electrode and a drain electrode on the second surface side of the barrier layer, and a gate electrode provided between the source electrode and the drain electrode; Including, A method for manufacturing a semiconductor device, wherein the step of forming the source electrode, the drain electrode, and the gate electrode includes a step of forming the drain electrode and the gate electrode such that the polarization layer is provided between the gate electrode and the source electrode, and between the gate electrode and the drain electrode.

[0122] (Additional Note 11) The step of forming the polarizing layer includes: forming the polarization layer in a first region on the second surface side of the barrier layer, a second region facing the first region, and a third region between the first region and the second region; removing the polarizing layer in the first region and the second region; Including, The step of forming the drain electrode and the gate electrode includes: forming the drain electrode in the first region from which the polarization layer has been removed; forming the gate electrode in the second region from which the polarization layer has been removed; 11. A method for manufacturing a semiconductor device according to claim 10, comprising:

[0123] (Appendix 12) The method for manufacturing a semiconductor device described in Appendix 10, wherein the step of forming the drain electrode and the gate electrode includes a step of forming the drain electrode and the gate electrode such that the polarization layer extends from an end of the gate electrode on the drain electrode side of a bottom surface facing the barrier layer toward the drain electrode side.

[0124] (Supplementary Note 13) A channel layer including a first nitride semiconductor; a barrier layer provided on the first surface side of the channel layer and including a second nitride semiconductor; a source electrode and a drain electrode provided on a second surface side of the barrier layer opposite to the channel layer; a gate electrode provided between the source electrode and the drain electrode on the second surface side of the barrier layer; a polarization layer provided on the second surface side of the barrier layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, the polarization layer including a third nitride semiconductor containing Al, the Al composition decreasing from the barrier layer side toward a third surface side opposite to the barrier layer side; An electronic device comprising a semiconductor device including: [Explanation of symbols]

[0125] 1, 1A Semiconductor Device 1a, 1b Semiconductor device model 10 Channel Layer 10a, 20a, 60a, 60b side 20 Barrier Layer 30 Gate electrode 30a, 40a, 50a pads 30b Bottom 31 edge 40 Source electrode 50 Drain electrode 60 Polarization Layer 61 1st layer 62 2nd layer 63 3rd layer 70 Insulating Film 71 Passivation Film 71a, 91a opening 72 Interlayer insulating film 80 2DEG area 90 Mask 91 Resist 100a, 100b, 100c layers 101, 102, 103 areas 200 Semiconductor Packages 210 Lead Frame 210a Die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch elements 320 Diode 330 Choke Coil 340, 350 Capacitor 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 Trans 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520, 530 Mixer 540 Power Amplifier a, b, c, AR1 area d, e, f parts g, h, i position

Claims

1. a channel layer including a first nitride semiconductor; a barrier layer provided on the first surface side of the channel layer and including a second nitride semiconductor; a source electrode and a drain electrode provided on a second surface side of the barrier layer opposite to the channel layer; a gate electrode provided on the second surface side of the barrier layer between the source electrode and the drain electrode; a polarization layer provided between the gate electrode and the drain electrode on the second surface side of the barrier layer, among between the gate electrode and the source electrode and between the gate electrode and the drain electrode, the polarization layer including a third nitride semiconductor containing Al, the Al composition decreasing from the barrier layer side toward a third surface side opposite to the barrier layer side; 13. A semiconductor device comprising:

2. 2 . The semiconductor device according to claim 1 , wherein the polarization layer extends from an end of the gate electrode on the drain electrode side at a bottom surface of the gate electrode facing the barrier layer toward the drain electrode side.

3. The semiconductor device according to claim 2 , wherein the polarization layer is separated from the drain electrode.

4. The semiconductor device according to claim 2 , wherein the polarization layer is in contact with the drain electrode.

5. The semiconductor device according to claim 1 , wherein a portion of said gate electrode is provided on said third surface of said polarization layer.

6. forming a barrier layer including a second nitride semiconductor on the first surface side of the channel layer including a first nitride semiconductor; forming a polarization layer including a third nitride semiconductor containing Al on a second surface side of the barrier layer opposite to the channel layer side, the polarization layer having an Al composition decreasing from the barrier layer side toward a third surface side opposite to the barrier layer side; forming a source electrode and a drain electrode on the second surface side of the barrier layer, and a gate electrode provided between the source electrode and the drain electrode; Including, A method for manufacturing a semiconductor device, wherein the step of forming the source electrode, the drain electrode, and the gate electrode includes a step of forming the drain electrode and the gate electrode such that the polarization layer is provided between the gate electrode and the source electrode, or between the gate electrode and the drain electrode.

7. a channel layer including a first nitride semiconductor; a barrier layer provided on the first surface side of the channel layer and including a second nitride semiconductor; a source electrode and a drain electrode provided on a second surface side of the barrier layer opposite to the channel layer; a gate electrode provided on the second surface side of the barrier layer between the source electrode and the drain electrode; a polarization layer provided between the gate electrode and the drain electrode on the second surface side of the barrier layer, among between the gate electrode and the source electrode and between the gate electrode and the drain electrode, the polarization layer including a third nitride semiconductor containing Al, the Al composition decreasing from the barrier layer side toward a third surface side opposite to the barrier layer side; An electronic device comprising a semiconductor device including:

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