Power overlay structure for multi-chip semiconductor package

Abstract

To provide a multi-chip semiconductor package having an interconnecting power overlay structure.SOLUTION: A multi-chip semiconductor package includes a dielectric interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of the interconnect layer, at least one common gate pad disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad that adhere onto the interconnect layer. The source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad. The source pads of the plurality of semiconductor devices are electrically connected in parallel with one another. The gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad. The gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor packages, and more particularly to multi-chip semiconductor packages having interconnecting power overlay structures. [Background technology]

[0002] Power semiconductor devices such as switches and rectifiers are the main components of power electronic circuits (e.g., switch mode power supplies, inverters, rectifiers, etc.). High power applications typically require a multi-chip assembly with multiple power semiconductor devices connected together to carry large amounts of current and support high voltages. When connecting the individual devices to the multi-chip assembly, it is important to maintain layout symmetry and low inductance interconnects to ensure good load sharing, minimize voltage and current overshoot, and reduce switching losses. The top surface of each power semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), includes a gate pad and at least one source pad that are electrically connected to the gate and source pads of other devices in the multi-chip assembly. The electrical connections of the multiple gate pads and source pads are typically made using wire bonds and complex routing configurations to a common gate pad and at least one common source pad. The common gate pad and at least one common source pad of the multi-chip semiconductor assembly can be connected to an external power electronic circuit, so that the multi-chip semiconductor assembly operates as a single power processing unit.

[0003] Instead of wire bonding of the gate and source pads, one or more planar interconnect layers may be used, separated by an interconnect layer disposed over the top surface of the semiconductor device. The interconnect layer may include metallized vias that extend through the interconnect layer and electrically couple the source and gate pads to common gate and common source pads disposed on a top interconnect layer of the multi-chip semiconductor assembly to deliver power through the metallized vias to the semiconductor device.

[0004] To establish a proper electrical connection to external power electronics, the common gate and common source pads on the top interconnect layer require sufficient surface area to connect the common gate and source pads of the multi-chip assembly to the external power electronics by methods such as soldering, sintering, copper bonding, copper clipping, etc. However, the available surface area of ​​the common gate and common source pads is typically limited by the total surface area of ​​the multi-chip semiconductor assembly. Furthermore, direct soldering, sintering, copper bonding, and copper clipping onto the smaller common gate and common source pads introduces bonding stresses into the multi-chip semiconductor assembly, resulting in less reliable interconnects.

[0005] In addition, connecting multiple gate pads to a common gate pad and multiple source pads to a common source pad together in a multi-chip semiconductor assembly requires good layout symmetry resulting in inductance matching of the individual connections to ensure good load sharing between the individual devices. To achieve a high current power module, it is necessary to parallel multiple semiconductor devices. For example, building a 480A power module would require the paralleling of eight devices, each rated at about 60A. Paralleling eight devices is difficult in terms of ensuring that all eight devices share the current equally due to the variation in the individual characteristics of the devices and the problem of connecting each device to the external power electronics to receive signals to switch each device on or off simultaneously. This is driven by the gate-source parasitic impedance, which is driven by the geometry of the trace connections between the devices. The more devices are paralleled, the more complex it becomes to balance the impedances to ensure that each device switches simultaneously and shares the current. One solution is to parallel two larger semiconductor devices, each rated at about 240A. A device rated at 240 A is significantly larger than a device rated at 60 A. This makes packaging and interconnection easier, but at the expense of significantly reduced device yield.

[0006] Finally, semiconductor manufacturing processes inherently result in variations in the characteristics of individual semiconductor devices within a wafer and from wafer to wafer, therefore, by constructing a multi-chip semiconductor assembly from individual devices having similar characteristics, the integrity of the performance of the individual devices within the multi-chip assembly is further preserved. Summary of the Invention [Means for solving the problem]

[0007] In one aspect, a multi-chip semiconductor package is disclosed, the package including: an interconnect layer having a top surface and a bottom surface, the interconnect layer including a dielectric material, at least one common source pad disposed on the top surface of the interconnect layer, at least one common gate pad disposed on the top surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad bonded onto the interconnect layer, the source pads of the plurality of semiconductor devices being electrically connected to the at least one common source pad, the source pads of the plurality of semiconductor devices being electrically connected in parallel to each other, the gate pads of the plurality of semiconductor devices being electrically connected to the common gate pad, and the gate pads of the plurality of semiconductor devices being electrically connected in parallel to each other.

[0008] In another aspect, a method of manufacturing a multi-chip semiconductor package is disclosed, the method including forming at least one source via path and at least one gate via path through an interconnect layer, aligning at least one source pad and gate pad of a plurality of semiconductor devices with the at least one source via path and the at least one gate via path, respectively, and bonding the plurality of semiconductor devices to the interconnect layer, wherein a surface area of ​​the interconnect layer is approximately equal to a surface area of ​​a footprint defined by the plurality of semiconductor devices.

[0009] The subject matter of the present disclosure is explained in more detail in the following text with reference to exemplary embodiments illustrated in the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a perspective view of a mold for a multi-chip semiconductor package according to one embodiment. [Diagram 3] 1 is a perspective view of a multi-chip semiconductor package according to an embodiment; [Figure 4] FIG. 4 is a plan view of the multi-chip semiconductor package of FIG. [Diagram 5] FIG. 4 is an exploded view of the multi-chip semiconductor package of FIG. [Figure 6] FIG. 4 is an exploded view of the multi-chip semiconductor package of FIG. [Figure 7] 4 is a cross-sectional view of the multi-chip semiconductor package of FIG. 3 taken along line A-A'. [Figure 8] 4 is a cross-sectional view of the multi-chip semiconductor package of FIG. 3 taken along line BB'. [Figure 9A] FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 9B] FIG. 2 is a see-through plan view of an exemplary interconnect layer and associated pathways in accordance with one or more embodiments of the present disclosure. [Figure 9C] 9C is a cross-sectional view of the interconnect layer and associated paths of FIG. 9B taken along line CC'. [Figure 9D] 9C is a cross-sectional view of the interconnect layer and associated paths of FIG. 9B taken along line D-D'. [Figure 10A] FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 10B] FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 11] FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 12] FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 13A] FIG. 2 is a plan view of an exemplary first interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 13B] FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 13C]FIG. 2 illustrates a plan view of an exemplary interconnect layer and associated paths in accordance with one or more embodiments of the present disclosure. [Figure 14A] FIG. 2 is a cross-sectional view of an exemplary rear structure. [Figure 14B] FIG. 2 is a cross-sectional view of an exemplary rear structure. [Figure 15A] 1 illustrates one embodiment of a method for manufacturing a multi-chip semiconductor package. [Figure 15B] 1 illustrates one embodiment of a method for manufacturing a multi-chip semiconductor package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The reference signs used in the drawings and their meanings are listed in summary form in the list of reference signs. In principle, identical parts are provided with the same reference signs in the figures.

[0012] In the following specification and claims, reference will be made to a number of terms, which shall be defined to have the following meanings.

[0013] As used herein, the singular forms "a," "an," and "the" include plural references unless otherwise indicated. Terms such as "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the elements listed. Terms such as "optional" or "optionally" mean that the subsequently stated event or occurrence may or may not occur, and that the description includes instances where the event occurs as well as instances where the event does not occur.

[0014] Unless otherwise indicated, approximating words such as "generally," "substantially," and "about" as used herein indicate that the term so modified is applicable to merely an approximate degree, as would be understood by one of ordinary skill in the art, rather than to an absolute or complete degree. Thus, values ​​modified by terms such as "about," "approximately," and "approximately" should not be limited to the exact value indicated. In at least some cases, approximating words may correspond to the precision of an instrument for measuring the value. Range limitations may be identified herein and throughout the specification and claims. Such ranges may be combined and / or interchangeable, and may include all of the subranges contained therein, unless otherwise indicated by context or language.

[0015] Further, unless otherwise indicated, terms such as "first," "second," etc. are used merely as labels and are not intended to impose any order, position, or hierarchical requirements on the items to which these terms refer. Further, for example, a reference to a "second" item does not require or preclude the presence of, for example, a "first" or fewer items, or a "third" or more items.

[0016] The disclosed embodiments generally relate to structures and methods for packaging multiple semiconductor devices, and more particularly to multi-chip semiconductor packages having interconnecting power overlay (POL) structures. The methods, systems, and apparatus described herein overcome at least some of the shortcomings of at least some known multi-chip semiconductor packages. More specifically, the systems and apparatus described herein provide a POL package configured as a redistribution layer (RDL) that is placed directly over multiple semiconductor devices. Thus, the POL package is also referred to herein as a POL-RDL package. The POL-RDL package includes a larger size surface area relative to the footprint of the mold defined by the semiconductor device (or more generally, the footprint of the semiconductor device), which improves the available surface area for placement of common gate pads, common source pads, and overlaid contact pads. The larger size surface area also allows placement of more complex configurations such as common source pads, common gate pads, and gate bridges, as well as additional interconnect layers and interconnect layers.

[0017] A multi-chip semiconductor package is disclosed. The multi-chip semiconductor package includes at least one interconnect layer having a top surface and a bottom surface, at least one common source pad disposed on the top surface of the at least one interconnect layer, at least one common gate pad disposed on the top surface of the at least one interconnect layer, and a plurality of semiconductor devices. Each of the semiconductor devices has a gate pad and at least one source pad bonded on a bottom surface of a first interconnect layer of the at least one interconnect layer. The bottom surface of the first interconnect layer has an adhesive layer. The source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other. The gate pads of the plurality of semiconductor devices are electrically connected to the at least one common gate pad, and the gate pads of the plurality of semiconductor devices are electrically connected in parallel to each other.

[0018] The term "vias" as used herein refers to metallized vias disposed within via paths of an interconnect layer, as well as trace connections, pads, contacts, and contact pads disposed on an interconnect layer. The vias may also include surface mount resistors, thin film resistors, and associated pads for post-fabrication placement of surface mount resistors.

[0019] Additional interconnect layers and paths can be laminated or otherwise fabricated over the first interconnect layer to facilitate additional routing configurations. As used herein, the terms "package gate pad" and "package source pad" refer to the common gate pad and common source pad on the topmost interconnect layer that are electrically connected to external power electronics. Any of the first interconnect layers and additional interconnect layers disclosed herein can be directly connected to external power electronics or can have additional interconnect layers and paths. Thus, "package gate pad", "package source pad", "common gate pad", and "common source pad" are used interchangeably.

[0020] FIG. 1 illustrates a perspective view of a semiconductor device 100 of one embodiment. FIG. 2 illustrates a perspective view of a mold 102 including at least two semiconductor devices 100 (also referred to as a plurality of semiconductor devices 100). As shown in FIGS. 1 and 2, the semiconductor device 100 includes a dielectric material 106 defining a top surface 101. The semiconductor device 100 further includes at least one source pad 110 and a gate pad 120 disposed on the top surface 101 of the semiconductor device 100. The at least one source pad 110 includes a top contact surface 112. Similarly, the gate pad 120 includes a top contact surface 122.

[0021] The top contact surfaces 112, 122 of each of the gate pad 120 and the at least one source pad 110 are electrically isolated from each other by the dielectric material 106. In some embodiments, at least a portion of the gate pad 120 and the at least one source pad 110 extend at least partially below the top surface 101. In some embodiments, the top contact surface 112 of the at least one source pad 110 and the top contact surface 122 of the gate pad 120 are flush with the surface of the dielectric material 106. In some embodiments, the top contact surface 112 of the at least one source pad 110 and the top contact surface 122 of the gate pad 120 are below the surface of the dielectric material 106. In some embodiments, the top contact surface 112 of the at least one source pad 110 and the top contact surface 122 of the gate pad 120 are above the surface of the dielectric material 106.

[0022] As shown in FIG. 2, the mold 102 includes an underfill material 103 defining a top surface 104, and a plurality of semiconductor devices 100 at least partially disposed within the mold 102 and surrounded by the underfill material 103. The plurality of semiconductor devices 100 embedded within the mold 102 define a footprint 105 (best shown in FIG. 4). FIGS. 3-8 illustrate one or more embodiments of a multi-chip semiconductor package 200. FIG. 3 illustrates a perspective view of the multi-chip semiconductor package 200, FIG. 4 illustrates a top partial see-through view of the semiconductor package 200, and FIGS. 5 and 6 illustrate exploded views of the semiconductor package 200. FIGS. 7 and 8 illustrate cross-sectional views of the semiconductor package 200 taken along lines A-A' and B-B', respectively, of FIG. 4.

[0023] The multi-chip semiconductor package 200 operates as a metal oxide semiconductor field effect transistor (MOSFET) having two or more semiconductor devices 100. The multi-chip semiconductor package 200 includes a POL-RDL package 250 having at least one common source pad 280 and a gate bridge 290. The POL-RDL package 250 includes a first interconnect layer 260 and an adhesive layer 262 disposed over the mold 102 (best shown in FIG. 5 ). In some embodiments, first interconnect layer 260 is in the form of a laminate or film and can be formed from one of several dielectric materials, such as Kapton® polyimide, Ultem® polyetherimide, polytetrafluoroethylene (PTEE), Upilex®, polysulfone materials (e.g., Udel® polysulfone, Radel® polyphenolsulfone), or another polymer film, such as liquid crystal polymer (LCP), bismaleimide triazine resin, Ajinomoto Build-up Film® ABF, or a polyimide material. In one embodiment, POL-RDL package 250 has an overall thickness in the range of 25 microns to 300 microns.

[0024] In some embodiments, the POL-RDL package 250 (which may include any number of interconnect layers 260, trace connections, source and gate pads) is completely fabricated and placed over the mold 102 (with multiple semiconductor devices 100 embedded within the mold 102), with the first interconnect layer 260 adhered to the source pads 110 and gate pads 120 by the adhesive layer 262. That is, the adhesive layer 262 is disposed between the first interconnect layer 260 and the mold 102. In some embodiments, the semiconductor devices 100 can be directly adhered onto the adhesive layer 262 without a mold. A mold or underfill material can be disposed between the semiconductor devices 100 at a later stage.

[0025] In operation, metallized vias are formed in source via paths 264 and gate via paths 266 that extend through the first interconnect layer 260 (and any number of additional interconnect layers, as described in more detail below with reference to FIGS. 9A-14B), associated metal interconnect structures and paths are constructed over the first interconnect layer 260 (and any number of additional interconnect layers), and an adhesive layer 262 is attached to a bottom surface of the first interconnect layer 260. The semiconductor device 100 (either as part of the mold 102 or separately) is aligned with the source via paths 264 and gate via paths 266 that extend through the first interconnect layer 160 according to one or more configurations, and the mold 102 is cured to form the multi-chip semiconductor package 200. It is understood that any of the steps in the fabrication may be performed in different sequences. As an example, the source via vias 264 and the gate via vias 266 may be filled (either as part of the mold 102 or separately) before the semiconductor device 100 is aligned and bonded.

[0026] At least one common source pad 280 and gate bridge 290 are formed on the top surface 261 of the first interconnect layer 260. A source via path 264 and a gate via path 266 extend through the first interconnect layer 260 and the adhesive layer 262. As best shown in FIGS. 7 and 8, the POL-RDL package 250 of the multi-chip semiconductor package 200 also includes a metal interconnect structure 267 that extends through the source via path 264 and the gate via path 266. The metal interconnect structure 267 electrically couples the top contact surface 112 of each of the source pads 110 to the at least one common source pad 280 of the POL-RDL package 250, and similarly, the metal interconnect structure 267 electrically couples the top contact surface 122 of the gate pad 120 to the gate bridge 290 of the POL-RDL package 250.

[0027] In some embodiments, the metal interconnect structure 267 is formed by filling the source via path 264 and the gate via path 266 with a conductive material (i.e., conductive epoxy, paste, or solder, etc.). In some embodiments, the vias have plated copper and a sputtered adhesion layer, such as titanium or Ti-tungsten. In some embodiments, the metal interconnect structure 267 is formed during deposition of the at least one common source pad 280 and the gate bridge 290. By way of example, when the at least one common source pad 280 and the gate bridge 290 are deposited, the source via path 264 and the gate via path 266 are also filled. The at least one common source pad 280 and the gate bridge 290 are then electroplated or otherwise plated or fabricated to a desired thickness.

[0028] In some embodiments, the gate bridge 290 includes a common gate pad 292 and a gate contact 296 connected by a trace connection 294. As best shown in FIG. 6, each of the gate contacts 296 of the gate bridge 290 is aligned with the gate pads 120 of the multiple semiconductor devices 100. As shown in FIGS. 7 and 8, the common gate pad 292, the trace connection 294, and the gate contact 296 are disposed on the first interconnect layer 260 of the POL-RDL package 250, and the gate contact 296 is electrically connected to the gate pad 120 by a metal interconnect structure 267. The trace connection 294 extends from the common gate pad 292 to the gate contact 296 and can have any number of branches and bends to establish an electrical connection between the common gate pad 292 and the gate contact 296. In the described embodiment, the gate bridge 290 has an I-shape with a pair of gate contacts 296 at each end that align with the gate pads 120 of multiple semiconductor devices 100, as shown in Figures 11 to 13A, however, the gate bridge 290 can have other shapes and configurations while maintaining equal path lengths, as described in more detail below.

[0029] As shown in FIG. 4, the trace connection 294 of the gate bridge 290 has the same length between the common gate pad 292 and the gate contact 296, so that there is an equal resistance between the common gate pad 292 and the gate contact 296. The length of the trace connection 294 affects the inductance. To achieve an approximately equal resistance instead, the length of the common gate pad 292 and the trace connection 294 can be made the same for all gate pads 120 of the semiconductor device 100. However, depending on how the source is connected, this may introduce asymmetry in the gate source loop inductance, which is a key parameter. The POL-RDL package 250 allows flexibility in optimizing the gate source loop inductance depending on how the gate source loop is oriented and connected to the next level circuit. For example, the resistance and trace length of two of the semiconductor devices 100 should be different from the other two semiconductor devices 100 so that the final gate source loop to each device is similar / equal.

[0030] To achieve trace connections 294 with equal lengths and equal resistance, the semiconductor devices 100 can be oriented or positioned on the adhesion layer 262 and first interconnect layer 260 such that the gate pads 120 of each of the semiconductor devices are equal distances from the common gate pad 292 of the gate bridge 290. In some embodiments, any one of the trace connections 294 can include a surface mount resistor or a thin film resistor to balance the resistance.

[0031] As shown in Figures 2, 4, and 7, the outer peripheral edge 108 of the underfill material 103 defines the surface area of ​​the mold 102. Each of the semiconductor devices 100 is spaced from the outer peripheral edge 108 of the mold 102, and the arrangement of the semiconductor devices 100 in the mold 102 defines the footprint 105 of the mold 102 (note that the footprint 105 as defined herein generally has a smaller surface area than the mold 102 itself). It is understood that in some embodiments, the semiconductor devices 100 are directly bonded to the first interconnect layer 260 (and adhesive layer 262) without the use of the mold 102, and in such embodiments, the footprint 105 is defined as the arrangement of the semiconductor devices 100 on the bottom surface of the first interconnect layer 260. Thus, the footprint 105 is defined as the outermost edge of the semiconductor devices 100.

[0032] The first interconnect layer 260 of the POL-RDL package 250 is generally disposed over the entire mold 102 and has a larger surface area than the footprint 105 of the mold 102. As a result, a peripheral edge 268 of the first interconnect layer 260 extends beyond the footprint 105 of the mold 102 and the outermost edge of the plurality of semiconductor devices 100 (note that the peripheral edge 268 does not extend beyond the perimeter of the mold 102 itself). In some embodiments, the adhesive layer 262 extends to the peripheral edge 268 of the first interconnect layer 260.

[0033] In some embodiments, the overhang region 274 of the POL-RDL package 250 increases the available surface area of ​​the first interconnect layer 260 for arranging a larger common source pad 280 and a larger common gate pad 292. The overhang region 274 also allows for arranging a more complex configuration of the common source pad 280, gate bridge 290, common gate pad 292, and trace connections for the common source pad 280 and common gate pad 292, as described in further detail below. The POL-EDL package 250 thus facilitates improved routing and more robust connection of at least one of the common source pad 280 and common gate pad 292 to external power electronics or to additional interconnect layers disposed over the first interconnect layer 260 (as described in further detail below). The connection of external power electronics, either directly on the at least one common source pad 280 and common gate pad 292 or through additional interconnect layers, allows the source pads 110 of the multiple semiconductor devices 100 to be used for power control and conversion. As an example, the source pads 110 of the multiple semiconductor devices 100 can be configured to turn on and off the power received from the respective gate pads 120 thousands of times per second. The at least one common source pad 280 and common gate pad 292 establish input / output (I / O) connections for the source pads 110 and the respective gate pads 120 through the metal interconnect structure 267. The input / output (I / O) connections allow the connection of the multi-chip semiconductor package 200 to external power electronics, such as a printed circuit board (PCB).

[0034] In at least some embodiments, a surface area of ​​the POL-RDL package 250 (e.g., a surface area of ​​the first interconnect layer 260) is approximately equal to a surface area of ​​the footprint 105 defined by the plurality of semiconductor devices 100. For example, the surface area of ​​the POL-RDL package 250 may be between a surface area 10% greater than the surface area of ​​the footprint 105 and a surface area 10% less than the surface area of ​​the footprint, more specifically, between a surface area 5% greater than the surface area of ​​the footprint 105 and a surface area 5% less than the surface area of ​​the footprint, and even more specifically, between a surface area 2% greater than the surface area of ​​the footprint 105 and a surface area 5% less than the surface area of ​​the footprint.

[0035] 9A-9D illustrate an embodiment of a trace 300 of an interconnect layer 302 disposed over the first interconnect layer 260. FIG. 9A illustrates a top view of the interconnect layer 302 and associated traces 300. FIG. 9B illustrates a top see-through view of the interconnect layer 302 and associated traces 300. FIG. 9C illustrates a cross-sectional view of the interconnect layer 302 and associated traces 300 taken along line C-C', and FIG. 9D illustrates a cross-sectional view of the interconnect layer 302 and associated traces 300. The interconnect layer 302 is stacked over the POL-RDL package 250 (specifically over the first interconnect layer 260) and includes pad and trace connections similar to the components shown in the multi-chip semiconductor package 200 of FIGS. 1-8.

[0036] The interconnect layer 302 is deposited over the first interconnect layer 260 of the POL-RDL package 250. The interconnect layer 302 includes at least one package contact pad 370 and a package gate pad 390, which facilitates connection of the multi-chip semiconductor package 200 to external power electronics. The electrical connections include one or more of soldering, sintering, copper bonding, copper clipping, and the like. In some embodiments, additional interconnect layers may be laminated over the interconnect layer 302 to facilitate more complex routing from the at least one package contact pad 370 and the package gate pad 390. In some embodiments, the at least one package contact pad 370 is a Kelvin contact.

[0037] A trace connection 372 extends from at least one package contact pad 370 to an attachment pad 374, which may have any number of branches and bends, to establish an electrical connection to an underlying structure, such as a common source pad 280 of the first interconnect layer 260. The common source pad 280 of the first interconnect layer 260 is electrically connected to the attachment pad 374 by a metal interconnect via path 362 that extends through the interconnect layer 302. The interconnect via path 362 is aligned with the at least one common source pad 280 for deposition of a metal interconnect structure that extends through the interconnect via path 362.

[0038] The interconnect layer 302 includes a gate via path 392 for connecting the common gate pad 292 to a package gate pad 390 on the interconnect layer 302. In some embodiments, the metal interconnect structure is formed by filling the interconnect via path 362 and the gate via path 392 with a conductive material (i.e., conductive epoxy, paste, solder, etc.). In some embodiments, the metal interconnect structure is formed during deposition of at least one of the package contact pad 370, the trace connection 372, the attachment pad 374, and the package gate pad 390.

[0039] The overhang region 274 and the larger surface area of ​​the POL-RDL package 250 facilitate complex routing. As shown in FIG. 9B , the trace connection 372 extends into the overhang region, but it is understood that the trace connection 372 can extend across at least one common source pad 280 of the first interconnect layer 260. By way of example, and not by way of limitation, FIG. 10A illustrates an embodiment in which the trace connection 372 extends across at least one common source pad 280 of the first interconnect layer 260.

[0040] 9A and 9B, the trace connection 372 extends at least partially into the overhang region 274, and the gate bridge 290 has an I-shape. Each of the gate contacts 296 and the trace connection 294 of the gate bridge 290 are equidistant from the common gate pad 292, so that the gate contacts 296 have the same resistance. In the illustrated embodiment, the interconnect layer 302 includes two common contact pads 370, each of which is connected to two corresponding semiconductor devices 100 by an attachment pad 374 and a trace connection 372. In some embodiments, there is at least one attachment pad 374 for each semiconductor device 100. The two common contact pads 370 and the common gate pad 292 are configured as input / output (I / O) connections to external power electronics for the multi-chip semiconductor package 200.

[0041] As shown in FIG. 10B, in some embodiments, a gate attachment pad 394 is electrically connected to the common gate pad 292 of the gate bridge 290 (as shown in FIG. 9B) by a gate via path 392. A package gate pad 390 is electrically connected to the gate attachment pad 394 by a trace connection 396. In some embodiments, the trace connection 396 includes a surface mount resistor 398. In some embodiments, the resistor 398 can be connected at a later time to allow for varying resistance values ​​to later meet different application needs. In some embodiments, the trace connection 396 includes an attachment pad for later mounting of the surface mount resistor 398.

[0042] Figures 11 and 12 illustrate further embodiments of traces (400, 500) on the interconnect layer 302. In Figures 11 and 12, at least one common source pad 280 is omitted for purposes of clarity of the drawings.

[0043] 11, one embodiment of the pathway 400 includes two common source or Kelvin pads 470, with each common contact pad 470 connected to two corresponding semiconductor devices 100 by a trace connection 472. The gate bridge 490 includes a common gate pad 492 disposed at least partially in the overhang region 274 and a gate contact 496 connected by a trace connection 494 to each of the corresponding semiconductor devices 100.

[0044] 12, another embodiment of the pathway 500 includes two common contacts or Kelvin pads 570 disposed at least partially in the overhang region 274, with each common contact pad 570 connected to two corresponding semiconductor devices 100 by a trace connection 572. In some embodiments, the two common contact pads 570 are Kelvin contacts. The gate bridge 590 includes a common gate pad 592 disposed at least partially in the overhang region 274 and a gate contact 596 connected by a trace connection 594 to each of the corresponding semiconductor devices 100.

[0045] The overhang region 274 and the larger surface area of ​​the POL-RDL package 250 facilitate the use of a large common gate pad (292, 492, 592), common contact pad (370, 470, 570), and associated trace connections (294, 494, 594, 372, 472, 572). The placement of the common gate pad (292, 492, 592) and at least one package contact pad 370 at least partially over the overhang region 274 also facilitates improved creep control between components. The POL-RDL package 250 also allows for an improved elastic (Young's) modulus of the first interconnect layer 260, which reduces bonding stresses on the semiconductor device 100. The first interconnect layer 260 of the POL-RDL package 250 may be polyimide, which has an elastic modulus of about 2.5 GPa, while the semiconductor device 100, which may be SiO2, may have an elastic modulus of about 70 GPa. The lower elastic modulus makes it possible to absorb bonding stresses, thereby reducing bonding stresses on the semiconductor device 100. The POL-RDL package 250 can thus buffer stresses during wire bonding to protect the semiconductor device 100.

[0046] The trace connections (294, 494, 594, 372, 472, 572) may have varying resistance values ​​and various trace configuration structures. Using different types of trace configurations allows for selectively adjusting the resistance value between the common gate pad (292, 492, 592) and the gate contact (296, 496, 596). The common gate pad and the common contact pad can then be connected to a package gate pad and a package contact pad on an additional interconnect layer. In particular, the additional resistance reduces crosstalk and therefore improves the efficiency of the semiconductor device 100. According to the embodiments described herein, the resistance value can be selectively adjusted for a particular application without altering the semiconductor device 100 during manufacturing and assembly. This allows for simplified manufacturing of multiple semiconductor devices 100 and binning during manufacturing.

[0047] For example, the resistance of the trace connections (294, 494, 594, 372, 472, 572) can be varied by depositing the trace connections with materials having different resistivities, modifying the width of the trace connections, and / or modifying the deposition thickness of the trace connections. An exemplary trace connection (294, 494, 594, 372, 472, 572) having a length of 2 mm, a width of 35 mm, and a thickness of 10 mm has a resistance of about 0.1 Ω. In some embodiments, the trace connections (294, 494, 594, 372, 472, 572) have a thickness in the range of 5 to 25 mm, and a trace width of about 25 mm. In some embodiments, the deposition depth of the trace connections (294, 494, 594, 372, 472, 572) ranges from 50 nanometers (nm) to 50 micrometers (μm). In some embodiments, the resistance of the trace connections (294, 494, 594, 372, 472, 572) is adjusted or changed by changing the volume of the trace connections (294, 494, 594, 372, 472, 572), changing the cross-sectional area of ​​the trace connections (294, 494, 594, 372, 472, 572), and / or changing the material of the trace connections (294, 494, 594, 372, 472, 572). In some embodiments, the trace connections (294, 494, 594, 372, 472, 572) are made of a combination of a first material having a first resistance value and a second material having a second resistance value, where the second material is laminated or layered over the first material. The resistance of the trace connections (294, 494, 594, 372, 472, 572) may be selectively adjustable within a range of 10 mΩ (microΩ) to 100 mΩ. In some embodiments, the trace connections (294, 494, 594, 372, 472, 572) are resistors. Additionally, in some embodiments, the trace connections (294, 494, 594, 372, 472, 572) are surface mount resistors. In some embodiments, the resistors 176 may be post-fabrication connected to allow for varying resistance values ​​to post-fabrication meet the needs of different applications.

[0048] To establish proper connection to external power electronics, the at least one common source pad 280 and the common gate pad 292 of the gate bridge 290 must have sufficient surface area to make the electrical connection. However, the complexity and surface area of ​​the at least one common source pad 280 and the gate bridge 290 are ultimately limited by the total surface area of ​​the first interconnect layer 260. By way of example, in at least some known semiconductor assemblies, the gate pads in a POL package can be up to 0.6 square millimeters (mm ) without the benefit of an overhang region 274. 2 ) surface area. Without the benefit of the additional surface area provided by the overhang region 274, the larger gate pads would necessarily reduce the available area for the placement of source pads, resulting in a lower current rating in each of the multi-chip semiconductor packages 200. In contrast, in at least some of the embodiments described herein, the common gate pad 292 of the gate bridge 290, assuming the benefit of the overhang region 274, can have a surface area of ​​0.5 mm. 2 ~1.5mm 2 9-12, the overhanging region 274 of the POL-RDL package 250 allows for redistribution and more complex configurations of the common gate pad 292 of the gate bridge 290 while still maintaining the current rating of the semiconductor device 100. Similar to the gate bridge 290, as shown in FIGS. 9-12, the overhanging region 274 of the POL-RDL package 250 allows for redistribution and more complex routing configurations of additional interconnect layers while still maintaining the current rating of the multi-chip semiconductor package 200.

[0049] Figure 13A illustrates an alternative embodiment of a via 702 disposed on a first interconnect layer, and Figure 13B illustrates an associated via 800 of an interconnect layer disposed over the first interconnect layer. The first interconnect layer and the vias include similar components as first interconnect layer 260 and interconnect layer 302, previously described with reference to Figures 1-10B.

[0050] As shown in FIG. 13A, the first interconnect layer path 700 includes a first common source pad 710, a second common source pad 712, and a gate bridge 730. The common source pads (710, 712) are electrically connected to the underlying semiconductor device 100 by a source via path 714 that extends through the first interconnect layer. The gate bridge 730 includes a common gate pad 732 and a gate contact 734 that are connected by a trace connection 736. The trace connection 736 is electrically connected to the underlying semiconductor device 100 by a gate via path 738 that extends through the first interconnect layer. As shown in FIG. 13B, the interconnect layer path 800 includes a package contact pad 810 that is electrically connected to the first common source pad 710 and the second common source pad 712, and a package gate pad 830 that is electrically connected to the common gate pad 732. The package contact pad 810 is electrically connected to the first common source pad 710 and the second common source pad 712 by the intermediate metal interconnect layer 802 .

[0051] As shown in Figure 13C, in some embodiments, a gate attachment pad 832 is electrically connected to the common gate pad 732 (of Figure 13A), and the gate attachment pad 832 is connected to a package gate pad 830 by a trace connection 834. In some embodiments, the trace connection 834 includes a surface mount resistor 836. In some embodiments, the resistor 836 can be connected at a later time to allow for a resistance value to be changed at a later time to meet the needs of different applications. In some embodiments, the trace connection 834 includes an attachment pad for later mounting of the surface mount resistor 836.

[0052] 14A and 14B illustrate a cross-sectional view of a backside structure 900 that is connected to the bottom surface 111 of a semiconductor device 100. The cross-sectional view is taken along line CC' in FIG. 9B.

[0053] As shown in FIG. 14A, the bottom surface 111 of the semiconductor device 100, including the drain pad, is left exposed. A sputtered layer 902 is sputtered onto the bottom surface 111 of the drain pad. The sputtered layer 902 facilitates electrical and thermal contact to the backside using solder, sintered silver, or conductive paste. The sputtered layer 902 substantially covers the entire bottom surface 111 of the semiconductor device 100, and in some embodiments, the sputtered layer 902 substantially covers the mold. A conductive plate 904 is then attached to the sputtered layer 902, as shown in FIG. 14B. In some embodiments, the conductive plate 720 is a direct bond copper DBC type substrate.

[0054] As shown in Fig. 14A, the sputtered layer 902 and the conductive plate 904 are applied to the bottom surface 111 of the semiconductor device 100 prior to application of the mold 102. As shown in Fig. 14B, the mold 102 extends below the bottom surface 111 of the semiconductor device 100, leaving the bottom surface 111 of the semiconductor device 100 partially exposed so that a partial nest is formed. The sputtered layer 902 fills into the gaps of the nest so that the sputtered layer 902 is flush with the mold 102. The conductive plate 904 is then applied to the sputtered layer 902.

[0055] 15A-15B illustrate one embodiment of a method 1000 of manufacturing a multi-chip semiconductor package, such as the previously described multi-chip semiconductor package 200. The method 1000 includes step 1002 of adhering an adhesive layer to a first interconnect layer of a POL-EDL package, and step 1004 of forming at least one source via path and at least one gate via path through the first interconnect layer and the adhesive layer.

[0056] The method 1000 further includes aligning 1006 at least one source pad and gate pad of the plurality of semiconductor devices with the at least one source via path and the at least one gate via path, respectively, and bonding 1008 the plurality of semiconductor devices to an adhesion layer. The method further includes 1010 filling 1010 the at least one source via path and the at least one gate via path, respectively, defined in the first interconnect layer with at least one metallized via. The method 1000 further includes 1012 depositing at least one common source pad and gate bridge, respectively, over the at least one gate via path.

[0057] In some embodiments, method 1000 further includes step 1014 of laminating an interconnect layer over the first interconnect layer and step 1016 of forming at least one source via path and at least one gate via path in the interconnect layer. Method 1000 further includes step 1018 of filling the at least one source via path and the at least one gate via path, respectively, defined in the interconnect layer with at least one metallized via. Method 1000 further includes step 1020 of depositing package contact pads and package gate pads over the at least one source via path and the at least one gate via path, respectively, defined in the interconnect layer.

[0058] In some embodiments, method 1000 further includes step 1022 of depositing a sputtered layer overlying a bottom surface of the plurality of semiconductor devices, the sputtered layer being electrically connected to a drain connection of the at least one common source pad of the plurality of semiconductor devices. In some embodiments, method 1000 further includes step 1024 of attaching a conductive plate overlying a bottom surface of the sputtered layer.

[0059] In some embodiments, the metallization layer is formed through a combination of sputtering and electroplating applications, although it is understood that other electroless methods of metal deposition can also be used. For example, a titanium adhesion layer and a copper seed layer are first deposited via a sputtering process, followed by an electroplating process that builds up the copper thickness to a desired level. The deposited metal material is then subsequently patterned into metal interconnects having the desired shape and functioning as vertical feedthroughs formed through the interconnect and adhesion layers.

[0060] The above-described embodiments overcome at least some of the shortcomings of semiconductor devices. Specifically, the embodiments improve surface bonding on the contact pads of the POL structure. In particular, the overhanging regions of the POL structure reduce bonding stress on the semiconductor device. The overhanging regions of the POL structure allow for redistribution of components of the POL-RDL package and the second stacked interconnect layer, allowing the contact pads to have a larger surface area. The overhanging regions also allow for utilization of a larger range of trace connections having varying resistance values.

[0061] The POL-RDL package also allows multiple semiconductor devices to operate as a single device with common gate and source pads. Individual semiconductor devices can be binned and grouped into devices with similar characteristics, thereby eliminating devices with wafer defects. This allows the formation of multi-chip semiconductor packages that exceed practical yield limits, as opposed to manufacturing a single large and complex semiconductor package. Furthermore, multi-chip semiconductor devices, when tiled together, allow for 5 mΩ devices. By way of example, and not limitation, binning four 20 mΩ semiconductor devices into a multi-chip semiconductor package and connecting the semiconductor devices in parallel with common gate and source pads results in a 5 mΩ device.

[0062] As described above, combining multiple semiconductor devices together into a multi-chip semiconductor package requires matching semiconductor devices with similar characteristics due to the inherent yield variations of individual semiconductor devices in semiconductor fabrication and manufacturing processes. In addition, the density limitations of multi-chip semiconductor package manufacturing and assembly increase the complexity of multi-chip semiconductor package design. Such factors may change the characteristics of the semiconductor devices. The POL-RDL package and the described systems and methods facilitate tiling semiconductor devices together. Each semiconductor device can be individually binned to improve packaging without having to overcome the variations in defect density of the larger semiconductor devices.

[0063] The methods, systems, and compositions disclosed herein are not limited to the specific embodiments described herein; rather, the method steps, system elements, and / or composition elements may be utilized independently and separately from other steps and / or elements described herein.

[0064] Although specific features of various embodiments may be shown in some figures and not in others, this is for convenience only. Moreover, references to "one embodiment" in the foregoing description are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. In accordance with the principles of the present disclosure, any feature of a figure may be referenced and / or claimed in combination with any feature of any other figure.

[0065] The description written herein uses examples, including the best mode, to enable one of ordinary skill in the art to practice the present disclosure, including making and using any device or system, and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that have insubstantial differences from the literal language of the claims.

[0066] Further aspects of the invention are provided by the subject matter of the following sections.

[0067] 1. An interconnect layer having a top surface and a bottom surface, the interconnect layer comprising a dielectric material; at least one common source pad disposed on the top surface of the interconnect layer; at least one common gate pad disposed on the top surface of the interconnect layer; a plurality of semiconductor devices each including a gate pad and at least one source pad bonded onto said interconnect layer; Equipped with the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other; a multi-chip semiconductor package, wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and the gate pads of the plurality of semiconductor devices are electrically connected in parallel to each other.

[0068] 2. The multi-chip semiconductor package of any preceding clause, further comprising an adhesive layer disposed on said bottom surface of said interconnect layer.

[0069] 3. The multi-chip semiconductor package of any preceding clause, further comprising a plurality of gate contacts disposed on the interconnect layer and electrically connected to the common gate pad by trace connections, each gate pad of each of the plurality of semiconductor devices being connected to an associated gate contact of the plurality of gate contacts.

[0070] 4. The multi-chip semiconductor package of any preceding clause, wherein the plurality of gate contacts are equidistant from the common gate pad.

[0071] 5. The multi-chip semiconductor package of any preceding clause, wherein the gate trace connections have equal resistance values.

[0072] 6. The multi-chip semiconductor package of any preceding clause, wherein at least one of the trace connections comprises one of a surface mount resistor and a thin film resistor.

[0073] 7. The multi-chip semiconductor package of any preceding clause, wherein the common gate pad and the at least one common source pad are configured to be electrically connected to external power electronics, such that the POL-RDL package operates as a single processing unit.

[0074] 8. The multi-chip semiconductor package of any preceding clause, further comprising a Kelvin contact electrically connected to said at least one common source pad to facilitate connecting said at least one common source pad to external power electronic circuitry.

[0075] 9. An additional interconnect layer disposed over the interconnect layer; a package gate pad disposed on the additional interconnect layer and electrically connected to the common gate pad of the additional interconnect layer; at least one package source pad disposed on the additional interconnect layer and electrically connected to the at least one common source pad of the additional interconnect layer; 2. The multi-chip semiconductor package of any preceding clause, further comprising:

[0076] 10. The multi-chip semiconductor package of any preceding clause, wherein the package gate pad is electrically connected by a trace connection to a gate attachment pad, the gate attachment pad being connected to the common gate pad of the interconnect layer.

[0077] 11. The multi-chip semiconductor package of any preceding clause, wherein the trace connection electrically connected to the package gate pad comprises one of a surface mount resistor and a thin film resistor.

[0078] 12. The multi-chip semiconductor package of any preceding clause, wherein the package gate pad and the at least one package source pad are configured to be electrically connected to external power electronics, such that the POL-RDL package operates as a single power switching unit.

[0079] 13. The multi-chip semiconductor package of any preceding clause, wherein a surface area of ​​the interconnect layer is approximately equal to a surface area of ​​a footprint defined by a plurality of semiconductor devices.

[0080] 14. The multi-chip semiconductor package of any preceding clause, wherein the rear sides of the semiconductor devices are electrically connected together by a conductive plate, thereby forming a common drain connection.

[0081] 15. The multi-chip semiconductor package of any preceding clause, further comprising a mold disposed between the interconnect layer and the conductive plate.

[0082] 16. Forming at least one source via path and at least one gate via path through an interconnect layer, the interconnect layer comprising a dielectric material; aligning at least one source pad and gate pad of a plurality of semiconductor devices to at least one source via path and at least one gate via path, respectively; bonding a plurality of semiconductor devices to an interconnect layer; wherein a surface area of ​​the interconnect layer is approximately equal to a surface area of ​​a footprint defined by a plurality of semiconductor devices.

[0083] 17. filling at least one source via path and at least one gate via path with at least one metallized via; depositing at least one common source pad and gate bridge over the at least one gate via path; The method of any preceding clause, further comprising:

[0084] 18. Laminating an additional interconnect layer over the first interconnect layer; forming at least one source via via and at least one gate via via in the additional interconnect layer; filling at least one source via path and at least one gate via path, each defined in the additional interconnect layer, with at least one second metallization via; The method of any preceding clause, further comprising:

[0085] 19. The method of any preceding clause, further comprising depositing a package contact pad and a package gate pad over the at least one source via path and the at least one gate via path, respectively, defined in the additional interconnect layer.

[0086] 20. Depositing a sputtered layer overlying the bottom surfaces of the plurality of semiconductor devices to form a common drain connection; depositing a conductive plate over the bottom surface of the sputtered layer; The method of any preceding clause, further comprising: [Explanation of symbols]

[0087] 100 Semiconductor Devices 101 Top surface 102 Mold 103 Underfill materials 104 Top surface 105 Footprint 106 Dielectric Materials 108 Outer edge 110 Sauce Pad 111 Bottom 112 Upper contact surface 120 Gate Pad 122 Upper contact surface 200 Multi-chip Semiconductor Package 250 POL-RDL Package 260 First Interconnect Layer 261 Top surface 262 Adhesive layer 264 Source Via Routing 266 Gate Via Route 267 Metallic Interconnect Structures 268 Outer edge 274 Overhang Area 280 Common Source Pad 290 Gate Bridge 292 Common Gate Pad 294 Trace Connections 296 Gate Contact 300 routes 302 Interconnection Layer 362 Metal Interconnect Via Path 370 Package Contact Pad 372 Trace Connections 374 Attachment Pad 390 Package gate pad, package gate bridge 392 Gate Via Route 394 Gate attachment pad 396 Trace Connection 398 Surface Mount Resistors 400 Routes 470 Common source pad, Kelvin pad, common contact pad 472 Trace Connection 490 Gate Bridge 492 Common Gate Pad 494 Trace Connection 496 Gate Contact 500 routes 570 common contact, Kelvin pad, common contact pad 572 Trace Connection 590 Gate Bridge 592 Common Gate Pad 594 Trace Connection 596 Gate Contact 700 routes 702 Routes 710 First Common Source Pad 712 Second Common Source Pad 714 Source Via Route 730 Gate Bridge 732 Common Gate Pad 734 Gate Contact 736 Trace Connection 738 Gate Via Route 800 Routes 802 Intermediate Metal Interconnect Layer 810 Package Contact Pad 830 Package Gate Pad 832 Gate attachment pad 834 Trace Connection 836 Surface Mount Resistor 900 Posterior structure 902 Sputtered layer 904 Conductive Plate

Claims

1. an interconnect layer having a top surface and a bottom surface, the interconnect layer comprising a dielectric material; at least one common source pad disposed on the top surface of the interconnect layer; at least one common gate pad disposed on the top surface of the interconnect layer; a plurality of semiconductor devices, each semiconductor device having a gate pad and at least one source pad bonded onto said interconnect layer; Equipped with the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and the source pads of the plurality of semiconductor devices are electrically connected in parallel to each other; the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and the gate pads of the plurality of semiconductor devices are electrically connected in parallel to each other; Multi-chip semiconductor package.

2. The multi-chip semiconductor package of claim 1 further comprising an adhesive layer disposed on said bottom surface of said interconnect layer.

3. 2. The multi-chip semiconductor package of claim 1, further comprising a plurality of gate contacts disposed on said interconnect layer and electrically connected to said common gate pad by trace connections, each gate pad of each of said plurality of semiconductor devices being connected to an associated gate contact of said plurality of gate contacts.

4. 4. The multi-chip semiconductor package of claim 3, wherein said gate contacts are equidistant from said common gate pad.

5. 4. The multi-chip semiconductor package of claim 3, wherein said gate trace connections have equal resistance values.

6. 6. The multi-chip semiconductor package of claim 5, wherein at least one of the trace connections comprises one of a surface mount resistor and a thin film resistor.

7. 4. The multi-chip semiconductor package of claim 3, wherein said common gate pad and said at least one common source pad are configured to be electrically connected to external power electronics such that said POL-RDL package operates as a single processing unit.

8. 8. The multi-chip semiconductor package of claim 7, further comprising a Kelvin contact electrically connected to said at least one common source pad to facilitate connecting said at least one common source pad to said external power electronic circuitry.

9. an additional interconnect layer disposed over the interconnect layer; a package gate pad disposed on the additional interconnect layer and electrically connected to the common gate pad of the additional interconnect layer; at least one package source pad disposed on the additional interconnect layer and electrically connected to the at least one common source pad of the additional interconnect layer; The multi-chip semiconductor package of claim 1 further comprising:

10. 10. The multi-chip semiconductor package of claim 9, wherein said package gate pad is electrically connected to a gate attachment pad by a trace connection, said gate attachment pad being connected to said common gate pad of said interconnect layer.

11. 11. The multi-chip semiconductor package of claim 10, wherein the trace connections electrically connected to the package gate pads comprise one of a surface mount resistor and a thin film resistor.

12. 10. The multi-chip semiconductor package of claim 9, wherein the package gate pad and the at least one package source pad are configured to be electrically connected to external power electronics such that the POL-RDL package operates as a single power switching unit.

13. 2. The multi-chip semiconductor package of claim 1, wherein a surface area of ​​said interconnect layer is approximately equal to a surface area of ​​a footprint defined by said plurality of semiconductor devices.

14. 2. The multi-chip semiconductor package of claim 1, wherein rear sides of said semiconductor devices are electrically connected together by a conductive plate, thereby forming a common drain connection.

15. The multi-chip semiconductor package of claim 14 further comprising a mold disposed between said interconnect layer and said conductive plate.

16. forming at least one source via path and at least one gate via path through an interconnect layer, said interconnect layer comprising a dielectric material; aligning at least one source pad and gate pad of a plurality of semiconductor devices to the at least one source via path and the at least one gate via path, respectively; bonding the plurality of semiconductor devices to the interconnect layer; Including, A method for manufacturing a multi-chip semiconductor package, wherein a surface area of ​​the interconnect layer is approximately equal to a surface area of ​​a footprint defined by the plurality of semiconductor devices.

17. filling said at least one source via path and said at least one gate via path with at least one metallization via; depositing at least one common source pad and gate bridge over the at least one gate via path; 20. The method of claim 16, further comprising:

18. depositing an additional interconnect layer over the first interconnect layer; forming at least one source via via and at least one gate via via in said additional interconnect layer; filling said at least one source via path and said at least one gate via path respectively defined in said additional interconnect layer with at least one second metallization via; 20. The method of claim 17, further comprising:

19. 20. The method of claim 18, further comprising depositing a package contact pad and a package gate pad over the at least one source via path and the at least one gate via path defined in the additional interconnect layer, respectively.

20. depositing a sputtered layer overlying bottom surfaces of the semiconductor devices to form a common drain connection; depositing a conductive plate over the bottom surface of the sputtered layer; 20. The method of claim 16, further comprising:

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