Nitride semiconductor device

Abstract

To provide a nitride semiconductor device capable of reducing an operating resistance value.SOLUTION: A nitride semiconductor device 10 includes: a substrate 12; a drift layer 14 with a first conductivity type; a first base layer 16 formed over the drift layer 14; a second base layer 18 with a second conductivity type formed above the first base layer 16; an electron transport layer 28 formed above the second base layer 18 and in portion along an inner surface of a gate opening 24; and an electronic supply layer 30 formed above the electron transport layer 28 covering the gate opening 24.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Nitride semiconductors such as GaN (gallium nitride) are wide-gap semiconductors with a large band gap, and are characterized by a large dielectric breakdown field and a high electron saturation drift velocity compared to GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors. For this reason, research and development is being conducted on power transistors that use nitride semiconductors, which are advantageous for achieving high output and high voltage resistance.

[0003] For example, Patent Document 1 discloses a semiconductor device formed on a GaN-based laminate. The semiconductor device described in Patent Document 1 is a vertical field effect transistor (FET) including a regrowth layer positioned so as to cover an opening provided in the GaN-based laminate, and a gate electrode positioned on the regrowth layer along the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer, realizing a FET with high mobility and low on-resistance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2011-82397 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the field effect transistor described in Patent Document 1, the current only flows directly below the opening and does not diffuse laterally, which causes a problem that the resistance value of the field effect transistor increases during operation.

[0006] In view of this, the present disclosure provides a nitride semiconductor device capable of reducing the resistance value during operation. [Means for solving the problem]

[0007] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, a first electron transport layer having a first conductivity type provided above the first main surface, a first electron supply layer provided above the first electron transport layer, a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron supply layer, a second electron transport layer provided above the first nitride semiconductor layer and along an inner surface of a first opening that penetrates the first electron supply layer and the first nitride semiconductor layer to reach the first electron transport layer, and a second electron supply layer provided above the second electron transport layer and covering the first opening.

[0008] A nitride semiconductor device according to an aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, a first electron transport layer having a first conductivity type provided above the first main surface, a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron transport layer, a second electron transport layer provided in an upper portion of the first nitride semiconductor layer and along an inner surface of a first opening that penetrates the first electron supply layer and the first nitride semiconductor layer to reach the first electron transport layer, and an electron supply layer provided above the second electron transport layer and covering the first opening. The first electron transport layer includes a third nitride semiconductor layer of the first conductivity type, and a fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first nitride semiconductor layer and having a higher impurity concentration than the third nitride semiconductor layer. Effect of the Invention

[0009] According to the nitride semiconductor device according to the present disclosure, the resistance value during operation can be reduced. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a planar layout of a nitride semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of the nitride semiconductor device according to the first embodiment. [Figure 3A] FIG. 3A is a cross-sectional view showing a nitride semiconductor lamination step in the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view showing a resist patterning step in the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 3C] FIG. 3C is a cross-sectional view showing a step of forming a gate opening in the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 3D] FIG. 3D is a cross-sectional view showing a nitride semiconductor regrowth step in the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 3E] FIG. 3E is a cross-sectional view showing a gate electrode formation step in the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 3F] FIG. 3F is a cross-sectional view showing a step of forming a source opening in the method for manufacturing the nitride semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a nitride semiconductor device according to the first modification. [Figure 5A] FIG. 5A is a cross-sectional view showing a step of patterning a resist used as a mask during ion implantation in a method for manufacturing a nitride semiconductor device according to Modification 1. In FIG. [Figure 5B] FIG. 5B is a cross-sectional view showing an ion implantation step in the method for manufacturing a nitride semiconductor device according to Modification 1. As shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view of a nitride semiconductor device according to the second modification. [Figure 7]FIG. 7 is a cross-sectional view of a nitride semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a nitride semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Summary of the Disclosure) In order to solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, a first electron transit layer having a first conductivity type provided above the first main surface, a first electron supply layer provided above the first electron transit layer, a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron supply layer, and a first electron supply layer penetrating the first electron supply layer and the first nitride semiconductor layer and the first electron transit layer. a second electron transit layer provided above the first nitride semiconductor layer and along an inner surface of the first opening; a second electron supply layer provided above the second electron transit layer and covering the first opening; a gate electrode provided above the second electron supply layer and covering the first opening; a source electrode connected to the first nitride semiconductor layer and the second electron transit layer; and a drain electrode provided on the second main surface side of the substrate.

[0012] As a result, the two-dimensional electron gas generated in the first electron transit layer forms a channel, and the source-drain current flowing through the opening diffuses laterally along the channel in the first electron transit layer. In other words, the path of the current flowing in the first electron transit layer can be widened, making it easier for the source-drain current to flow. Therefore, this aspect provides a nitride semiconductor device that can reduce the resistance value during operation.

[0013] Also, for example, the nitride semiconductor device according to one aspect of the present disclosure may further include a high-resistance layer made of a nitride semiconductor and having a higher resistance than the first nitride semiconductor layer, the high-resistance layer being provided along an inner surface of the first opening, between the first nitride semiconductor layer and the second electron transport layer.

[0014] As a result, since the high-resistance layer is provided between the first nitride semiconductor layer and the second electron transit layer, the high-resistance layer suppresses leakage current from the source electrode through the first nitride semiconductor layer and the second electron transit layer to the gate electrode. For example, the high-resistance layer functions as an insulating layer, so that the path of the leakage current is substantially blocked and the leakage current can be sufficiently reduced.

[0015] For example, the high resistance layer may contain iron.

[0016] Thus, by including iron in the nitride semiconductor, the resistance of the high resistance layer can be increased, and leakage current can be further reduced. Furthermore, the high resistance layer can be easily formed in a desired shape in a desired region by ion implantation or the like. For example, ion implantation can easily cause the nitride semiconductor in the region where iron ions are implanted to be in an amorphous state, and the resistance of the region can be increased. Ion implantation can accurately adjust the resistance value and shape of the high resistance layer, and therefore the reliability of the leakage current suppression effect can be improved.

[0017] Furthermore, for example, the high resistance layer may be provided along an inner surface of the first opening, between the first electron supply layer and the second electron transit layer.

[0018] This allows not only the first nitride semiconductor layer but also the exposed portion of the first electron supply layer in the first opening to be covered with the high resistance layer, thereby ensuring that the end portion of the first nitride semiconductor layer is covered with the high resistance layer, thereby further improving the reliability of the effect of suppressing leakage current.

[0019] Furthermore, for example, the first opening may include a bottom portion and a sidewall portion, and the high-resistance layer may be provided from the sidewall portion to a part of the bottom portion.

[0020] Since the first opening has an inner surface extending from the sidewall to a part of the bottom, electric field concentration at the boundary between the sidewall and the bottom can be suppressed. Suppression of electric field concentration can increase the breakdown voltage of the nitride semiconductor device.

[0021] Also, for example, the nitride semiconductor device according to one aspect of the present disclosure may further include a second nitride semiconductor layer having the second conductivity type and provided between the gate electrode and the second electron transit layer.

[0022] This allows the second nitride semiconductor layer to reduce the carrier concentration directly below the gate electrode, and the threshold voltage of the nitride semiconductor device can be shifted to the positive side, so that the nitride semiconductor device according to this embodiment can be operated as a normally-off type FET.

[0023] Furthermore, for example, when the substrate is viewed from above, an end of the gate electrode may be located closer to the source electrode than an end of the first opening.

[0024] This allows for improved control of the channel formed in the regrown layer.

[0025] Also, for example, the nitride semiconductor device according to one aspect of the present disclosure may further include a second opening at a position away from the gate electrode, penetrating the second electron transit layer and reaching the first nitride semiconductor layer, and at least a portion of the source electrode may be provided within the second opening.

[0026] This allows a depletion layer to be formed near the interface between the second nitride semiconductor layer and the first nitride semiconductor layer by a voltage applied between the source electrode and the drain electrode. The formation of the depletion layer makes it possible to suppress the occurrence of leakage current between the source and drain. Therefore, the breakdown voltage of the nitride semiconductor device can be increased.

[0027] Also, for example, the first electron transport layer may include a third nitride semiconductor layer of the first conductivity type, and an undoped fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first electron supply layer.

[0028] As a result, the two-dimensional electron gas generated in the fourth nitride semiconductor layer forms a channel, and the source-drain current flowing through the opening diffuses laterally along the channel in the fourth nitride semiconductor layer. In other words, the path of the current flowing in the first electron transit layer can be widened, making it easier for the source-drain current to flow. Therefore, according to this aspect, a nitride semiconductor device capable of reducing the resistance value during operation is provided. In addition, the fourth nitride semiconductor layer is an undoped nitride semiconductor layer containing a small amount of impurities, and therefore mobility can be increased.

[0029] a first nitride semiconductor layer having a second conductivity type different from the first conductivity type and provided above the first electron transport layer; a first opening penetrating the first nitride semiconductor layer to reach the first electron transport layer; a second electron transport layer provided in an upper portion of the first nitride semiconductor layer and along an inner surface of the first opening; an electron supply layer provided above the second electron transport layer and covering the first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode connected to the first nitride semiconductor layer and the second electron transport layer; and a drain electrode provided on the second main surface side of the substrate. The first electron transport layer includes a third nitride semiconductor layer of the first conductivity type, and a fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first nitride semiconductor layer and having a higher impurity concentration than the third nitride semiconductor layer.

[0030] As a result, two-dimensional electron gas generated in the fourth nitride semiconductor layer having a high impurity concentration forms a channel, and the source-drain current flowing through the opening diffuses laterally along the channel in the fourth nitride semiconductor layer. In other words, the path of the current flowing in the first electron transit layer can be widened, making it easier for the source-drain current to flow. In addition, since the fourth nitride semiconductor layer has a high impurity concentration and low resistance, the diffusion of the current can be further promoted. Therefore, according to this aspect, a nitride semiconductor device capable of further reducing the resistance value during operation is provided.

[0031] Hereinafter, the embodiment will be specifically described with reference to the drawings.

[0032] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims are described as optional components.

[0033] In addition, each figure is a schematic diagram and is not necessarily illustrated precisely. Therefore, for example, the scales in each figure do not necessarily match. In addition, in each figure, substantially the same configurations are given the same reference numerals, and duplicated explanations are omitted or simplified.

[0034] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or coincident, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that include a substantially equivalent range, for example, a difference of about a few percent.

[0035] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. In addition, the terms "above" and "below" are applied not only to the case where two components are arranged with a gap between them and another component exists between the two components, but also to the case where two components are arranged closely together and are in contact with each other.

[0036] (Embodiment 1) [composition] First, the configuration of a nitride semiconductor device according to the first embodiment will be described with reference to FIGS.

[0037] Fig. 1 is a plan view showing a planar layout of a nitride semiconductor device 10 according to the present embodiment. Fig. 2 is a cross-sectional view of the nitride semiconductor device 10 according to the present embodiment.

[0038] Here, (a) of Fig. 1 is a plan view of the nitride semiconductor device 10 as viewed from above. (b) of Fig. 1 shows an enlarged view of one unit cell 11 of the nitride semiconductor device 10. Fig. 2 shows a cross section of the nitride semiconductor device 10 according to the present embodiment taken along line II-II of Fig. 1.

[0039] As shown in (a) of FIG. 1, a nitride semiconductor device 10 includes a plurality of unit cells 11. The plurality of unit cells 11 are arranged two-dimensionally. The plurality of unit cells 11 each have the same configuration. The shape of each unit cell 11 in a plan view is a hexagon. The plurality of unit cells 11 are arranged such that the centers of the respective unit cells 11 are located at the vertices of the regular hexagons in which they are packed together in a plan view.

[0040] Each unit cell 11 is configured with one source electrode 36 at its center. Fig. 2 shows a cross section taken along line II-II passing through the centers of two adjacent unit cells 11.

[0041] As shown in Fig. 2, the nitride semiconductor device 10 includes a substrate 12, a drift layer 14, a first underlayer 16, a second underlayer 18, a third underlayer 20, a fourth underlayer 22, a gate opening 24, an electron transit layer 28, an electron supply layer 30, a gate electrode 32, a source opening 34, a source electrode 36, and a drain electrode 38. Furthermore, as shown in Fig. 1(a), the nitride semiconductor device 10 includes a gate electrode pad 40 and a source electrode pad 42. In Fig. 1(a), the outline of the source electrode pad 42 is diagrammatically represented by a dashed line.

[0042] The nitride semiconductor device 10 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN, etc. Specifically, the nitride semiconductor device 10 has a heterostructure of an AlGaN film and a GaN film.

[0043] In the heterostructure of an AlGaN film and a GaN film, spontaneous polarization or piezoelectric polarization on the c-plane, which is represented by the (0001) plane, generates a high concentration of two-dimensional electron gas (2DEG) at the heterointerface. Even in an undoped state, the interface has a high concentration of 1×10 13 cm -2 The sheet carrier concentration is characterized by the above.

[0044] The nitride semiconductor device 10 has a plurality of heterostructures. Specifically, the stacked structure of the drift layer 14 and the first underlayer 16 and the stacked structure of the electron transit layer 28 and the electron supply layer 30 each form a heterostructure. In the drift layer 14, a two-dimensional electron gas 46 is generated in the vicinity of the interface between the drift layer 14 and the first underlayer 16. In the electron transit layer 28, a two-dimensional electron gas 44 is generated in the vicinity of the interface between the electron transit layer 28 and the electron supply layer 30. The nitride semiconductor device 10 according to the present embodiment is a field effect transistor (FET) that uses the two-dimensional electron gas 44 generated in the electron transit layer 28 as a channel. Specifically, the nitride semiconductor device 10 is a so-called vertical FET. In FIG. 2, the two-dimensional electron gases 44 and 46 are each diagrammatically shown by a broken line.

[0045] The substrate 12 is made of a nitride semiconductor, and has a first principal surface 12a and a second principal surface 12b facing each other as shown in Fig. 2. The first principal surface 12a is the principal surface on the side on which the drift layer 14 is formed. Specifically, the first principal surface 12a approximately coincides with the c-plane. The second principal surface 12b is the principal surface on the opposite side to the first principal surface 12a, and is the principal surface on the side on which the drain electrode 38 is formed. The planar shape of the substrate 12 is, for example, rectangular, but is not limited thereto.

[0046] The substrate 12 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 18 cm -3 The substrate is made of n-type GaN, which is n-type GaN. Note that n-type and p-type indicate the conductivity types of semiconductors. In this embodiment, n-type is an example of a first conductivity type of a nitride semiconductor. P-type is an example of a second conductivity type having a polarity different from that of the first conductivity type.

[0047] The substrate 12 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0048] The drift layer 14 is an example of a first electron transport layer having a first conductivity type that is provided above the first main surface 12a of the substrate 12. The drift layer 14 is made of a nitride semiconductor of the first conductivity type. The drift layer 14 has a thickness of 8 μm and a carrier concentration of 1×10 16 cm -3 The drift layer 14 is provided in contact with the first main surface 12a of the substrate 12.

[0049] The first underlayer 16 is an example of a first electron supply layer provided above the drift layer 14. The first underlayer 16 is made of a nitride semiconductor. For example, the first underlayer 16 is made of undoped AlN.sub.2O.sub.3 with a thickness of 50 nm. 0.2 Ga 0.8 The first underlayer 16 is a film made of N. An AlGaN / GaN heterointerface is formed between the first underlayer 16 and the drift layer 14. As a result, two-dimensional electron gas 46 is generated in the drift layer 14.

[0050] The second underlayer 18 is an example of a first nitride semiconductor layer having a second conductivity type different from the first conductivity type, which is provided above the first underlayer 16. The second underlayer 18 has a thickness of 400 nm and a carrier concentration of 1×10 17 cm -3 The second underlayer 18 is provided in contact with the upper surface of the first underlayer 16.

[0051] The second underlayer 18 suppresses leakage current between the source electrode 36 and the drain electrode 38. For example, when a reverse voltage is applied to the pn junction formed between the second underlayer 18 and the drift layer 14, specifically, when the drain electrode 38 has a higher potential than the source electrode 36, a depletion layer extends to the drift layer 14. This allows the nitride semiconductor device 10 to withstand high voltages.

[0052] The third underlayer 20 is disposed on the second underlayer 18. The third underlayer 20 is formed of an insulating or semi-insulating nitride semiconductor. The third underlayer 20 is, for example, a film made of undoped GaN having a thickness of 200 nm. The third underlayer 20 is provided in contact with the second underlayer 18.

[0053] Here, "undoped" means that the GaN layer is not doped with a dopant such as silicon (Si) or magnesium (Mg) that changes the polarity of the GaN layer to n-type or p-type. In this embodiment, the third underlayer 20 is doped with carbon. Specifically, the carbon concentration of the third underlayer 20 is higher than the carbon concentration of the second underlayer 18.

[0054] The third underlayer 20 may contain silicon (Si) or oxygen (O) that is mixed in during film formation. In this case, the carbon concentration of the third underlayer 20 is, for example, 3×10 17 cm -3 That's it, but 1×10 18 cm -3 The silicon concentration or oxygen concentration of the third underlayer 20 may be, for example, 5×10 16 cm -3 Below, 2×10 16 cm -3 The following is also fine.

[0055] If the nitride semiconductor device 10 does not include the third underlayer 20, a laminated structure of n-type electron supply layer 30 and electron transit layer 28 / p-type second underlayer 18 / n-type first underlayer 16 and n-type drift layer 14 is formed between the source electrode 36 and the drain electrode 38. This laminated structure forms a parasitic bipolar transistor having a parasitic npn structure.

[0056] When the nitride semiconductor device 10 is in an off state, if a current flows through the second underlayer 18, this parasitic bipolar transistor may turn on, which may reduce the breakdown voltage of the nitride semiconductor device 10. In this case, the nitride semiconductor device 10 is likely to malfunction.

[0057] The third underlayer 20 suppresses the formation of this parasitic npn structure, thereby reducing malfunction of the nitride semiconductor device 10 caused by the formation of the parasitic npn structure. Note that, if the current flowing through the second underlayer 18 is sufficiently suppressed, the nitride semiconductor device 10 does not need to include the third underlayer 20.

[0058] The fourth underlayer 22 is disposed on the third underlayer 20. The fourth underlayer 22 is, for example, an Al 0.2 Ga 0.8 The fourth underlayer 22 is provided in contact with the third underlayer 20.

[0059] The fourth underlayer 22 suppresses the diffusion of p-type impurities such as Mg from the second underlayer 18. If Mg diffuses to the channel in the electron transit layer 28, the carrier concentration of the two-dimensional electron gas 44 may decrease, resulting in an increase in on-resistance. The degree of Mg diffusion varies depending on the epitaxial growth conditions, etc. For this reason, if the diffusion of Mg is suppressed, the nitride semiconductor device 10 does not need to include the fourth underlayer 22.

[0060] The fourth underlayer 22 may have a function of supplying electrons to a channel formed at the interface between the electron transit layer 28 and the electron supply layer 30. The fourth underlayer 22 has a larger band gap than the electron supply layer 30, for example.

[0061] The gate opening 24 is an example of a first opening penetrating the first underlayer 16 and reaching the drift layer 14. Specifically, the gate opening 24 penetrates from the upper surface of the fourth underlayer 22 through the fourth underlayer 22, the third underlayer 20, the second underlayer 18, and the first underlayer 16 in this order, and reaches the drift layer 14. A bottom 24a of the gate opening 24 is the upper surface of the drift layer 14. In this embodiment, as shown in FIG. 2, the bottom 24a of the gate opening 24 is located below the interface between the drift layer 14 and the first underlayer 16.

[0062] In this embodiment, the gate opening 24 is formed so that the opening area increases as it gets farther from the substrate 12. Specifically, the sidewall 24b of the gate opening 24 is inclined obliquely. For example, the cross-sectional shape of the gate opening 24 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In FIG. 1(b), the outline of the upper end of the gate opening 24 is shown by a dashed line. The outline of the bottom 24a of the gate opening 24 is slightly smaller than the outline shown in FIG. 1(b).

[0063] The electron transit layer 28 is an example of a second electron transit layer provided in an upper portion of the second underlayer 18 and along the inner surface of the gate opening 24. The electron transit layer 28 is a first regrown layer formed by regrowth of a nitride semiconductor after the gate opening 24 is formed. Specifically, the electron transit layer 28 is formed with a substantially uniform thickness along the upper surface of the fourth underlayer 22 and the sidewall portion 24b and bottom portion 24a of the gate opening 24. The electron transit layer 28 is, for example, a film made of undoped GaN having a thickness of 100 nm.

[0064] The electron transit layer 28 is in contact with the drift layer 14 at the bottom 24a of the gate opening 24. The electron transit layer 28 is in contact with each side surface of the first underlying layer 16, the second underlying layer 18, the third underlying layer 20, and the fourth underlying layer 22 at the sidewall portion 24b of the gate opening 24. In addition, the electron transit layer 28 is in contact with the upper surface of the fourth underlying layer 22.

[0065] The electron transit layer 28 has a channel. Specifically, a two-dimensional electron gas 44 is generated in the vicinity of the interface between the electron transit layer 28 and the electron supply layer 30. The two-dimensional electron gas 44 functions as the channel of the electron transit layer 28. The electron transit layer 28 is undoped, but may be made n-type by Si doping or the like.

[0066] Although not shown, in this embodiment, an AlN film having a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 28 and the electron supply layer 30. The AlN film can suppress alloy scattering and improve the mobility of the channel. Note that the AlN film does not have to be provided, and the electron transit layer 28 and the electron supply layer 30 may be in direct contact with each other.

[0067] The electron supply layer 30 is an example of a second electron supply layer provided above the second underlayer 18 and along the inner surface of the gate opening 24. The electron supply layer 30 is a third regrown layer formed by regrowth of a nitride semiconductor after the gate opening 24 is formed. The electron transit layer 28 and the electron supply layer 30 are provided in this order from the substrate 12 side. The electron supply layer 30 is formed with a shape that conforms to the upper surface of the electron transit layer 28 and with a substantially uniform thickness. The electron supply layer 30 is, for example, a 50 nm-thick undoped Al 0.2 Ga 0.8 The membrane is made of N.

[0068] The electron supply layer 30 forms an AlGaN / GaN heterointerface between itself and the electron transit layer 28, with an AlN film having a thickness of, for example, 1 nm sandwiched therebetween. As a result, a two-dimensional electron gas 44 is generated in the electron transit layer 28.

[0069] The electron supply layer 30 supplies electrons to a channel (i.e., two-dimensional electron gas 44) formed in the electron transit layer 28. As described above, in this embodiment, the fourth underlayer 22 also has an electron supply function. Both the electron supply layer 30 and the fourth underlayer 22 are made of AlGaN, but the Al composition ratio is not particularly limited. For example, the Al composition ratio of the electron supply layer 30 may be 20%, and the Al composition ratio of the fourth underlayer 22 may be 25%.

[0070] The gate electrode 32 is provided above the electron supply layer 30 so as to cover the gate opening 24. In the present embodiment, the gate electrode 32 is formed in a shape that conforms to the upper surface of the electron supply layer 30, in contact with the upper surface of the electron supply layer 30, and with a substantially uniform thickness.

[0071] The gate electrode 32 is formed of a conductive material such as a metal. For example, the gate electrode 32 is formed of palladium (Pd). Note that, as the material of the gate electrode 32, a material that is connected to an n-type semiconductor through a Schottky connection can be used, such as a nickel (Ni)-based material, tungsten silicide (WSi), or gold (Au).

[0072] The gate electrode 32 is formed to be separated from the source electrode 36 in a plan view so as not to contact the source electrode 36. Specifically, as shown in Fig. 1(b), the gate electrode 32 is provided to surround the source electrode 36 in a plan view. More specifically, the gate electrode 32 is formed in the shape of a plate provided with a plurality of openings corresponding to the hexagonal source electrode 36.

[0073] In this embodiment, in a plan view, an end of the gate electrode 32 is located closer to the source electrode 36 than an end of the gate opening 24. Specifically, in a plan view, the gate opening 24 is provided inside the gate electrode 32. That is, in a plan view, the gate electrode 32 completely covers the gate opening 24.

[0074] The source opening 34 is an example of a second opening that penetrates the electron transit layer 28 at a position away from the gate electrode 32 and reaches the second underlayer 18. Specifically, the source opening 34 penetrates the electron supply layer 30, the electron transit layer 28, the fourth underlayer 22, and the third underlayer 20 in this order, and reaches the second underlayer 18. In this embodiment, as shown in FIG. 2, a bottom 34a of the source opening 34 is the upper surface of the second underlayer 18. The bottom 34a is located below the interface between the second underlayer 18 and the third underlayer 20. The source opening 34 is located at a position away from the gate opening 24 in a plan view.

[0075] 2, the source opening 34 is formed to have a substantially constant opening area. Specifically, the sidewall portion 34b of the source opening 34 is substantially parallel to the thickness direction of the substrate 12. For example, the cross-sectional shape of the source opening 34 is rectangular. Alternatively, the cross-sectional shape of the source opening 34 may be an inverted trapezoid, similar to the gate opening 24.

[0076] In this embodiment, the opening shape of the source opening 34, i.e., the shape in plan view, is a regular hexagon as shown in Fig. 1(b). The distance from the gate electrode 32 provided so as to surround the outer periphery of the source opening 34 is approximately constant. The sidewall portion 34b of the source opening 34 has a {1-100} plane. Here, the {1-100} plane collectively refers to the (1-100) plane and a plane equivalent to the (1-100) plane.

[0077] The source electrode 36 is provided in the source opening 34. Specifically, the source electrode 36 is provided so as to fill the inside of the source opening 34.

[0078] The source electrode 36 is connected to the second under layer 18. Specifically, the source electrode 36 is connected to each end face of the electron supply layer 30, the electron transit layer 28, the fourth under layer 22, and the third under layer 20. The source electrode 36 is ohmic-connected to the electron transit layer 28 and the electron supply layer 30.

[0079] The source electrode 36 is formed of a conductive material such as a metal. The material of the source electrode 36 may be, for example, a material that forms an ohmic connection with the n-type semiconductor layer, such as Ti / Al.

[0080] Since the source electrode 36 is connected to the third underlayer 20, it is possible to fix the potential of the third underlayer 20. This makes it possible to stabilize the operation of the nitride semiconductor device 10.

[0081] Furthermore, Al is Schottky-connected to the second underlayer 18 made of a p-type nitride semiconductor. For this reason, a metal material with a large work function, such as Pd or Ni, which provides low contact resistance with the p-type nitride semiconductor, may be provided in the lower layer of the source electrode 36. This makes it possible to further stabilize the potential of the second underlayer 18.

[0082] The drain electrode 38 is provided on the second main surface 12b side of the substrate 12. Specifically, the drain electrode 38 is provided in contact with the second main surface 12b. The drain electrode 38 is formed using a conductive material such as a metal. As with the material of the source electrode 36, the material of the drain electrode 38 may be, for example, Ti / Al, which is ohmic-connected to the n-type semiconductor layer.

[0083] The gate electrode pad 40 is electrically connected to the gate electrode 32. The gate electrode pad 40 is provided, for example, above the gate electrode 32. In this embodiment, since the gate electrode 32 is formed in the shape of a single plate, the gate electrode pad 40 is provided only in a partial region of the nitride semiconductor device 10 in a plan view, as shown in (a) of Fig. 1. A power supply for controlling the gate electrode 32 is connected to the gate electrode pad 40.

[0084] The source electrode pad 42 is electrically connected to each of the multiple source electrodes 36. The source electrode pad 42 is provided above the source electrode 36. In the present embodiment, each of the multiple source electrodes 36 is formed in a hexagonal island shape. For this reason, the source electrode pad 42 is provided in most of the region excluding the gate electrode pad 40 in a plan view of the nitride semiconductor device 10 so as to cover each of the multiple source electrodes 36.

[0085] As described above, in the nitride semiconductor device 10 according to the present embodiment, the interface between the electron transit layer 28 and the electron supply layer 30 is an AlGaN / GaN heterointerface. This generates a two-dimensional electron gas 44 in the electron transit layer 28, forming a channel. Since the two-dimensional electron gas 44 has a high carrier concentration, the mobility of the channel increases, and the resistance value (on-resistance) during operation is reduced.

[0086] In the nitride semiconductor device 10, the two-dimensional electron gas 46 is formed in the drift layer 14 so as to extend laterally (specifically, in a direction parallel to the first main surface 12a of the substrate 12) from the vicinity of the bottom 24a of the gate opening 24. Therefore, electrons moving through the two-dimensional electron gas 44 in the electron transit layer 28 tend to spread laterally through the two-dimensional electron gas 46 in the vicinity of the bottom 24a. Therefore, not only the portion located directly below the bottom 24a in the drift layer 14 but also the portion located outside the portion (outside the bottom 24a in a plan view) can be used as a path for current flow. Therefore, the source-drain current tends to diffuse over a wide region in the drift layer 14. This makes it possible to reduce the resistance value during operation of the nitride semiconductor device 10.

[0087] [Manufacturing method] Next, a method for manufacturing the nitride semiconductor device 10 according to the present embodiment will be described with reference to Figures 3A to 3F. Figures 3A to 3F are cross-sectional views showing each step of the method for manufacturing the nitride semiconductor device 10 according to the present embodiment.

[0088] In the following, a case will be described in which each nitride semiconductor layer constituting the nitride semiconductor device 10 is formed by a metal organic vapor phase epitaxy (MOVPE) method. Note that the method for forming the nitride semiconductor layers is not limited to this, and they may be formed by, for example, a molecular beam epitaxy (MBE) method.

[0089] An n-type nitride semiconductor is formed by adding, for example, silicon (Si). A p-type nitride semiconductor is formed by adding magnesium (Mg). Note that the n-type impurities and p-type impurities are not limited to these.

[0090] First, a substrate 12 made of n-type GaN with a first main surface 12a being a (0001) plane, i.e., a c-plane, is prepared. As shown in FIG. 3A, an n-type GaN film 13 doped with Si as an n-type impurity, an undoped Al 0.2 Ga 0.8 The undoped AlGaN film 15 is made of N, the p-type GaN film 17 is doped with Mg as a p-type impurity, the undoped GaN film 19 is made of N, and the p-type GaN film 17 is made of N. 0.2 Ga 0.8 An undoped AlGaN film 21 made of N is formed in this order. The n-type GaN film 13, the undoped AlGaN film 15, the p-type GaN film 17, the undoped GaN film 19, and the undoped AlGaN film 21 are patterned into predetermined shapes to become the drift layer 14, the first underlayer 16, the second underlayer 18, the third underlayer 20, and the fourth underlayer 22 shown in FIG.

[0091] The thickness and carrier concentration of each layer are, for example, as follows: n-type GaN film 13 has a thickness of 8 μm and a carrier concentration of 1×10 16 cm -3 The undoped AlGaN film 15 has a thickness of 20 nm. The p-type GaN film 17 has a thickness of 400 nm and a carrier concentration of 1×10 17 cm -3The undoped GaN film 19 has a thickness of 200 nm. The undoped AlGaN film 21 has a thickness of 20 nm. Note that these values ​​are merely examples.

[0092] 3B, a resist is applied onto the undoped AlGaN film 21, and the applied resist is patterned by photolithography to form a resist mask 90. ​​The resist mask 90 is a mask for forming the gate opening 24, and has an opening 91 corresponding to the shape of the gate opening 24 in a plan view.

[0093] Next, as shown in FIG. 3C, a gate opening 24 is formed by dry etching. The gate opening 24 penetrates the undoped AlGaN film 21, the undoped GaN film 19, the p-type GaN film 17, and the undoped AlGaN film 15, and the n-type GaN film 13 is exposed. At this time, the bottom 24a of the gate opening 24 is parallel to the first main surface 12a of the substrate 12. The sidewall 24b of the gate opening 24 is inclined at a predetermined inclination angle with respect to the bottom 24a. The inclination angle is, for example, in the range of 20° to 80°. This allows a regrown layer to be formed on the sidewall 24b with a uniform thickness, thereby suppressing the narrowing of the channel and suppressing both a decrease in carrier concentration and an increase in on-resistance.

[0094] Next, after removing the resist mask 90, as shown in Fig. 3D, an undoped GaN film 27, an undoped AlN film (not shown), and an undoped AlGaN film 29 are deposited in this order by MOVPE over the entire surface along the shape of the gate opening 24. The undoped GaN film 27 and the undoped AlGaN film 29 are patterned into predetermined shapes to become an electron transit layer 28 and an electron supply layer 30, respectively.

[0095] The thickness of each layer is approximately uniform, for example, as follows: the undoped GaN film 27 is 100 nm thick; the undoped AlN film is 1 nm thick; and the undoped AlGaN film 29 is 50 nm thick. Note that these values ​​are merely examples.

[0096] Next, a gate metal film made of Pd is formed by evaporation or sputtering, etc., so as to cover the gate opening 24. As shown in FIG. 3E, the formed gate metal film is patterned to form a gate electrode 32.

[0097] 3F, a source opening 34 is formed at a position away from the gate electrode 32, penetrating the undoped AlGaN film 29, the undoped AlN film (not shown), the undoped GaN film 27, the undoped AlGaN film 21, and the undoped GaN film 19 to reach the p-type GaN film 17. The source opening 34 is formed by photolithography and dry etching, similar to the gate opening 24. The undoped AlGaN film 29, the undoped GaN film 27, the undoped AlGaN film 21, the undoped GaN film 19, and the p-type GaN film 17 are patterned, respectively, to form the electron supply layer 30, the electron transit layer 28, the fourth underlayer 22, the third underlayer 20, and the second underlayer 18.

[0098] Next, a source metal film made of Ti and Au is deposited by deposition or sputtering so as to fill the source opening 34, and is patterned to form a source electrode 36. Furthermore, a drain metal film made of Ti and Al is deposited by deposition or sputtering on the second main surface 12b of the substrate 12, and is patterned as necessary to form a drain electrode 38.

[0099] Through the above steps, the nitride semiconductor device 10 shown in FIG. 2 is formed.

[0100] After the gate electrode 32 and the source electrode 36 are formed, an insulating film is formed, and contact holes that expose a part of each of the source electrodes 36 and a part of the gate electrode 32 are formed in the formed insulating film. Thereafter, a metal film is formed and patterned to form the gate electrode pad 40 and the source electrode pad 42.

[0101] [Variations] Here, a modification of the nitride semiconductor device 10 according to the present embodiment will be described.

[0102] [Variation 1] Fig. 4 is a cross-sectional view of a nitride semiconductor device 110 according to Modification 1. As shown in Fig. 4, the nitride semiconductor device 110 differs from the nitride semiconductor device 10 shown in Fig. 2 in that it additionally includes a high-resistance layer 126. The following description will focus on the differences from the embodiment, and description of commonalities will be omitted or simplified.

[0103] The high resistance layer 126 is provided between the second underlayer 18 and the electron transit layer 28 in the gate opening 24. In this modification, the high resistance layer 126 is also provided between the first underlayer 16 and the electron transit layer 28. Specifically, the high resistance layer 126 is provided from the sidewall 24b to a part of the bottom 24a of the gate opening 24. More specifically, the high resistance layer 126 is provided so as to cover the entire surface of the sidewall 24b from the upper end of the gate opening 24, i.e., from a part of the upper surface of the fourth underlayer 22 to a part of the bottom 24a. In other words, the high resistance layer 126 is provided between each of the first underlayer 16, the second underlayer 18, the third underlayer 20, and the fourth underlayer 22 and the electron transit layer 28.

[0104] 4, for example, the upper surface of the upper end of the high resistance layer 126 is flush with the upper surface of the fourth underlayer 22. Also, the upper surface of the lower end of the high resistance layer 126 is flush with a portion of the upper surface of the drift layer 14 that forms the bottom 24a. The high resistance layer 126 is formed so as to be embedded in each of the surface layer portion and end surface portion of the fourth underlayer 22, the end surface portion of the third underlayer 20, the end surface portion of the second underlayer 18, the end surface portion of the first underlayer 16, and the surface layer portion of the drift layer 14.

[0105] The high resistance layer 126 has a higher resistance than the second under layer 18. In this modification, the high resistance layer 126 has a higher resistance than the third under layer 20.

[0106] The high resistance layer 126 is made of a nitride semiconductor. In this modification, the high resistance layer 126 contains iron (Fe). The high resistance layer 126 is made of, for example, GaN doped with iron to have a high resistance. The thickness of the high resistance layer 126 is, for example, 50 nm.

[0107] A method for manufacturing the nitride semiconductor device 110 according to this modification will now be described with reference to Figures 5A and 5B. Figures 5A and 5B are cross-sectional views illustrating the method for manufacturing the nitride semiconductor device 110 according to this modification.

[0108] The manufacturing method of the nitride semiconductor device 110 according to this modification is similar to that of the nitride semiconductor device 10 according to the first embodiment in the steps up to the formation of the gate opening 24. After the gate opening 24 shown in FIG. 3C is formed, the resist mask 90 is removed. Then, a resist is again applied onto the undoped AlGaN film 21 and within the gate opening 24. As shown in FIG. 5A, the applied resist is patterned by photolithography to form a resist mask 192.

[0109] The resist mask 192 is a mask for forming the high-resistance layer 126. The resist mask 192 has an opening 193 larger than the sidewall 24b of the gate opening 24. The opening 193 is provided from the upper end of the sidewall 24b to a part of the upper surface of the undoped AlGaN film 21 to a part of the bottom 24a, and exposes at least the entire sidewall 24b in a plan view.

[0110] Next, iron ions are implanted into the portions exposed through the openings 193 of the resist mask 192 to form a high-resistance layer 126, as shown in FIG. 5B. The high-resistance layer 126 is a layer in which iron is doped into the portions exposed through the openings 193 of the undoped AlGaN film 21, the undoped GaN film 19, the p-type GaN film 17, the undoped AlGaN film 15, and the n-type GaN film 13. The portion of the n-type GaN film 13 excluding the high-resistance layer 126 becomes the drift layer 14.

[0111] The ion implantation conditions are, for example, an acceleration energy of 40 keV and a dose of 1×10 14 cm -2 This forms a high resistance layer 126 with a thickness of about 50 nm. The region where the iron ions are implanted, i.e., the high resistance layer 126, has its crystal structure destroyed and becomes amorphous, so that it becomes highly resistive.

[0112] In this case, instead of iron ions, ions of metals with a large atomic number, such as titanium ions, chromium ions, copper ions, or nickel ions, may be used, which can suppress recrystallization of the high resistance layer 126 due to a heat treatment in a later step, and increase the resistance value of the high resistance layer 126.

[0113] The process steps after forming the high-resistance layer 126 are the same as those of the nitride semiconductor device 10 according to the first embodiment. Specifically, after forming the high-resistance layer 126, an undoped GaN film 27, an undoped AlN film (not shown), and an undoped AlGaN film 29 are formed by regrowth in this order, as shown in Fig. 3D. Since the high-resistance layer 126 is made of a nitride semiconductor, the film quality is improved by the regrowth of the undoped GaN film 27, the undoped AlN film (not shown), and the undoped AlGaN film 29.

[0114] As described above, in this modification, the high-resistance layer 126 is provided between the electron transit layer 28 and the second underlayer 18, so that it is possible to suppress the leakage current from the source electrode 36 through the second underlayer 18 and the electron transit layer 28 to the gate electrode 32. In this manner, this modification realizes a nitride semiconductor device 110 in which the leakage current is suppressed.

[0115] The resist mask 192 may be formed such that the opening 193 exposes only the p-type GaN film 17 at the sidewall portion 24b. That is, the shape of the opening 193 in plan view may coincide with the boundary between the p-type GaN film 17 and the undoped GaN film 19 and the boundary between the p-type GaN film 17 and the undoped AlGaN film 15. Alternatively, the resist mask 192 may be formed such that the opening 193 exposes the entire p-type GaN film 17 and the entire undoped AlGaN film 15 at the sidewall portion 24b. By exposing the entire p-type GaN film 17 at the sidewall portion 24b through the opening 193, the high resistance layer 126 can be formed to reliably cover the portion of the p-type GaN film 17 exposed at the sidewall portion 24b.

[0116] [Variation 2] Fig. 6 is a cross-sectional view of a nitride semiconductor device 210 according to Modification 2. As shown in Fig. 6, the nitride semiconductor device 210 differs from the nitride semiconductor device 10 shown in Fig. 2 in that it includes a threshold control layer 248. The following description will focus on the differences from the first embodiment, and description of commonalities will be omitted or simplified.

[0117] The threshold control layer 248 is an example of a second conductivity type second nitride semiconductor layer provided between the gate electrode 32 and the electron transit layer 28. The threshold control layer 248 is provided on the electron supply layer 30 and is in contact with the electron supply layer 30 and the gate electrode 32.

[0118] In this modification, when the substrate 12 is viewed in plan, an end of the threshold control layer 248 is located closer to the source electrode 36 than an end of the gate electrode 32. The threshold control layer 248 and the source electrode 36 are spaced apart from each other and are not in contact with each other.

[0119] The threshold control layer 248 has a thickness of, for example, 100 nm and a carrier concentration of 1×10 17 cm -3 p-type Al 0.2 Ga 0.8It is a nitride semiconductor layer made of N. The threshold control layer 248 is formed by depositing the undoped AlGaN film 29 that forms the electron supply layer 30 by MOVPE method, and then patterning the film.

[0120] According to this modification, the potential of the conduction band edge of the channel portion is raised by the threshold control layer 248. This makes it possible to increase the threshold voltage of the nitride semiconductor device 210. As a result, the nitride semiconductor device 210 can be realized as a normally-off type FET.

[0121] The threshold control layer 248 may be formed using an insulating material, that is, the threshold control layer 248 may be an insulating layer.

[0122] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, the first electron transit layer has a two-layer structure, which is different from embodiment 1. The following description will focus on the differences from embodiment 1, and descriptions of commonalities will be omitted or simplified.

[0123] Fig. 7 is a cross-sectional view of a nitride semiconductor device 310 according to this embodiment. As shown in Fig. 7, the nitride semiconductor device 310 differs from the nitride semiconductor device 10 shown in Fig. 2 in that it includes an electron transit layer 314 instead of the drift layer 14.

[0124] The electron transit layer 314 is an example of a first electron transit layer. The electron transit layer 314 includes a drift layer 314a and an undoped nitride semiconductor layer 314b.

[0125] The drift layer 314a is an example of a third nitride semiconductor layer of the first conductivity type, and is substantially the same as the drift layer 14 according to the first embodiment. In the present embodiment, the drift layer 314a is different only in that the gate opening 24 does not reach the drift layer 314a. Therefore, the upper surface of the drift layer 314a is flat.

[0126] The undoped nitride semiconductor layer 314b is an example of an undoped fourth nitride semiconductor layer located between the drift layer 314a and the first underlayer 16. Specifically, the undoped nitride semiconductor layer 314b is a film made of undoped GaN. The thickness of the undoped nitride semiconductor layer 314b is, for example, 200 nm, but is not limited to this.

[0127] The undoped nitride semiconductor layer 314b is in contact with the first underlayer 16, and forms an AlGaN / GaN heterointerface with the first underlayer 16. As a result, a two-dimensional electron gas 46 is generated in the undoped nitride semiconductor layer 314b.

[0128] The drift layer 314a and the undoped nitride semiconductor layer 314b are formed, for example, by the following method. Specifically, in the manufacturing process shown in FIG. 3A, after the n-type GaN film 13 is formed, an undoped GaN film is formed before the undoped AlGaN film 15 is formed. Then, in the manufacturing process shown in FIG. 3C, a gate opening 24 is formed so as to expose the undoped GaN film. Therefore, in this embodiment, the bottom 24a of the gate opening 24 becomes the upper surface of the undoped nitride semiconductor layer 314b.

[0129] According to the present embodiment, the two-dimensional electron gas 46 formed in the undoped nitride semiconductor layer 314b spreads electrons laterally. Therefore, similar to the first embodiment, the source-drain current is easily diffused in a wide region in the drift layer 314a. In addition, the undoped nitride semiconductor layer 314b has a small amount of impurities, so that the electron mobility can be increased. Thus, the nitride semiconductor device 310 can operate at a high speed.

[0130] (Embodiment 3) Next, a description will be given of embodiment 3. In embodiment 3, the first electron transit layer has a two-layer structure and does not include a first electron supply layer, which is different from embodiment 1. The following description will focus on the differences from embodiment 1, and descriptions of commonalities will be omitted or simplified.

[0131] Fig. 8 is a cross-sectional view of a nitride semiconductor device 410 according to this embodiment. As shown in Fig. 8, the nitride semiconductor device 410 differs from the nitride semiconductor device 10 shown in Fig. 2 in that it includes an electron transit layer 414 instead of the drift layer 14. In addition, the nitride semiconductor device 410 does not include the first underlayer 16.

[0132] The electron transit layer 414 is an example of a first electron transit layer. The electron transit layer 414 includes a low concentration layer 414a and a high concentration layer 414b.

[0133] The low-concentration layer 414a is an example of a third nitride semiconductor layer of the first conductivity type, and is substantially the same as the drift layer 14 according to the first embodiment. In the present embodiment, the only difference is that the gate opening 24 does not reach the low-concentration layer 414a. Therefore, the upper surface of the low-concentration layer 414a is flat.

[0134] The high concentration layer 414b is an example of a fourth nitride semiconductor layer located between the low concentration layer 414a and the second underlayer 18 and has a higher impurity concentration than the low concentration layer 414a. Specifically, the high concentration layer 414b is a film made of n-type GaN having a higher concentration of n-type impurities than the low concentration layer 414a. The carrier concentration of the high concentration layer 414b is, for example, 1×10 18 cm -3 The above is an example, but is not limited to this. The thickness of the high concentration layer 414b is smaller than that of the low concentration layer 414a, for example, less than 1 μm, but is not limited to this. By making the low concentration layer 414a thicker than the high concentration layer 414b, the breakdown voltage of the nitride semiconductor device can be increased.

[0135] The high-concentration layer 414b is in contact with the second underlayer 18. In this embodiment, the band gap difference between the low-concentration layer 414a, the high-concentration layer 414b, and the second underlayer 18 is small, and no heterointerface is formed. For this reason, the two-dimensional electron gas 46 shown in FIG. 2 and the like is not generated.

[0136] Although the two-dimensional electron gas 46 is not generated, the high-concentration layer 414b has a high concentration of n-type impurities and therefore has a low resistance. Therefore, electrons spread laterally in the high-concentration layer 414b. Therefore, similar to the first embodiment, the source-drain current is easily diffused in a wide region in the high-concentration layer 414b and the low-concentration layer 414a.

[0137] The low concentration layer 414a and the high concentration layer 414b are formed, for example, by the following method. Specifically, in the manufacturing process shown in Fig. 3A, after the n-type GaN film 13 is formed, an n-type GaN film having a higher impurity concentration than the n-type GaN film 13 is formed before the undoped AlGaN film 15 is formed. Then, in the manufacturing process shown in Fig. 3C, a gate opening 24 is formed so as to expose the n-type GaN film having a higher impurity concentration. Therefore, in this embodiment, the bottom 24a of the gate opening 24 becomes the upper surface of the high concentration layer 414b.

[0138] According to the present embodiment, the resistance of the high concentration layer 414b is small, so that electrons tend to spread laterally. Therefore, as in the first embodiment, the source-drain current tends to spread over a wide region in the electron transit layer 414. This makes it possible to further reduce the resistance value during operation.

[0139] (Other embodiments) Although the nitride semiconductor device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceivable by a person skilled in the art to the present embodiment and forms constructed by combining components in different embodiments are also included in the scope of the present disclosure.

[0140] For example, in each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type.

[0141] Furthermore, for example, the high-resistance layer 126 may be provided only between the electron transit layer 28 and the second underlayer 18. For example, the high-resistance layer 126 may be provided only on a part of the sidewall portion 24b of the gate opening 24, and may not cover the end faces of the first underlayer 16, the third underlayer 20, and the fourth underlayer 22.

[0142] Furthermore, for example, in a plan view, an end of the gate electrode 32 may coincide with an end of the gate opening 24. Alternatively, in a plan view, the gate electrode 32 may be provided inside the gate opening 24.

[0143] In addition, for example, in the above embodiment, the source opening 34 is provided so as to reach the second underlayer 18, but this is not limiting. For example, the source opening 34 may be an opening that reaches the electron transit layer 28, and the source electrode 36 may be connected to the electron transit layer 28 and not connected to the second underlayer 18.

[0144] For example, the drift layer 14, which is an example of a first electron transport layer, may have the same composition as the electron transport layer 28, which is an example of a second electron transport layer. Alternatively, the carbon concentration of the drift layer 14 may be higher than the carbon concentration of the electron transport layer 28. For example, the carbon concentration of the drift layer 14 may be 10 18 cm -3 The carbon concentration of the electron transport layer 28 is on the order of 10 16 cm -3 By increasing the carbon concentration in the drift layer 14, the breakdown voltage of the nitride semiconductor device 10 can be increased.

[0145] Furthermore, the carbon concentration does not have to be uniform within the drift layer 14. For example, the carbon concentration may be low in the surface portion of the drift layer 14, i.e., in the vicinity of the interface with the first underlayer 16. This can promote the generation of two-dimensional electron gas 46 and increase channel mobility, making it easier to diffuse the current.

[0146] Furthermore, for example, the planar layout of the nitride semiconductor device is not limited to the example shown in Fig. 1. For example, the source electrode 36 may have a rectangular shape extending in one direction in a plan view. A plurality of source electrodes 36 may be arranged in the short side direction. In this case, the short side direction corresponds to the direction along the line II-II.

[0147] Furthermore, each of the above embodiments can be modified, substituted, added, omitted, and the like in various ways within the scope of the claims or their equivalents. [Industrial Applicability]

[0148] The present disclosure can be used as a nitride semiconductor device with a low resistance value, for example, as a power transistor used in the power supply circuits of consumer devices such as televisions. [Explanation of symbols]

[0149] 10, 110, 210, 310, 410 Nitride semiconductor device 11 Unit Cell 12 Substrate 12a First main surface 12b Second main surface 13 n-type GaN film 14, 314a Drift layer 15, 21, 29 Undoped AlGaN films 16 First Undercoat Layer 17 p-type GaN film 18 Second Undercoat Layer 19, 27 Undoped GaN film 20 The third base layer 22 The fourth base layer 24 Gate opening 24a, 34a bottom 24b, 34b side wall part 28, 314, 414 Electron transport layer 30 Electron supply layer 32 Gate electrode 34 Source opening 36 Source electrode 38 Drain electrode 40 Gate electrode pad 42 Source electrode pad 44, 46 Two-dimensional electron gas 90, 192 Resist mask 91, 193 aperture 126 High resistance layer 248 Threshold Control Layer 314b Undoped nitride semiconductor layer 414a Low concentration layer 414b High concentration layer

Claims

1. a substrate having a first major surface and a second major surface opposite the first major surface; a first electron transit layer having a first conductivity type provided above the first main surface; a first electron supply layer provided above the first electron transit layer; a first nitride semiconductor layer having a second conductivity type different from the first conductivity type, the first nitride semiconductor layer being provided above the first electron supply layer; a second electron transit layer provided in an upper portion of the first nitride semiconductor layer and along an inner surface of a first opening that penetrates the first electron supply layer and the first nitride semiconductor layer and reaches the first electron transit layer; a second electron supply layer provided above the second electron transit layer and covering the first opening. Nitride semiconductor devices.

2. The semiconductor device further includes a high-resistance layer, which is made of a nitride semiconductor and has a higher resistance than the first nitride semiconductor layer, and is provided between the first nitride semiconductor layer and the second electron transport layer along an inner surface of the first opening. The nitride semiconductor device according to claim 1 .

3. The high resistance layer contains iron. The nitride semiconductor device according to claim 2 .

4. The high resistance layer is provided along an inner surface of the first opening between the first electron supply layer and the second electron transit layer. The nitride semiconductor device according to claim 2 or 3.

5. a gate electrode provided above the second electron supply layer and covering the first opening; a second nitride semiconductor layer having the second conductivity type provided between the gate electrode and the second electron supply layer. The nitride semiconductor device according to any one of claims 1 to 4.

6. a source electrode connected to the first nitride semiconductor layer and the second electron transit layer; When the substrate is viewed from above, an end of the gate electrode is located closer to the source electrode than an end of the first opening. The nitride semiconductor device according to claim 5 .

7. a second opening portion is provided at a position away from the gate electrode, the second opening portion penetrating the second electron transit layer and reaching the first nitride semiconductor layer; At least a portion of the source electrode is provided within the second opening.

7. The nitride semiconductor device according to claim 5 or 6.

8. The first electron transport layer comprises: a third nitride semiconductor layer of the first conductivity type; and an undoped fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first electron supply layer. The nitride semiconductor device according to any one of claims 1 to 7.

9. a substrate having a first major surface and a second major surface opposite the first major surface; a first electron transit layer having a first conductivity type provided above the first main surface; a first nitride semiconductor layer having a second conductivity type different from the first conductivity type, the first nitride semiconductor layer being provided above the first electron transport layer; a second electron transport layer provided in an upper portion of the first nitride semiconductor layer and along an inner surface of a first opening that penetrates the first nitride semiconductor layer and reaches the first electron transport layer; an electron supply layer provided above the second electron transit layer and covering the first opening; Equipped with The first electron transport layer comprises: a third nitride semiconductor layer of the first conductivity type; a fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first nitride semiconductor layer and having a higher impurity concentration than the third nitride semiconductor layer. Nitride semiconductor devices.

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