Transistor

Abstract

To provide a new metal oxide.SOLUTION: A metal oxide is provided, having a plurality of energy gaps. The metal oxide has a first region having a high energy level at low end of a conduction band and a second region having a lower energy level at the low end of the conduction band than that of the first region. The second region has more carriers than that of the first region. Difference between conduction band at the low end of the first region and that of the second region is 0.2 eV or more. An energy gap of the first region is 3.3 eV or more and 4.0 eV or less. The energy gap of the second region is 2.2 eV or more and 2.9 eV or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a metal oxide.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. In particular, one aspect of the present invention relates to a metal oxide or a method for producing the metal oxide. Another embodiment of the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, The present invention relates to a device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] Oxides are attracting attention as semiconductor materials that can be used in transistors. For example, In Reference 1, In-Zn-Ga-O oxides, In-Zn-Ga-Mg-O oxides, and I n-Zn-O oxide, In-Sn-O oxide, In-O oxide, In-Ga-O oxide The present invention relates to a method for manufacturing a semiconductor device having an amorphous oxide, which is either an oxide of a Zn-In-Zn-O system or an oxide of a Sn-In-Zn-O system. A field effect transistor is disclosed.

[0005] In addition, Non-Patent Document 1 describes a transistor using an In-Zn-O oxide and A structure with a two-layered metal oxide with In-Ga-Zn-O oxide is being considered. . [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5118810 [Non-patent literature]

[0007] [Non-Patent Document 1] John F. Wager, "Oxide TFTs: A Progress Report", Information Display 1 / 16, SID 2016, Jan / Feb 2016, Vol.32,No.1, p.16-21 Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Document 1, In-Zn-Ga-O oxide and In-Zn-Ga-Mg-O oxide are In-Zn-O oxides, In-Sn-O oxides, In-O oxides, In-Ga Amorphous oxides that are either Sn-In-Zn-O-based oxides or Sn-In-Zn-O-based oxides. In other words, the active layer of the transistor is The active layer of the transistor has an amorphous oxide of any one of the above oxides. When the transistor is made of any one of the above amorphous oxides, one of the electrical characteristics Alternatively, the active layer of the transistor may have a problem of being low in the above-mentioned non- If the material is made of either one of the amorphous oxides, the reliability of the transistor will be poor. There is a problem.

[0009] In addition, in Non-Patent Document 1, in a channel-protected bottom-gate transistor, The active layer of the transistor is a two-layer stack of In-Zn oxide and In-Ga-Zn oxide. The In-Zn oxide layer, which forms the channel, is 10 nm thick, resulting in a high current. Field effect mobility (μ=62 cm 2 V -1 s -1 On the other hand, transistor characteristics The S value (also called Subthreshold Swing, SS), which is one of the characteristics, is 0.4 1V / decade. In addition, the threshold voltage (V th) is -2.9V, which is the so-called normally-on transistor characteristic.

[0010] In view of the above problems, an object of one embodiment of the present invention is to provide a novel metal oxide. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. It is an object of the present invention to provide a semiconductor device having a novel structure. One of the objectives of the project is to provide a place where

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a metal oxide having multiple energy gaps, The material is divided into a first region with a higher energy level at the conduction band minimum and a second region with a lower energy level at the conduction band minimum than the first region. and a second region having a lower energy level, the second region having a higher carrier density than the first region. The difference in the energy level of the conduction band minimum between the first region and the second region is 0.2 eV or less. The energy gap of the first region is 3.3 eV or more and 4.0 eV or less, and the second region is The energy gap of region 2 is 2.2 eV or more and 2.9 eV or less.

[0013] Another embodiment of the present invention is a metal oxide having a plurality of energy gaps, Metal oxides are divided into a first region with a higher energy level at the bottom of the conduction band and a second region with a lower energy level than the first region. and a second region having a lower energy level at the bottom end, the first region being made of M (M is Al, G a) At least two selected from Si, Mg, Zr, Be, and B) oxide, M nitride The first region has an In oxide or an In-Zn oxide. It has a compound.

[0014] In addition, one embodiment of the present invention is a semiconductor device including a first region having a first energy gap and a second region having a second energy gap. a metal oxide including a second region having an energy gap, the first region being The first region has a higher energy level at the bottom of the conduction band than the first oxide of the first metal element. the second region comprises a second oxide of a second metallic element, the first oxide being an energy In order to increase the gap, a third element different from the first metal element is included, and the second If the region includes a third element, the concentration of the third element in the first region is higher than the concentration of the third element in

[0015] In the above embodiment, the first metal element is Ga, the second metal element is In, and the third metal element is Ga. The element includes at least two selected from Al, Si, Mg, Zr, Be, and B. preferable.

[0016] In the above embodiment, the first region further comprises In and Zn, and the second region further comprises Zn. This is preferable.

[0017] Another embodiment of the present invention is a semiconductor device comprising the above metal oxide, a gate electrode, a source electrode, and a drain electrode. and an electrode. Effect of the Invention

[0018] According to one embodiment of the present invention, a novel metal oxide can be provided. According to one embodiment, a semiconductor device can have good electrical characteristics. It is possible to provide a semiconductor device having a high performance. Alternatively, a display device having a novel configuration can be provided.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a conceptual diagram illustrating a structure of a metal oxide. [Diagram 2] 1A and 1B are schematic diagrams illustrating a transistor and distribution of energy levels in the transistor; [Diagram 3] FIG. 1 illustrates a band diagram model of a transistor. [Figure 4] FIG. 1 illustrates a band diagram model of a transistor. [Diagram 5] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 8] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] 1A to 1C are a top view, a cross-sectional view, and a conceptual cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 16] FIG. 2 is a diagram for explaining a band structure. [Figure 17] 1A and 1B are diagrams illustrating an example of the configuration of a display panel. [Figure 18] 1A and 1B are diagrams illustrating an example of the configuration of a display panel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the present invention in various forms without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0023] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0024] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0025] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0026] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0027] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect" In this case, "something that has some electrical effect" includes a case where the device is connected via the "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0028] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. The silicon nitride oxide film is a film that contains more nitrogen than oxygen. This represents a film with a high content of

[0029] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, The reference numerals may be commonly used among different drawings.

[0030] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that the two straight lines are arranged at an angle of -30° to 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0031] In this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0032] Even if a material is described as a "semiconductor," it may be considered an "insulator" if, for example, its electrical conductivity is sufficiently low. In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. In some cases, the distinction cannot be made precisely. Therefore, the term "semiconductor" as used herein means "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." In some cases, this can be rephrased as "body."

[0033] In this specification, normally-on means that no potential is applied from the power supply (0 V For example, the normally-on characteristic of a transistor is When the voltage applied to the gate is 0V, the threshold voltage becomes negative. There is.

[0034] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplifying and rectifying properties. and switching action, the metal oxide is Metal oxide semiconductor, abbreviated as OS. In addition, when describing OS FET, it is possible to use a metal oxide or an oxide semiconductor. In other words, it is a transistor having a conductor.

[0035] In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0036] (Embodiment 1) In this embodiment, a metal oxide which is one embodiment of the present invention will be described.

[0037] The metal oxide according to one embodiment of the present invention preferably contains at least In. In addition to In and Zn, the metal oxide of one embodiment of the present invention preferably contains The element M (the element M is at least one selected from Al, Ga, Si, Mg, Zr, Be, and B) In particular, the element M may be selected from Al, Ga, and Si. As the element M, Al and Ga, Al and S are preferable. A combination of i or Ga and Si is preferred.

[0038] Examples of the metal oxide of one embodiment of the present invention include In-Al-Ga-Zn oxide, In -Al-Si-Zn oxide, In-Ga-Si-Zn oxide, etc.

[0039] Note that the metal oxide of one embodiment of the present invention includes a plurality of components.

[0040] A metal oxide according to one embodiment of the present invention has a first region and a second region, M (M is at least two selected from Al, Ga, Si, Mg, Zr, Be, and B) The second region has In oxide, I n-Zn oxide. The conduction band minimum energy level is at least 0.2 eV higher than the conduction band minimum energy level in the region It is preferable that the metal oxide having the energy level of .

[0041] In addition, among the M oxides, Al and Si may be replaced with nitrides. Alternatively, the M oxide may be replaced with aluminum nitride or silicon nitride.

[0042] The metal oxide according to one embodiment of the present invention is composed of a plurality of components, and therefore has a plurality of energy More specifically, the metal oxide of one embodiment of the present invention has a plurality of conduction band minimums. In some cases, multiple components can be referred to as multiple regions. Good too.

[0043] In this specification, the energy gap is the energy gap at the top of the valence band in the band structure. The energy difference between the energy level at the bottom of the conduction band (Ev edge) and the energy level at the bottom of the conduction band (Ec edge) is This can also be called the band gap.

[0044] The metal oxide according to one embodiment of the present invention has a first region having a high Ec edge and a second region having a lower Ec edge than the first region. and a second region having a lower charge, the second region having more carriers than the first region, The difference in Ec edge between the first region and the second region is 0.2 eV or more. The energy gap of the second region is 3.3 eV or more and 4.0 eV or less. The energy gap is between 2.2 eV and 2.9 eV.

[0045] Here, the structure of the metal oxide having In, element M, and Zn will be described with reference to FIG. Do the following.

[0046] <Metal oxide composition> FIG. 1 illustrates a Cloud-Aligned Composer (CAC) system according to an embodiment of the present invention. It is a conceptual diagram of a metal oxide having a tetrahydrofuran (tetrahydrofuran) structure. When the metal oxide has a semiconductor function, the metal oxide is called a cloud-aligned (CAC) metal oxide. ed Composite)-OS (Oxide Semiconductor) do.

[0047] CAC-OS is a matrix composite. or metal matrix composite. In some cases.

[0048] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are unevenly distributed, as shown in Figure 1. By this, regions 001 and 002, each of which is mainly composed of each element, are formed, and each region is mixed. In other words, the elements that make up the metal oxide are 0.5 nm or more apart. 0 nm or less, preferably 1 nm to 2 nm or less, or materials distributed unevenly in the vicinity of the size. In the following, the metal oxide is one of the components of the material. The region containing the element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm or less. A mixed state with a size of 2 nm or less or close to that size is called a mosaic or patch state. Also called.

[0049] For example, an In-M-Zn oxide having a CAC structure is an In oxide (hereinafter, InO X 1 (X1 is a real number greater than 0).) or In-Zn oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are all real numbers greater than 0.) and In-M-Zn oxide (hereafter referred to as In W3 M X3 Zinc Y3 O Z3 (W3, X3, Y3, and Z3 are real numbers greater than 0. The materials are divided into M oxides, etc. By separating the layers, a mosaic pattern is formed. X1 Or In X2 Zinc Y2 O Z2 , In W3 M X3 Zinc Y3 O Z3 , M oxide, etc. are distributed in the film (hereinafter referred to as "Crown It is also called dome-shaped.

[0050] In other words, the metal oxide of one embodiment of the present invention is an In oxide, an In-Zn oxide, an In- Selected from M oxide, M oxide, In-M-Zn oxide, or M-Zn oxide; It has at least two or more oxides or components.

[0051] For example, when the element M is Al and Ga, the metal oxide of one embodiment of the present invention is a Ga oxide. oxide, In oxide, In-Zn oxide, Ga-Al oxide, In-Ga oxide, In-G a-Zn oxide, Ga-Zn oxide, Al oxide, In-Al oxide, In-Al-Ga In particular, the present invention provides a gold oxide having at least two of the above-mentioned metal oxides. The metal oxides are a combination of the above oxides, an oxide containing Al, and an oxide containing Zn, e.g. For example, In-Al-Zn oxide or In-Al-Ga-Zn oxide may be used.

[0052] When the element M is Si and Ga, the metal oxide of one embodiment of the present invention is Ga oxide. In oxide, In-Zn oxide, Ga-Si oxide, In-Ga oxide, In-Ga -Zn oxide, Ga-Zn oxide, Si oxide, In-Si oxide, In-Si-Ga- In particular, the metal of one embodiment of the present invention is selected from the group consisting of Zn oxide and Zn oxide. The oxide may be a combination of the above oxides, an oxide containing Si, and an oxide containing Zn, for example. , In-Si-Zn oxide, or In-Si-Ga-Zn oxide.

[0053] That is, the metal oxide of one embodiment of the present invention is a composite having multiple materials or multiple components. It can also be called a material or a composite material.

[0054] Here, let us assume that the concept shown in FIG. 1 is an In-M-Zn oxide having a CAC structure. In this case, the region 001 is a region mainly composed of an oxide containing element M, and the region 002 is a region mainly composed of an oxide containing element M. InO X1 Or InX2 Zinc Y2 O Z2 It can be said that this is a region whose main component is In the case of area 001 and area 002, the peripheral areas are unclear (blurred), so In some cases, a clear boundary may not be observed.

[0055] In other words, the In-M-Zn oxide with the CAC structure is mainly composed of oxides containing element M. In a certain area, InO X1 Or In X2 Zinc Y2 O Z2 The area where the main component is mixed with Therefore, metal oxides are sometimes referred to as composite metal oxides.

[0056] In addition, in the In-M-Zn oxide having the CAC structure, the region 001 and the region 00 The crystal structure of region 001 and region 002 are not particularly limited. Each may have a different crystal structure.

[0057] For example, In-M-Zn oxide having a CAC structure is an oxide semiconductor having a non-single crystal structure. It is preferable that the material is a conductor. Non-single crystal refers to amorphous and polycrystalline materials other than single crystals. Examples of non-single crystal structures include CAAC-OS, polycrystalline oxide semiconductors, and nc-O S(nanocrystalline oxide semiconductor), pseudo Amorphous-like oxide semiconductor (a-like OS) e semiconductor and amorphous oxide semiconductor.

[0058] The CAAC-OS has a CAAC structure. The oxide has a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion is caused by the misalignment of the lattice arrangement in the area where multiple nanocrystals are connected. The area where the orientation of the lattice array changes between the area where the lattice array is aligned and the area where the lattice array is aligned is called the area where the orientation of the lattice array changes. Point.

[0059] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. Therefore, in the CAAC-OS, clear grain boundaries (grain boundaries) are observed even in the vicinity of the strain. It is not possible to confirm the presence of undulations (also called undulations). This is because the CAAC-OS is aligned in the ab-plane direction. In the case of the ferroelectric material, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is believed to be because the distortion can be tolerated by changing the

[0060] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0061] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. A-like OS has voids or low density areas. e OS has an unstable structure compared to nc-OS and CAAC-OS.

[0062] For example, the CAC-OS preferably has a CAAC structure. It may be formed in a range including area 001 or area 002. In other words, CAC-OS In this case, the region that becomes the CAAC-OS is formed in a range of several nm to several tens of nm.

[0063] CAAC-OS is a highly crystalline oxide semiconductor. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries occurs. Therefore, when a metal oxide has CAAC-OS, it is difficult to obtain a metal oxide. As a result, the physical properties of all the metal oxides are stable, making it possible to provide highly reliable metal oxides that are resistant to heat. Cut.

[0064] Here, when the metal oxide according to one embodiment of the present invention is an In-Al-Ga-Zn oxide, I will explain about InO X1 Or In X2 Zinc Y2 O Z2 And, In W3 Al X3 Zinc Y 3O Z3 Or In a Al b Ga c Zinc d O e (a, b, c, d, and e are each 0 ), the material separates into a mosaic shape.

[0065] In other words, the CAC-OS in the In-Al-Ga-Zn oxide is W3 Al X3 Z n Y3 O Z3 Or In a Al b Ga cZinc d O e The region where InO is the main component and the region where InO is the main component. X1 , Or In X2 Zinc Y2 O Z2 A composite having a structure in which the main component is a region and is mixed with It is a metal oxide. W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Z n d O e The region where InO is the main component and the region where InO is the main component. X1 Or In X2 Zinc Y2 O Z2 The main component is The area where the boundary is unclear (blurred) and no clear boundary can be observed. There is.

[0066] For example, in the conceptual diagram shown in Figure 1, area 001 is In w3 Al x3 Zinc y3 O Z3 Ma Or In a Al b Ga c Zinc d O e The region 001 corresponds to the region mainly composed of InO X 1 or In X2 Zinc Y2 O Z2 This corresponds to the region where In is the main component. w3 Al x 3Zn y3 O Z3 Or In a Al b Ga c Zinc d O e The region mainly composed of InO X1 Or In X2Zinc Y2 O Z2 The regions that are mainly composed of these are called nanoparticles. The nanoparticles may have a particle diameter of 0.5 nm or more and 10 nm or less, typically 1 nm or less. The nanoparticles are 2 nm or less in size. In addition, the peripheral areas of the nanoparticles are unclear (blurred). , a clear boundary may not be observable.

[0067] The sizes of areas 001 and 002 were measured using energy dispersive X-ray spectroscopy (ED X: Energy Dispersive X-ray spectroscopy For example, area 001 can be evaluated by EDX mapping obtained by cross-sectional imaging. In the true EDX mapping, the diameter of the area 001 is 0.5 nm or more and 10 nm or less, The size of the grains may be between 1 nm and 2 nm. As a result, the density of the main element gradually decreases. The number of elements that can be detected (hereinafter referred to as abundance) increases from the center to the periphery. In EDX mapping of cross-sectional photographs, the periphery of the region is unclear (blurred). For example, In a Al b Ga c Zinc d O e In the region where is the main component, Al atoms The number of In and Ga atoms gradually decreases from the center to the periphery, and instead, the number of In and Ga atoms increases. The increase in In and Zn atoms X2 Zinc Y2 O Z2 Step by step, the area where Therefore, in EDX mapping, In a Al b Ga c Zinc d O eis the main component The periphery of the area is observed to be unclear (blurred).

[0068] In addition, the crystal structure of the In-Al-Ga-Zn oxide having the CAC structure is not particularly limited. In addition, the regions 001 and 002 have different crystal structures. For example, an In-Al-Ga-Zn oxide having a CAC structure may be a non-single crystal. It is preferable that the oxide semiconductor have the structure.

[0069] Regarding the crystallinity of the CAC-OS in the In-Al-Ga-Zn oxide, The In-Al-Ga- When analyzing Zn oxide, a ring-shaped area of ​​high brightness appears in the electron beam diffraction pattern image. , and multiple spots may be observed within the ring-shaped bright area.

[0070] In addition, InO X1 Or In X2 Zinc Y2 O Z2 The area where is the main component (area in Figure 1) Region 002) is In W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Zinc d O e but This region has higher conductivity than the region that is the main component (region 001 in FIG. 1). Mari, InO X1 Or In X2 Zinc Y2 O Z2 The carriers flow through the area where By this, the conductivity of the oxide semiconductor is expressed. X1 Or In X2 Zinc Y2 O Z2 The region in which the main component is is distributed in a cloud-like shape in the oxide semiconductor. InO X1 Or In X2 Zinc Y2 O Z2 The region where these are the main components can be said to be a semiconductor region, which has properties close to those of a conductor.

[0071] On the other hand, In W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Zinc d O e is the main component The region where X1 Or In X2 Zinc Y2 O Z2 Compared to the area where , the region of low conductivity. W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Zinc d O e The regions where the main component is distributed in the metal oxide reduce the leakage current. This suppresses the inductance of the In and realizes good switching operation. W3 Al X3 Zinc Y3 O Z 3 or In a Al b Ga c Zinc d O e The region where the main component is a semiconductor with properties close to an insulator. It can also be said to be a conductor region. W3 Al X3 ZincY3 O Z3 The conductivity of In a Al b Ga c Zinc d O e The conductivity of In containing oxides of Al and Ga is compared with that of a A l b Ga c Zinc d O e The conductivity of the CrN film is higher.

[0072] Therefore, when the CAC-OS of In-Al-Ga-Zn oxide is used in a semiconductor device, In W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Zinc d O e Sexuality due to Quality and InO X1 Or In X2 Zinc Y2 O Z2 The properties resulting from this act in a complementary manner. This results in a high on-state current (I on ), high field-effect mobility (μ), and low off-state current Flow (I off ) can be realized.

[0073] In addition, semiconductor devices using CAC-OS based on In-Al-Ga-Zn oxide have Therefore, the CAC-OS of In-Al-Ga-Zn oxide is a display It is ideal for a variety of semiconductor devices, including RAID.

[0074] <Transistors with metal oxide> Next, the case where the above metal oxide is used as a semiconductor in a transistor will be described with reference to FIG. I will explain it below.

[0075] By using the above metal oxide as a semiconductor in a transistor, the field effect mobility can be increased. This makes it possible to realize a transistor with high reliability and switching characteristics. Therefore, a highly reliable transistor can be realized.

[0076] FIG. 2A is a schematic diagram of a transistor using the above metal oxide in a channel region. In FIG. 2A, a transistor includes a source, a drain, a first gate, and a second gate. The semiconductor device has a gate, a first gate insulating portion, a second gate insulating portion, and a channel portion. The resistance of the channel of a transistor can be controlled by applying a voltage to the gate. That is, the source and drain are connected by the potential applied to the first gate or the second gate. Controls conduction (transistor on) and non-conduction (transistor off) between the It is possible.

[0077] Here, the channel portion is made up of a region 001 having a first energy gap and a region 002 having a second energy gap. The region 002 has an energy gap, and the CAC-OS is cloud-like. The first energy gap is larger than the second energy gap. .

[0078] For example, the CAC-OS in the channel region is In-Al-Ga-Z The case where an In-Al-Ga-Zn oxide is used will be described. The In oxide is region 001, which has a higher concentration of Al or Ga than region 002. W3 Al X3 Zinc Y3 O Z3 Or In a Al b Gac Zinc d O e The area with the main component of 02 is InO, which has a higher In concentration than region 001. X1 Or In X2 Zinc Y2 O Z The material is separated into areas where In is the main component and areas where In is the mosaic-like structure. W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Zinc d O e and InO X1 Or In X2 Zinc Y2 O Z2 The In is distributed in the film (cloud-like). W3 Al X3 Zinc Y3 O Z3 Or In a Al b Ga c Zinc d O e The region 001, which is mainly composed of InO X 1 or In X2 Zinc Y2 O Z2 The area has a larger energy gap than the area 002, which is mainly composed of It also has an In W3 Al X3 Zinc Y3 O Z3 The energy gap of In a Al b Ga c Zinc d O e The energy gap of Al and Ga oxides is In containing chlorine a Al b Ga c Zinc dO e The energy gap is smaller in region 00. The energy gap of region 1 is 3.3 eV or more and 4.0 eV or less, and the energy gap of region 002 is The energy gap is 2.2 eV or more and 2.9 eV or less.

[0079] Next, the conduction model of the transistor shown in FIG. 2(A) will be explained using FIG. 2(B). FIG. 2B shows the structure of the transistor shown in FIG. 2A between the source and drain. FIG. 2(C) is a schematic diagram for explaining the distribution of energy levels. This is a conduction band diagram of a transistor along the solid line indicated by X-X'. In the conduction band diagram, the solid line indicates the energy at the bottom of the conduction band. f The dashed and dotted line indicated by denotes the energy of the quasi-Fermi level of electrons. In addition, here, the first gate voltage is , a negative voltage is applied between the gate and source, and a drain voltage is applied between the source and drain. Voltage (V d In Fig. 2, the energy at the bottom of the conduction band is assumed to be Lugi will be referred to as CB.

[0080] When a negative gate voltage is applied to the transistor shown in Figure 2(A), the transistor shown in Figure 2(B) As shown in the figure, the energy of the conduction band minimum originating from the 001 region between the source and drain CB 001 and the conduction band edge energy CB 002 And, is formed Here, since the first energy gap is larger than the second energy gap, Conduction band edge energy CB 001 The potential barrier at the energy -CB 002In other words, the potential barrier in the channel The maximum value of the barrier is due to the region 001. By using this, it is possible to suppress leakage current and create a transistor with high switching characteristics. can be done.

[0081] As shown in FIG. 2C, the region 001 having the first energy gap is The energy gap is relatively wider than that of region 002, which has an energy gap of 2. The Ec edge of the region 001 having the first energy gap is The Ec edge of the region 002 having the loop may be located relatively higher than the Ec edge of the region 002 having the loop.

[0082] Here, the metal oxide of one embodiment of the present invention is In-Al-Ga-Zn oxide. Assume.

[0083] In the In-Al-Ga-Zn oxide, the Al oxide is in contact with the In oxide and the In-Zn oxide. In other words, Al oxide has higher insulating properties than In oxide, In-Zn The energy gap is larger than that of Ga oxide and Ga oxide. By incorporating Al oxide with a large gap, the first energy gap is achieved. The energy of the Ec edge of the region with a second energy gap is Therefore, the difference between the energy of the metal oxide of one embodiment of the present invention can be increased. When the material is used in a semiconductor layer of a transistor, the field effect mobility of the transistor is increased, and By suppressing oxygen vacancies, a highly reliable semiconductor device can be obtained.

[0084] In the above configuration, Al has been described, but Si, Mg, Z, etc. may be used instead of Al. r, Be and B may also be used.

[0085] In the above configuration, the component of the region 001 having the first energy gap is In -Al-Ga-Zn oxide or In-Al-Zn oxide, The components of the gapped region 002 may be due to In-Zn oxide or In oxide. In this case, the first energy gap is equal to or greater than 3.3 eV and equal to or less than 4.0 eV, The second energy gap is 2.2 eV or more and 2.9 eV or less. The gap value can be obtained by measuring a single film of each material with an ellipsometer. Cut.

[0086] In addition, in the metal oxide of one embodiment of the present invention, the energy of the conduction band minimum originating from the region 001 The difference between the energy level of the conduction band minimum originating from the region 002 and the energy level of the conduction band minimum originating from the region 002 is at least 0.2 eV or more. However, it is preferable that the energy gap is 001. The energy position of the valence band top and the region 002 having the second energy gap The energy position of the top of the valence band may differ depending on the region 001. The energy level of the conduction band minimum due to the region 002 The difference between these is preferably 0.3 eV or more, and more preferably 0.4 eV or more.

[0087] In addition, under the above assumption, when carriers flow during CAC-OS, a second energy This occurs in In-Zn oxide or In oxide, which have a small gap, i.e., energy gap. At this time, carriers flow from the second energy gap to the first energy gap. In-Al-Ga-Zn oxide or In with a large energy gap In other words, the carriers overflow to the I-Al-Zn oxide side, which has a small energy gap. n-Zn oxide or In oxide generates carriers more easily, and the carriers are In-Al-Ga-Zn oxide or In-Al-Zn oxide with large energy gap Move.

[0088] In addition, the carrier density in the first band gap, i.e., the region with a large energy gap, Degree is 1 x 10 10 cm -3 More than 1×10 16 cm -3 Less than 1×10 15 cm -3 In addition, the second band gap, that is, the small energy gap, The carrier density in the low region is 1×10 18 cm -3 More than 1×10 21 cm -3 Less than is preferred stomach.

[0089] In the metal oxide forming the channel portion, the region 001 and the region 002 are It is a mosaic, and areas 001 and 002 are irregularly distributed. The conduction band diagram along the solid line indicated by X-X' is an example.

[0090] Next, the conduction band diagram shown in Fig. 2(C) is different from that shown in Fig. 3(A)(B)(C). In FIG. 3, the energy at the bottom of the conduction band is denoted as Ec.

[0091] In the metal oxide of one embodiment of the present invention, basically, as shown in FIG. It is sufficient that region 002 forms a band sandwiched between region 001. Or, region 001 is a region It is sufficient that a band sandwiched between 002 is formed.

[0092] In addition, in CAC-OS, the region 001 with the first energy gap and the region 002 with the second energy gap are The junction with the region 002, which has an energy gap, shows fluctuations in the aggregation morphology and composition of the region. Therefore, as shown in Fig. 3(B) and Fig. 3(C), the The band may change continuously. That is, when the carrier flows during CAC-OS, In other words, the first energy gap and the second energy gap are linked. is also good.

[0093] Next, in the transistor shown in FIG. 2(A), the band gap on the solid line indicated by X-X' is The model diagram of the diagram is shown in Figure 4 (A) (B) (C). Note that when a voltage is applied to the first gate, If a voltage is applied, the same voltage is also applied to the second gate.

[0094] FIG. 4A shows the first gate voltage V g As a positive voltage between the gate and source (V g 4B shows the state where the first gate Voltage V g Do not apply (V g FIG. 4C shows the first gate voltage V g As a result, a negative voltage (V g <0) is applied (OFFS In each conduction band diagram, the solid line indicates the energy CB Also, E fThe dashed dotted line indicates the energy of the electron quasi-Fermi level.

[0095] The transistor having the CAC-OS in the channel portion has a first energy gap. The region 001 having the first energy gap and the region 002 having the second energy gap electrically interact with each other. In other words, the region 001 having the first energy gap and the region 002 having the second energy gap The region 002 having a gap functions complementary to the region 002 having a gap.

[0096] As shown in FIG. 4(A), the potential (V g >0) is the first When a voltage is applied to the gate, the conduction band edge has a second energy gap that is lower in energy. The region 002 becomes the main conduction path, and electrons flow through it. At the same time, the first energy gap Electrons also flow into the region 001, which has a high current. Thus, a large current driving force, that is, a large on-current and a high field effect mobility can be obtained.

[0097] On the other hand, as shown in FIG. 4B and FIG. 4C, when the first gate is charged with a voltage lower than the threshold voltage, Voltage (V g ≦0), the region 001 having the first energy gap , behaves as a dielectric (insulator), so the conduction path in region 001 is blocked. The region 002 having the second energy gap is Therefore, the region 001 having the first energy gap is in contact with the region 001 itself. In addition to the first region, the second region has a second energy gap. This cuts off the conduction path in region 002, which has an energy gap of 0.2. The entire loop is non-conductive, and the transistor is turned off.

[0098] As explained above, by using CAC-OS in transistors, the operation of the transistors When a potential difference occurs between the gate and the source or drain, It is possible to reduce or prevent leakage current between the source or drain.

[0099] In addition, it is preferable to use a metal oxide film having a reduced hydrogen concentration in the film for the transistor. The metal oxide film having a reduced hydrogen concentration is called a high-purity intrinsic or substantially high-purity metal oxide. Metal oxides that are pure or substantially pure are called pure metal oxides. , hydrogen-based carriers (e.g., V where hydrogen is bonded to an oxygen vacancy) O H, etc.) are few Therefore, the carrier density can be reduced. Metal oxides with a low defect level density may also have a low trap level density. .

[0100] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. Transistors with a channel region formed in metal oxide may have unstable electrical characteristics. be.

[0101] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be In order to reduce the impurity concentration in the metal oxide, it is effective to It is also preferable to reduce the concentration of impurities in the film. etc.

[0102] Here, the influence of each impurity in the metal oxide will be described.

[0103] When carbon, one of the group 14 elements, is included in a metal oxide, Therefore, the concentration of carbon in the metal oxide and the The carbon concentration near the interface (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by mass spectrometry was 2×10 18 ato ms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0104] In addition, when an alkali metal is contained in a metal oxide, a defect level is formed and carriers are generated. Therefore, transistors using metal oxides containing alkali metals may Normally-on characteristics are easily obtained. Therefore, the concentration of alkali metals in the metal oxide is reduced. Specifically, it is preferable to obtain an alkali metal in a metal oxide by SIMS. The concentration of is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 The following applies.

[0105] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. , oxygen deficiency (V o ) may be formed. o ) hydrogen enters the In some cases, electrons that are carriers are generated. In other cases, some of the hydrogen atoms are bonded to the metal atoms. It can combine with hydrogen to produce electrons, which are carriers. Transistors using metal oxides tend to be normally-on. It is preferable that the amount of hydrogen in the material is reduced as much as possible. The hydrogen concentration obtained by SIMS was 1×10 16 atoms / cm 3 More than 3×10 21 atoms / cm 3 Less than 1 x 10 17 atoms / cm 3 More than 3×10 20 atoms / cm 3 Less than.

[0106] In addition, oxygen vacancies (V o ) is reduced by introducing oxygen into metal oxides. In other words, oxygen vacancies (V o ) is supplemented with oxygen And oxygen deficiency (V o ) disappears. Therefore, by diffusing oxygen into the metal oxide, Oxygen deficiency in transistors (V o ) and improve reliability.

[0107] As a method for introducing oxygen into a metal oxide, for example, a stoichiometric amount of oxygen may be added to the metal oxide. It is possible to provide an oxide that contains more oxygen than the stoichiometric composition. In the oxide, there is a region where oxygen is present in excess of the stoichiometric composition (hereinafter referred to as the excess oxygen region). In particular, when a metal oxide is used for a transistor, Providing an oxide having an excess oxygen region in an undercoat film near a transistor or an interlayer film Therefore, oxygen vacancies in the transistor can be reduced, and the reliability can be improved.

[0108] A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. Thus, stable electrical characteristics can be imparted.

[0109] <Metal oxide film formation method> An example of a method for forming a metal oxide film will be described below.

[0110] The temperature during the formation of the metal oxide film is preferably from room temperature (e.g., 25° C.) to 17° C. The temperature is preferably 0°C or lower, more preferably 100°C or higher but lower than 150°C. For example, a large substrate such as G10 The temperature of the substrate is limited depending on the size of the plate. Top) A higher temperature that is as easy to maintain as possible and that also provides good throughput. The room temperature may be selected as appropriate. Note that room temperature includes a state where no heating is intentionally performed.

[0111] The sputtering gas may be a rare gas (typically argon), oxygen, or a rare gas and oxygen. In the case of mixed gas, the ratio of oxygen gas in the entire deposition gas is 0. % or more and 30% or less, preferably 5% or more and 20% or less.

[0112] In addition, it is also necessary to increase the purity of the sputtering gas. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using this, it is possible to prevent moisture and the like from being absorbed into the metal oxide as much as possible.

[0113] In addition, when forming a metal oxide film by sputtering, the thickness of the sputtering device is The chamber is equipped with a cryopump to remove water and other impurities that are harmful to metal oxides. A high vacuum (5×10 -7 Pa to 1×10 -4 It is preferable to evacuate the gas to a temperature of about 10 Pa. Alternatively, a turbo molecular pump and a cold trap can be used. By combining these, gases, especially those containing carbon or hydrogen, flow back into the chamber from the exhaust system. It is preferable to keep this in mind.

[0114] In addition, an In-M-Zn metal oxide target can be used as the target. For example, In:Al:Ga:Zn=4:1:1:4 [atomic ratio], In:Al:Si: Zn=4:1:1:4[atomic ratio], In:Ga:Si:Zn=4:1:1:4[atomic number ratio], In:Al:Ga:Zn=5:0.5:0.5:7[atomic ratio], In:Al:S i:Zn=5:0.5:0.5:7 [atomic ratio], In:Ga:Si:Zn=5:0.5 A metal oxide target with an atomic ratio of 0.5:7 or a value close to that ratio is used. It is preferable to use

[0115] In addition, in the sputtering device, a magnet unit disposed near the target For example, the magnet unit may be rotated or moved up and down during deposition. By rotating the substrate from side to side and / or from side to side, a metal oxide according to one embodiment of the present invention can be formed. For example, the magnet unit can be oscillated at a beat of 0.1 Hz to 1 kHz. That's good.

[0116] In addition, for example, the sputtering gas may be oxygen with a gas ratio of about 10%. A mixture of rare gas and In:Al:Ga: is used, the substrate temperature is set to, for example, 130° C., and In-Al-Ga-Zn metal oxide target with Zn=5:0.5:0.5:7 [atomic ratio] The film is formed while oscillating the magnet unit placed near the substrate (e.g., on the back side). In this manner, the metal oxide of one embodiment of the present invention can be formed.

[0117] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. There can be.

[0118] (Embodiment 2) In this embodiment, a semiconductor device including a metal oxide according to one embodiment of the present invention and a semiconductor device including the metal oxide according to the present embodiment will be described. A method for fabricating the device will be described with reference to FIGS.

[0119] <2-1. Configuration example 1 of semiconductor device> FIG. 5A is a top view of a transistor 100A which is a semiconductor device of one embodiment of the present invention. FIG. 5B is a cross-sectional view taken along the dashed line X1-X2 in FIG. 5A. FIG. 5C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. FIG. 5D corresponds to a cross-sectional conceptual diagram in which the region P1 shown in FIG. 5B is enlarged. do.

[0120] In FIG. 5A, in order to avoid complication, the structure of the transistor 100A is In the figure, some of the components (such as an insulating film that functions as a gate insulating film) are omitted. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. Note that the top view of a transistor is also shown in the following drawings. As with 5(A), some of the components may be omitted in the illustration.

[0121] The transistor 100A includes a conductive film 106 on a substrate 102 and a conductive film 10 6, an insulating film 104 on the insulating film 104, a metal oxide 108 on the metal oxide 108, and a conductive film The conductive film 112a, the conductive film 112b on the metal oxide 108, the metal oxide 108, the conductive film 1 12a, an insulating film 114 on the conductive film 112b, an insulating film 116 on the insulating film 114, The conductive film 120a is on the insulating film 116, and the conductive film 120b is on the insulating film 116.

[0122] The insulating film 104 has an opening 151. A conductive film 112c is formed so as to be electrically connected to the conductive film 106. 4 and the insulating film 116 have an opening 152a reaching the conductive film 112b and an opening 152b reaching the conductive film 112c. and an opening 152b through which the

[0123] The metal oxide 108 includes the metal oxide of one embodiment of the present invention described in Embodiment 1. Next, connection between a metal oxide and a conductive film according to one embodiment of the present invention will be described with reference to FIG. Do the following.

[0124] As shown in the region P1 in FIG. 5(D), the upper and side surfaces of the metal oxide 108 and the conductive film 112 Since the metal oxide 108 is in contact with the CAC Since the CAC structure has a region 002, that is, a region with high conductivity and a region with low conductivity, Since the film 112a is in contact with the metal film 112b, the contact resistance can be further reduced. The connection between the metal oxide 108 and the conductive film 112b is similar to that in the region P1.

[0125] The metal oxide of one embodiment of the present invention has a highly conductive region and has low contact resistance with a conductive film. Therefore, the field effect mobility of the transistor having the metal oxide is increased. It can be done.

[0126] Specifically, the field effect mobility of the transistor 100A is 50 cm 2 / Vs, More preferably, the field effect mobility of the transistor 100A is 100 cm 2 / Vs This makes it possible.

[0127] For example, the above-mentioned high field effect mobility transistor is By using this in the gate driver that generates the MOS transistors, a display device with a narrow frame width (also called a narrow frame) can be provided. In addition, the above-mentioned transistor having high field effect mobility can be effectively used in a display device. A source driver (especially a system having a source driver) that supplies signals from a signal line to the By using it as a demultiplexer connected to the output terminal of a soft register, It is possible to provide a display device having a small number of connected wires.

[0128] In addition, impurities such as hydrogen or moisture mixed in the metal oxide 108 may cause problems, particularly with transistors. Therefore, in the channel region of the metal oxide 108, In the case of the metal oxide 108, the less impurities such as hydrogen or moisture, the better. The oxygen vacancies formed in the channel region of the transistor are problematic because they affect the transistor characteristics. For example, when oxygen vacancies are formed in the channel region of the metal oxide 108, the oxygen vacancies Hydrogen bonds to the metal oxide 108, which becomes a carrier source. When the source is generated, the electrical properties of the transistor 100A having the metal oxide 108 change. This causes a shift in the channel of the metal oxide 108, typically resulting in a shift in the threshold voltage. In the hole region, the fewer the oxygen deficiencies, the more preferable.

[0129] The conductive film 112c and the conductive film 120a are electrically connected to each other through the opening 152b. The conductive film 112b and the conductive film 120b are electrically connected to each other through the opening 152a. The conductive film 120a and the conductive film 120b are formed by processing the same conductive film. do.

[0130] In addition, an insulating film 118 is provided on the transistor 100A. The insulating film 116, the conductive film 120a, and the conductive film 120b are formed so as to cover the insulating film 116, the conductive film 120a, and the conductive film 120b.

[0131] In the transistor 100A, the insulating film 104 is The insulating films 114 and 116 function as gate insulating films for the transistor 100A. The insulating film 118 functions as a second gate insulating film and serves to protect the transistor 100A. It functions as an insulating film.

[0132] In the transistor 100A, the conductive film 106 functions as a first gate electrode. The conductive film 120a functions as a second gate electrode, and the conductive film 120b functions as a The transistor 100A functions as a pixel electrode for use in a display device. The conductive film 112a functions as a source electrode, and the conductive film 112b functions as a drain electrode. In the transistor 100A, the conductive film 112c functions as a connection electrode. In this specification, the insulating film 104 is referred to as a first insulating film. The insulating films 114 and 116 are referred to as second insulating films, and the insulating film 118 is referred to as a third insulating film. It may be referred to as.

[0133] As shown in FIG. 5C, the conductive film 120a functioning as the second gate electrode is A conductive film 112c serving as a connection electrode is sandwiched between the first gate electrode and the second gate electrode. The conductive film 106 is electrically connected to the conductive film 120a. The same potential is applied.

[0134] As shown in FIG. 5C, the metal oxide 108 functions as a first gate electrode. and a conductive film 120a functioning as a second gate electrode. The conductive film 120a is located so as to be sandwiched between two films that function as gate electrodes. The length in the channel length direction and the length in the channel width direction of the conductive film 120a are 8 in the channel length direction and the length of the metal oxide 108 in the channel width direction, The metal oxide 108 is entirely covered by the conductive film 120a via the insulating films 114 and 116. It is believed that.

[0135] In other words, in the channel width direction of the transistor 100A, The conductive film 106 functioning as a first gate electrode and the conductive film 120a functioning as a second gate electrode are An insulating film 104 functioning as a gate insulating film and an insulating film functioning as a second gate insulating film The metal oxide 108 is surrounded by the metal layers 114 and 116 .

[0136] With this configuration, the metal oxide 108 included in the transistor 100A A conductive film 106 functions as a first gate electrode and a conductive film 107 functions as a second gate electrode. The electric field of the conductive film 120a can electrically surround the transistor 100A. A channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the metal oxide is called the Surrounded cha This can be called a nnel (S-channel) structure.

[0137] Since the transistor 100A has an S-channel structure, the first gate electrode and The conductive film 106 functions as a metal oxide to effectively generate an electric field to induce a channel. This allows the current drive capability of the transistor 100A to be improved. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 100A. A is a conductive film 106 in which a metal oxide 108 functions as a first gate electrode and a second gate electrode. Since the transistor has a structure surrounded by a conductive film 120a that functions as a transistor electrode, The mechanical strength of 100A can be increased.

[0138] <2-2. Configuration example 2 of semiconductor device> Next, regarding the modified example of the transistor 100A shown in FIGS. 5(A), 5(B), and 5(C), This will be explained with reference to FIG.

[0139] First, an explanation will be given with reference to Figures 6(A), (B), (C), and (D).

[0140] 6(A), (B), and (C) are diagrams showing variations of the transistor 100A shown in FIGS. 5(A), (B), and (C). 6A and 6B are a top view and a cross-sectional view of a transistor 100B according to an embodiment of the present invention. This corresponds to a schematic cross-sectional view in which a region P2 shown in (B) is enlarged.

[0141] The transistor 100B shown in FIGS. 6A, 6B, and 6C is a transistor 100B shown in FIGS. The metal oxide 108 of the transistor 100A has a two-layer structure. Specifically, the metal oxide 108 of the transistor 100B is a metal oxide 108_2. , and a metal oxide 108_3 on the metal oxide 108_2.

[0142] For example, the metal oxide 108_2 included in the metal oxide 108 may be a metal oxide according to one embodiment of the present invention. Compounds such as fluorine-containing fluorine compounds can be used.

[0143] As shown in a region P2 in FIG. 6D, the upper and side surfaces of the metal oxide 108 and the conductive film Since the metal oxide 108 is in contact with the metal oxide 112a, the contact resistance can be reduced. Since the compound 108_2 has the CAC configuration shown in FIG. That is, the highly conductive region and the conductive film 112a come into contact with each other, so that the contact resistance is further reduced. In addition, metal oxides with low electrical conductivity, such as wide band gaps (Eg Even if an oxide having a charge transport property of 3.3 eV or more is used as the metal oxide 108_3, The contact resistance can be reduced by bringing the side surface of 8_2 into contact with the conductive film 112a. Although not shown, the connection between the metal oxide 108 and the conductive film 112b is also Similar to area P2.

[0144] Next, a description will be given with reference to Figures 7(A), (B), (C), and (D).

[0145] 7(A), (B), and (C) are diagrams showing variations of the transistor 100A shown in FIGS. 5(A), (B), and (C). 7A and 7B are a top view and a cross-sectional view of a transistor 100C according to an example embodiment of the present invention. This corresponds to a schematic cross-sectional view in which a region P3 shown in (B) is enlarged.

[0146] The transistor 100C shown in FIGS. 7A, 7B, and 7C is the same as the transistor 100 shown in FIGS. The metal oxide 108 of the transistor 100A has a three-layer structure. Specifically, the metal oxide 108 of the transistor 100C is a metal oxide 108_1. , a metal oxide 108_2 on a metal oxide 108_1, and a metal oxide on a metal oxide 108_2 Compound 108_3.

[0147] For example, the metal oxide 108_2 included in the metal oxide 108 may be a metal oxide according to one embodiment of the present invention. Compounds such as fluorine-containing fluorine compounds can be used.

[0148] As shown in a region P3 in FIG. 7D, the upper and side surfaces of the metal oxide 108 and the conductive film Since the metal oxide 108 is in contact with the metal oxide 112a, the contact resistance can be reduced. Since the compound 108_2 has the CAC configuration shown in FIG. That is, the highly conductive region and the conductive film 112a come into contact with each other, so that the contact resistance is further reduced. In addition, metal oxides with low electrical conductivity, such as wide band gaps (Eg The oxides with a valence of 3.3 eV or more were used for the metal oxide 108_1 and the metal oxide 108_3. However, the contact resistance between the side surface of the metal oxide 108_2 and the conductive film 112a is small. Although not shown, the metal oxide 108 and the conductive film 112 The connection with b is similar to that of region P3.

[0149] Next, a description will be given with reference to Figures 8(A), (B), (C), and (D).

[0150] 8(A), (B), and (C) are diagrams showing variations of the transistor 100A shown in FIGS. 8A and 8B are a top view and a cross-sectional view of a transistor 100D according to an example embodiment of the present invention. This corresponds to a schematic cross-sectional view in which a region P4 shown in (B) is enlarged.

[0151] The transistor 100D shown in FIGS. 8A, 8B, and 8C is The metal oxide 108 of the transistor 100A has a three-layer structure. Specifically, the metal oxide 108 of the transistor 100D is a metal oxide 108_1. , a metal oxide 108_2 on a metal oxide 108_1, and a metal oxide on a metal oxide 108_2 Compound 108_3.

[0152] For example, the metal oxide 108_2 included in the metal oxide 108 may be a metal oxide according to one embodiment of the present invention. Also, as shown in the region P4 of FIG. 8(D), a metal oxide 10 Since the upper surface and side surface of the metal oxide film 8 are in contact with the conductive film 112a, the contact resistance can be reduced. Since the metal oxide 108_2 of the compound 108 has the CAC structure shown in FIG. The region 002 of the C configuration, that is, the region with high conductivity, is in contact with the conductive film 112a. This further reduces the contact resistance.

[0153] In addition, the transistor 100D is a transistor having a metal oxide 108_3. The metal oxide 108_3 of the transistor 100D is disposed at a different position from the source electrode 104. The metal oxide is formed on the conductive films 112a and 112b which function as the positive and negative electrodes. The metal oxide 108_2 is disposed on the conductive films 112a and 112b. This can further reduce the contact resistance with the conductive films 112a and 112b.

[0154] As shown in FIGS. 6 to 8, in the transistor of one embodiment of the present invention, a metal oxide is A laminated structure is preferred.

[0155] <2-3. Band structure> Next, the band structure when the metal oxide 108 has a laminated structure will be described with reference to FIG. explain.

[0156] The insulating film 104, the metal oxides 108_1, 108_2, 108_3, and the insulating film 114 The band structure, the insulating film 104, the metal oxides 108_2 and 108_3, and the insulating film 1 The band structure of 14 is shown in Figure 16.

[0157] FIG. 16(A) shows an insulating film 104, metal oxides 108_1, 108_2, 108_3, and 16(a) and the insulating film 114. B) has an insulating film 104, metal oxides 108_2 and 108_3, and an insulating film 114. 1 is an example of a band structure in the thickness direction of a laminated structure. Note that the band structure is shown in FIG. The insulating film 104, the metal oxides 108_1, 108_2, 108_3, and the insulating film 114 The energy level (Ec) at the bottom of the conduction band of

[0158] As shown in FIG. 16A, in the metal oxides 108_1, 108_2, and 108_3, The energy level at the bottom of the conduction band changes gradually. In the metal oxides 108_2 and 108_3, the energy level at the bottom of the conduction band is gently In other words, it can be said that the material changes continuously or joins continuously. In order to have such a band structure, the metal oxide 108_1 and the metal oxide 108_2 must be At the interface between the metal oxide 108_2 and the metal oxide 108_3, It is assumed that there are no impurities that would form defect levels such as centers or recombination centers.

[0159] To form a continuous junction in the metal oxides 108_1, 108_2, and 108_3, Using a multi-chamber type film formation device (sputtering device) equipped with a lock chamber, It is necessary to laminate the films continuously without exposing them to the atmosphere.

[0160] By adopting the structure shown in FIG. 16(A)(B), the metal oxide 108_2 becomes a well. In the transistor using the above-mentioned stacked structure, the channel region is a metal oxide 108 _ It can be seen that it is formed into 2.

[0161] The metal oxide of one embodiment of the present invention can be used as the metal oxide 108_2. Therefore, in FIG. 16, the band structure of the metal oxide 108_2 is shown as a flat shape. Although the band structure of the metal oxide 108_2 is illustrated as a band structure, the band structure of the metal oxide 108_2 is the same as that described in the first embodiment. In some cases, the band structure shown in Figure 3(A), (B), and (C) may result.

[0162] By providing the metal oxides 108_1 and 108_3, the metal oxide 108_2 The metal oxide 108_1 or the metal oxide 108_3 is provided with a trap level that can be formed in the Therefore, a trap level is unlikely to be formed in the metal oxide 108_2. It becomes a structure.

[0163] In addition, the trap level is at the bottom of the conduction band of the metal oxide 108_2, which functions as a channel region. The energy level (Ec) of the electron can be farther from the vacuum level, and the electron can be trapped in the trap level. When electrons accumulate in the trap level, the negative fixed charge This causes a load and the threshold voltage of the transistor to shift in the positive direction. The trap level is lower than the vacuum level (Ec) of the conduction band minimum of the metal oxide 108_2. It is preferable to configure the trap level so that the electrons are close to the trap level. This makes it difficult for the on-state current of the transistor to accumulate, and the on-state current of the transistor can be increased. The field effect can increase the mobility.

[0164] In addition, the metal oxides 108_1 and 108_3 have a lower conduction band edge than the metal oxide 108_2. The energy level of the metal oxide 108_2 is close to the vacuum level, typically at the bottom of the conduction band. Energy levels and the energy levels at the bottom of the conduction band of metal oxides 108_1 and 108_3 The difference is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less That is, the electron affinity of the metal oxides 108_1 and 108_3 and the electron affinity of the metal oxide 10 The difference between the electron affinity of 8_2 is 0.15 eV or more, or 0.5 eV or more and 2 eV or more. or 1 eV or less.

[0165] With such a configuration, the metal oxide 108_2 becomes a main current path. The metal oxide 108_2 functions as a channel region, and the metal oxide 108_1 The metal oxides 108_1, 108_2, and 108_3 function as oxide insulating films. 08_3 is a type of metal element that constitutes the metal oxide 108_2 in which the channel region is formed. It is preferable to use a metal oxide composed of the above and element M. As a result, the interface between the metal oxide 108_1 and the metal oxide 108_2 and the interface between the metal oxide 108_ At the interface between the metal oxide 108_3 and the metal oxide 108_2, the interface scattering is unlikely to occur. Since the movement of carriers is not hindered in the do.

[0166] In addition, the metal oxides 108_1 and 108_3 function as part of the channel region. To prevent this, a material with sufficiently low electrical conductivity is used. 08_1 and 108_3 are also called oxide insulating films based on their physical properties and / or functions. Alternatively, the metal oxides 108_1 and 108_3 have electron affinities (vacuum levels and conduction bands) The difference between the energy level at the bottom of the conduction band and the energy level at the bottom of the conduction band is smaller than that of metal oxides 108_2. The energy level of the metal oxide 108_2 is the difference (band offset) between the conduction band edge and the In addition, a material having a threshold voltage that depends on the magnitude of the drain voltage is used. In order to suppress the occurrence of a difference in the value voltage, the conduction of the metal oxides 108_1 and 108_3 is The energy level of the conduction band of the metal oxide 108_2 is higher than that of the metal oxide 108_2. It is preferable to use a material close to the vacuum level. For example, the conduction band minimum of the metal oxide 108_2 The energy levels of the conduction band of the metal oxides 108_1 and 108_3 The difference between these is preferably 0.2 eV or more, and more preferably 0.5 eV or more.

[0167] In addition, the metal oxides 108_1 and 108_3 do not include a spinel type crystal structure in the film. It is preferable that the metal oxide films 108_1 and 108_3 have a spinel type crystal structure. When the spinel type crystal structure includes the conductive film 120a, 120b, the conductive film 120c is formed at the interface between the spinel type crystal structure and other regions. The constituent elements of 0b may diffuse into the metal oxide 108_2. When 108_1 and 108_3 are CAAC-OS, the configuration of the conductive films 120a and 120b An element such as copper is preferred because it has high blocking properties.

[0168] The metal oxides 108_1 and 108_3 were In:Ga:Zn=1:1:1 [original metal oxide target with In:Ga:Zn=1:3:4 [atomic ratio], and metal oxide target with In:Ga:Zn=1:3:4 [atomic ratio] Zn:Ga:Zn=1:3:6 [atomic ratio] metal oxide target It can be formed using the above.

[0169] <2-4. Configuration example 3 of semiconductor device> Next, referring to FIG. 9, a transistor having a different configuration from the transistors described above will be described. I will use this to explain.

[0170] FIG. 9A is a top view of a transistor 200A which is a semiconductor device of one embodiment of the present invention. FIG. 9B is a cross-sectional view taken along the dashed line X1-X2 in FIG. 9A. FIG. 9C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. FIG. 9D corresponds to a cross-sectional conceptual diagram in which the region P5 shown in FIG. 9B is enlarged. do.

[0171] The transistor 200A shown in FIGS. 9A, 9B, and 9C is a so-called top-gate transistor. It is a ninja.

[0172] The transistor 200A includes a conductive film 206 on a substrate 202 and a conductive film 20 6, a metal oxide 208 on the insulating film 204, and a metal oxide 208 on the insulating film 204. The insulating film 210, the conductive film 212 on the insulating film 210, the insulating film 204, the metal oxide 208, and and an insulating film 216 on the conductive film 212 .

[0173] The metal oxide 208 is preferably a metal oxide according to one embodiment of the present invention.

[0174] The metal oxide 208 overlaps with the conductive film 212 and contacts with the insulating film 210. The region 208i overlaps with the insulating film 216, and the region 208n overlaps with the insulating film 216. In other words, the metal oxide 208 has a region having a higher carrier density than the region 208i. The region 208n has a plurality of regions with different carrier densities. It can also be called the in-region.

[0175] Here, the connection between the area 208i and the area 208n will be described with reference to FIG. 9(D). conduct.

[0176] As shown in region P5 of FIG. 9(D), the side of region 208i and the side of region 208n are in contact with each other. Therefore, the contact resistance can be reduced. Since the CAC structure shown in FIG. 1 has a region 002 having a CAC structure, i.e., a region having a conductive property Since the high region and the region 208n, i.e., the source region, are in contact with each other, the contact resistance can be further reduced. Although not shown, the other side surface of the region 208i and the side surface of the region 208n may be The connections are the same as in area P5.

[0177] The metal oxide of one embodiment of the present invention has a highly conductive region and is Therefore, the contact resistance with the semiconductor region is reduced. The field effect mobility of the semiconductor can be improved.

[0178] The region 208n is in contact with the insulating film 216. The insulating film 216 contains nitrogen or hydrogen. Therefore, nitrogen or hydrogen in the insulating film 216 is added to the region 208n. 208n has a high carrier density due to the addition of nitrogen or hydrogen from the insulating film 216. become.

[0179] The transistor 200A also includes an insulating film 218 on the insulating film 216, and an insulating film 216, A conductive film 2 is electrically connected to the region 208n through an opening 241a provided in the conductive film 2 20a, and through an opening 241b provided in the insulating films 216 and 218, a region 208n is and a conductive film 220b electrically connected thereto.

[0180] As shown in FIG. 9C, the insulating film 204 and the insulating film 210 have an opening 243. The conductive film 206 is electrically connected to the conductive film 212 through the opening 243. Therefore, the conductive film 206 and the conductive film 212 are applied with the same potential. The opening 243 may not be provided, and different potentials may be applied to the conductive film 206 and the conductive film 212. .

[0181] The conductive film 206 functions as a first gate electrode (also called a bottom gate electrode). The conductive film 212 functions as a second gate electrode (also called a top gate electrode). The insulating film 204 functions as a first gate insulating film, and the insulating film 21 0 functions as a second gate insulating film.

[0182] In this manner, the transistor 200A shown in FIGS. The transistor 200A has a structure in which conductive films functioning as gate electrodes are provided above and below the transistor 8. As shown in FIG. 1, the semiconductor device according to one embodiment of the present invention may be provided with two or more gate electrodes. .

[0183] As shown in FIG. 9C, the metal oxide 208 functions as a first gate electrode. and a conductive film 212 functioning as a second gate electrode. The gate electrode is located as shown in FIG. 1 and is sandwiched between two conductive films that function as gate electrodes.

[0184] The length of the conductive film 212 in the channel width direction is The metal oxide 208 is electrically conductive through the insulating film 210 in the entire channel width direction. The conductive film 212 and the conductive film 206 are covered with the insulating film 204 and the insulating The connection is made at the opening 243 provided in the insulating film 210, so that the chamfer of the metal oxide 208 One of the side surfaces in the panel width direction faces a conductive film 212 with an insulating film 210 interposed therebetween.

[0185] In other words, in the channel width direction of the transistor 200A, the conductive film 206 and the conductive The film 212 is connected to the insulating film 204 and the insulating film 210 at an opening 243 provided therein. At the same time, the insulating film 204 and the insulating film 210 surround the metal oxide 208. That is, the transistor 200A has the S-channel structure shown above.

[0186] <2-5. Configuration example 4 of semiconductor device> Next, regarding the modified example of the transistor 200A shown in FIGS. 9(A), 9(B), and 9(C), This will be explained with reference to FIG.

[0187] First, a description will be given with reference to Figures 10(A), (B), (C), and (D).

[0188] 10(A), (B), and (C) are diagrams showing the structure of the transistor 200A shown in FIG. 10A and 10B are a top view and a cross-sectional view of a transistor 200B, which is a modified example. This corresponds to a schematic cross-sectional view in which a region P6 shown in FIG. 10(B) is enlarged.

[0189] The transistor 200B shown in FIG. 10(A), (B), and (C) has the same structure as that shown in FIG. The metal oxide 208 of the transistor 200A shown in FIG. Specifically, the metal oxide 208 of the transistor 200B includes a region 208i_1 and A region 208i_2 on the region 208i_1 and a region 208n overlapping the insulating film 216 are provided. do.

[0190] For example, the metal oxide 208 may be formed by adding a metal oxide film of one embodiment of the present invention to the region 208i_2 of the metal oxide 208. can be used.

[0191] As shown in the region P6 in FIG. 10D, the side of the region 208i_2 and the side of the region 208n Since the metal oxide 208 is in contact with the metal oxide 208, the contact resistance can be reduced. Since the _2 has the CAC configuration shown in FIG. 1, the area 002 of the CAC configuration, i.e. Since the highly conductive region contacts the region 208n, i.e., the source region, the contact resistance is further increased. Although not shown, the other side surface of the region 208i_2 and the region 20 The connection to the side surface of region 8n is similar to that of region P6.

[0192] Next, a description will be given with reference to Figures 11(A), (B), (C), and (D).

[0193] 11(A), (B), and (C) are diagrams showing the structure of the transistor 200A shown in FIG. 11A and 11B are a top view and a cross-sectional view of a transistor 200C, which is a modified example. This corresponds to a schematic cross-sectional view in which a region P7 shown in FIG. 11(B) is enlarged.

[0194] The transistor 200C shown in FIGS. 11A, 11B, and 11C has the same structure as that shown in FIGS. The metal oxide 208 of the transistor 200A shown in FIG. Specifically, the metal oxide 208 of the transistor 200C includes a region 208i_1 and A region 208i_2 on the region 208i_1, a region 208i_3 on the region 208i_2, and a region 208n overlapping the insulating film 216.

[0195] For example, the metal oxide 208 may be formed by adding a metal oxide film of one embodiment of the present invention to the region 208i_2 of the metal oxide 208. can be used.

[0196] As shown in the region P7 in FIG. 11D, the side of the region 208i_2 and the side of the region 208n Since the metal oxide 208 is in contact with the metal oxide 208, the contact resistance can be reduced. Since the _2 has the CAC configuration shown in FIG. 1, the area 002 of the CAC configuration, i.e. Since the highly conductive region contacts the region 208n, i.e., the source region, the contact resistance is further increased. Although not shown, the other side surface of the region 208i_2 and the region 20 The connection to the side surface of region 8n is similar to that of region P7.

[0197] Next, a description will be given with reference to Figures 12(A), (B), (C), and (D).

[0198] 12(A), (B), and (C) are diagrams showing the structure of the transistor 200A shown in FIG. 12D is a top view and a cross-sectional view of a transistor 200D, which is a modified example. This corresponds to a schematic cross-sectional view in which a region P8 shown in FIG. 12(B) is enlarged.

[0199] The transistor 200D shown in FIG. 12(A), (B), and (C) has the same structure as that shown in FIG. The metal oxide 208 of the transistor 200A shown in FIG. Specifically, the metal oxide 208 of the transistor 200D includes a region 208i_1 and A region 208i_2 on the region 208i_1, a region 208i_3 on the region 208i_2, and a region 208n overlapping the insulating film 216.

[0200] For example, the metal oxide 208 may be formed by adding a metal oxide film of one embodiment of the present invention to the region 208i_2 of the metal oxide 208. As shown in the region P8, the side surface of the region 208i_2 and the region 2 Since the side surface of the metal oxide 208 contacts the side surface of the metal oxide 208, the contact resistance can be reduced. Since the area 208i_2 has the CAC configuration shown in FIG. 1, the area 00 2, that is, the highly conductive region contacts region 208n, that is, the source region, The contact resistance can be further reduced. The connection to the side surface of region 208n is similar to that of region P8.

[0201] Note that the metal oxide 208 of the transistor 200D is the same as that of the transistor 200C. The shape of the metal oxide 208 and the region 208i_3 are different. The metal oxide 208 in the region 200D is formed on the side of the region 208i_1 and the region 208i_2. The side surface of the region 208i_3 is covered by the region 208i_3. This results in a structure in which the side surface of the region 8i_1 and the side surface of the region 208i_2 are not in contact with the insulating film 210. By adopting this structure, in the region 208i_1 and the region 208i_2, especially the region 208i_ 2. It is possible to suppress impurities that may get into the semiconductor device, providing highly reliable semiconductor devices. It is possible.

[0202] As shown in FIGS. 10 to 12, in the transistor of one embodiment of the present invention, a metal oxide It is preferable to use a laminated structure for the metal oxide. For details, please refer to <2-3. Band structure>.

[0203] <2-6. Components of Semiconductor Device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0204] [substrate] There is no particular restriction on the material of the substrates 102 and 202, but it is necessary that the material can at least withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, etc. A substrate, a sapphire substrate, or the like may be used as the substrate 102, 202. In addition, silicon or Single crystal semiconductor substrates, polycrystalline semiconductor substrates, and silicon germanium made of silicon carbide It is also possible to apply compound semiconductor substrates such as SOI substrates, and semiconductors can be formed on these substrates. A substrate provided with a conductive element may be used as the substrate 102 or 202. 2. When using a glass substrate as 202, 6th generation (1500mm x 1850mm) , 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2400mm) , 9th generation (2400mm x 2800mm), 10th generation (2950mm x 3400mm By using a large-area substrate such as a liquid crystal display (LCD), a large display device can be manufactured.

[0205] In addition, a flexible substrate is used as the substrate 102, 202, and the transistor is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 or 202 and the transistor. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. , 202, and can be transferred to another substrate. The data can be transferred to substrates with poor heat resistance or flexible substrates.

[0206] [Conductive film] The conductive film 106, 206 functions as a first gate electrode, and the conductive film 206 functions as a source electrode. Conductive films 112a and 220a, conductive films 112b and 220b functioning as drain electrodes, and A conductive film 112c serving as an electrode, a conductive film 120a serving as a second gate electrode, 212, and the conductive film 120b functioning as a pixel electrode are made of chromium (Cr), copper (C u), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (M o), Tantalum (Ta), Titanium (Ti), Tungsten (W), Manganese (Mn), Ni A metal element selected from nickel (Ni), iron (Fe), and cobalt (Co), or the above The alloys are made of metal elements or alloys combining the above metal elements. It can be formed.

[0207] In addition, the conductive films 106, 112a, 112b, 112c, 120a, 120b, 206, 220a, 220b, and 212 are oxides having indium and tin, tungsten and in oxides containing tungsten, indium and zinc; oxides containing tungsten, indium and zinc; and indium; oxide having titanium, indium and tin; indium and zinc, an oxide having silicon, indium, and tin, an oxide having indium and gallium, Alternatively, an oxide conductor such as an oxide containing lithium and zinc may be used.

[0208] In particular, the conductive films 120a and 212 can be preferably made of the oxide conductor described above. In this specification, the oxide conductor is referred to as OC (Oxide Conductor). The oxide conductor may be, for example, a semiconductor having an oxygen vacancy formed therein. When hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. The oxide semiconductor that has become a conductor is called an oxide conductor. In general, oxide semiconductors have a large energy gap. It is transparent to visible light. On the other hand, oxide conductors have donor levels near the conduction band. Therefore, the effect of absorption due to donor levels is small in oxide conductors. The transparent semiconductor has a light transmittance to visible light comparable to that of an oxide semiconductor.

[0209] In addition, the conductive films 106, 112a, 112b, 112c, 120a, 120b, 206, 220a, 220b, and 212 are Cu-X alloy films (X is Mn, Ni, Cr, Fe, C The Cu-X alloy film can be used to Since the process can be performed by hot etching, the manufacturing cost can be reduced.

[0210] In particular, the conductive films 112a, 112b, 220a, and 220b are made of the above-mentioned Cu-X alloy film. As the Cu-X alloy film, a Cu-Mn alloy film is particularly preferable. .

[0211] [Insulating film functioning as the first gate insulating film] The insulating films 104 and 204 functioning as the first gate insulating film of the transistor are Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon oxide is deposited by vapor deposition, sputtering, etc. silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film , hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, oxide Tantalum film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film Each of the insulating films 104 and 204 can be an insulating layer containing one or more films. The insulating film may be a single layer of insulating film selected from the above-mentioned materials, or may be two or more layers of insulating film. good.

[0212] In addition, the metal oxides 108 and 208 that function as channel regions of the transistors are in contact with each other. The insulating film is preferably an oxide insulating film, and contains oxygen in excess of the stoichiometric composition. It is more preferable that the oxygen-containing region (excess oxygen region) is included.

[0213] However, the present invention is not limited to the above configuration. For example, the insulating film in contact with the metal oxide 108 or 208 may be a nitride film. An insulating film may be used. As an example of such a structure, a silicon nitride film is formed, By performing oxygen plasma treatment on the surface of the silicon nitride film, the surface of the silicon nitride film The surface of the silicon nitride film may be oxidized by oxygen plasma treatment. In such cases, the surface of the silicon nitride film may be oxidized at the atomic level. Even if a cross section of a transistor is observed, the oxide film may not be observed. When a cross section of the transistor was observed, the silicon nitride film and the metal oxide were in contact with each other. In particular, the metal oxide according to one embodiment of the present invention shown in Embodiment 1 may be observed. Since the material has a large energy gap, it is possible to use metal oxide 108 or 208 and nitride The silicon film may be in contact with the insulating film.

[0214] In addition, the silicon nitride film has a higher dielectric constant than the silicon oxide film. Since a large film thickness is required to obtain the same capacitance as that of a gate insulating film of a transistor, By including the silicon nitride film, the insulating film can be made thicker. By suppressing the decrease in the dielectric strength voltage of the transistor and improving the dielectric strength voltage, It can be suppressed.

[0215] Furthermore, when hafnium oxide is used as the insulating film 104, 204, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating films 104 and 204 can be made larger. Therefore, the leakage current due to the tunnel current can be reduced. Furthermore, it is possible to realize a transistor with a small capacitance. Hafnium oxide has a higher dielectric constant than hafnium oxide having an amorphous structure. To make a transistor with a small off-state current, hafnium oxide with a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0216] [Metal oxides] The metal oxides 108 and 208 may be the metal oxide of one embodiment of the present invention described in Embodiment 1. can be used.

[0217] The metal oxide 108, 208 has an energy gap of 2 eV or more, preferably 2 The energy gap is preferably 0.5 eV or more, and more preferably 3 eV or more. By using a thin metal oxide, the off-state current of a transistor can be reduced.

[0218] The thickness of the metal oxide 108, 208 is 3 nm or more and 200 nm or less, preferably 3 The thickness is preferably from 3 nm to 50 nm, and more preferably from 3 nm to 50 nm.

[0219] In order to obtain the required semiconductor characteristics of the transistor, the metal oxides 108 and 208 The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, density, etc. of the It is preferable to use the following.

[0220] [Insulating film that functions as the second gate insulating film] The insulating films 114, 116, and 210 function as second gate insulating films of the transistors. In addition, the insulating films 114, 116, and 210 supply oxygen to the metal oxides 108 and 208. That is, the insulating films 114, 116, and 210 contain oxygen. The film 114 is an insulating film that is permeable to oxygen. It also functions as a film for mitigating damage to the metal oxide 108 when forming the insulating film 116 that forms the metal oxide 108. do.

[0221] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0222] In addition, it is preferable that the insulating film 114 has a small number of defects. (ESR measurement) shows that g=2.001 is due to silicon dangling bonds. The spin density of the signal is 3×10 17 spins / cm 3 It is preferable that the following is true: If the insulating film 114 contains a large number of defects, oxygen will bond to the defects, causing the insulating film This is because the amount of oxygen permeating through 114 decreases.

[0223] In the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, In some cases, oxygen may move through the film 114. When the oxide insulating film capable of forming the insulating film 116 is formed over the insulating film 114, The desorbed oxygen can be transferred to the metal oxide 108 through the insulating film 114.

[0224] The insulating film 114 is formed using an oxide insulating film having a low density of states caused by nitrogen oxides. The density of states caused by the nitrogen oxides can be calculated by the valence electrons of the metal oxide. The energy of the upper edge of the conduction band (Ev_os) and the energy of the lower edge of the conduction band of metal oxides (Ec_ In some cases, the oxide insulating film may be formed during the period of the oxide insulating film. Silicon oxynitride film with low nitrogen oxide emission or aluminum oxynitride film with low nitrogen oxide emission etc. can be used.

[0225] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectrometry (TD S: Thermal Desorption Spectroscopy This is a membrane that releases more ammonia than elemental oxide, and is typically The amount is 1×10 18 cm -3 5×10 or more 19 cm -3 The following is the ammonia emission. The amount of leakage is determined when the surface temperature of the film is 50°C or more and 650°C or less, preferably 50°C or more and 550°C or less. This is the amount released due to heat treatment.

[0226] Nitrogen oxides (NO x , x is more than 0 and not more than 2, preferably 1 or more and not more than 2), typically NO2 or NO forms a level in the insulating film 114. 8. Therefore, the nitrogen oxide is in contact with the insulating film 114 and the metal When the oxide 108 diffuses to the interface, the level traps electrons on the insulating film 114 side. As a result, the trapped electrons may flow through the boundary between the insulating film 114 and the metal oxide 108. Since it remains near the surface, it shifts the threshold voltage of the transistor in the positive direction.

[0227] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with ammonia contained in the insulating film 116 during the heat treatment. Therefore, the amount of nitrogen oxide contained in the insulating film 114 is reduced. At the interface between the metal oxide 108 and the silicon dioxide, electrons are less likely to be trapped.

[0228] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0229] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less: The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.001 to 2.002. A second signal with a g value of .003 or less and a third signal with a g value between 1.964 and 1.966, inclusive. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The sum of the spin densities of the third signal is 1 × 10 18 spins / cm 3 Less than Typically, it is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Not yet It is full.

[0230] In the ESR spectrum below 100K, the g value is 2.037 or more and 2.039 or less. The first signal below, the second signal with a g-value between 2.001 and 2.003, and the g-value The sum of the spin densities of the third signal, which is greater than or equal to 1.964 and less than or equal to 1.966, is the nitrogen oxide Monster (NO x (x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2) It corresponds to the total density of the pins. Representative examples of nitrogen oxides include nitrogen monoxide, nitrogen dioxide, etc. That is, the first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.00 A second signal between 1 and 2.003 and a g value between 1.964 and 1.966. The smaller the total spin density of the third signal, the more the nitrogen oxide in the oxide insulating film is. It can be said that the content of the substance is low.

[0231] The nitrogen concentration of the oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 The following is the result.

[0232] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film by the VD method, a dense and hard film can be obtained. It can be formed.

[0233] The insulating films 116 and 210 are made of oxides containing more oxygen than the stoichiometric composition. It is preferable to form the insulating film using an insulating film. When the oxide insulating film containing oxygen is heated, some of the oxygen is released. The oxide insulating film containing more oxygen than the oxide insulating film is analyzed by TDS, and the amount of oxygen desorbed is calculated as oxygen atoms. The separation is 1.0×10 19 atoms / cm 3 More than 3.0×10 20 atom s / cm 3The oxide insulating film is the above temperature. The temperature range is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower.

[0234] The insulating films 116 and 210 have a thickness of 30 nm to 500 nm, preferably 50 Silicon oxide, silicon oxynitride, etc. having a thickness of 400 nm or more can be used.

[0235] In addition, it is preferable that the insulating films 116 and 210 have a small number of defects. Typically, the insulating films 116 and 210 have an ESR The measurement revealed that the signal at g = 2.001 originated from the dangling bond of silicon. Pin density is 1.5 x 10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 It is preferable that the insulating film 116 has a thickness of 100 nm or less than that of the insulating film 114. Since it is separated from the metal oxide 108, it may have a higher defect density than the insulating film 114.

[0236] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single layer structure or a laminated structure of three or more layers. Good too.

[0237] [Insulating film functioning as a protective insulating film] The insulating films 118 and 216 function as protective insulating films for the transistors.

[0238] The insulating films 118 and 216 contain either or both of hydrogen and nitrogen. Or, The insulating films 118 and 216 contain nitrogen and silicon. Has the ability to block oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 118, 216, oxygen from the metal oxide 108, 208 is prevented from escaping to the outside. The diffusion of oxygen contained in the insulating films 114, 116, and 210 to the outside, and the diffusion of gold from the outside This makes it possible to prevent hydrogen, water, etc. from entering the metal oxides 108 and 208.

[0239] For example, a nitride insulating film can be used as the insulating film 118, 216. Examples of insulating films include silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride. Minium, etc.

[0240] The various films described above, such as the conductive film, insulating film, metal oxide film, and metal film, are formed by sputtering. It can be formed by a ring method or a PECVD method, but other methods, such as thermal CVD ( It may be formed by the chemical vapor deposition method. As an example of the VD method, MOCVD (Metal Organic Chemical Vapor Deposition) or Deposition) method, or ALD (Atomic Layer Deposition) method Examples include the (sition) method.

[0241] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0242] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0243] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence.

[0244] Thermal CVD methods such as MOCVD and ALD are used to form the conductive film, insulating film, and metal oxide film of the above-mentioned embodiment. Various films, such as oxide films, can be formed.

[0245] <2-7. Manufacturing method of semiconductor device> Next, a manufacturing method of the transistor 200C which is a semiconductor device of one embodiment of the present invention will be described. This will be explained with reference to FIG. 13 to FIG.

[0246] 13(A) to 13(D), 14(A) to 14(C), and 15( 13A to 15C are cross-sectional views illustrating a method for manufacturing a semiconductor device. (A) to (D), (A) to (C), and (A) to (C) of FIG. 15. In (C), the left side is a cross-sectional view in the channel length direction, and the right side is a cross-sectional view in the channel width direction. It is.

[0247] First, a conductive film 206 is formed on a substrate 202. Next, the substrate 202 and the conductive film 206 are An insulating film 204 is formed on the insulating film 204, and a first metal oxide and a second metal oxide are formed on the insulating film 204. Then, the first metal oxide, the second metal oxide, and the third metal oxide are formed. The third metal oxide is processed into islands to form metal oxide 208_1a and metal oxide 208 _2a and a metal oxide 208_3a are formed (see FIG. 13(A)).

[0248] The conductive film 206 can be formed by selecting the above-mentioned material. In this example, a tungsten film having a thickness of 50 nm was deposited as the conductive film 206 using a sputtering apparatus. A laminate film is formed of a silicon film and a copper film having a thickness of 400 nm.

[0249] The conductive film to be the conductive film 206 can be processed by wet etching and drapery. In this embodiment, either one or both of the wet etching methods may be used. After etching the copper film by etching method, the tungsten film is removed by dry etching method. The conductive film is processed by etching to form a conductive film 206 .

[0250] The insulating film 204 can be formed by sputtering, CVD, vapor deposition, pulsed laser deposition ( The film can be formed by appropriately using a PLD method, a printing method, a coating method, or the like. In this case, a silicon nitride film having a thickness of 400 nm was deposited as the insulating film 204 using a PECVD apparatus. Then, a silicon oxynitride film having a thickness of 50 nm is formed.

[0251] After the insulating film 204 is formed, oxygen may be added to the insulating film 204. The oxygen added to 4 can be oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions. The doping method includes ion doping, ion implantation, plasma treatment, etc. In addition, a film for suppressing oxygen desorption is formed on the insulating film 204, and then the insulating film is Oxygen may be added to the insulating film 204 .

[0252] The above-mentioned oxygen desorption-suppressing film may be made of indium, zinc, gallium, tin, aluminum, or the like. Aluminum, Chromium, Tantalum, Titanium, Molybdenum, Nickel, Iron, Cobalt, or Tungsten The insulating film can be formed using a conductive film or a semiconductor film having one or more tennines.

[0253] In addition, when oxygen is added in plasma treatment, the oxygen is excited by microwaves to produce high-density oxygen. By generating atomic plasma, the amount of oxygen added to the insulating film 204 can be increased. .

[0254] The metal oxide 208_1a, the metal oxide 208_2a, and the metal oxide 208_3a are It is preferable to form the metal oxide 208 in a vacuum using a sputtering device. _1a, metal oxide 208_2a, and metal oxide 208_3a are sputtered by a sputtering apparatus. By forming the layers in a vacuum, impurities (e.g., hydrogen, Water, etc.) can be suppressed.

[0255] The conditions for forming the metal oxide 208_2a are as follows: It is preferable that the oxide 208_3a is formed at a lower oxygen partial pressure than either or both of the oxides 208_3a and 208_4a. It is nice.

[0256] In addition, the metal oxide 208_1a, the metal oxide 208_2a, and the metal oxide 208_3 When forming a, oxygen gas is mixed with an inert gas (e.g., helium gas, argon gas, In addition, the composition when forming the metal oxide 208_1a may be mixed with a gas such as cerium oxide gas. The ratio of oxygen gas to the total membrane gas (hereinafter referred to as the oxygen flow ratio) is 70% or more. 100% or less, preferably 80% or more and 100% or less, and more preferably 90% or more and 100% or less. % or less. In addition, the oxygen flow rate ratio when forming the metal oxide 208_2a is 0% or less. The metal oxide 208 is preferably from 5% to 15%. The oxygen flow rate ratio when forming 3a is 70% or more and 100% or less, preferably 80% More preferably, it is 90% or more and 100% or less.

[0257] The conditions for forming the metal oxide 208_2a are as follows: It may be formed at a lower substrate temperature than either or both of the oxides 208_3a.

[0258] Specifically, the conditions for forming the metal oxide 208_2a are as follows: the substrate temperature is set to 150° C. or higher than room temperature. The temperature may be set to less than 140° C., preferably from room temperature to 140° C. The conditions for forming the metal oxide 208_3a are as follows: the substrate temperature is from room temperature to 300° C. Preferably, the substrate temperature is set to a temperature between room temperature and 200° C. a, the substrate temperature during the formation of the metal oxide 208_2a and the metal oxide 208_3a is the same ( For example, a temperature of room temperature or higher but lower than 150° C. is preferable because it increases productivity.

[0259] By setting the above-mentioned formation conditions, the metal oxide 208_2a is 1a and the metal oxide 208_3a. do.

[0260] The thickness of the metal oxide 208_1a is 1 nm or more and less than 20 nm, preferably The thickness of the metal oxide 208_2a may be set to 5 nm or more and 10 nm or less. The thickness may be 20 nm or more and 100 nm or less, and preferably 20 nm or more and 50 nm or less. The thickness of the metal oxide 208_3a is 1 nm or more and less than 20 nm, preferably 5 nm or less. It may be set to 15 nm or less.

[0261] The metal oxide 208_1a, the metal oxide 208_2a, and the metal oxide 208_3 a is heated to form a film, whereby a metal oxide 208_1a, a metal oxide 208_2a, and The crystallinity of the metal oxide 208_3a can be improved. When using a type glass substrate (e.g., 6th generation to 10th generation), the metal oxide 208 _ The substrate temperature during the deposition of the metal oxide 208_1a, the metal oxide 208_2a, and the metal oxide 208_3a is If the temperature is set to 200° C. or higher and 300° C. or lower, the substrate 202 may deform (distort or warp). Therefore, when a large glass substrate is used, the metal oxide 208_1a and the gold The substrate temperature during the deposition of the metal oxide 208_2a and the metal oxide 208_3a was set at 100° C. By setting the heating temperature to 200° C. or higher and lower than 200° C., deformation of the glass substrate can be suppressed.

[0262] In addition, the sputtering gas must be highly purified. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using this, it is possible to prevent moisture and the like from being absorbed into the metal oxide as much as possible.

[0263] In addition, when forming a metal oxide film by sputtering, the thickness of the sputtering device is The chamber is equipped with a cryopump to remove water and other impurities that are harmful to metal oxides. A high vacuum (5×10 -7 Pa to 1×10 - 4 It is preferable to evacuate the gas to a pressure of about 10 Pa, especially when the sputtering device is in standby mode. The gas molecules equivalent to H2O (gas molecules equivalent to m / z = 18) in the chamber were analyzed. Pressure 1×10 -4 Pa or less, preferably 5×10 -5 It is preferable to set the pressure to 0.1 Pa or less.

[0264] The first metal oxide, the second metal oxide, and the third metal oxide are collectively referred to as metal oxide 2. To process the metal oxide 208_1a, metal oxide 208_2a, and metal oxide 208_3a, Either or both of a wet etching method and a dry etching method may be used.

[0265] In addition, the metal oxide 208_1a, the metal oxide 208_2a, and the metal oxide 208_3 After forming the metal oxide 208_1a, the metal oxide 208_2a, and the metal oxide 208_3a are heated. The metal oxide 208_3a may be dehydrogenated or dehydrated. Typically, the temperature is between 150° C. and the distortion point of the substrate, or between 250° C. and 450° C., or The temperature is between 300°C and 450°C.

[0266] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or It can be carried out in an inert gas atmosphere containing nitrogen. Alternatively, it can be heated in an inert gas atmosphere. After that, heating may be performed in an oxygen atmosphere. Note that hydrogen, water, etc. may be added to the inert atmosphere and oxygen atmosphere. It is preferable that the treatment time does not include the above-mentioned. The treatment time may be from 3 minutes to 24 hours.

[0267] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. The processing time can be reduced.

[0268] A metal oxide is formed while being heated, or a heat treatment is performed after the metal oxide is formed. By doing so, the hydrogen concentration obtained by SIMS in the metal oxide is increased by 5×10 19 atom s / cm 3 or less, or 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5×10 17 ato ms / cm 3 or less, or 1×10 16 atoms / cm 3 It can be as follows:

[0269] Next, the insulating film 210_0 is formed on the insulating film 204 and the metal oxide film 208_3a. See Figure 13(B).

[0270] The insulating film 210_0 may be a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. The silicon film is deposited in a plasma enhanced chemical vapor deposition (PECVD) system, or simply called a plasma CVD system. In this case, the source gas is a silicon-containing deposit. It is preferable to use an oxidizing gas and an insulating gas. Representative examples of the deposition gas containing silicon are: Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. These include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0271] In addition, for the insulating film 210_0, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas. The pressure in the treatment chamber should be 100P or more but less than 100 times, or 40 times or more but less than 80 times. By using a PECVD device with a pressure of less than a or 50 Pa or less, the amount of defects is reduced. A silicon nitride film can be formed.

[0272] In addition, as the insulating film 210_0, a film is placed in a vacuum-evacuated processing chamber of a PECVD apparatus. The substrate is maintained at a temperature of 280° C. or higher and 400° C. or lower, and a source gas is introduced into the processing chamber. The pressure in the chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. By supplying high-frequency power to the electrodes in the treatment chamber, the dense oxide A silicon film or a silicon oxynitride film can be formed.

[0273] The insulating film 210_0 may be formed by using a PECVD method using microwaves. Microwaves refer to the frequency range from 300MHz to 300GHz. The temperature is low and the electron energy is small. Also, the amount of power used to accelerate the electrons is small. The proportion of the oxygen that can be absorbed is small, and the oxygen can be used to dissociate and ionize a larger number of molecules. It is possible to excite a high density plasma. and forming an insulating film 210_0 with less defects by reducing plasma damage to the deposit. can be done.

[0274] In this embodiment, a PECVD apparatus is used to deposit a 100 nm thick insulating film 210_0. A silicon oxynitride film is formed.

[0275] Next, a mask is formed by lithography at a desired position on the insulating film 210_0, The insulating film 210_0 and part of the insulating film 204 are etched to reach the conductive film 206. An opening 243 is formed through the insulating layer 244 (see FIG. 13(C)).

[0276] The opening 243 can be formed by wet etching or dry etching. In this embodiment, a dry etching method is used. 2. The opening 243 is formed using the fluorine-containing ...

[0277] Next, the conductive film 21 is formed on the conductive film 206 and the insulating film 210_0 so as to cover the opening 243. In addition, when a metal oxide film is used as the conductive film 212_0, for example, In some cases, oxygen may be added to the insulating film 210_0 during the formation of the conductive film 212_0 (see FIG. 13( See D).

[0278] In FIG. 13D, oxygen added to the insulating film 210_0 is indicated by arrows. In addition, the conductive film 212_0 is formed so as to cover the opening 243. The conductive film 206 and the conductive film 212_0 are electrically connected to each other.

[0279] When a metal oxide film is used as the conductive film 212_0, the conductive film 212_0 is formed by the following method. In this case, it is preferable to use a sputtering method and form the layer in an atmosphere containing oxygen gas. The conductive film 212_0 is formed in an atmosphere containing oxygen gas, so that the insulating film 210 In addition, oxygen can be suitably added to the conductive film 212_0. The deposition method is not limited to the sputtering method, and other methods, such as the ALD method, may be used.

[0280] In this embodiment, the conductive film 212_0 is formed by a sputtering method. The thickness of the In-Ga-Zn oxide film was 100 nm (In:Ga:Zn=4:2:4.1 (atomic ratio) )) is formed. In addition, before or after the formation of the conductive film 212_0, In addition, oxygen addition treatment may be performed in the insulating film 210_0. The oxygen addition treatment may be the same as the oxygen addition treatment that can be performed after the insulating film 204 is formed.

[0281] Next, a mask 240 is formed at a desired position on the conductive film 212_0 by a lithography process. (See FIG. 14(A)).

[0282] Next, etching is performed from above the mask 240 to remove the conductive film 212_0 and the insulating film 210 After the conductive film 212_0 and the insulating film 210_0 are processed, the mask 24 By processing the conductive film 212_0 and the insulating film 210_0, an island-shaped conductive A film 212 and an island-shaped insulating film 210 are formed (see FIG. 14(B)).

[0283] In this embodiment, the conductive film 212_0 and the insulating film 212_1 are formed by dry etching. Process 210_0.

[0284] Note that when the conductive film 212_0 and the insulating film 210_0 are processed, the conductive film 212 overlaps with the insulating film 210_0. The thickness of the metal oxide 208 in the non-conductive region may be thin. When processing the insulating film 210_0, the insulating film 204 in the region where the metal oxide 208 does not overlap is In addition, the thickness of the conductive film 212_0 and the insulating film 210_0 may become thin. During this process, an etchant or etching gas (e.g., chlorine) is introduced into the metal oxide 208. The conductive film 212_0 or the insulating film 210_0 is added or the constituent element is a metal oxide. In some cases, the substance 208 may be added.

[0285] Next, an insulating film 216 is formed on the insulating film 204, the metal oxide film 208, and the conductive film 212. Note that by forming the insulating film 216, the metal oxide 208 in contact with the insulating film 216 is In addition, in the metal oxide 208 overlapping with the conductive film 212, a region 20 8i_1, a region 208i_2, and a region 208i_3 are formed. (See FIG. 14(C) ).

[0286] The insulating film 216 can be formed by selecting the above-mentioned material. In this example, a silicon oxynitride film having a thickness of 100 nm is deposited as the insulating film 216 using a PECVD apparatus. In forming the silicon oxynitride film, a plasma treatment is performed. The two steps of the plasma treatment, the deposition treatment and the deposition treatment, are carried out at a temperature of 220° C. Argon gas with a flow rate of 100 sccm and nitrogen gas with a flow rate of 1000 sccm were introduced into the chamber before the The pressure in the chamber was set to 40 Pa, and the RF power source (27.12 MHz) was turned on. The power of 1000W is supplied to the silane gas at a flow rate of 50sccm for the film formation process. The mixture was mixed with nitrogen gas at a flow rate of 5000 sccm and ammonia gas at a flow rate of 100 sccm. The pressure in the chamber was set to 100 Pa, and the RF power source (27.12 M It supplies 1000W of power to a frequency of 1000 Hz.

[0287] By using a silicon oxynitride film as the insulating film 216, the region in contact with the insulating film 216 Nitrogen or hydrogen in the silicon nitride oxide film can be supplied to 208n. By setting the temperature during the formation of the film 216 to the above temperature, the excess oxygen contained in the insulating film 210 is It is possible to suppress the release of the hydrogen to the outside.

[0288] Next, an insulating film 218 is formed over the insulating film 216 (see FIG. 15(A)).

[0289] The insulating film 218 can be formed by selecting the above-mentioned material. In this example, a PECVD apparatus is used to deposit a silicon oxynitride film having a thickness of 300 nm as the insulating film 218. Form a cone film.

[0290] Next, a mask is formed by lithography at a desired position on the insulating film 218, and then the insulating film 218 and a part of the insulating film 216 are etched to form an opening 2 41a and 241b are formed (see FIG. 15(B)).

[0291] The insulating film 218 and the insulating film 216 are etched by a wet etching method. Either one or both of the dry etching method and the dry etching method may be used. For this purpose, the insulating film 218 and the insulating film 216 are processed by dry etching.

[0292] Next, a conductive layer is formed on the region 208n and the insulating film 218 so as to cover the openings 241a and 241b. The conductive film is then processed into a desired shape to form the conductive films 220a and 220b. (See FIG. 15(C)).

[0293] The conductive films 220a and 220b can be formed by selecting the above-mentioned materials. In the embodiment, a sputtering device is used to deposit the conductive films 220a and 220b. A laminate film of a 50 nm thick tungsten film and a 400 nm thick copper film is formed.

[0294] The conductive films 220a and 220b are processed by wet etching. Either one or both of a rubbing method and a dry etching method may be used. The copper film is etched by wet etching, and then the tin film is removed by dry etching. The conductive film is processed by etching the stainless steel film to form conductive films 220a and 220b. do.

[0295] Through the above steps, a transistor 200C shown in FIGS. 11(A), 11(B), and 11(C) is manufactured. It is possible.

[0296] The films constituting the transistor (insulating film, metal oxide, conductive film, etc.) may be any of the above-mentioned In addition to the formation method, sputtering method, chemical vapor deposition (CVD) method, vacuum deposition method, pulse laser deposition method, The thin-film transistor can be formed by using a photochemical laser deposition (PLD) method or an ALD method. The film can be formed by a printing method. The film can be formed by a sputtering method, a plasma chemical vapor deposition method, etc. The deposition (PECVD) method is typical, but a thermal CVD method may also be used. Examples of thermal CVD methods include Metal-organic chemical vapor deposition (MOCVD) is one example.

[0297] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0298] Note that the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0299] (Embodiment 3) In this embodiment, a semiconductor device according to one embodiment of the present invention is used for a display portion or the like of a display device. An example of a display panel that can be used will be described with reference to FIGS. 17 and 18. The display panel shown in FIG. 1 has both a reflective liquid crystal element and a light emitting element, and is capable of displaying both a transmissive mode and a reflective mode. The display panel is capable of displaying both in the two modes. The metal oxide and the transistor having the metal oxide are used as a transistor of a pixel of a display device. Or a driver that drives a display device, or an LSI that supplies data to a display device, etc. It can be suitably used for the following:

[0300] <3-1. Display panel configuration examples> FIG. 17 is a perspective schematic diagram of a display panel 600 according to an embodiment of the present invention. 17 has a structure in which a substrate 651 and a substrate 661 are bonded together. is indicated by a dashed line.

[0301] The display panel 600 includes a display portion 662, a circuit 659, wiring 666, and the like. In the pixel 650, for example, a circuit 659, a wiring 666, a conductive film 663 functioning as a pixel electrode, and the like are provided. Figure 17 shows an example where IC673 and FPC672 are mounted on board 651. Therefore, the configuration shown in FIG. 17 includes the display panel 600, the FPC 672, and the I It can also be said to be a display module having C673.

[0302] The circuit 659 can be, for example, a circuit that functions as a scan line driver circuit.

[0303] The wiring 666 has a function of supplying signals and power to the display portion 662 and the circuit 659. Signals and power are input to the wiring 666 from the outside via FPC 672 or from IC 673. do.

[0304] In FIG. 17, a substrate 651 is formed by a COG (Chip On Glass) method or the like. The IC 673 is, for example, a scanning line driver circuit, Alternatively, an IC having a function as a signal line driver circuit or the like can be applied. 0 includes a circuit that functions as a scanning line driver circuit and a signal line driver circuit, The circuit that functions as the signal line driver circuit is provided externally, and the display panel is connected to the FPC672. When inputting a signal to drive the module 600, the IC 673 is not provided. Also, IC673 may be mounted on a F It may also be implemented in PC672.

[0305] FIG. 17 shows an enlarged view of a part of the display unit 662. The display unit 662 has a plurality of displays. The conductive film 663 of the display element is arranged in a matrix. The liquid crystal display 600 functions as a reflective electrode for the liquid crystal element 640 described later.

[0306] 17, the conductive film 663 has an opening. A light emitting element 660 is provided on the substrate 651 side. The light from the light emitting element 660 is incident on a conductive film 663. The light is emitted to the substrate 661 side through the opening.

[0307] <3-2. Example of cross-sectional structure> FIG. 18 shows a part of the area including the FPC 672 and the circuit 65 of the display panel shown in FIG. 9 and a section of a region including a display unit 662. An example is shown below.

[0308] The display panel has an insulating film 620 between a substrate 651 and a substrate 661. Between the insulating film 620 and the light-emitting element 660, the transistor 601, the transistor 605, The transistor 606, the coloring layer 634, and the like are included. In addition, between the insulating film 620 and the substrate 661, The substrate 661 and the insulating film 620 are bonded to each other by an adhesive layer 64. 1, and the substrate 651 and the insulating film 620 are bonded via an adhesive layer 642. .

[0309] The transistor 606 is electrically connected to the liquid crystal element 640. The transistor 605 and the transistor 606 are electrically connected to the optical element 660. Since the insulating film 620 is also formed on the surface of the substrate 651 side, these can be formed by the same process. It can be made by

[0310] The substrate 661 is provided with a colored layer 631, a light-shielding film 632, an insulating film 621, and a liquid crystal element 640. A conductive film 613 functioning as a common electrode, an alignment film 633b, an insulating film 617, etc. are provided. The insulating film 617 functions as a spacer to maintain the cell gap of the liquid crystal element 640. It works.

[0311] On the substrate 651 side of the insulating film 620, an insulating film 681, an insulating film 682, an insulating film 683, and an insulating film 684 are provided. Insulating layers such as a film 684 and an insulating film 685 are provided. The insulating film 682, the insulating film 683, and the insulating film 684 function as a gate insulating layer of the transistor. The insulating film 684 is provided to cover each transistor. 5 is provided. The insulating film 684 and the insulating film 685 function as planarizing layers. Here, an insulating film 682, an insulating film 683, and an insulating film 684 are used as insulating layers covering transistors and the like. Although the embodiment shows a case in which the membrane 684 has three layers, the present invention is not limited to this and may have four or more layers. The insulating film 684 serving as a planarization layer may be a single layer or a two-layer structure. If not required, it need not be provided.

[0312] In addition, the transistors 601, 605, and 606 are partially A conductive film 654 functions as a gate, and a conductive film 655 functions as a source or drain. 52 and a semiconductor film 653. In this example, the same conductive film is processed into multiple layers. , have the same hatching pattern.

[0313] The liquid crystal element 640 is a reflective liquid crystal element. The liquid crystal element 640 includes a conductive film 635, a liquid crystal layer The conductive film 635 has a laminated structure in which a conductive film 612 and a conductive film 613 are laminated. A conductive film 663 that reflects visible light is provided in contact with the opening 655. The conductive film 635 and the conductive film 613 contain a material that transmits visible light. An alignment film 633a is provided between the liquid crystal layer 612 and the conductive film 635. An alignment film 633b is provided between the substrate 661 and the polarizing plate 65. Has 6.

[0314] In the liquid crystal element 640, the conductive film 663 has a function of reflecting visible light, and the conductive film 613 The light incident from the substrate 661 side is polarized by the polarizing plate 656. The light is polarized, passes through the conductive film 613 and the liquid crystal layer 612, and is reflected by the conductive film 663. The light passes through the conductive film 612 and the conductive film 613 again and reaches the polarizing plate 656. The orientation of the liquid crystal is controlled by applying a voltage between the conductive film 635 and the conductive film 613. That is, the intensity of the light emitted through the polarizing plate 656 can be controlled. In addition, the colored layer 631 absorbs light outside a specific wavelength range. By collecting the light, the extracted light becomes, for example, red light.

[0315] The light emitting element 660 is a bottom emission type light emitting element. A laminate in which a conductive film 643, an EL layer 644, and a conductive film 645b are laminated in this order from the film 620 side. In addition, a conductive film 645a is provided to cover the conductive film 645b. The conductive film 45b includes a material that reflects visible light, and the conductive film 643 and the conductive film 645a transmit visible light. The light emitted by the light emitting element 660 is guided through the colored layer 634, the insulating film 620, the opening 65, and the insulating film 620. 5. The light is emitted to the substrate 661 side through the conductive film 613 and the like.

[0316] Here, as shown in FIG. 18, a conductive film 635 that transmits visible light is provided in the opening 655. In this way, even in the area overlapping with the opening 655, the other area Since the liquid crystal is oriented in the same way as in the other regions, the alignment of the liquid crystal is poor at the boundaries between these regions, resulting in unintended alignment of the liquid crystal. This can prevent unwanted light from leaking out.

[0317] Here, a linear polarizing plate may be used as the polarizing plate 656 disposed on the outer surface of the substrate 661. However, a circular polarizer can also be used. For example, a linear polarizer and a 1 / 4 wave A laminate of long retardation plates can be used. This can suppress the reflection of external light. In addition, the cell gap of the liquid crystal element used in the liquid crystal element 640 can be adjusted according to the type of the polarizing plate. By adjusting the flip-flop, orientation, driving voltage, etc., the desired contrast can be achieved. good.

[0318] An insulating film 647 is provided in contact with a part of the insulating film 646 that covers the end of the conductive film 643. The insulating film 647 prevents the insulating film 620 and the substrate 651 from coming closer than necessary. The EL layer 644 and the conductive film 645a are covered with a shielding mask (mesh When forming the insulating film using a mask, the mask is prevented from contacting the surface to be formed. Note that the insulating film 647 does not have to be provided if it is not necessary.

[0319] One of the source and drain of the transistor 605 is connected to the light-emitting element 6 through a conductive film 648. It is electrically connected to the conductive film 643 of 60 .

[0320] One of the source and drain of the transistor 606 is connected to the conductive film 66 through a connection portion 607. The conductive film 663 and the conductive film 635 are provided in contact with each other. Here, the connection portion 607 is electrically connected through an opening provided in the insulating film 620. In other words, it is a portion that connects the conductive layers provided on both sides of the insulating film 620 to each other.

[0321] A connection portion 604 is provided in the area where the substrate 651 and the substrate 661 do not overlap. The connection portion 604 is electrically connected to the FPC 672 via the connection layer 649. The upper surface of the connection portion 604 is the same as the conductive film 635. The conductive layer obtained by processing the first conductive film is exposed. C672 can be electrically connected via a connection layer 649.

[0322] A connection portion 687 is provided in a portion of the area where the adhesive layer 641 is provided. In 87, a conductive layer obtained by processing the same conductive film as the conductive film 635 and a conductive film 613 A part of the wiring is electrically connected to the substrate 661 by the connector 686. A signal input from an FPC 672 connected to the substrate 651 side is input to the conductive film 613 formed on the substrate 651 side. or a potential can be provided via connection 687.

[0323] The connector 686 may be, for example, a conductive particle. For this purpose, it is possible to use particles of organic resin or silica coated with a metal material. It is preferable to use nickel or gold as the metal material because it is possible to reduce the contact resistance. Particles coated with layers of two or more metal materials, such as nickel coated with gold, are It is preferable to use a material that is elastically deformable or plastically deformable as the connector 686. In this case, the connector 686, which is a conductive particle, is preferably used as shown in FIG. In this way, the connector 686 and the This increases the contact area with the electrically conductive layer, reducing contact resistance and preventing connection failures. The occurrence of such defects can be suppressed.

[0324] The connector 686 is preferably disposed so as to be covered with the adhesive layer 641. For example, The connectors 686 may be dispersed in the adhesive layer 641 before curing.

[0325] FIG. 18 shows an example of a circuit 659 in which a transistor 601 is provided. do.

[0326] In FIG. 18, a transistor 601 and a transistor 605 are shown as examples in which a channel is formed. The semiconductor film 653 is sandwiched between two gates. The other gate is a conductive film overlapping the semiconductor film 653 via the insulating film 682. The film 623 is used as the gate insulating film. The voltage can be controlled by connecting two gates and applying the same signal to them. Such a transistor may be driven by supplying a It is possible to increase the field effect mobility compared to conventional transistors, and increase the on-current. As a result, a circuit capable of high speed operation can be fabricated. By using a transistor with a large on-current, Even if the number of wirings increases when the display panel is made larger or has higher resolution, each wiring It is possible to reduce signal delay in the lines, and to suppress display unevenness.

[0327] Note that the transistors in the circuit 659 and the transistors in the display portion 662 are the same. The multiple transistors in the circuit 659 may all have the same structure. Alternatively, transistors having different structures may be used in combination. The multiple transistors in 662 may all have the same structure, or may have different structures. Transistors may also be used in combination.

[0328] At least one of the insulating film 682 and the insulating film 683 that cover each transistor is resistant to water and hydrogen. It is preferable to use a material in which impurities are unlikely to diffuse, such as the insulating film 682. In this case, the insulating film 683 can function as a barrier film. It is possible to effectively suppress the diffusion of impurities into the transistor from the outside. This makes it possible to realize a highly reliable display panel.

[0329] On the substrate 661 side, an insulating film 621 is provided to cover the colored layer 631 and the light-shielding film 632. The insulating film 621 may function as a planarizing layer. Since the surface of the conductive film 613 can be made substantially flat, the alignment state of the liquid crystal layer 612 can be made uniform. do.

[0330] An example of a method for manufacturing the display panel 600 will be described. A conductive film 635, a conductive film 663, and an insulating film 620 are formed in this order on a substrate. After forming the stator 605, the transistor 606, the light emitting element 660, etc., Then, the substrate 651 and the support substrate are bonded together. Then, the separation layer and the insulating film 620, and the separation layer and the conductive The support substrate and the release layer are removed by peeling off the conductive film 635 at their respective interfaces. In addition, a colored layer 631, a light-shielding film 632, a conductive film 613, etc. are formed on a substrate in advance. A plate 661 is prepared. Then, liquid crystal is dropped onto the substrate 651 or the substrate 661, and an adhesive layer 641 is formed. By bonding the substrate 651 and the substrate 661 together, the display panel 600 can be manufactured. can.

[0331] For the peeling layer, a material that causes peeling at the interface between the insulating film 620 and the conductive film 635 is appropriately selected. In particular, a layer containing a high melting point metal material such as tungsten can be used as the release layer. A layer containing an oxide of the metal material is laminated, and a nitride film is used as an insulating film 620 on the peeling layer. It is preferable to use a multi-layer structure including silicon, silicon oxynitride, silicon oxynitride, etc. When a high melting point metal material is used for the peeling layer, the formation temperature of the subsequent layers is increased. This makes it possible to reduce the concentration of impurities and realize a highly reliable display panel.

[0332] The conductive film 635 is made of an oxide or a nitride such as a metal oxide or a metal nitride. When a metal oxide is used, hydrogen, boron, phosphorus, nitrogen, and the like are preferably used. At least one of the concentration of other impurities and the amount of oxygen vacancies is determined by the concentration of the other impurities in the semiconductor layer used in the transistor. The conductive film 635 may be made of a material having a higher thermal conductivity than that of the conductive film 635.

[0333] <3-3. About each component> Each of the above components will be described below.

[0334] [Adhesive layer] The adhesive layer may be a light-curing adhesive such as an ultraviolet-curing adhesive, a reaction-curing adhesive, or a heat-curing adhesive. Various curing adhesives such as viscoelastic adhesives, anaerobic adhesives, etc. can be used. Epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, E VA (ethylene vinyl acetate) resin, etc. In particular, the moisture permeability of epoxy resin, etc. A material with low adhesion is preferable. Two-part mixed resin may also be used. It may be used.

[0335] The resin may contain a desiccant. For example, an oxide of an alkaline earth metal (an acid The material used is one that adsorbs moisture by chemical adsorption, such as calcium chloride or barium oxide. Alternatively, materials such as zeolite and silica gel can absorb water by physical adsorption. If a desiccant is included, impurities such as moisture may enter the element. This is preferable because it can suppress the occurrence of the problem of the noise and improve the reliability of the display panel.

[0336] In addition, by mixing a filler with a high refractive index or a light scattering material into the resin, it is possible to improve the light extraction efficiency. For example, titanium oxide, barium oxide, zeolite, and di Ruthenium, etc. can be used.

[0337] [Connection layer] The connection layer is made of anisotropic conductive film (ACF). conductive film) and anisotropic conductive paste (ACP) Conductive Paste) can be used.

[0338] [Colored layer] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. Examples of such materials include resin materials.

[0339] [Light blocking layer] Materials that can be used for the light-shielding layer include carbon black, titanium black, Examples of the material include a metal, a metal oxide, and a composite oxide including a solid solution of a plurality of metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, the light-shielding layer may be a laminated film of a film containing the material of the colored layer. A film containing a material for a colored layer that transmits light and a material for a colored layer that transmits light of another color By using the same material for the colored layer and the light-shielding layer, a laminated structure with a film containing This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0340] The above is a description of each component.

[0341] <3-4. Example of manufacturing method> Here, an example of a method for manufacturing a display panel using a flexible substrate will be described.

[0342] Here, the following elements are included: display elements, circuits, wiring, electrodes, optical members such as colored layers and light-shielding layers, and insulating layers. For example, the element layer includes a display element. In addition to display elements, wiring electrically connecting to display elements, transistors used in pixels and circuits, etc. The device may include the following elements:

[0343] In addition, in this case, at the stage where the display element is completed (the manufacturing process is completed), the element layer is The supporting and flexible member is called a substrate. For example, the substrate may have a thickness of This also includes extremely thin films with a thickness of 10 nm or more and 300 μm or less.

[0344] Representative methods for forming an element layer on a substrate having a flexible insulating surface include There are two methods as follows: One is to form an element layer directly on a substrate. The other is to form an element layer on a support substrate different from the substrate, and then peel the element layer from the support substrate. The method is to transfer the element layer to the substrate by using a semiconductor device. In addition to the above method, an element layer is formed on a non-flexible substrate, and the substrate is thinned by polishing or the like. There is also a method for providing flexibility by

[0345] If the material constituting the substrate is heat resistant to the heat applied in the process of forming the element layer, It is preferable to form the element layer directly on the substrate, since the process is simplified. If the element layer is formed while the plate is fixed to the support substrate, the plate can be easily transported within and between devices. This is preferable because it is easier.

[0346] In addition, when a method of forming an element layer on a supporting substrate and then transferring the element layer to the substrate is used, the element layer is first A release layer and an insulating layer are laminated on a supporting substrate, and an element layer is formed on the insulating layer. The element layer is then transferred to the substrate by peeling the element layer from the support substrate. It is only necessary to select a material that causes peeling at the interface between the peeling layer and the insulating layer or within the peeling layer. In this method, a material having high heat resistance is used for a support substrate and a peeling layer, and thus an element layer is formed. This allows the upper limit of the temperature during the formation of the semiconductor device to be increased, forming a device layer having more reliable devices. This is preferable because it is possible.

[0347] For example, a layer containing a high melting point metal material such as tungsten as a peeling layer and a layer containing the metal material A layer containing an oxide is laminated, and silicon oxide or silicon nitride is used as an insulating layer on the peeling layer. It is preferable to use a stack of a plurality of layers of silicon oxynitride, silicon nitride oxide, or the like.

[0348] The element layer and the support substrate can be separated by applying a mechanical force or by etching the separation layer. Examples include etching the surface or allowing a liquid to penetrate the peeled interface. Alternatively, the difference in thermal expansion coefficient between the two layers that form the peeling interface can be utilized to heat or cool the material. The peeling may be performed by

[0349] Furthermore, if peeling is possible at the interface between the support substrate and the insulating layer, there is no need to provide a peeling layer.

[0350] For example, glass is used as the support substrate, and an organic resin such as polyimide is used as the insulating layer. At this time, a part of the organic resin is locally heated using a laser beam or the like. Or, the organic resin is physically cut or penetrated with a sharp object to remove it. Alternatively, the starting point of the peeling may be formed at the interface between the glass and the organic resin. As a material for the opening, a photosensitive material is preferable because it is easy to create the shape of the opening. The above-mentioned laser light is, for example, light in the wavelength range from visible light to ultraviolet light. For example, light having a wavelength of 200 nm or more and 400 nm or less, preferably light having a wavelength of Light with a wavelength of 250 nm or more and 350 nm or less can be used. The use of a sigma laser is preferable because of its excellent productivity. Solid-state UV lasers (also called semiconductor UV lasers) such as the 355 nm UV laser, which is a harmonic (referred to as "the first method") may also be used.

[0351] Alternatively, a heat generating layer is provided between a support substrate and an insulating layer made of an organic resin, and the heat generating layer is heated. The heat generating layer may be formed by applying a current to the heat generating layer and the insulating layer. Materials that generate heat when current flows through them, materials that generate heat when light is absorbed, and materials that generate heat when a magnetic field is applied. For example, the heat generating layer can be made of various materials such as The material to be used can be selected from the group consisting of semiconductors, metals, and insulators.

[0352] In the above-mentioned method, the insulating layer made of organic resin is used as a substrate after peeling. It is possible.

[0353] The above is a description of the method for producing a flexible display panel.

[0354] Note that the structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination. [Explanation of symbols]

[0355] P1 area P2 area P3 area P4 area P5 area P6 area P7 area P8 area 001 area 002 Area 100A Transistor 100B Transistor 100C transistor 100D Transistor 102 Substrate 104 Insulating film 106 Conductive Film 108 Metal Oxides 108_1 Metal oxides 108_2 Metal oxides 108_3 Metal oxides 112a Conductive film 112b Conductive film 112c conductive film 114 Insulating film 116 Insulating film 118 Insulating film 120a Conductive film 120b Conductive film 151 Opening 152a opening 152b opening 200A Transistor 200B Transistor 200C transistor 200D Transistor 202 Substrate 204 Insulating film 206 Conductive Film 208 Metal Oxides 208_1a Metal oxides 208_2a Metal oxide 208_3a Metal oxides 208i area 208i_1 area 208i_2 area 208i_3 area 208n area 210 Insulating film 210_0 Insulating film 212 Conductive Film 212_0 Conductive film 216 Insulating film 218 Insulating film 220a Conductive film 220b Conductive film 240 Mask 241a opening 241b opening 243 Opening 600 Display Panel 601 Transistor 604 Connection 605 Transistor 606 Transistor 607 Connection 612 Liquid crystal layer 613 Conductive Film 617 Insulating film 620 Insulating film 621 Insulating film 623 Conductive Film 631 Colored layer 632 Light-shielding film 633a Orientation film 633b Alignment film 634 Colored layer 635 Conductive Film 640 Liquid crystal element 641 Adhesive layer 642 Adhesive layer 643 Conductive Film 644 EL layer 645a Conductive film 645b Conductive film 646 Insulating Film 647 Insulating Film 648 Conductive Film 649 Connection Layer 651 Substrate 652 Conductive film 653 Semiconductor Film 654 Conductive film 655 Aperture 656 Polarizing Plate 659 Circuit 660 Light emitting element 661 Substrate 662 Display section 663 Conductive Film 666 Wiring 672 FPC 673 IC 681 Insulating film 682 Insulating film 683 Insulating Film 684 Insulating film 685 Insulating Film 686 Connectors 687 Connection

Claims

[Claim 1] a metal oxide, a pair of electrodes in contact with the metal oxide, an insulator in contact with the metal oxide, and a gate electrode overlapping the metal oxide with the insulator interposed therebetween; The metal oxide is A first region and a second region are included. the first region and the second region are mixed in a mosaic pattern, the energy level of the second region at the bottom of the conduction band is lower by 0.2 eV or more than the energy level of the first region at the bottom of the conduction band; The energy gap of the first region is 3.3 eV or more and 4.0 eV or less, The energy gap of the second region is 2.2 eV or more and 2.9 eV or less.

Images