Varistor array containing matched varistor

Abstract

To provide a varistor array having an overlapping area of an alignment non-sensibility, and a formation method of the same.SOLUTION: In a varistor array 100, a first varistor 114 contains: a first external terminal 116 that can be formed to a monolithic body, and is in a first end part of the monolithic body; a plurality of first electrodes 118 that is connected to the first external terminal; a second external terminal 120 that is in a second end part of the monolithic body; and a plurality of second electrodes 122 that is connected to the second external terminal. The plurality of second electrodes is interleaved to the plurality of first electrodes, and is overlapped with the plurality of first electrodes in an overlapping area 123. The overlapping area is not sensitive in regard to a misalignment if a relative misalignment between the plurality of first electrodes and the plurality of second electrodes is smaller than a threshold value. A second varistor 130 can be formed in the monolithic body, and can be separated from the first varistor.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 159514, filed March 11, 2021, the entirety of which is incorporated herein by reference.

[0002] 2. Background of the Invention The subject matter herein relates generally to electronic components adapted for mounting on a circuit board, and more particularly to varistor arrays. [Background technology]

[0003]

[0003] Multilayer ceramic devices, such as varistor arrays, are typically constructed with multiple stacked dielectric-electrode layers. During fabrication, the layers are often pressed together into a vertically stacked structure. Multilayer ceramic devices can contain a single component or multiple components in an array.

[0004]

[0004] Varistors are voltage-dependent nonlinear resistors that are used as surge absorbing electrodes, arresters, and voltage stabilizers. They can be connected, for example, in parallel with sensitive electrical components. The nonlinear resistance response of a varistor is often characterized by a parameter known as the clamping voltage. For applied voltages less than the clamping voltage of the varistor, the varistor generally has a very high resistance and therefore behaves similar to an open circuit. However, when the varistor is exposed to a voltage greater than its clamping voltage, its resistance is reduced and the varistor behaves similar to a short circuit, allowing more current to flow. This nonlinear response can be used to divert current surges and / or to prevent voltage spikes from damaging sensitive electrical components.

[0005]

[0005] Some applications can benefit from two or more varistors with closely matched characteristics, such as capacitance, etc. However, the individual varistors generally do not have characteristics that are sufficiently similar. Summary of the Invention

[0006]

[0006] According to one embodiment of the present disclosure, a varistor array can include a monolithic body including a plurality of dielectric layers stacked in a Z-direction perpendicular to a vertical direction. The monolithic body can have a first end and a second end spaced apart in a vertical direction from the first end. A first varistor can be formed in the monolithic body. The first varistor can include a first external terminal at the first end of the monolithic body, a first plurality of electrodes connected to the first external terminal, a second external terminal at the second end of the monolithic body, and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes with an overlap area, the overlap area being insensitive to relative misalignment between the first plurality of electrodes and the second plurality of electrodes when the misalignment is less than a threshold value. A second varistor can be formed in the monolithic body, the second varistor can be separate from the first varistor, and can include a first external terminal at a first end of the monolithic body and a second external terminal at a second end of the monolithic body.

[0007]

[0007] According to another embodiment of the present disclosure, the varistor array may include a monolithic body including a plurality of dielectric layers stacked in a Z direction perpendicular to the longitudinal direction. The monolithic body may have a first end and a second end spaced apart from the first end in the longitudinal direction. The first varistor may be formed in the monolithic body, and the second varistor may be formed in the monolithic body and may be separate from the first varistor. The first varistor may include a first external terminal at the first end of the monolithic body, a first plurality of active electrodes connected to the first external terminal, a second external terminal at the second end of the monolithic body, and a second plurality of active electrodes connected to the second external terminal. Each active electrode of the second plurality of active electrodes may be coplanar with each active electrode of the first plurality of active electrodes. The plurality of floating electrodes can overlap the first plurality of active electrodes along a first overlap area, the first overlap area being insensitive to relative misalignment between the first plurality of active electrodes and the plurality of floating electrodes. The floating electrodes can overlap the second plurality of active electrodes along a second overlap area, the second overlap area being insensitive to relative misalignment between the second plurality of active electrodes and the plurality of floating electrodes below a threshold.

[0008]

[0008] According to another embodiment of the present disclosure, the varistor array may include a monolithic body including a plurality of dielectric layers stacked in a Z direction perpendicular to the longitudinal direction. The monolithic body may have a first end and a second end spaced apart from the first end in the longitudinal direction. The first varistor may be formed in the monolithic body. The first varistor may include a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body, a first plurality of electrodes connected to the first external terminal, and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes of the first varistor may be interleaved with the first plurality of electrodes of the first varistor and may overlap the first plurality of electrodes of the first varistor at a first overlap area. The second varistor may be formed in the monolithic body. The second varistor may be separate from the first varistor and may include a first external terminal at a first end of the monolithic body and a second external terminal at a second end of the monolithic body. The first plurality of electrodes may be connected to the first external terminal. The second plurality of electrodes may be connected to the second external terminal. The second plurality of electrodes of the second varistor overlap the first plurality of electrodes of the second varistor at a second overlap area. A ratio of the first overlap area to the second overlap area may range from 0.9 to 1.1.

[0009]

[0009] A complete and enabling disclosure of the subject matter herein is set forth in the specification, which disclosure contains the best mode of the subject matter and is directed to a person skilled in the art, and the specification refers to the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1A] FIG. 1A is a simplified top-down view of a varistor array in accordance with aspects of the present disclosure. [Figure 1B]FIG. 1B is a side view of the varistor array of FIG. 1A taken along section AA of FIG. 1A. [Figure 1C] FIG. 1C shows the first layer of the varistor array of FIGS. 1A and 1B. [Figure 1D] FIG. 1D shows a second layer of the varistor array of FIGS. 1A and 1B. [Figure 2A] FIG. 2A shows a simplified top-down view of a varistor array in accordance with aspects of the present disclosure. [Figure 2B] FIG. 2B is a side view of the varistor array of FIG. 2A taken along section AA of FIG. 2A. [Diagram 3] FIG. 3 illustrates another example embodiment of a varistor array in accordance with aspects of the present disclosure. [Figure 4] FIG. 4 is a flow chart of a method of forming a varistor array in accordance with an aspect of the present disclosure. [Diagram 5] FIG. 5 shows the current wave for testing varistors according to ANSI standard C62.1. [Figure 6] FIG. 6 illustrates a voltage response curve of a varistor according to an aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0020] Repeated use of reference characters throughout this specification and the accompanying drawings is intended to represent the same or similar features, electrodes or steps in the subject matter herein.

[0012] Detailed Description of the Preferred Embodiments

[0021] Those skilled in the art will appreciate that the present disclosure is a description of example embodiments only, and is not intended to limit the broad aspects of the subject matter herein, which may be implemented in the illustrated configurations.

[0013]

[0022] In general, the present disclosure relates to a varistor array having two or more varistors. The varistors may have closely matched electrical performance characteristics, such as capacitance, insertion loss, etc. During fabrication, slight misalignment between the various layers of a multilayer ceramic component may result in slight variations in the size of the overlap area between the electrodes. However, a varistor array according to features of the present disclosure may provide two or more varistors with alignment-insensitive overlap areas. As a result, the varistor array may exhibit capacitance values ​​and / or other electrical performance characteristics that are closely matched to one another, despite small misalignments of the various layers that may occur during fabrication of the varistor array.

[0014]

[0023] For example, a varistor array can include a first varistor having overlapping electrodes that overlap along a first overlap area and a second varistor having overlapping electrodes that overlap along a second overlap area. The ratio of the first overlap area to the second overlap area can range from about 0.9 to about 1.1, in some embodiments from about 0.92 to about 1.08, in some embodiments from about 0.94 to about 1.06, in some embodiments from about 0.96 to about 1.04, and in some embodiments from about 0.98 to about 1.02. However, in alternative embodiments, the ratio of the first overlap area to the second overlap area can be any suitable number as desired by design considerations.

[0015]

[0024] For example, the varistors of the varistor array can include multiple electrodes with suitable geometric configurations such that their individual overlap areas are insensitive to small misalignments between the various layers. In other words, small misalignments can have little or no effect on the absolute size of the first and second overlap areas and / or on the ratio of the first and second overlap areas. As a result, the varistor array can include multiple individual varistors with closely controlled overlap areas, which can provide very closely matched performance characteristics.

[0016]

[0025] A varistor array according to an aspect of the present disclosure may include a monolithic body including a plurality of dielectric layers stacked in a Z-direction. The varistor array may include a first varistor formed in the monolithic body. The first varistor may include a first external terminal at a first end of the monolithic body. The first varistor may include a first plurality of electrodes connected to the first external terminal. The first varistor may include a second external terminal at a second end of the monolithic body. The first varistor may include a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes may be interleaved with the first plurality of electrodes and may overlap the first plurality of electrodes with an overlap area, the overlap area being insensitive to relative misalignment between the first and second plurality of electrodes if the misalignment is less than a threshold value.

[0017]

[0026] For example, the second plurality of electrodes can have a lateral width greater than the width of the first plurality of electrodes in the lateral direction. The width of the overlap area between the first plurality of electrodes and the second plurality of electrodes can be equal to the width of the first plurality of electrodes. Alternatively, the width of the second plurality of electrodes can be smaller than the width of the first plurality of electrodes. The width of the overlap area between the first plurality of electrodes and the second plurality of electrodes can be equal to the width of the second plurality of electrodes.

[0018]

[0027] The second varistor can be formed in the monolithic body. The second varistor can be separate from the first varistor. For example, the second varistor can be free of the internal electrodes (e.g., floating electrodes, active electrodes, etc.) included in the first varistor. The second varistor can be free of external terminals included in and / or connected to the first varistor. Additionally, the second varistor is laterally separated from the first varistor.

[0019]

[0028] The first varistor may include a first external terminal at a first end of the monolithic body and a second external terminal at a second end of the monolithic body. The second varistor may include a first plurality of electrodes connected to the first external terminal and a second plurality of electrodes connected to the second external terminal. The second plurality of electrodes of the second varistor may overlap the first plurality of electrodes of the second varistor at an overlap area, the overlap area being insensitive to relative misalignment between the first plurality of electrodes of the second varistor and the second plurality of electrodes of the second varistor if the misalignment is less than a threshold value.

[0020]

[0029] As described herein, the varistor array may include two varistors, however, in some embodiments the varistor array may include four or more varistors, in some embodiments six or more varistors, in some embodiments eight or more varistors, and in some embodiments ten or more varistors.

[0021]

[0030] The total overlap area of ​​the first varistor, in some embodiments, can be about 10% or less of the total overlap area of ​​the second varistor, in some embodiments, about 5% or less, in some embodiments, about 3% or less, in some embodiments, about 2% or less, in some embodiments, about 1% or less, and in some embodiments, about 0.5% or less.

[0022]

[0031] The one or more varistors may represent a capacitance of less than 50 pF with a DC bias of 0.0 volts and a 0.5 volt root mean square sine wave signal at an operating frequency of 1 MHz, a temperature of about 23° C., and a relative humidity of 25%. For example, a first varistor may represent a first capacitance and a second varistor may represent a second capacitance that is within 5% of the first capacitance represented by the first varistor.

[0023]

[0032] According to a feature of the present disclosure, the varistor array can include a floating electrode. The varistor array can include a monolithic body including a plurality of dielectric layers stacked in a Z-direction. A first varistor can be formed in the monolithic body, and a second varistor can be formed in the monolithic body, separate from the first varistor.

[0024]

[0033] The first varistor may include a first external terminal at a first end of the monolithic body and a first plurality of active electrodes connected to the first external terminal. The first varistor may include a second external terminal at a second end of the monolithic body. The second plurality of active electrodes may be connected to the second external terminal. Each active electrode of the second plurality of active electrodes may be coplanar with each active electrode of the first plurality of active electrodes. The plurality of floating electrodes may overlap with the first plurality of active electrodes along a first overlap area, the first overlap area being insensitive to relative misalignment between the first plurality of active electrodes and the plurality of floating electrodes. The floating electrodes may overlap with the second plurality of active electrodes along a second overlap area, the second overlap area being insensitive to relative misalignment between the second plurality of active electrodes and the plurality of floating electrodes that is less than a threshold value.

[0025]

[0034] For example, the plurality of floating electrodes can have a lateral width greater than a width of the first plurality of active electrodes in the lateral direction, and a width of a first overlap area between the plurality of floating electrodes and the first plurality of active electrodes can be equal to a width of the first plurality of active electrodes. As another example, the floating electrodes can have a lateral width less than a width of the first plurality of active electrodes in the lateral direction, and a width of a first overlap area between the plurality of floating electrodes and the first plurality of active electrodes can be equal to a width of the plurality of floating electrodes.

[0026]

[0035] The second varistor may include a plurality of floating electrodes separate from the plurality of floating electrodes of the first varistor. The floating electrodes of the second varistor may be electrically isolated from the floating electrodes of the first varistor. For example, the floating electrodes of the second varistor may be laterally spaced apart from the floating electrodes of the first varistor.

[0027]

[0036] The second varistor may be generally configured similarly to the first varistor. For example, the second varistor may include a first plurality of active electrodes overlapping the plurality of floating electrodes at a first overlap area. The second varistor may include a second plurality of active electrodes overlapping the plurality of floating electrodes at a second overlap area.

[0028]

[0037] In some embodiments, a varistor array according to features of the present disclosure may exhibit low capacitance. For example, one or more of the varistors of the varistor array may have a capacitance of less than about 50 picofarads ("pF") with a DC bias of 0.0 volts and a 0.5 volt root mean square sine wave signal at an operating frequency of 1 MHz, a temperature of about 23°C, and a relative humidity of 25%. For example, the varistor may have a capacitance of less than about 45 pF in some embodiments, less than about 40 pF in some embodiments, less than about 10 pF in some embodiments, and less than about 5 pF in some embodiments, less than about 2 pF, and less than about 1 pF in some embodiments. For example, the varistor may have a capacitance in the range of about 0.1 pF to about 50 pF in some embodiments, about 0.1 pF to about 10 pF in some embodiments, about 0.7 pF to about 7 pF, about 1 pF to about 5 pF in some embodiments, and about 0.1 pF to about 1 pF in some embodiments.

[0029]

[0038] Varistor arrays according to features of the present disclosure may also exhibit other capacitance values. For example, one or more of the varistors of the varistor array may have a capacitance greater than about 50 picofarads ("pF") with a DC bias of 0.0 volts and a 0.5 volt root mean square sine wave signal at an operating frequency of 1 MHz, a temperature of about 23°C, and a relative humidity of 25%. For example, the capacitance of the varistor under the above conditions may be greater than about 50 pF in some embodiments, greater than about 75 pF in some embodiments, greater than about 100 pF in some embodiments, greater than about 200 pF in some embodiments, greater than about 300 pF in some embodiments, greater than about 400 pF in some embodiments, and greater than about 500 pF in some embodiments. As a further example, the capacitance of the varistor under the above conditions may be greater than about 600 pF in some embodiments, greater than about 750 pF in some embodiments, and greater than about 1000 pF in some embodiments. For example, the varistor may have a capacitance ranging from about 50 pF to about 1000 pF in some embodiments, from about 75 pF to about 750 pF in some embodiments, and from about 100 pF to about 500 pF in some embodiments.

[0030]

[0039] In some embodiments, the varistor array and / or one or more varistors of the varistor array may exhibit low leakage current. For example, the leakage current at an operating voltage of about 30 volts may be less than about 10 microamps (μA). For example, the leakage current at an operating voltage of about 30 volts may range from 0.01 μA to about 5 μA in some embodiments, from about 0.005 μA to about 1 μA in some embodiments, from about 0.05 μA to about 0.15 μA in some embodiments, e.g., 0.1 μA.

[0031]

[0040] In some embodiments, one or more varistors of the varistor array have a resistance of at least about 0.05 J / mm when tested with a 10×1000 μs current wave. 3 , and in some embodiments at least about 0.1 J / mm 3, and in some embodiments at least about 0.2 J / mm 3 , and in some embodiments at least about 0.5 J / mm 3 , and in some embodiments, at least about 1.0 J / mm 3 The transient energy capability per unit active volume of one or more varistors can be determined by dividing the transient energy capability of the varistor by the active volume of the varistor. The active volume of a varistor can be defined as the area of ​​the active electrodes multiplied by the number of active electrodes multiplied by the thickness of the dielectric layer between the active electrodes.

[0032]

[0041] According to features of the present disclosure, the varistor array can exhibit a non-linear resistance response that can deflect voltage spikes and / or deflect current voltages so as not to damage nearby or connected electrical components. For example, the varistor array can be configured to provide a relatively low current flow for voltages applied to the varistor array that are below a breakdown voltage of the varistor array. As the applied voltage increases to exceed the breakdown voltage, the varistor array can facilitate a larger relative current flow through the varistor array, which can prevent or reduce voltage spikes through the varistor array and, thereby, to nearby or adjacent components.

[0033]

[0042] For example, the varistor array and / or one or more varistors of the varistor array may exhibit a resistance that follows a first resistance curve that is non-linear over a first voltage range below a clamping voltage of the varistor / varistor array, and may exhibit a resistance that follows a second resistance curve that is approximately linear over a second voltage range above the clamping voltage.

[0034]

[0043] A varistor array may exhibit a non-linear response. The voltage per unit length across the varistor array may vary with respect to the current per unit area through the varistor array. Over the prebreakdown voltage range, the varistor array, or one or more varistors of the varistor array, may generally exhibit a first response curve, and over a non-linear voltage range that is generally above the prebreakdown voltage range and below the clamping voltage, may exhibit a second response curve. A varistor / varistor array may generally exhibit a voltage that approximately follows the relationship:

[0035]

number

[0036] Here, V represents voltage, I represents current, C is a constant, and α is defined in the nonlinear region as follows:

[0037]

number

[0038]

[0044] In the pre-breakdown voltage range, the voltage per unit length generally increases faster with respect to the current per unit area through the varistor / varistor array than in the non-linear region. Over the upturn voltage range above the clamping voltage, the varistor or varistor array may generally exhibit a third response curve, in which the voltage per unit length generally increases faster with respect to the current per unit area through the varistor / varistor array than in the non-linear region.

[0039]

[0045] In some embodiments, a varistor array according to features of the present disclosure, or one or more varistors of a varistor array described herein, may be capable of withstanding repeated electrostatic discharge strikes without substantial degradation in performance. For example, the breakdown voltage of the varistor array after 5000 or more electrostatic discharge strikes of about 8000 volts may be greater than about 0.9 times the initial breakdown voltage of the varistor array, in some embodiments greater than about 0.95 times the initial breakdown voltage, and in some embodiments greater than about 0.98 times the initial breakdown voltage.

[0040]

[0046] The multiple dielectric layers are pressed together and sintered to form a unitary structure. The dielectric layers may include any suitable dielectric material, such as, for example, barium titanate, zinc oxide, or any other suitable dielectric material. For example, various additives may be included in the dielectric material to create or enhance the voltage-dependent resistance of the dielectric material. For example, in some embodiments, the additives may include oxides of cobalt, bismuth, manganese, praseodymium, or combinations thereof. In some embodiments, the additives may include oxides of gallium, aluminum, antimony, chromium, titanium, lead, barium, nickel, vanadium, tin, or combinations thereof. The dielectric material may be doped with additives (one or more) in the range of about 0.5 mole percent to about 3 mole percent, and in some embodiments, from about 1 mole percent to about 2 mole percent. The average grain size of the dielectric material may contribute to the nonlinear properties of the dielectric material. In some embodiments, the average grain size may range from about 1 micron to 100 microns, and in some embodiments, from about 2 microns to 80 microns.

[0041]

[0047] Reference will now be made in detail to example embodiments of multi-layer varistor arrays. Referring now to the drawings, FIG. 1A illustrates a simplified top-down view of a varistor array 100 in accordance with aspects of the present disclosure. FIG. 1B illustrates a side view of the varistor array 100 of FIG. 1A taken along cross section AA of FIG. 1A. The varistor array 100 can include a monolithic body 102 having a first end 106 and a second end 104 spaced apart from the first end 106 in a longitudinal direction 108. The monolithic body 102 can include multiple dielectric layers stacked in a Z-direction 110 that is perpendicular to the longitudinal direction 108 and the transverse direction 112.

[0042]

[0048] The first varistor 114 may be formed in the monolithic body 102. The first varistor 114 may include a first external terminal 116 at a first end 106 of the monolithic body 102. The first varistor 114 may include a first plurality of electrodes 118 connected to the first external terminal 116. The first varistor 114 may include a second external terminal 120 at a second end 104 of the monolithic body 102. The first varistor 114 may include a second plurality of electrodes 122 connected to the second external terminal 120. The second plurality of electrodes 122 may be interleaved with the first plurality of electrodes 118 and may overlap the first plurality of electrodes 118 with an overlap area 123 that is insensitive to relative misalignment between the first plurality of electrodes 118 and the second plurality of electrodes 122 if the misalignment is less than a threshold value 127. In this example, the threshold value 127 is equal to one-half the difference between a width 126 of the first plurality of electrodes 118 and a width 128 of the overlap area 123.

[0043]

[0049] For example, the second plurality of electrodes 122 can have a width 124 in the lateral direction 112 that is smaller than the width 126 in the lateral direction 112 of the first plurality of electrodes 118, such that the width 128 of the overlap area 123 between the first plurality of electrodes 118 and the second plurality of electrodes 122 is equal to the width 124 of the second plurality of electrodes 122. Alternatively, the width 124 of the second plurality of electrodes 122 can be larger than the width 126 of the first plurality of electrodes 118, such that the width 128 of the overlap area 123 between the first plurality of electrodes 118 and the second plurality of electrodes 122 is equal to the width 126 of the first plurality of electrodes 118.

[0044]

[0050] 1B, the overlap area 123 can have a length 125 in the longitudinal direction 108. The length 125 can vary based on, for example, the length in the longitudinal direction 108 of the first plurality of electrodes 118 and / or the length in the longitudinal direction 108 of the second plurality of electrodes 122.

[0045]

[0051] The second varistor 130 may be formed in the monolithic body 102. The second varistor 130 may be separate from the first varistor 114. The second varistor 130 may be spaced laterally 112 from the first varistor 114. The second varistor 130 may include a first external terminal 132 at the first end 106 of the monolithic body 120 and a second external terminal 134 at the second end 104 of the monolithic body 102.

[0046]

[0052] The second varistor 130 can include a first plurality of electrodes 136 connected to the first external terminal 132 and a second plurality of electrodes 138 connected to the second external terminal 134. The second plurality of electrodes 138 of the second varistor 130 can overlap the first plurality of electrodes 186 of the second varistor 130 at an overlap area 140 that is insensitive to relative misalignment between the first plurality of electrodes of the second varistor and the second plurality of electrodes of the second varistor if the misalignment is less than a threshold value 127.

[0047]

[0053] In some embodiments, the area of ​​the overlap area 123 of the first varistor 114 may be approximately equal to the area of ​​the overlap area 140 of the second varistor 130. For example, the ratio of the area of ​​the overlap area 123 of the first varistor 114 to the area of ​​the overlap area 140 of the second varistor 130 may range from about 0.9 to about 1.1.

[0048]

[0054] One or both of the first varistor 114 and the second varistor 130 may represent a capacitance of less than 50 pF with a DC bias of 0.0 volts and a 0.5 volt root mean square sine wave signal at an operating frequency of 1 MHz, a temperature of about 23° C., and a relative humidity of 25%. For example, the first varistor 114 may represent a first capacitance and the second varistor 130 may represent a second capacitance that is within 5% of the first capacitance represented by the first varistor 114.

[0049]

[0055] 1C and 1D show alternating first and second layers 160 and 162, respectively, of the varistor array 100 of FIGS. 1A and 1B. The first layers 160 may be alternated with the second layers 162 to form the monolithic body 102. In some embodiments, a dielectric layer (e.g., one without electrodes or other patterned conductive material) may be disposed between the first and second layers 160 and 162.

[0050]

[0056] FIG. 2A shows a simplified top-down view of a varistor array 200 in accordance with aspects of the present disclosure. FIG. 2B is a side view of the varistor array 200 of FIG. 2A along cross section AA of FIG. 2A. The varistor array 200 can include a monolithic body 202 including a plurality of dielectric layers stacked in a Z-direction 210 perpendicular to a longitudinal direction 208. The monolithic body 202 can have a first end 206 and a second end 204 spaced apart in the longitudinal direction 208 from the first end 206. A first varistor 214 can be formed in the monolithic body 202. A second varistor 230 can be formed in the monolithic body 202. The second varistor 230 can be separate from the first varistor 214.

[0051]

[0057] The first varistor 214 can include a first external terminal 216 at a first end 206 of the monolithic body 202 and a first plurality of active electrodes 218 connected to the first external terminal 216. The first varistor 214 can include a second external terminal 220 at a second end 204 of the monolithic body 202. The second plurality of active electrodes 222 can be connected to the second external terminal 220. Each active electrode 222 of the second plurality of active electrodes 222 can be coplanar with each active electrode 218 of the first plurality of active electrodes 218. The plurality of floating electrodes 224 can overlap the first plurality of active electrodes 218 along a first overlap area 226, the first overlap area 226 being insensitive to relative misalignment between the first plurality of active electrodes 218 and the plurality of floating electrodes 224. The floating electrode 224 can overlap the second plurality of active electrodes 222 along a second overlap area 228, the second overlap area 228 being insensitive to relative misalignment between the second plurality of active electrodes 222 and the floating electrodes 224 that is less than a threshold.

[0052]

[0058] For example, the plurality of floating electrodes 224 can have a width 233 in the lateral direction 212 that is greater than a width 236 in the lateral direction 212 of the first plurality of active electrodes 218, such that a width 238 of a first overlap area 226 between the plurality of floating electrodes 224 and the first plurality of active electrodes 218 is equal to the width 236 of the first plurality of active electrodes 218. As another example, the width 236 of the first plurality of active electrodes 218 can be greater than the width 233 of the floating electrode 224, e.g., as described below in connection with FIG.

[0053]

[0059] In this embodiment, the combined area of ​​overlap areas 226 and 228 can be insensitive to relative misalignment between the first and second pluralities of electrodes 218 and 222 and the floating electrode 224 if the misalignment is less than a threshold value 227 in the lateral direction 212. In this example, the threshold value 227 is equal to one-half the difference between the width 223 of the floating electrode 224 and the width 236 of the first plurality of electrodes 218. The second plurality of electrodes 222 can generally have the same width 236.

[0054]

[0060] The second varistor 230 may include a plurality of floating electrodes 240 separate from the plurality of floating electrodes 224 of the first varistor 214. The floating electrodes 240 of the second varistor 230 may be electrically isolated from the floating electrodes 224 of the first varistor 214. For example, the floating electrodes 240 of the second varistor 230 may be spaced apart from the floating electrodes 224 of the first varistor 214 by a distance 242 in the lateral direction 212. The distance 242 may range from 10% to 200% of the width 238 of the overlap areas 226 and 228.

[0055]

[0061] The second varistor 230 may be generally configured similarly to the first varistor 214. For example, the second varistor 230 may include a first plurality of active electrodes 232 overlapping the plurality of floating electrodes 240 at a first overlap area 244. The second varistor 230 may include a second plurality of active electrodes 246 overlapping the plurality of floating electrodes 240 at a second overlap area 248.

[0056]

[0062] Figure 3 illustrates another example embodiment of a varistor array 300 in accordance with aspects of the present disclosure. Reference numerals similar to those in Figure 2A are used in Figure 3. For example, a first varistor 314 can include a first plurality of active electrodes 318, a plurality of floating electrodes 324, and a second plurality of active electrodes 322.

[0057]

[0063] In some embodiments, the plurality of floating electrodes 324 can have a lateral 312 width 336 that is smaller than the lateral 312 width 333 of the first plurality of active electrodes 316, such that a width 338 of a first overlap area 326 between the plurality of floating electrodes 324 and the first plurality of active electrodes 318 can be equal to the width 336 of the plurality of floating electrodes 324.

[0058]

[0064] In this embodiment, the combined area of ​​overlap areas 326 and 328 can be insensitive to relative misalignment between the first and second pluralities of electrodes 318 and 322 and the floating electrode 324 if the misalignment is less than a threshold value 327 in the lateral direction 312. In this example, the threshold value 327 is equal to one-half the difference between a width 336 of the floating electrode 324 and a width 333 of the first plurality of electrodes 218. The second plurality of electrodes 322 can generally have the same width 333.

[0059]

[0065] 4 is a simplified flow chart of a method 400 of forming a varistor array. The method can include, at 402, patterning a first plurality of electrodes and a third plurality of electrodes into a first plurality of dielectric layers. For example, referring again to FIG. 1C, electrodes 118 and 136 can be patterned into first dielectric layer 160.

[0060]

[0066] The method may include patterning the second plurality of electrodes and the fourth plurality of electrodes into the second plurality of dielectric layers, at 404. For example, referring again to FIG. 1D , electrodes 122 and 138 may be patterned into second dielectric layer 162.

[0061]

[0067] The method may include, at 406, stacking the first and second dielectric layers to form a monolithic body such that a first varistor is formed between the first and second electrodes and a second varistor is formed between the third and fourth electrodes. The second varistor may be separate from the first varistor. For example, referring again to Figures 1A-1D, the first and second dielectric layers 160 and 162 may be stacked alternately to form the monolithic body 102 including the varistors 114 and 130. The external terminals 116, 120, 132, and 134 may be formed by plating or other suitable methods.

[0062] application

[0068] The varistor arrays disclosed herein can be applied in a variety of devices. For example, the varistors can be used in a variety of devices, such as radio frequency antennas, amplifier circuits, and communication lines, such as Ethernet. The varistor arrays may be particularly suitable for high frequency applications, such as 5G frequencies (e.g., greater than 10 GHz).

[0063]

[0069] Varistor arrays may also find application in a wide variety of technologies including laser drivers, sensors, radar, RFID chips, short-range communications, data lines, Bluetooth, optics, Ethernet, and any suitable circuitry. Improved matching of electrical properties between the varistors in a varistor array facilitates increased communication bandwidth.

[0064]

[0070] The varistor arrays disclosed herein may also find particular application in the automotive industry. For example, the varistor arrays may be used in any of the circuits described above in automotive applications. The improved communication bandwidth may facilitate communication between multiple devices on the same communication line. As a result, the total length and / or number of communication lines within a given vehicle may be significantly reduced.

[0065] How we tested

[0071] The following paragraphs provide examples of how to test varistors and / or varistor arrays to determine various varistor characteristics.

[0066] Transient energy capability

[0072] The transient energy capability of the varistors and / or varistor arrays described herein can be measured using a waveform generator and / or pulse generator, such as Frothingham's FEC CV300B. The varistor / varistor array can be subjected to a 10 x 1000 μs current wave. The peak current value can be empirically selected to determine the maximum energy the varistor / varistor array can dissipate without failing (e.g., by overheating). An example current pulse or wave is shown in FIG. 5. Current (vertical axis 502) is plotted against time (horizontal axis 504). The current increases to a peak current value 506 and then decays. The “rise” time period (shown by vertical dotted line 505) is from the start of the current pulse (t=0) to when the current reaches 90% of the peak current value 506 (shown by horizontal dotted line 508). The "decay time" (shown by the vertical dotted line 510) is from the start of the current pulse (t=0) to when the current has returned to 50% (shown by the horizontal dotted line 512) of the peak current value 506. For a 10 x 1000 μs pulse, the "rise" time is 10 μs and the decay time is 1000 μs.

[0067]

[0073] The voltage across the varistor / varistor array can be measured while a pulse passes through it. Figure 6 shows an example plot of the current through the varistor / varistor array (horizontal axis 602) versus the voltage across the varistor / varistor array (vertical axis 604). Figure 6 is described in more detail below.

[0068]

[0074] The transient energy handling capability of a varistor or varistor array according to the present subject matter can be determined by calculating the amount of energy passed through the varistor / varistor array. More specifically, the transient energy rating can be calculated by integrating the product of the measured current and the measured voltage with respect to the time between pulses.

[0069]

number

[0070] where E is the total energy dissipated by the varistor / varistor array, I is the instantaneous current through the varistor / varistor array, V is the instantaneous voltage across the varistor array, and t represents time.

[0071]

[0075] Alternatively, a rectangular current pulse of fixed duration of 2 ms can be applied to the varistor / varistor array using a waveform generator and / or pulse generator such as Frothingham's FEC CV300B. The current through the varistor / varistor array and the voltage across the varistor / varistor array can be detected as described above. The total energy absorbed by the varistor / varistor array (in Joules) can be determined based on the measured current and voltage as described above. The current amplitude of the applied rectangular current pulse can be determined based on the active volume of the varistor / varistor array. The active volume of the varistor / varistor array can be defined as the area of ​​the active electrodes multiplied by the number of active electrodes multiplied by the thickness of the dielectric layer between the active electrodes.

[0072]

[0076] When using any of the above methods for determining the transient energy capability of a varistor / varistor array, the transient energy capability per unit active volume of the varistor / varistor array may be determined by dividing the transient energy capability of the varistor / varistor array by the active volume of the varistor / varistor array. A varistor / varistor array shall have a transient energy capability of at least about 0.05 J / mm when tested with a 10 x 1000 μs current wave. 3 , and in some embodiments at least about 0.1 J / mm 3 , and in some embodiments at least about 0.2 J / mm 3 , and in some embodiments at least about 0.5 J / mm 3, and in some embodiments, at least about 1.0 J / mm 3 The transient energy capability per unit active volume may be:

[0073]

[0077] Additionally, to determine the electrostatic discharge capability of a varistor or varistor array, a series of repeated electrostatic discharge attacks can be administered. For example, 5000 or more 8000 volt electrostatic discharge attacks can be administered to the varistor / varistor array. The breakdown voltage of the varistor / varistor array can be measured at regular intervals during this series of attacks (as described below). The breakdown voltage of the varistor / varistor array after the electrostatic discharge attacks can be measured and compared to the initial breakdown voltage before the attacks.

[0074] Breakdown Voltage

[0003] The breakdown voltage of a varistor or varistor array can be measured using a Keithley 2400 series source measure unit (SMU), for example, a Keithley 2410-C SMU. By definition, the breakdown voltage is the low current voltage of the varistor / varistor array. Typically, the breakdown voltage is measured at a current of 1 milliamp (mA).

[0075] Clamp Voltage

[0078] The clamping voltage is the transition voltage or onset of conduction of a varistor / varistor array. The varistor / varistor array may be subjected to an 8 / 20μs current wave, for example according to ANSI standard C62.1. Typically the clamping voltage is measured at a current of 1 ampere (A), 5A, or 10A.

[0076] Peak Current

[0079] The peak current is the maximum current that the varistor / varistor array can withstand, as measured, for example, using an 8 / 20 μs current pulse or other current pulse. Example 8 / 20 μs, 10 / 1000 μs, etc. current pulses are shown in FIG. 5. Current (vertical axis 502) is plotted against time (horizontal axis 504). The current may increase to a peak current value 506 and then decay. The “rise” time period (shown by vertical dotted line 505) is from the start of the current pulse (t=0) to when the current reaches 90% of the peak current value 506 (shown by horizontal dotted line 508). The “rise” time may be, for example, 8 μs. The “decay time” (shown by vertical dotted line 510) is from the start of the current pulse (t=0) to 50% of the peak current value 506 (shown by horizontal dotted line 512). The “decay time” may be, for example, 20 μs. The clamping voltage is measured as the maximum voltage across the varistor / varistor array during a current wave.

[0077]

[0080] 6, the current per unit area through a varistor / varistor array (horizontal axis 602) is plotted against the voltage per unit length of the varistor / varistor array (vertical axis 604). Over a pre-breakdown voltage range 612, the varistor / varistor array may generally exhibit a first response curve, and over a non-linear voltage range 614 above the pre-breakdown voltage range 612 and below the clamping voltage 606, the varistor / varistor array may generally exhibit a second response curve. An ideal varistor / varistor array may generally exhibit voltages that roughly follow the relationship:

[0078]

number

[0079] where V represents voltage, I represents current, C is a constant, and α is defined in the nonlinear region 614 as follows:

[0080]

number

[0081] In the pre-breakdown voltage range 612, the voltage per unit length generally increases at a greater rate with respect to the current per unit area through the varistor / varistor array than in the non-linear region 614. Over the up-turn voltage range 616 above the clamp voltage 606, the varistor / varistor array may generally exhibit a third response curve, in which the voltage per unit length generally increases at a greater rate with respect to the current per unit area through the varistor / varistor array than in the non-linear region 614.

[0082] capacitance The capacitance of the varistor / varistor array can be measured using a Keithley 3330 Precision LCZ Meter at 0.0 volts DC bias (0.5 volts root mean square sine wave signal). The operating frequency is 1 MHz. The temperature is room temperature (approximately 23°C) and the relative humidity is 25%.

[0083]

[0083] These and other modifications and variations of the present invention may be implemented by those skilled in the art without departing from the spirit and scope of the present invention. It should be further understood that the features of the various embodiments may be interchanged in whole or in part. Furthermore, those skilled in the art will appreciate that the above description is merely illustrative and is not intended to limit the invention as set forth in the appended claims.

Claims

1. 1. A varistor array comprising: a monolithic body including a plurality of dielectric layers stacked in a Z-direction perpendicular to a vertical direction, the monolithic body having a first end and a second end spaced apart from the first end in the vertical direction; a first varistor formed in the monolithic body, a first external terminal at the first end of the monolithic body; a first plurality of electrodes connected to the first external terminal; a second external terminal at the second end of the monolithic body; a second plurality of electrodes connected to the second external terminal of the first varistor, the second plurality of electrodes being interleaved with the first plurality of electrodes and overlapping the first plurality of electrodes at an overlap area, the overlap area being insensitive with respect to a relative misalignment between the first and second plurality of electrodes when the misalignment is less than a threshold value; A first varistor comprising: a second varistor formed in the monolithic body, the second varistor being separate from the first varistor; a first external terminal at the first end of the monolithic body; a second external terminal at the second end of the monolithic body; a first plurality of electrodes connected to the first external terminal of the second varistor; a second plurality of electrodes connected to the second external terminal of the second varistor, the second plurality of electrodes of the second varistor overlapping the first plurality of electrodes of the second varistor in an overlap area, the overlap area being insensitive with respect to a relative misalignment between the first plurality of electrodes of the second varistor and the second plurality of electrodes of the second varistor when the misalignment is less than the threshold value; A second varistor comprising: A varistor array.

2. 2. A varistor array as claimed in claim 1, wherein the second plurality of electrodes of the first varistor have a lateral width greater than a width of the first plurality of electrodes of the first varistor in the lateral direction, such that a width of the overlap area between the first plurality of electrodes of the first varistor and the second plurality of electrodes of the first varistor is equal to a width of the first plurality of electrodes of the first varistor.

3. 2. The varistor array of claim 1, wherein in said first varistor, said threshold value is equal to one-half the difference between the width of said first plurality of electrodes and the width of an overlap area.

4. 2. The varistor array of claim 1, wherein a ratio of said overlap area of ​​said first varistor to said overlap area of ​​said second varistor is in the range of 0.9 to 1.

1.

5. 2. The varistor array of claim 1, wherein the first varistor exhibits a capacitance of less than 50 pF with a DC bias of 0.0 volts and a 0.5 volt root mean square sine wave signal at an operating frequency of 1 MHz, a temperature of approximately 23° C., and a relative humidity of 25%.

6. 6. The varistor array of claim 5, wherein the second varistor exhibits a second capacitance with a DC bias of 0.0 volts and a 0.5 volt root mean square sine wave signal at an operating frequency of 1 MHz, a temperature of about 23 degrees Celsius, and a relative humidity of 25%; A varistor array wherein the second capacitance represented by the second varistor is within 5% of the first capacitance represented by the first varistor.

7. 2. The varistor array of claim 1, wherein the varistor array exhibits a resistance that follows a resistance curve that is non-linear.

8. 2. The varistor array of claim 1, wherein a breakdown voltage of the varistor array after 5000 or more electrostatic discharge strikes of about 8000 volts is greater than about 0.9 times the initial breakdown voltage of the varistor array.

9. 2. The varistor array of claim 1, wherein the varistor array has a resistance of at least about 0.05 J / mm when tested with a 10 x 1000 μs current wave. ３ A varistor array having a transient energy capability per unit active volume of 1000 mA.

10. 2. The varistor array of claim 1, wherein said plurality of dielectric layers comprises zinc oxide.

11. 2. The varistor array of claim 1, wherein said plurality of dielectric layers comprises an oxide of at least one of cobalt, bismuth, praseodymium, and manganese.

12. 2. The varistor array of claim 1, wherein said plurality of dielectric layers have an average grain size ranging from about 1 micron to 100 microns.

13. 1. A method of forming a varistor array, comprising the steps of: patterning a first plurality of electrodes and a third plurality of electrodes into the first plurality of dielectric layers; patterning a second plurality of electrodes and a fourth plurality of electrodes into the second plurality of dielectric layers; stacking the first and second plurality of dielectric layers to form a monolithic body, such that a first varistor is formed between the first and second plurality of electrodes and a second varistor is formed between the third and fourth plurality of electrodes, the second varistor being distinct from the first varistor, the monolithic body having a first end and a second end longitudinally spaced from the first end; forming a first external terminal of the first varistor at the first end of the monolithic body and a second external terminal of the first varistor at the second end of the monolithic body; forming a first external terminal of the second varistor at the first end of the monolithic body and a second external terminal of the second varistor at the second end of the monolithic body; Including, the first plurality of electrodes of the first varistor are connected to the first external terminal of the first varistor, and the second plurality of electrodes of the first varistor are connected to the second external terminal of the first varistor; the second plurality of electrodes are interleaved with the first plurality of electrodes and overlap the first plurality of electrodes with an overlap area, the overlap area being insensitive to relative misalignment between the first and second plurality of electrodes if the misalignment is less than a threshold; the third plurality of electrodes of the second varistor are connected to the first external terminal of the second varistor, and the fourth plurality of electrodes of the second varistor are connected to the second external terminal of the second varistor; the fourth plurality of electrodes overlapping the third plurality of electrodes with an overlap area, the overlap area being insensitive with respect to relative misalignment between the third and fourth plurality of electrodes if the misalignment is less than the threshold.

14. 1. A varistor array comprising: a monolithic body including a plurality of dielectric layers stacked in a Z-direction perpendicular to a vertical direction, the monolithic body having a first end and a second end spaced apart from the first end in the vertical direction; a first varistor formed in the monolithic body, a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body; a first plurality of electrodes connected to the first external terminal; a second plurality of electrodes connected to the second external terminal, the second plurality of electrodes being interleaved with the first plurality of electrodes and overlapping the first plurality of electrodes at a first overlap area; A first varistor comprising: a second varistor formed in the monolithic body and separate from the first varistor, a first external terminal at the first end of the monolithic body and a second external terminal at the second end of the monolithic body; a first plurality of electrodes connected to the first external terminal; a second plurality of electrodes connected to the second external terminal, the second plurality of electrodes of the second varistor overlapping the first plurality of electrodes of the second varistor in a second overlap area; and a second varistor comprising: A varistor array, wherein a ratio of said first overlap area to said second overlap area is in the range of 0.9 to 1.1.

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