RC oscillation circuit

Abstract

To provide an RC oscillation circuit with increased reliability and stability.SOLUTION: An Rc oscillation circuit includes: a first current source unit that outputs a first current Iref; a second current source unit that generates second currents Icharge1,2; an oscillation resistor Rref; a first oscillation capacitor Cint1; a second oscillation capacitor Cint2; two oscillation MOS tube Mn1,2; two comparators COMP1,2; and an RS latch. Input terminals of the first and second current source unit are connected to an external power supply VDD. An output terminal of the first current source unit is connected to one end of the oscillation resistor and positive-phase input terminals of the two comparators. Another end of the oscillation resistor is grounded. One output terminal of the second current source unit is connected to one end of the first oscillation capacitor and an inverse-phase input terminal of one of the comparators. Another end of the first oscillation capacitor is grounded. Another output terminal of the second current source unit is connected to one end of the second oscillation capacitor and an inverse-phase input terminal of the other of the comparators.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to the field of integrated circuits, and more particularly to RC oscillator circuits. [Background technology]

[0002] The RC oscillator is a common electronic oscillator for generating stable AC signals. It is composed of a resistor (R) and a capacitor (C) and realizes the oscillation function by utilizing the characteristics of the RC network. Therefore, the RC oscillator is widely used in fields such as communications, computers, and audio.

[0003] The core element of the RC oscillator is an RC network consisting of resistors and capacitors, which generates a self-oscillating operation in the circuit through the positive feedback effect in the continuous charging and discharging process. Its circuit structure is shown in Figure 1. In the operation process of the RC oscillator shown in Figure 1, the current Icharge1 charges the capacitor Cint1, and when it charges to Vref within the Tint time, the comparator COMP1 reverses, the charge of the capacitor Cint1 is reset, and then the comparator COMP1 reverses again, and then it further charges the capacitor Cint2, and when it charges to Vref within the Tint time, the comparator COMP2 reverses, and then the charge of the capacitor Cint2 is reset, and then the comparator COMP2 reverses again. This makes the RC oscillator circuit start to oscillate, and the oscillation period is 2Tint.

[0004] In the above RC oscillator circuit, if we ignore the delay in the comparator and the logic part of the path, and the parasitic capacitance of the negative terminal of the comparator, and assume that the current Icharge and the current Iref come from the same bias circuit and the ratio of the current values ​​is K, then: JPEG2025029105000002.jpg11170 and Icharge1 = Icharge2 = Icharge, Cint1 = Cint2 = Cint. Additionally, the charge calculation formula: Charge and discharge time according to JPEG2025029105000003.jpg5170: The result is JPEG2025029105000004.jpg8170. Output frequency according to formula (2): The result is JPEG2025029105000005.jpg8170. As can be seen above, Icharge and Iref come from the same bias circuit and have a ratio of K, and the output frequency: The result is JPEG2025029105000006.jpg8170.

[0005] As can be seen from the above, the frequency F of the RC oscillator is inversely proportional to the value of the resistor Rref and the capacitor Cint. In addition, there are process variations in the resistors and capacitors, especially when the process temperature is high, the resistance increases, and the substrate bias effect in generating the current Icharge and the current Iref is also ignored, so the output frequency F becomes very unstable, which reduces the reliability of the product.

[0006] Therefore, there is a need to provide an improved RC oscillator circuit to overcome the above deficiencies. Summary of the Invention

[0007] The object of the present invention is to provide an RC oscillator circuit, the frequency of the output clock signal of which is not affected by the substrate bias effect and resistance change of the MOS tube, the frequency of the output clock signal is stable and has small variation, and the reliability and stability of the RC oscillator circuit are greatly improved.

[0008] In order to achieve the above object, according to the present invention, there is provided an RC oscillator circuit including a first current source unit, a second current source unit, an oscillation resistor, a first oscillation capacitor, a second oscillation capacitor, two oscillation MOS tubes, two comparators and an RS latch, wherein input terminals of the first current source unit and the second current source unit are both connected to an external power supply, the first current source unit generates a first current, and an output terminal thereof is connected to one end of the oscillation resistor and positive-phase input terminals of two comparators, and the other end of the oscillation resistor is grounded, the second current source unit generates a second current and has two output terminals, one output terminal of the second current source unit is connected to one end of the first oscillation capacitor and a negative-phase input terminal of one of the comparators, and the other end of the first oscillation capacitor is grounded, and the other output terminal of the second current source unit is connected to one end of the second oscillation capacitor and a negative-phase input terminal of the other of the comparators, and the other end of the second oscillation capacitor is grounded, the sources of the first MOS tube and the second MOS tube are all grounded, the drains of the two MOS tubes are connected to one end of corresponding oscillation capacitors, the gates of the two MOS tubes are connected to an RS latch output, and the output terminals of the two comparators are respectively connected to the input terminals of the RS latch, and the latch outputs a clock signal; the first current source unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, and a first resistor, the sources of the first MOS tube and the second MOS tube are all grounded, the drains of the first MOS tube and the gates of the second MOS tube are commonly connected and connected to one end of the first resistor, and the other ends of the first resistor are respectively connected to the gate of the first MOS tube and the drain of the third MOS tube, the drains of the third MOS tube and the fourth MOS tube are all connected to an external power supply, and the drain and gate of the fourth MOS tube are commonly connected and connected to the gate of the third MOS tube and the drain of the second MOS tube.

[0009] Preferably, the second current source unit includes a 5th MOS tube, a 6th MOS tube, a 7th MOS tube, an 8th MOS tube, and a second resistor, the sources of the 5th MOS tube and the 6th MOS tube are all grounded, the drain of the 5th MOS tube and the drain of the 7th MOS tube are commonly connected and connected to the gates of the 7th MOS tube and the 8th MOS tube, the source of the 7th MOS tube and one end of the second resistor are both connected to an external power supply, the other end of the second resistor is connected to the source of the 8th MOS tube, and the drain and gate of the 6th MOS tube are commonly connected and connected to the gate of the 5th MOS tube and the drain of the 8th MOS tube.

[0010] Preferably, the third MOS tube and the fourth MOS tube have the same aspect ratio.

[0011] Preferably, the gate-source voltage of the first MOS tube is V GS1 The current generated by the first current source unit is I ref The resistance of the first resistor is Rs, and the gate-source voltage of the second MOS tube is V GS2 The drain current of the second MOS tube is I out Then, according to the KVL formula, The result is JPEG2025029105000007.jpg41170. During the ceremony, JPEG2025029105000008.jpg11170 is the aspect ratio of the second MOS tube and the first MOS tube, and the value of the ratio between them is N1, and V TH1 and V TH2 are the threshold voltages of the first and second MOS tubes, and μ n is the channel mobility, and C ox is the gate oxide capacitance per unit area, and I out =I ref In this case, the current I generated by the first current source unit is ref : JPEG2025029105000009.jpg18170

[0012] Preferably, the aspect ratio value between the eighth MOS tube and the seventh MOS tube is N2, the current generated by the second current source unit is Icharge, and the resistance value of the second resistor is Rr: JPEG2025029105000010.jpg11170, where V T is the thermal voltage.

[0013] Preferably, the current generated by the first current source unit and the current generated by the second current source unit are duplicated in an equal proportion, the current generated by the second current source unit has two identical duplicated currents, and the duplicated currents are input to corresponding devices.

[0014] Preferably, by combining equations (1) and (2), the frequency F of the output clock signal of the RC oscillator is JPEG2025029105000011.jpg26170, where R ref is the resistance of the oscillator resistor.

[0015] Compared with the prior art, in the RC oscillator circuit of the present invention, the sources of the first MOS tube, the second MOS tube, the fifth MOS tube and the MOS tube in the first current source unit and the second current source unit are all grounded, and the substrates of these MOS tubes are also directly grounded, so that the currents from these MOS tubes do not cause substrate bias effect. In addition, when calculating the frequency of the output clock signal, the process temperature variation caused by resistance is also offset. Therefore, the frequency of the output clock signal of the RC oscillator circuit of the present invention is not affected by the substrate bias effect and resistance change of the MOS tube, and the frequency of the output clock signal is stable and has very small variation, which greatly improves the reliability and stability of the RC oscillator circuit.

[0016] The invention will become clearer from the following description and drawings, which are intended to illustrate embodiments of the invention. [Brief description of the drawings]

[0017] [Figure 1]FIG. 1 is a schematic diagram showing the structure of an RC oscillator circuit according to the prior art. [Diagram 2] 1 is a structural schematic diagram of an RC oscillator circuit according to the present invention; [Diagram 3] FIG. 2 is a structural schematic diagram of a first current source unit of the RC oscillator circuit of the present invention. [Figure 4] FIG. 2 is a structural schematic diagram of the second current source unit of the RC oscillator circuit of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, detailed description will be given with reference to the drawings and embodiments of the present invention. Similar reference numerals in the drawings refer to similar elements. As described above, the present invention provides an RC oscillator circuit. The frequency of the output clock signal of the RC oscillator circuit of the present invention is not affected by the substrate bias effect and resistance change of the MOS tube, and the frequency of the output clock signal is stable and has very small variation, which greatly improves the reliability and stability of the RC oscillator circuit.

[0019] As shown in FIG. 2, the RC oscillator circuit of the present invention includes a first current source unit, a second current source unit, an oscillation resistor Rref, a first oscillation capacitor Cint1, a second oscillation capacitor Cint2, two oscillation MOS tubes (Mn1, Mn2), two comparators (COMP1, COMP2), and an RS latch D1. The input terminals of the first current source unit and the second current source unit are both connected to an external power supply VDD. The first current source unit outputs a first current Iref, and an output terminal of the first current source unit is connected to one end of the oscillation resistor Rref and the positive-phase input terminals of two comparators (COMP1, COMP2), thereby outputting the first current Iref to the oscillation resistor Rref and the positive-phase input terminals of the two comparators (COMP1, COMP2). The other end of the oscillation resistor Rref is grounded. The second current source unit generates a second current Icharge and has two output terminals, thereby outputting two currents Icharge1, Icharge2 that are completely the same. One output terminal of the second current source unit is connected to one end of the first oscillation capacitor Cint1 and the inverting input terminal of one of the comparators COMP1, thereby inputting the second current Icharge1 to the first oscillation capacitor Cint1 and the inverting input terminal of the comparator COMP1. The other end of the first oscillation capacitor Cint1 is grounded, and the other output terminal of the second current source unit is connected to one end of the second oscillation capacitor Cint2 and the inverting input terminal of the other comparator COMP2. The other end of the second oscillation capacitor is grounded, thereby inputting the second current Icharge2 to the second oscillation capacitor Cint2 and the inverting input terminal of the comparator COMP2. The sources of the two oscillation MOS tubes (Mn1, Mn2) are both grounded. The drains of the two oscillation MOS tubes (Mn1, Mn2) are connected to one end of the corresponding oscillation capacitor.Specifically, the drain of the oscillation MOS tube Mn1 is connected to one end of a first oscillation capacitor Cint1, the drain of the oscillation MOS tube Mn2 is connected to one end of a second oscillation capacitor Cint2, the gates of the two oscillation MOS tubes (Mn1, Mn2) are both connected to the RS latch output, and the output terminals of the two comparators (COMP1, COMP2) are respectively connected to the input terminals of the RS latch. The latch outputs a clock signal OUT1. The clock signal OUT1 is shaped by two inverters INV1, INV2 and then output as a final clock signal OUT0. Specifically, as shown in Fig. 2, in the RC oscillator circuit of the present invention, the second current Icharge1 charges the first oscillation capacitor Cint1, and after charging it to a predetermined reference voltage Vref within the Tint time, the comparator COMP1 inverts, and after the charge of the first oscillation capacitor Cint1 is reset, the comparator COMP1 inverts again, and then charges the second oscillation capacitor Cint2, and after charging it to a voltage Vref within the Tint time, the comparator COMP2 inverts, and after the charge of the second oscillation capacitor Cint2 is reset, the comparator COMP2 inverts again. In this way, the entire RC oscillator circuit begins to oscillate, the oscillation period is 2Tint, and finally outputs the clock signal OUT0.

[0020] Specifically, as shown in FIG. 3 and FIG. 4, in the present invention, the first current source unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, and a first resistor Rs. The sources of the first MOS tube M1 and the second MOS tube M2 are both grounded, and thus the substrates of the first MOS tube M1 and the second MOS tube M2 are also grounded. The drain of the first MOS tube M1 and the gate of the second MOS tube M2 are commonly connected and connected to one end of the first resistor Rs. The ends of the first resistor Rs are respectively connected to the gate of the first MOS tube M1 and the drain of the third MOS tube M3. The drains of the third MOS tube M3 and the fourth MOS tube M4 are both connected to an external power supply VDD. The drain and gate of the fourth MOS tube M4 are commonly connected and connected to the gate of the third MOS tube M3 and the drain of the second MOS tube M2. As a preferred embodiment of the present invention, the third MOS tube M3 and the fourth MOS tube M4 have the same aspect ratio. For example, the aspect ratio of the third MOS tube M3 is JPEG2025029105000012.jpg10170, and the aspect ratio of the 4th MOS tube M4 is If you set it to JPEG2025029105000013.jpg10170, JPEG2025029105000014.jpg10170. In addition, by setting the voltage value of the external power supply VDD, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 all operate in the saturation region. As shown in FIG. 3, when calculating the current generated by the first current source unit, the gate-source voltage of the first MOS tube is set to VGS1, and the current generated by the first current source unit is set to the first current I ref The resistance value of the first resistor is Rs, the gate-source voltage of the second MOS tube is VGS2, and the drain current of the second MOS tube is I out Then, JPEG2025029105000015.jpg10170, so I out =I ref Furthermore, by the KVL (Kirchhoff's Voltage Law) formula, The result is JPEG2025029105000016.jpg5170. This results in The result is JPEG2025029105000017.jpg40170. Here, JPEG2025029105000018.jpg10170 is the aspect ratio of the second MOS tube M2 and the first MOS tube M1, and the value of the ratio between the aspect ratio of the second MOS tube M2 and the aspect ratio of the first MOS tube M1 is N1, that is, Let's say JPEG2025029105000019.jpg20170. V TH1 and V TH2 is the threshold voltage of the first MOS tube M1 and the second MOS tube M2, and μ n is the channel mobility, and C ox is the gate oxide capacitor per unit area, and μ n and C ox are all process-related parameters and constants that vary from process to process but are not related to the device. out =I ref Therefore, the first current I generated by the first current source unit ref teeth, The image is JPEG2025029105000020.jpg18170.

[0021] As can be seen from the above, the substrates of the first MOS tube M1 and the second MOS tube M2 are grounded, and the substrates of the third MOS tube M3 and the fourth MOS tube M4 are connected to a power supply, so that the first current I ref There is no substrate bias effect.

[0022] 4, the second current source unit includes a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, and a second resistor Rr. The sources of the fifth MOS tube M5 and the sixth MOS tube M6 are both grounded, so that the substrates of the fifth MOS tube M5 and the sixth MOS tube M6 are also grounded. The drain of the fifth MOS tube M5 and the drain of the seventh MOS tube M7 are connected in common and are connected to the gates of the seventh MOS tube M7 and the eighth MOS tube M8, the source of the seventh MOS tube M7 and one end of the second resistor Rr are both connected to an external power supply VDD, and the other end of the second resistor Rr is connected to the source of the eighth MOS tube M8. The drain and gate of the sixth MOS tube M6 are connected in common and are connected to the gate of the fifth MOS tube M5 and the drain of the eighth MOS tube M8. As shown in FIG. 4, when calculating the current generated by the second current source unit, the ratio between the aspect ratio of the eighth MOS tube M8 and the aspect ratio of the seventh MOS tube M7 is N2, i.e., JPEG2025029105000021.jpg20170, where JPEG2025029105000022.jpg12170 are the aspect ratios of the eighth MOS tube M8 and the seventh MOS tube M7, respectively. The current generated by the second current source unit is the second current I charge Let the resistance of the second resistor be Rr. JPEG2025029105000023.jpg11170. Here, V T is a thermal voltage, which is a constant parameter related to the process and varies with the process, but is not related to the device. As can be seen from the above, the substrates of the fifth MOS tube M5 and the sixth MOS tube M6 are grounded, the substrate of the seventh MOS tube M7 is connected to a power supply, and the substrate of the eighth MOS tube M8 is connected to the power supply end of M8, so that the second current Icharge generated by the second current source unit also has no substrate bias effect.

[0023] As can be seen from the above, the first current I ref and the second current I chargeare generated by the first current source unit and the second current source unit, respectively, and these two currents must be input to the RC oscillator circuit. Therefore, in the present invention, the first current I generated by the first current source unit is ref and the second current I generated by the second current source unit. charge in equal proportions, and the current generated by the second current source unit is divided into two identical replicated currents I charge1 , I charge2 and input the copied current to the corresponding device. Specifically, as shown in FIG. 2, MOS tube M0 mirrors the current on the fourth MOS tube M4. By simply making the aspect ratios of the fourth MOS tube M4 and MOS tube M0 the same, the current on the fourth MOS tube M4 can be mirrored at an equal rate. In addition, MOS tube M9 mirrors the current on the sixth MOS tube M6. By making the aspect ratios of the sixth MOS tube M6 and MOS tube M9 the same, the current on the sixth MOS tube M6 can be mirrored at an equal rate. By setting the aspect ratios of MOS tube M9 and MOS tube M10, the currents on MOS tube M9 and MOS tube M10 can be made the same, that is, the current on MOS tube M10 and the current on the sixth MOS tube M6 are the same. MOS tube M11 and MOS tube M12 mirror the current of MOS tube M10. By making the aspect ratios of the MOS tube M10, the MOS tube M11, and the MOS tube M12 the same, the current on the MOS tube M10 can be mirrored in equal proportions. How to duplicate an existing current in equal proportions is a common technique for those skilled in the art, so a detailed explanation is omitted here. When the MOS tube M0 mirrors the current on the fourth MOS tube M4 (the first current I ref ) is mirrored, the first current I ref is input to the positive input terminals of the two comparators, and the MOS tubes M11 and M12 respectively receive the current of the MOS tube M10 (the second current I charge ) are mirrored to produce the second current I charge1 and the second current I charge2 That is, the sources of the MOS tube M11 and the MOS tube M12 respectively form two output terminals of the second current unit, and form a second current I charge1are input to the first oscillation capacitor Cint1, the oscillation MOS tube Mn1, and the inverting input terminal of the comparator COMP1, respectively, and the second current I charge2 are input to the second oscillation capacitor Cint2, the oscillation MOS tube Mn2, and the inverting input terminal of the comparator COMP2, respectively.

[0024] As shown above, the first current I ref and the second current I charge After inputting the above into the corresponding device, the following equations (1), (2) and the above equations described in the Background Art are input: JPEG2025029105000024.jpg12170 (where R ref is the resistance value of the oscillation resistor Rref. By combining The result is JPEG2025029105000025.jpg27170.

[0025] As can be seen from the above, the clock signal OUT1 is shaped by two inverters INV1 and INV2 and then output as the final clock signal OUT0, so the frequency F0 of the clock signal OUT0 and the frequency F of the clock signal OUT1 are completely the same. Furthermore, as can be seen from the formula (3), the frequency F of the clock signal OUT1 finally obtained in the present invention (i.e., the frequency F0 of the clock signal OUT0) not only eliminates the substrate bias effect, but also cancels out the resistances (oscillating resistor Rref, first resistor Rs, second resistor Rr), so that the variation in process temperature due to each resistor is also canceled out. Here, V T is a positive temperature coefficient, and μ n is a negative temperature coefficient, and the temperature characteristics are also compensated. Therefore, the output frequency F0 of the RC oscillator circuit of the present invention is not affected by the substrate bias effect and the change in resistance, and the frequency of the output clock signal is stable and has very small variations, which greatly improves the reliability and stability of the RC oscillator circuit.

[0026] Although the present invention has been described above with reference to the most preferred embodiments, the present invention is not limited to the above embodiments and should include modifications and equivalent combinations based on the essence of the present invention.

Claims

1. An RC oscillator circuit including a first current source unit, a second current source unit, an oscillation resistor, a first oscillation capacitor, a second oscillation capacitor, two oscillation MOS tubes, two comparators and an RS latch, The input terminals of the first current source unit and the second current source unit are both connected to an external power supply, the first current source unit generates a first current, an output terminal of the first current source unit is connected to one end of the oscillation resistor and the positive input terminals of two comparators, and the other end of the oscillation resistor is grounded, the second current source unit generates a second current and has two output terminals, one output terminal of the second current source unit is connected to one end of the first oscillation capacitor and the negative input terminal of one of the comparators, and the other end of the first oscillation capacitor is grounded. is grounded, another output terminal of the second current source unit is connected to one end of the second oscillation capacitor and the inverting input terminal of the other comparator, the other end of the second oscillation capacitor is grounded, the sources of the two oscillation MOS tubes are both grounded, the drains of the two oscillation MOS tubes are connected to one end of corresponding oscillation capacitors, the gates of the two oscillation MOS tubes are connected to the output of an RS latch, the output terminals of the two comparators are respectively connected to the input terminals of an RS latch, and the latch outputs a clock signal; the first current source unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, and a first resistor, the sources of the first MOS tube and the second MOS tube are all grounded, the drain of the first MOS tube and the gate of the second MOS tube are connected in common and to one end of the first resistor, the other end of the first resistor is connected to the gate of the first MOS tube and the drain of the third MOS tube, respectively, the drains of the third MOS tube and the fourth MOS tube are all connected to an external power supply, and the drain and gate of the fourth MOS tube are connected in common and to the gate of the third MOS tube and the drain of the second MOS tube.

2. 2. The RC oscillator circuit according to claim 1, wherein the second current source unit includes a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, and a second resistor, the sources of the fifth MOS tube and the sixth MOS tube are all grounded, the drains of the fifth MOS tube and the seventh MOS tube are commonly connected and are connected to the gates of the seventh MOS tube and the eighth MOS tube, the source of the seventh MOS tube and one end of the second resistor are both connected to an external power supply, the other end of the second resistor is connected to the source of the eighth MOS tube, and the drain and gate of the sixth MOS tube are commonly connected and are connected to the gate of the fifth MOS tube and the drain of the eighth MOS tube.

3. 3. The RC oscillator circuit according to claim 2, wherein the third MOS tube and the fourth MOS tube have the same aspect ratio.

4. The gate-source voltage of the first MOS tube is V ＧＳ１ The current generated by the first current source unit is I ｒｅｆ The resistance value of the first resistor is Rs, and the gate-source voltage of the second MOS tube is V ＧＳ２ The drain current of the second MOS tube is I ｏｕｔ Then, according to the KVL formula, is obtained, During the ceremony, is the aspect ratio of the second MOS tube and the first MOS tube, the value of the aspect ratio of the second MOS tube and the aspect ratio of the first MOS tube is N1, and V ＴＨ１ and V ＴＨ２ are the threshold voltages of the first and second MOS tubes, and μ ｎ is the channel mobility, and C ｏｘ is the gate oxide capacitor per unit area, and I ｏｕｔ = I ｒｅｆ In this case, the current I generated by the first current source unit ｒｅｆ :

4. The RC oscillator circuit according to claim 3, wherein:

5. Let N2 be the aspect ratio between the eighth MOS tube and the seventh MOS tube, Icharge be the current generated by the second current source unit, and Rr be the resistance value of the second resistor. where V Ｔ 5. The RC oscillator circuit of claim 4, wherein: is a thermal voltage.

6. 6. The RC oscillator circuit according to claim 5, characterized in that the current generated by the first current source unit and the current generated by the second current source unit are replicated in equal proportions, the current generated by the second current source unit has two identical replicated currents, and the replicated currents are input to corresponding devices.

7. Combining equations (1) and (2), the frequency F of the output clock signal of the RC oscillator is where R ｒｅｆ 7. The RC oscillator circuit according to claim 6, wherein: is a resistance value of the oscillation resistor.

Images