Display device and electronic device

Abstract

To provide a novel display device.SOLUTION: A display device has: a pixel unit; and a drive circuit unit that is arranged outside the pixel unit. The pixel unit has: a pixel electrode that is arranged in a matrix way; and a transistor that is electrically connected to the pixel electrode. The transistor has: a gate electrode; a gate insulation layer that is on the gate electrode; an oxide semiconductor layer that is on the gate insulation layer; and a source electrode and drain electrode that are on the oxide semiconductor layer. The drive circuit unit has: first wiring to third wiring that are formed by the same step as that of the gate electrode; fourth wiring to sixth wiring that are formed by the same steps as those of the source electrode and drain electrode; seventh wiring that is formed by the same step as that of the pixel electrode; a first area where the second wiring goes across the fifth wiring; and a second area where the third wiring goes across the sixth wiring, in which the first wiring and fourth wiring are connected via the seventh wiring, and the second area is longer in a distance between the wiring than the first area.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an object, a method, a manufacturing method, a process, a machine, manufacture, or The present invention relates to a composition of matter. Devices, displays, light-emitting devices, electronic devices, driving methods thereof, or manufacturing methods thereof In particular, the present invention relates to a semiconductor device, a display device, and an electronic device having an oxide semiconductor. or a light emitting device.

[0002] The display device refers to a device having a display element. In some cases, the display device includes a driver circuit for driving the pixels. The integrated circuit may include a control circuit, a power supply circuit, a signal generating circuit, etc. [Background technology]

[0003] Display devices, such as liquid crystal display devices, have been undergoing technological innovation in recent years, with the miniaturization of elements and wiring. The technology has been progressing and mass production technology has also progressed. Therefore, there is a demand to reduce costs.

[0004] When a surge voltage caused by static electricity or the like is applied to a display device, the elements are destroyed and the device is no longer able to function normally. This can lead to a decrease in manufacturing yield. The display device is provided with a protection circuit for discharging the surge voltage to another wiring (for example, See, for example, Patent Documents 1 to 7. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2010-92036 A [Patent Document 2] JP 2010-92037 A [Patent Document 3] JP 2010-97203 A [Patent Document 4] JP 2010-97204 A [Patent Document 5] JP 2010-107976 A [Patent Document 6] JP 2010-107977 A [Patent Document 7] JP 2010-113346 A Summary of the Invention [Problem to be solved by the invention]

[0006] In display devices, configurations aimed at improving reliability, such as protection circuits, are important. be.

[0007] However, the protection circuit is a device that is manufactured during the manufacturing process of the display device, i.e., Therefore, the transistor during the manufacturing process is connected to the protection circuit. That is, the transistor in the manufacturing process and the transistor connected to the transistor are not connected to the Wiring, etc. can be destroyed by static electricity or overcurrent that can occur during the transistor manufacturing process. Highly likely.

[0008] In this way, static electricity or overcurrent that may occur during the manufacturing process of a transistor can cause the transistor to In a state where there is a high possibility that the transistor and the wiring connected to the transistor will be destroyed, When the device was manufactured, there was a problem that the manufacturing yield was very low.

[0009] In view of the above, one embodiment of the present invention provides a display device having a novel structure capable of reducing electrostatic damage. Another object of the present invention is to provide a device that can improve reliability. Another object of the present invention is to provide a display device having a novel structure. The object of the present invention is to provide a display device having a novel configuration capable of reducing the effects of static electricity. Alternatively, in one embodiment of the present invention, the influence of defects caused when a touch sensor is used is reduced. It is an object of the present invention to provide a display device having a novel structure that can reduce the In one embodiment of the present invention, fluctuation or deterioration of transistor characteristics can be reduced. Another object of the present invention is to provide a display device having a novel structure. A novel configuration that can reduce the variation or degradation of the threshold voltage of a transistor. Another object of the present invention is to provide a display device comprising a transistor. The object of the present invention is to provide a display device having a novel configuration capable of reducing the normally-on state. According to another embodiment of the present invention, the manufacturing yield of a transistor can be improved. It is an object of the present invention to provide a display device having a novel structure. In one embodiment, a display device having a novel configuration is provided that can discharge charges accumulated in pixel electrodes. Another object of one embodiment of the present invention is to provide a method for discharging charge accumulated in a wiring. Another object of the present invention is to provide a display device having a novel structure that can realize the above-mentioned display device. In one aspect, a display device having a novel configuration is provided that can easily display normally. One of the goals of the project is to

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract issues other than those mentioned above from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a liquid crystal display device including a pixel portion and a driver circuit portion disposed outside the pixel portion. The pixel electrode is arranged in a matrix and a transistor is electrically connected to the pixel electrode. The transistor has a gate electrode, a gate insulating layer on the gate electrode, and a gate The insulating layer includes an oxide semiconductor layer, and a source electrode and a drain electrode on the oxide semiconductor layer. The driving circuit section includes first to third wirings and a solenoid, which are formed in the same process as the gate electrode. The fourth wiring to the sixth wiring, which are formed in the same process as the source electrode and the drain electrode, and the pixel electrode A seventh wiring formed in the same process as the electrode, and a first region where the second wiring and the fifth wiring intersect and a second region where the third wiring and the sixth wiring intersect, are connected via a seventh wiring, and the second region is longer in distance than the first region. It is a display device that has the following characteristics. Effect of the Invention

[0012] According to one embodiment of the present invention, a display device having a novel structure capable of reducing electrostatic damage is provided. It can be provided. [Brief description of the drawings]

[0013] [Figure 1] 1A and 1B are a schematic top view of a display device and a circuit diagram illustrating a protective circuit. [Diagram 2] FIG. 2 is a schematic top view of a display device. [Diagram 3] FIG. 2 is a cross-sectional view of a display device. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 18] FIG. 2 is a cross-sectional view of a display device. [Figure 19] 1A and 1B are cross-sectional views of a transistor. [Figure 20] FIG. 2 is a cross-sectional view of a display device. [Figure 21] 1A and 1B are a top view of a display device and an outer periphery of the display device, and a cross-sectional view of the outer periphery of the display device. [Figure 22] FIG. 1 is a circuit diagram illustrating a pixel circuit that can be used in a display device. [Figure 23] 1A to 1C are cross-sectional views of a transistor and a diagram illustrating an oxide stack. [Figure 24] 1A and 1B are diagrams illustrating a touch sensor. [Diagram 25] FIG. 2 is a circuit diagram illustrating a touch sensor. [Figure 26] FIG. 2 is a cross-sectional view illustrating a touch sensor. [Figure 27] 1A and 1B are diagrams illustrating a display module using a display device which is one embodiment of the present invention. [Figure 28] 1A to 1C are diagrams illustrating electronic devices using a display device which is one embodiment of the present invention. [Figure 29] 1A to 1C are diagrams illustrating electronic devices using a display device which is one embodiment of the present invention. [Diagram 30] 1 shows ultramicroelectron beam diffraction patterns of oxide semiconductors. [Diagram 31] FIG. 1 is a diagram illustrating a radiation image detecting device. [Diagram 32] FIG. 2 is a diagram illustrating a radiation detection element. [Diagram 33] 1A and 1B are a top view and a cross-sectional view illustrating a TEG used in the examples. [Diagram 34] FIG. 4 is a diagram for explaining the dielectric breakdown voltage of each sample used in the examples. [Diagram 35] 1A and 1B are a circuit diagram illustrating a protection circuit and a schematic diagram illustrating signal waveforms. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the present invention in various forms without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0015] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0016] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) The transistor has a channel region and allows a current to flow through the drain, the channel region, and the source. This is what is possible.

[0017] Here, the source and drain are different depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are called the source and drain. First, one of the source and drain is referred to as a first electrode, and the other of the source and drain is referred to as a second electrode. It may be written as "polar."

[0018] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0019] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, A and B are also connected electrically. Being electrically connected means that there is an object between A and B that has some electrical effect. A device that enables the transmission and reception of electrical signals between A and B.

[0020] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0021] In addition, the positional relationship of each circuit block in the block diagram in the drawing is specified for the purpose of explanation. Although different circuit blocks are shown to realize different functions, In the circuits or regions, different functions are realized within the same circuit or region. In addition, the functions of each circuit block in the block diagram in the drawings may be different for the purpose of explanation. Although it is shown as a single circuit block, it may not correspond to the actual circuit or area. In this case, the processing that would normally be done by one circuit block is performed by multiple circuit blocks. In some cases.

[0022] A pixel is a pixel that contains one color element (for example, one of R (red), G (green), or B (blue)). This corresponds to a display unit that can control the brightness. Therefore, in the case of a color display device, The minimum display unit of a color image is composed of three pixels: an R pixel, a G pixel, and a B pixel. However, the color elements for displaying a color image are not limited to three colors. The above may be used, or colors other than RGB may be used.

[0023] In this specification, the embodiments of the present invention will be described with reference to the drawings. The embodiments will be described in the following order. 1. First embodiment (basic configuration of the display device) 2. Embodiment 2 (Manufacturing method of a display device) 3. Third embodiment (modification of display device) 4. Fourth embodiment (modification of electrostatic breakdown area) 5. Fifth embodiment (Regarding the configuration of the pixel section) 6. Sixth embodiment (transistor configuration) 7. Seventh embodiment (Regarding touch sensor and display module) 8. Eighth embodiment (regarding electronic devices) 9. Ninth embodiment (radiation image detection device) 10. Example (Breakdown voltage)

[0024] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described with reference to FIGS. conduct.

[0025] The display device shown in FIG. 1A includes a region having pixels of a display element (hereinafter, referred to as a pixel portion 102). A circuit section (hereinafter referred to as a pixel section) is disposed outside the pixel section 102 and has a circuit for driving the pixels. A circuit having a function of protecting the element (hereinafter, referred to as a protection circuit 106) The protection circuit 106 is not necessarily provided, and the terminal portion 107 is also provided. Good too.

[0026] A part or the whole of the driver circuit section 104 is formed on the same substrate as the pixel section 102. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the driving circuit is not formed on the same substrate as the pixel section 102, In many cases, a part or the whole of the path portion 104 is implemented by COG or TAB. .

[0027] The pixel units 102 are arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device includes a circuit for driving a plurality of display elements (hereinafter, referred to as a pixel circuit section 108). The circuit unit 104 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. A signal (data signal) for driving the display element of the pixel is supplied to the pixel. The pixel circuit 104 includes a driving circuit such as a circuit for driving the pixel electrodes 104 (hereinafter, referred to as a source driver 104b).

[0028] The gate driver 104a includes a shift register and the like. A signal for driving the shift register is input via the terminal unit 107, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 104a. The gate driver 104a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 104a are provided, and the plurality of gate drivers 104a drive the scanning lines GL_1 to Alternatively, the gate driver 104a may control the gates GL_X and GL_X separately. However, the gate driver 10 has a function of supplying 4a may also provide another signal.

[0029] The source driver 104b includes a shift register and the like. Through the terminal section 107, a signal for driving the shift register as well as a source of a data signal are input. The source driver 104b outputs a signal (image signal) to the pixel circuit based on the image signal. The source driver 104b has a function of generating a data signal to be written to the data input section 108. The data is generated according to the pulse signal obtained by inputting the start pulse, clock signal, etc. The source driver 104b has a function of controlling the output of a signal. The potential of the wiring (hereinafter, referred to as data lines DL_1 to DL_Y) is controlled. Alternatively, the source driver 104b may have a function for supplying an initialization signal. However, the present invention is not limited to this, and the source driver 104b may supply a different signal. is also possible.

[0030] The source driver 104b is configured using, for example, a plurality of analog switches. The source driver 104b sequentially turns on a plurality of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. The source driver 104b may be configured using this.

[0031] Each of the pixel circuit units 108 is connected to one of the scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuit units 108 via a gate driver. The driver 104a controls the writing and holding of data of the data signal. For example, The pixel circuit unit 108 in the nth column is gated via a scanning line GL_m (m is a natural number equal to or smaller than X). A pulse signal is input from the driver 104a, and the data line DL A data signal is input from the source driver 104b via the source driver 104b. do.

[0032] The protection circuit 106 shown in FIG. 1A includes, for example, a gate driver 104a and a pixel circuit unit 104b. 08. Alternatively, the protection circuit 106 is connected to the scanning line GL, which is the wiring between the source driver The pixel circuit unit 108 is connected to a data line DL, which is a wiring between the driver 104b and the pixel circuit unit 108. The protection circuit 106 is connected to the wiring between the gate driver 104a and the terminal unit 107. Alternatively, the protection circuit 106 may be provided between the source driver 104b and the terminal unit 107. The terminal unit 107 can be connected to a wiring. The term "LCD" refers to a section provided with terminals for inputting image signals, control signals, and video signals.

[0033] When a potential outside a certain range is applied to the wiring to which the protection circuit 106 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0034] As shown in FIG. 1A, a pixel section 102 and a driver circuit section 104 are provided with a protection circuit 106. By providing a This can improve the resistance of the display device to overcurrents caused by electrical discharges, etc. However, the configuration of the protection circuit 106 is not limited to this. For example, A configuration in which a protection circuit 106 is connected, or a configuration in which a protection circuit 106 is connected to the source driver 104b Alternatively, the protection circuit 106 may be connected to the terminal portion 107. It can also be composed of

[0035] In FIG. 1A, the gate driver 104a and the source driver 104b However, the present invention is not limited to this configuration. For example, only the gate driver 104a is formed, and a source driver circuit is separately formed. A substrate (e.g., a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted. It may be configured as follows.

[0036] That is, the protection circuit 106 is provided for either the pixel section 102 or the driver circuit section 104, or is preferably electrically connected to both.

[0037] The protection circuit 106 is configured using, for example, a diode-connected transistor. 1B and 1C show an example of the protective circuit 106.

[0038] The protective circuit 106 shown in FIG. 1B includes a diode connected between the wiring 110 and the wiring 116. The wiring 110 is, for example, the wiring 110 shown in FIG. The scanning lines GL and data lines DL shown in A) or the wiring from the terminal section 107 to the drive circuit section 104 In particular, the protection circuit 106 shown in FIG. 1B is a wiring that is connected to the pixel portion 102 and the gate It is preferable to provide it between the gate drivers 104a.

[0039] The wiring 116 supplies power to, for example, the gate driver 104a shown in FIG. This is the wiring that is given the power supply potential (VDD, VSS or GND) for the purpose of is a wiring (common line) to which a common potential is applied. Reference numeral 116 denotes a power supply line for supplying power to the gate driver 104a, particularly a line for supplying a low potential. It is preferable that the scanning line GL is connected to the wiring that supplies the signal. Therefore, if the potential of the wiring 116 is also low, During normal operation, the current leaking from the scanning line GL to the wiring 116 can be reduced. Yes, it is possible.

[0040] The protective circuit 106 illustrated in FIG. 1C includes a wiring 118, a wiring 120, a wiring 122, and a wiring Transistors 128, 130, and 132 are diode-connected to the line 124 and the wiring 126. The wiring 118 and the wiring 120 are connected to, for example, the source The potential of the power supply line for supplying power to the driver 104b (VDD, VSS, or GND ), or a sampling pulse or the like is applied. 6 is, for example, the data line DL shown in FIG. 1(A). In particular, the protection circuit shown in FIG. The path 106 is preferably provided between the pixel section 102 and the source driver 104b.

[0041] In this way, by providing the protection circuit 106 in the display device shown in FIG. 102 and the drive circuit unit 104 are designed to have high resistance to overcurrent caused by ESD or the like. It is possible.

[0042] In addition, the transistors 112 and 114 used in the protection circuit 106 shown in FIGS. The semiconductor layers 128, 130, 132, and 134 are preferably made of oxide semiconductors. A transistor using an oxide semiconductor is a transistor using silicon or the like for a semiconductor layer. Compared to conventional transistors, they have no avalanche breakdown and are therefore more resistant to electric fields. The transistor structures of the transistors 112, 114, 128, 130, 132, and 134 are as follows: For example, a planar type and an inverted staggered type can be used. Using a modified version of the circuit 106, the current and electron flow through the protection circuit will be explained.

[0043] A modification of the protection circuit 106 in FIG. 1B is shown in FIG.

[0044] The protection circuit 206 shown in FIG. , and wiring 208, 224, and 226.

[0045] One of the source and drain of the transistor 212 is connected to the wiring 224. The other of the source or drain of the transistor 212 is connected to the source or drain of the transistor 214. is connected to one of the drains of the transistor 214, and the other of the source or drain of the transistor 214 is connected to the wiring 208, and one of the source and drain of the transistor 216 is , connected to the other of the source and drain of the transistor 214 and the wiring 208, The other of the source or drain of the transistor 216 is connected to the source or drain of the transistor 218. is connected to one of the drains of the transistor 218, and the other of the source or drain of the transistor 218 is connected to the wiring 226.

[0046] The transistors 212, 214, 216, and 218 each have a gate and a source. is a drain-connected transistor, i.e., a diode-connected transistor. do.

[0047] The wiring 224 is connected to a wiring to which a high power supply potential VDD is applied, and the wiring 226 is connected to a wiring to which a low power supply potential VDD is applied. The line 208 is connected to a line to which a power supply potential VSS is applied, and a signal potential SIG is applied to the line 209. is connected to the wiring.

[0048] In FIG. 35A, a transistor 212 and a transistor 214 form a transistor. The transistors 216 and 218 are shown as transistor group 220. 2. In FIG. 35A, the transistor group 220 and the transistor group Although the example of the configuration of 222 has two transistors, the present invention is not limited to this. The number of transistors may be one or three or more.

[0049] In the protection circuit 206 shown in FIG. 35A, a signal potential SIG When certain conditions are met, the current of the transistor group 220 or the transistor group 22 2 to the high power supply potential VDD or the low power supply potential VSS. In the figure, the current flowing through the high power supply potential VDD and the low power supply potential VSS is indicated by solid arrows. The flow of electrons through the power supply potential VDD and the low power supply potential VSS is indicated by dashed arrows.

[0050] Here, referring to FIG. 35B, the current flowing through the transistor group 220 and the transistor group 222 is This section explains the electric current and electron flow that occur.

[0051] The waveform shown in FIG. 35B is a schematic representation of the signal potential SIG applied to the wiring 208. Ripples may occur in the signal potential SIG at the rising and falling edges of the signal. The ripple can be of two types: ripple on the high power supply potential side and ripple on the low power supply potential side. In Figure 35(B), the ripple potential on the high power supply side is represented as HVDD, and The potential of the ripple on the source potential side is represented as HVSS. If a ripple occurs during a transition, that is, if the signal potential SIG exceeds the high power supply potential VDD, At this time, a current flows through the transistor group 220. An electron flow flows to the line 208 side. Also, a ripple occurs at the falling edge of the signal potential SIG. When the signal potential SIG is lower than the low power supply potential VSS, the transistor At this time, an electron flow flows from the low power supply potential VSS side to the wiring 208 side. can be.

[0052] In this way, by providing the protection circuit 206, it becomes possible to release the overcurrent. .

[0053] The protective circuits 106 and 206 are formed during the manufacturing process of the transistors included in the display device. Therefore, during the transistor fabrication process, the protection circuits 106 and 206 are in their normal function. In other words, during the transistor fabrication process, The transistor or the wiring connected to the transistor is resistant to overcurrent caused by ESD, etc. is not enough.

[0054] Overcurrents that occur during the transistor manufacturing process are caused by large potential differences between different wiring. For example, when the gate electrode or gate A wiring formed in the same process as the electrode, and a source electrode and a drain electrode or a source electrode and When the potential difference between the drain electrode and the wiring formed in the same process becomes large, the gate electrode or The gate electrode and the wiring formed in the same process, the source electrode and the drain electrode, or the source Electrostatic breakdown may occur between the source electrode and the drain electrode and wiring formed in the same process. In particular, the wiring formed in the same process as the gate electrode and the wiring formed in the same process as the source electrode and the drain electrode are Electrostatic breakdown may occur in the area where the wiring formed in the process intersects or in the adjacent area. It is highly likely that

[0055] In view of this, in one embodiment of the present invention, a transistor or In order to prevent electrostatic breakdown from occurring in wiring etc. connected to the transistor, In this way, an area where electrostatic breakdown can occur during the transistor manufacturing process is formed. By using a structure that allows possible overcurrent to escape to the electrostatic breakdown inducing area, reliability is high and manufacturing yield is high. It is therefore possible to provide a display device with high resolution.

[0056] Here, as an example of the display device shown in FIG. 1(A), a display device shown in FIG. A specific configuration is shown below.

[0057] The display devices shown in FIGS. 2A, 2B, and 2C are the same as the pixel portion 1 of the display device shown in FIG. 02 and a top view of an example of the driver circuit portion 104. The structure of a display device using a liquid crystal element (also called a liquid crystal display device) is shown in FIG. 2(A) and (B ), (C) will be used for the explanation.

[0058] FIG. 2A is a top view of a part of the driver circuit unit 104, and FIG. 2B is a top view of the driver circuit unit 104. 2(A) is a top view of a part different from that of FIG. 2(A), and FIG. 2(C) is a top view of a pixel portion 102. In addition, in order to avoid cluttering the drawings, in Figs. 2(A), (B), and (C), For this reason, some of the components such as the gate insulating layer are not illustrated.

[0059] In FIG. 2A, a conductive layer 304a functioning as a gate electrode and a gate insulating layer ( 2(A), a semiconductor layer 308a in which a channel region is formed, and a source electrode and the conductive layers 310a and 310b functioning as drain electrodes, The semiconductor layer 308a is provided on the gate insulating layer. The conductive layer 304b (which is called the first wiring) is formed in the same process as the conductive layer 304a which functions as an electrode. The conductive layers 310a and 310b functioning as a source electrode and a drain electrode are the same. The conductive layer 310c (also referred to as a fourth wiring) formed in one step, the conductive layer 304b, and the conductive A light-transmitting conductive layer 316a (also referred to as a seventh wiring) is provided to connect the layer 310c. The light-transmitting conductive layer 316a is exposed through the conductive layer 304 in the openings 372a and 374a. b and connects to conductive layer 310c at opening 374b.

[0060] In FIG. 2B, a conductive layer 304a that functions as a gate electrode is formed in the same process. A conductive layer 304c (also referred to as a second wiring) and a gate insulating layer (not shown in FIG. 2B) In the same process as the conductive layers 310a and 310b which function as the source and drain electrodes, The conductive layer 310d (also referred to as a fifth wiring) and the light-transmitting conductive layer 316a are The electrostatic breakdown inducing region 360 is formed by the conductive layer 316b formed in the same process. The conductive layer 304c and the conductive layer 310d are connected to the conductive layer 316 in the openings 374c and 374d. The conductive layer 304c, which is the second wiring, and the conductive layer 304b, which is the fifth wiring, are connected via the conductive layer 304c. The region where the layers 310d intersect is defined as a first region 380. The first region 380 is defined as a region where the conductive layer 30 An insulating layer that functions as a gate insulating layer is provided between 4c and the conductive layer 310d.

[0061] In FIG. 2B, the area adjacent to the electrostatic breakdown inducing area 360 is A conductive layer 304d (third layer) formed in the same process as the conductive layer 304a functioning as a gate electrode. The conductive layers 310a and 310b function as a source electrode and a drain electrode. A conductive layer 310e (also called a sixth wiring) formed in the same process as b intersects with , a second region 382 is provided. The second region 382 is formed by the conductive layer 304d and the conductive layer 3 Between the gate insulating layer (not shown in FIG. 2B) and the semiconductor layer 308b, By forming the semiconductor layer 308b in the second region 382, ​​the conductive layer 304d and Since the distance between the conductive layers 310e can be increased, the conductive layers 304d and 310e In addition, the parasitic capacitance between the conductive layer 304d and the conductive layer 310e can be reduced. The increased distance creates a large potential difference between the conductive layer 304d and the conductive layer 310e. In this case, the conductive layer 304d and the conductive layer 310e are prevented from being short-circuited due to electrostatic breakdown. This can be done.

[0062] Thus, the first region 380 and the second region 382 have different distances between the conductive layers. The region 382 is located at a greater distance than the first region 380 because the semiconductor layer 308b is formed therein. long.

[0063] In FIG. 2C, the conductive layer 304e functioning as a scanning line is substantially perpendicular to the signal line. The conductive layer 31 functions as a signal line. The capacitance line and the capacitance line 0e are provided so as to extend in a direction substantially perpendicular to the scanning line (the vertical direction in the figure). The conductive layer 310g, which functions as a signal line, is provided so as to extend in a direction parallel to the signal line. The conductive layer 304e, which functions as a scan line, is connected to the gate driver 104a (see FIG. 1(A)). and a conductive layer 310e that functions as a signal line and a conductive layer 310f that functions as a capacitance line are electrically connected to the The conductive layer 310g is electrically connected to the source driver 104b (see FIG. 1(A)). It has been done.

[0064] In addition, in FIG. 2C, the transistor 131_1 is disposed at a position where the scan line and the signal line intersect. The transistor 131_1 is provided in a conductive layer 3 serving as a gate electrode. 04e, a gate insulating layer (not shown in FIG. 2(C)), a channel formed on the gate insulating layer, The semiconductor layer 308c in which the hole region is formed is a conductive layer that functions as a source electrode and a drain electrode. The layers 310e and 310f constitute a transistor. The conductive layer 304e is a scanning line The region overlapping with the semiconductor layer 308c serves as the gate voltage of the transistor 131_1. The conductive layer 310e also functions as a signal line, and the semiconductor layer 308c The region overlapping with the transistor 131_1 functions as a source electrode or a drain electrode of the transistor 131_1. do.

[0065] In FIG. 2C, the end of the scanning line is aligned with the end of the semiconductor layer 308c in the top view. Therefore, the scanning lines are located outside the light shielding area that blocks light from a light source such as a backlight. As a result, the semiconductor layer 308c included in the transistor is irradiated with light. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed.

[0066] In FIG. 2C, the conductive layer 310f is connected to the pixel electrode in the opening 374e. The light-transmitting conductive layer 316c functions as a light-transmitting conductive layer.

[0067] In addition, in FIG. 2C, in the capacitor 133_1, a conductive line functioning as a capacitor line The layer 310g and the semiconductor layer 308d are in contact with each other. A light-transmitting semiconductor layer 308d formed on the light-transmitting insulating layer and a transparent A conductive layer 316c having optical properties and an insulating layer including hydrogen provided over the transistor 131_1 That is, the capacitor element 133_1 is configured with a light-transmitting Yes.

[0068] In this manner, since the capacitor 133_1 has a light-transmitting property, the capacitor 13 Therefore, the aperture ratio can be increased while the alternative Generally speaking, it is possible to set the charge capacity to 55% or more, preferably 60% or more. For example, a display device with a high resolution, such as a liquid crystal display, can be obtained. In a display device, the area of ​​a pixel is reduced, and the area of ​​a capacitance element is also reduced. In a display device with a high resolution, the charge capacity stored in the capacitance element is small. However, since the capacitor 133_1 shown in this embodiment has a light-transmitting property, the capacitor By providing the pixel electrodes at 100 nm to 150 nm, it is possible to obtain a sufficient charge capacity in each pixel while increasing the aperture ratio. Typically, the pixel density is 200ppi or higher, or even 300ppi or higher. The present invention can be suitably used in such display devices.

[0069] In addition, the pixel portion 102 shown in FIG. 2C has a conductive layer 310e that functions as a signal line and a The side parallel to the conductive layer 304e functioning as the scanning line is longer than the side parallel to the conductive layer 304e. The conductive layer 310g functions as a capacitance line and the conductive layer 310e functions as a signal line. As a result, the conductive layer 310g occupies the pixel portion 102. Since the area of ​​the capacitance line can be reduced, the aperture ratio can be increased. The conductive layer 310g that functions as a conductive layer having light transmitting properties directly functions without using a connecting electrode. Since the semiconductor layer 308d is in contact with the semiconductor layer 308a, the aperture ratio can be further increased. In this embodiment, the side parallel to the conductive layer 304e is larger than the side parallel to the conductive layer 310e. Although the above description is directed to a shape having a long side, the present invention is not limited to this. For example, The side parallel to the conductive layer 304e may be shorter than the side parallel to the conductive layer 304a. In this case, the area of ​​the conductive layer 304e in the pixel can be reduced, and the aperture ratio can be increased. It is possible.

[0070] In addition, according to one embodiment of the present invention, the aperture ratio can be increased even in a high-resolution display device. This allows the light from light sources such as backlights to be used efficiently, and reduces the power consumption of the display device. The force can be reduced.

[0071] Next, the cross-sectional structure of the display device shown in FIGS. 2(A), (B), and (C) will be described with reference to FIG. Provide an explanation.

[0072] FIG. 3A is a cross-sectional view corresponding to the cut surface taken along dashed line X1-Y1 shown in FIG. 2A. 3(B) shows a cross section taken along dashed lines X2-Y2 and X3-Y3 shown in FIG. 2(B). 3(C) is a cross-sectional view corresponding to the cross section taken along the dashed line X4-Y4 shown in FIG. 2(C). The corresponding cross-sectional view is shown.

[0073] The display device shown in FIG. 3 has a liquid crystal element 322 between a pair of substrates (substrate 302 and substrate 342). It is clamped (see Figure 3(C)).

[0074] The liquid crystal element 322 is made up of a conductive layer 316c above the substrate 302 and a layer for controlling the orientation (hereinafter , 352), a liquid crystal layer 320, and a conductive layer 350. The conductive layer 316c functions as one electrode of the liquid crystal element 322, and the conductive layer 350 functions as a liquid crystal It functions as the other electrode of the element 322. In addition, in FIG. A field-type liquid crystal element will be described below.

[0075] The driving circuit unit 104 shown in FIG. 3A includes a substrate 302 and a conductive film formed on the substrate 302. The layers 304a and 304b, the substrate 302, and the insulating layer formed on the conductive layers 304a and 304b. A border layer 305, an insulating layer 306 formed on the insulating layer 305, and a conductive layer 307 formed on the insulating layer 306. a semiconductor layer 308a formed in a position overlapping with the conductive layer 304a, an insulating layer 306, and Conductive layers 310a and 310b are formed on the semiconductor layer 308a, and a conductive layer 310b is formed on the insulating layer 306. The conductive layer 310c is formed by arranging the semiconductor layer 308a and the conductive layers 310a, 310b, and 310c. An insulating layer 312 is formed so as to cover the insulating layer 312, and an insulating layer 314 is formed on the insulating layer 312. and a conductive layer 316a formed on the edge layer 314.

[0076] In the driver circuit portion 104 shown in FIG. 3A, the conductive layer 316a is The conductive layer 304b functions as a wiring that connects the insulating layer 304b and the conductive layer 310c. Through the openings formed in 305, 306, 312, and 314, the conductive layer 310c is The layers 312 and 314 are connected to each other through an opening formed in the layers 312 and 314 by a conductive layer 316a. In FIG. 3A, when the conductive layer 304b and the conductive layer 316a are connected, the insulating layer 30 After providing the openings in layers 6 and 312, the insulating layers 314 and 305 are opened together. This allows the insulating layers 305, 306, 312, and 314 to be opened more easily than when they are opened all at once. As a result, the depth of each opening (the amount of insulating layer etched) is smaller. Therefore, etching can be easily performed. However, one embodiment of the present invention is not limited thereto. As shown in FIG. 3B at the connection portion between the conductive layer 304c and the conductive layer 316b, the insulating layer 305 , 306, 312, and 314 can be opened at the same time. can reduce the area of ​​the opening region.

[0077] The driving circuit unit 104 shown in FIG. 3B includes a substrate 302 and a conductive film formed on the substrate 302. The layers 304c and 304d, the substrate 302, and the insulating layer formed on the conductive layers 304c and 304d. A border layer 305, an insulating layer 306 formed on the insulating layer 305, and a conductive layer 307 formed on the insulating layer 306. The semiconductor layer 308b is formed in a position overlapping with the conductive layer 304d, and the insulating layer 306 is formed in a position overlapping with the conductive layer 304c. A conductive layer 310d formed on the semiconductor layer 308b, a conductive layer 310e formed on the semiconductor layer 308b, and an insulating layer 306, and an insulating layer 312 formed to cover the conductive layers 310d and 310e; 312 and an insulating layer 314 formed on the insulating layer 314. 16b is formed.

[0078] In the driver circuit portion 104 shown in FIG. 3B, the conductive layer 316b is The conductive layer 316b functions as a wiring that connects the insulating layer 316c to the conductive layer 310d. The openings formed in the insulating layers 312 and 314 are The conductive layer 304 is connected to the conductive layer 310d through the opening. When c and the conductive layer 316b are connected, the insulating layers 305, 306, 312, and 314 are This allows the area of ​​the opening to be reduced. One embodiment of the present invention is not limited to this. As with the connection portion, openings are provided in the insulating layers 306 and 312, and then the insulating layers 314 and 30 are 5 may be opened at the same time. The number of times the nozzles are opened is increased compared to when the nozzles 314 are opened all at once. As a result, This reduces the depth (the amount of etching of the insulating layer) and facilitates etching.

[0079] In addition, the driving circuit section 104 shown in FIG. 3B has an electrostatic breakdown inducing region 360 formed therein. The electrostatic breakdown inducing region 360 is made up of the conductive layer 304c, the insulating layers 305 and 306, and the conductive layer 310d, insulating layers 312 and 314, and conductive layer 316b. The electrical breakdown inducing region 360 may be configured without providing the insulating layers 305 and 306 .

[0080] As shown in the top view of FIG. 2B, the conductive layer 304c of the electrostatic breakdown inducing region 360 is partially The conductive layer 304c is formed in a comb-like shape as shown in the cross-sectional view of FIG. The conductive layer 310c has a plurality of protrusions and is formed so as to easily short-circuit with the conductive layer 310d.

[0081] The electrostatic breakdown inducing region 360 is, for example, a region where a large current flows between the conductive layer 304c and the conductive layer 310d. When a potential difference occurs, the insulating layer 305, 306 formed between the conductive layer 304c and the conductive layer 310d Destroy 06, causing a short circuit.

[0082] The electrostatic breakdown inducing region 360 is particularly intended to connect the conductive layer 316b to another conductive layer. For example, the opening is formed by dry etching. When using a dry etching device, the electric field of plasma, etc. generated in the dry etching device The potential difference between the conductive layer 304c and the conductive layer 310d increases. If the display device is not protected against ESD, electrostatic damage may occur due to defects in the wiring patterns of the display device. However, in the display device according to one embodiment of the present invention, the electrostatic breakdown induction By forming the region 360, an overcurrent caused by ESD is prevented from reaching the electrostatic breakdown inducing region 360. You can escape to.

[0083] The conductive layer 304c and the conductive layer 310d are formed by removing the conductive layer 31 after the opening is formed in the insulating layer. 6b, electrostatic breakdown occurs and the conductive layer 304c and the conductive layer 310d are short-circuited. Even if such a voltage is applied, there is no or very little effect on the display device.

[0084] In this way, by providing the electrostatic breakdown inducing region 360, the conductive layer 304c is formed in the same process. Other conductive layers (e.g., conductive layers 304a, 304b) formed in the process or conductive layer 310 Other conductive layers (e.g., conductive layers 310a, 310b, 310c) formed in the same process as d can be prevented from being destroyed.

[0085] The driving circuit unit 104 shown in FIGS. 3A and 3B includes a substrate 342 and a The light-shielding layer formed on the light-shielding layer 344 is a layer having a light-shielding property (hereinafter, referred to as a light-shielding layer 344). 3, the insulating layer 348 is disposed on the insulating layer 348, and a conductive layer 350 is formed on the insulating layer 348.

[0086] In the driving circuit section 104 shown in FIGS. 3A and 3B, the substrate 302 and the substrate 342 A liquid crystal layer 320 is sandwiched between the alignment films 318 and 352. The liquid crystal layer 320 is formed on the substrate 302 and the substrate 342. A seal material (not shown) may be used to seal between substrate 302 and substrate 342. In order to prevent moisture from entering from the outside, the insulating material is preferably in contact with an inorganic material. In addition, the liquid crystal layer 320 is formed by using spacers (not shown) to adjust the thickness of the liquid crystal layer (cell gap). It is possible to maintain a certain level of stability (also called a "top").

[0087] The pixel section 102 shown in FIG. 3C includes a substrate 302 and a conductive layer 3 formed on the substrate 302. 304e, an insulating layer 305 formed on the substrate 302 and the conductive layer 304e, and an insulating layer 30 5, and a conductive layer 304e formed on the insulating layer 306. A semiconductor layer 308c is formed at a position where the insulating layer 306 is located, and a semiconductor layer 308d is formed on the insulating layer 306. and conductive layers 310f and 310g formed on the insulating layer 306 and the semiconductor layer 308c. The semiconductor layer 308c and the conductive layers 310f and 310g are formed so as to cover the semiconductor layer 308c and the conductive layers 310f and 310g. An insulating layer 312 that covers a part of the semiconductor layer 308d and is formed on the insulating layer 312. An insulating layer 314 is formed on the insulating layer 314 and is connected to a conductive layer 310g. and a conductive layer 316c.

[0088] The conductive layer 316c is formed through an opening formed in the insulating layers 312 and 314. Connected to 310g.

[0089] The pixel portion 102 shown in FIG. 3C includes a substrate 342 and a shielding film formed on the substrate 342. A light-transmitting layer 344 and a layer having color formed on the substrate 342 (hereinafter referred to as a color layer 346) ), an insulating layer 348 formed on the light-shielding layer 344 and the colored layer 346, and and a conductive layer 350 formed on the substrate 30.

[0090] In the pixel section 102 shown in FIG. 3C, a liquid crystal layer is provided between the substrate 302 and the substrate 342. The liquid crystal layer 320 is sandwiched between the substrate 302 and the alignment film 318, 352. and substrate 342, respectively.

[0091] As for the other components, a manufacturing method of a display device will be described later in detail. do.

[0092] As described above, in the display device shown in this embodiment, the electrostatic breakdown inducing region is formed in the driver circuit portion. The electrostatic breakdown inducing region includes a wiring formed in the same process as the gate electrode and a source The thickness of the insulating film formed between the drain electrode and the wiring formed in the same process as the drain electrode is By making it thinner, i.e. shortening the distance between the wiring, the insulating film between other wiring patterns can be In the electrostatic breakdown inducing region, the gate electrode and The wiring formed in the same process has a comb-like shape, which prevents overcurrent caused by ESD. The structure is easy to flush.

[0093] As described above, one embodiment of the present invention is a display device having an electrostatic breakdown inducing region in a driver circuit portion. By doing so, it is possible to provide a novel display device with improved reliability.

[0094] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0095] (Embodiment 2) In this embodiment mode, a manufacturing method of the display device described in FIG. 3 of Embodiment Mode 1 will be described with reference to FIG. This will be explained with reference to FIG.

[0096] The display device described in FIG. 3 of the first embodiment simultaneously displays the driving circuit section 104 and the pixel section 102. Therefore, in this embodiment, the driver circuit section 104, the pixel The method for manufacturing the driver circuit portion 104 will be described below. Regarding Figs. 4(A), (B), 5(A), (B), 6(A), (B), and Fig. 7(A), (B), Fig. 8(A), (B), Fig. 9(A), (B), Fig. 10(A), ( B), Figs. 11(A) and (B), Figs. 12(A) and (B), Figs. 13(A) and (B), 14(A), (B), 15(A), (B), 16(A), (B), and 17( A method for manufacturing the pixel portion 102 is shown in FIG. 4(C) and FIG. 5(C). ), FIG. 6(C), FIG. 7(C), FIG. 8(C), FIG. 9(C), FIG. 10(C), FIG. 11(C), 12(C), 13(C), 14(C), 15(C), and 16(C) and 17(C).

[0097] First, a substrate 302 is prepared. The substrate 302 is made of aluminosilicate glass, aluminum. Glass materials such as minoborosilicate glass and barium borosilicate glass are used. Above, the substrate 302 is 8th generation (2160mm x 2460mm), 9th generation (2400 mm x 2800mm, or 2450mm x 3050mm, 10th generation (2950mm It is preferable to use mother glass such as 3400 mm × 3400 mm. Since the temperature is high and the processing time is long, the glass shrinks significantly. The heat treatment in the manufacturing process is preferably performed at 600° C. or less, more preferably at 450° C. or less, and It is more preferable to set the temperature at 350° C. or lower.

[0098] Next, a conductive film is formed on the substrate 302, and the conductive film is processed into a desired region. The conductive layers 304a, 304b, 304c, 304d, and 304e are formed. The formation of 304a, 304b, 304c, 304d, and 304e is a first patterning in a desired area. The mask is formed by etching the area not covered by the mask. It can be achieved.

[0099] The conductive layers 304a, 304b, 304c, 304d, and 304e may be made of aluminum. A metal element selected from the group consisting of chromium, copper, tantalum, titanium, molybdenum, and tungsten, The alloy is made of the above-mentioned metal elements or a combination of the above-mentioned metal elements. The conductive layers 304a, 304b, 304c, 304d, and 30 4e may be a single layer structure or a laminated structure of two or more layers. For example, Two-layer structure with titanium film laminated, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride Two-layer structure in which a tungsten film is laminated on a tantalum nitride film, a tantalum nitride film or a tungsten nitride film A two-layer structure with a tungsten film on top, a titanium film, and an aluminum film on the titanium film. There are three-layer structures, such as a laminate of aluminum and a titanium film on top of that. , titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A film of a selected element, an alloy film of a combination of a plurality of elements, or a nitride film may be used. The conductive layers 304a, 304b, 304c, 304d, and 304e may be, for example, It can be formed by using a tarring method.

[0100] Next, on the substrate 302 and the conductive layers 304a, 304b, 304c, 304d, and 304e Then, insulating layers 305 and 306 are formed on the insulating film 304 (see FIGS. 4(A), (B), and (C)).

[0101] The insulating layer 305 may be, for example, a silicon oxynitride film, a silicon nitride film, or an aluminum oxide film. A PE-CVD device can be used to form a multilayer or single layer. When the insulating layer 305 has a laminated structure, a silicon nitride film having few defects is used as the first silicon nitride film. A silicon nitride film was formed on the first silicon nitride film, and a second silicon nitride film was formed on the first silicon nitride film. It is preferable to provide a silicon nitride film that emits less ammonia. The hydrogen and nitrogen contained in 05 are then transferred to the semiconductor layers 308a, 308b, and 308c that will be formed later. It is possible to suppress the migration or diffusion of the

[0102] The insulating layer 306 may be a silicon oxide film, a silicon oxynitride film, or the like. It is formed in a multilayer or single layer using an E-CVD device.

[0103] As the insulating layers 305 and 306, for example, the insulating layer 305 is a nitride film having a thickness of 300 nm. A silicon film is formed, and then a silicon oxynitride film having a thickness of 50 nm is formed as an insulating layer 306. The silicon nitride film and the silicon oxynitride film can be formed continuously in a vacuum. It is preferable to form the conductive layers 304a and 304e so that the inclusion of impurities is suppressed. The insulating layers 305 and 306 in the overlapping regions function as gate insulating layers of the transistors. can be done.

[0104] Silicon nitride oxide is an insulating material whose nitrogen content is greater than its oxygen content. On the other hand, silicon oxynitride is an insulating material with a higher oxygen content than nitrogen content. This refers to.

[0105] By configuring the gate insulating layer as described above, the following effects can be obtained, for example: The silicon nitride film has a higher dielectric constant than the silicon oxide film, and has the same static Since the thickness required to obtain capacitance is large, the gate insulating layer cannot be physically thickened. This prevents the transistor from decreasing its dielectric strength, and improves its dielectric strength. Electrostatic damage to the transistor can be suppressed.

[0106] Next, a semiconductor layer 307 is formed on the insulating layer 306 (see FIGS. 5(A), (B), and (C)). ).

[0107] The semiconductor layer 307 may be, for example, an oxide semiconductor. The oxide semiconductor that can be applied to 7 is at least indium (In), zinc (Zn) and M( In-M- containing elements such as Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf It is preferable that the layer contains a layer represented by Zn oxide. Alternatively, the layer contains both In and Zn. In addition, it is preferable to reduce variation in electrical characteristics of a transistor including the oxide semiconductor. Therefore, it is preferable to include a stabilizer therewith.

[0108] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminium. Aluminum (Al) or zirconium (Zr), etc. Also, other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er) Er, Thulium, Tm, Ytterbium, Lutetium, etc. do.

[0109] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. substances, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn Oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-D y-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn Oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-A In-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0110] In this case, the In-Ga-Zn oxide is a material having In, Ga, and Zn as main components. It means oxide, and the ratio of In, Ga, and Zn does not matter. Also, In, Ga, and Zn In addition, in this specification, the term "In-Ga-Zn oxide" refers to a metal element other than In-Ga-Zn oxide. Films made of IGZO are sometimes called IGZO films.

[0111] In addition, InMO3(ZnO) m (m>0 and m is an integer) M may be one or more metal elements selected from Ga, Fe, Mn, and Co. In2SnO5(ZnO) n (n>0 and n is Materials expressed as (integer) may be used.

[0112] The oxide semiconductor film may be non-single-crystal. C Axis Aligned Crystal), polycrystalline, microcrystalline, and amorphous parts .

[0113] The oxide semiconductor may include a CAAC. CAAC-OS(C Axis Aligned Crystalline Oxide It is called a semiconductor.

[0114] CAAC-OS is a transmission electron microscope (TEM). When crystals can be confirmed in the image observed by a Tron Microscope The crystal part in CAAC-OS is small enough to fit inside a cube with one side of 100 nm. In addition, in TEM images of CAAC-OS, the crystals are separated into crystal parts. In addition, the boundary between the two regions may not be clearly visible in the TEM images. In some cases, the grain boundaries cannot be clearly identified. C-OS does not have clear grain boundaries, so impurities are less likely to segregate. Since C-OS does not have clear grain boundaries, the density of defect states is unlikely to become high. Since the CAAC-OS does not have clear grain boundaries, the decrease in electron mobility is small.

[0115] The CAAC-OS may have a plurality of crystal parts, and the c-axis of each of the crystal parts may be different. may be aligned in a direction parallel to the normal vector of the surface on which the image is formed or in a direction parallel to the normal vector of the surface. In addition, CAAC-OS was found to have When the out-of-plane analysis was performed using a 3-D NMR spectrometer, the 2θ value indicating the orientation was 31. In addition, in the electron diffraction pattern of CAAC-OS, a peak may appear around 100°. Spots (bright points) may be observed. The electron beam diffraction pattern obtained using an electron beam of 5 nm or less is called the ultrafine electron beam diffraction pattern. In addition, the CAAC-OS has a-axis and b-axis orientations that are different between different crystal regions. For example, the CAAC-OS may be c-axis oriented and a-axis or / and The a and b axes may not be aligned to the macro.

[0116] FIG. 30(A) is an example of an electron microbeam diffraction pattern of a sample having a CAAC-OS. Here, the sample was cut in a direction perpendicular to the CAAC-OS surface to have a thickness of 40 nm. In addition, the electron beam with a beam diameter of 1 nm was focused on the sample. The electron beam is incident from a direction perpendicular to the cut surface. It can be seen that spots are observed in the fold pattern.

[0117] The c-axis of the crystalline part in the CAAC-OS is the normal vector of the CAAC-OS surface. Or, they are aligned parallel to the surface normal vector and perpendicular to the ab plane. When viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in a triangular or hexagonal shape. The metal atoms and oxygen atoms are arranged in layers or in layers. The directions of the a-axis and the b-axis may be different. In this specification, the term "vertical" is used. In this case, the range of 80° to 100°, preferably 85° to 95°, is also included. In addition, when simply describing it as parallel, it is -10° or more and 10° or less, preferably -5° This also includes the range of 5° or less.

[0118] The c-axis of the crystalline part in the CAAC-OS is the normal vector of the surface on which the CAAC-OS is formed. Or, the shape of CAAC-OS ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, the directions may differ from each other. In addition, the crystallization process such as heat treatment was performed when or after the film was formed. Therefore, the c-axis of the crystal part is the same as that of the unformed part when CAAC-OS is formed. Aligns to be parallel to the face normal vector or surface normal vector.

[0119] CAAC-OS can sometimes be formed by reducing the impurity concentration. Here, impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon have a higher oxidation resistance than the metal elements that make up oxide semiconductors. Therefore, when the element takes oxygen from the oxide semiconductor, It can disrupt the atomic arrangement of the body and reduce crystallinity. It can also cause damage to heavy metals such as iron and nickel. , argon, and carbon dioxide have large atomic (or molecular) radii, so they are not suitable for oxide semiconductors. This can disrupt the atomic arrangement of the oxide semiconductor and reduce the crystallinity of the oxide semiconductor. The -OS is an oxide semiconductor with a low concentration of impurities. may be a carrier generation source.

[0120] In the CAAC-OS, the distribution of the crystal parts may not be uniform. In the process of forming C-OS, when crystal growth is performed from the surface side of the oxide semiconductor, The proportion of crystalline parts may be higher near the surface than near the bottom. -When impurities are mixed into the OS, the crystallinity of the crystal part in the region where the impurities are mixed is reduced. It may go down.

[0121] CAAC-OS can be formed by reducing the density of defect states. In semiconductors, oxygen vacancies are defect states. Oxygen vacancies can become trap states or , and can become a carrier generation source by capturing hydrogen. In order to achieve this, it is important to prevent oxygen vacancies from occurring in the oxide semiconductor. AC-OS is an oxide semiconductor with a low density of defect states. It is an oxide semiconductor with few element vacancies.

[0122] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high purity intrinsic or A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor is In some cases, the carrier density can be reduced because there are fewer carrier generation sources. In addition, a transistor including the oxide semiconductor in a channel formation region has a low threshold voltage. In some cases, the electrical characteristics are less likely to become normally on. Since a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor has a low density of defect states, In this case, the density of trap states may be reduced. The transistors used in this region have small fluctuations in electrical characteristics and are highly reliable. Note that it takes time for the charge trapped in the trap level of the oxide semiconductor to disappear. The charge may remain trapped for a long time and behave as if it were a fixed charge. A transistor that uses an oxide semiconductor with high potential density for the channel formation region has unstable electrical characteristics. This may be determined.

[0123] In addition, transistors using CAAC-OS that are high purity intrinsic or substantially high purity intrinsic are The electrical characteristics of this capacitor change little when exposed to visible or ultraviolet light.

[0124] The CAAC-OS can be formed, for example, by a sputtering method using a DC power source. can be done.

[0125] The oxide semiconductor may have, for example, polycrystals. The polycrystalline oxide semiconductor includes a plurality of crystal grains.

[0126] In polycrystalline oxide semiconductors, crystal grains can often be seen in TEM images. The crystal grains contained in the polycrystalline oxide semiconductor are, for example, 2 nm in size in a TEM observation image. Particle size is 300nm or more, 3nm or more, 100nm or less, or 5nm or more, 50nm or less In addition, in the case of polycrystalline oxide semiconductors, the crystal grains are often separated from each other in the TEM images. In addition, in the case of polycrystalline oxide semiconductors, the boundary between the In some cases, grain boundaries can be seen.

[0127] The polycrystalline oxide semiconductor has a plurality of crystal grains, and the crystal grains have different orientations. In addition, polycrystalline oxide semiconductors may be out-of-plane diffracted using an XRD device. When performing lane analysis, single or multiple peaks may appear. For example, In the case of crystalline IGZO films, the 2θ value, which indicates orientation, shows a peak near 31°, or shows multiple types of orientation. In addition, multiple peaks may appear in the electron beam diffraction pattern of polycrystalline oxide semiconductors. Spots may be observed.

[0128] A polycrystalline oxide semiconductor has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor for a channel formation region has a high field effect. However, impurities may segregate at grain boundaries in polycrystalline oxide semiconductors. In addition, the grain boundaries of polycrystalline oxide semiconductors become defect states. Since the polycrystalline oxide semiconductor may become a carrier generation source and a trap state, The transistor used in the region is a transistor that uses CAAC-OS in the channel formation region. In comparison, the variation in electrical characteristics is large, resulting in a transistor with low reliability.

[0129] The polycrystalline oxide semiconductor is formed by a heat treatment at a high temperature or a laser light treatment. can be done.

[0130] The oxide semiconductor may have, for example, microcrystals. The resulting semiconductor is called a microcrystalline oxide semiconductor.

[0131] In the TEM observation image of the microcrystalline oxide semiconductor, the crystal parts can be clearly seen. The crystal parts included in the microcrystalline oxide semiconductor may have a size of, for example, 1 nm or more and 100 nm or less. The size is usually less than 1 m, or between 1 nm and 10 nm. Microcrystals of less than 0 nm are called nanocrystals (nc). The oxide semiconductor that can achieve this is called nanocrystalline oxide semiconductor (nc-OS). In addition, nc-OS is characterized by a crystalline structure in TEM images. In some cases, the boundary between the crystal and crystalline parts cannot be clearly identified. In the observation image, there are no clear grain boundaries, so impurities are less likely to segregate. Since the -OS does not have a clear grain boundary, the defect level density is unlikely to be high. Since c-OS does not have clear grain boundaries, the decrease in electron mobility is small.

[0132] The nc-OS has atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm). In addition, the nc-OS has a periodic structure between the crystal regions. Therefore, the atomic arrangement may not show periodicity or long-range order macroscopically. Therefore, depending on the analysis method, nc-OS may be difficult to distinguish from amorphous oxide semiconductors. In nc-OS, the beam diameter is larger than the crystal part using an XRD device. When the out-of-plane X-ray analysis was performed, a peak indicating orientation was detected. In addition, the nc-OS may not be able to produce a beam with a diameter larger than the crystal part (e.g., 20 nm). In the electron diffraction pattern using an electron beam of 50 nm or more (50 nm or more), a halo pattern is In addition, nc-OS has bead structures that are the same size as or smaller than the crystalline parts. Ultrafine electron beam circuits using electron beams with diameters of 10 nm or less, or 5 nm or less In the folding pattern, spots may be observed. The pattern may be observed as a circular area of ​​high brightness. In the electron microbeam diffraction pattern, a plurality of spots may be observed within the region.

[0133] FIG. 30(B) shows an example of an electron microbeam diffraction pattern of a sample having an nc-OS. In this example, the sample was cut in a direction perpendicular to the surface on which the nc-OS was formed, and the thickness was about 40 nm. In this experiment, an electron beam with a beam diameter of 1 nm was applied to the cut surface of the sample. The electron diffraction pattern of nc-OS is shown in Fig. 30(B). A circular area of ​​high brightness is observed, and multiple spots are observed within the area. It can be seen that this is possible.

[0134] nc-OS has periodic atomic arrangement in small regions, so it is amorphous. The defect density is lower than that of oxide semiconductors. However, the nc-OS has a crystalline structure. Since there is no regularity between the regions, the density of defect states is higher than that of the CAAC-OS.

[0135] Therefore, the carrier density of the nc-OS may be higher than that of the CAAC-OS. Oxide semiconductors with high carrier density can have high electron mobility. A transistor using an -OS for a channel formation region can have high field-effect mobility. In addition, the nc-OS has a higher defect density than the CAAC-OS, which reduces the trapping Therefore, the density of the gate states may be increased when the nc-OS is used for the channel formation region. The electrical characteristics of the transistor are higher than those of a transistor that uses CAAC-OS in the channel formation region. However, the nc-OS has a large variation in the characteristics and can result in unreliable transistors. However, it can be formed even if it contains relatively many impurities, so it is more effective than CAAC-OS. It is easy to form and may be suitable for some applications. For example, AC The nc-OS may be formed by a deposition method such as a sputtering method using a power source. The sputtering method using a C power supply is capable of depositing a highly uniform film on a large substrate. Therefore, semiconductor devices having transistors using nc-OS in their channel formation regions can be manufactured with high productivity. It can be easily produced.

[0136] The oxide semiconductor may have, for example, an amorphous portion. The amorphous oxide semiconductor is a semiconductor in which the atomic arrangement is disordered. The amorphous oxide semiconductor has no crystal parts. It has a state and there is no regularity in the atomic arrangement.

[0137] In addition, in the amorphous oxide semiconductor film, for example, a halo pattern is observed in the electron beam diffraction pattern. In addition, the amorphous oxide semiconductor film may be, for example, In some cases, no spots can be observed and a halo pattern is observed.

[0138] Amorphous oxide semiconductors are formed by, for example, containing a high concentration of impurities such as hydrogen. Therefore, the amorphous oxide semiconductor may be formed by, for example, It is an oxide semiconductor containing

[0139] When an oxide semiconductor contains a high concentration of impurities, defects such as oxygen vacancies occur in the oxide semiconductor. Therefore, an amorphous oxide semiconductor with a high impurity concentration has a high density of defect states. In addition, amorphous oxide semiconductors have low crystallinity, so The defect level density is higher than that of

[0140] Therefore, the amorphous oxide semiconductor has a higher carrier density than the nc-OS. Therefore, a transistor in which an amorphous oxide semiconductor is used for a channel formation region may Therefore, if normally-on electrical characteristics are required, The amorphous oxide semiconductor may be preferably used for a transistor in which Since the defect density is high, the trap density may also be high. Transistors using semiconductors in the channel formation region are based on CAAC-OS and nc-OS. Compared to transistors used in the channel formation region, the electrical characteristics fluctuate greatly and the reliability is low. However, amorphous oxide semiconductors contain a relatively large amount of impurities. Since it can be formed by a film formation method that is usually used, it is easy to form and has a wide range of applications. For example, the spin coating method and the sol-gel method may be used. , dip printing, spraying, screen printing, contact printing, inkjet printing Amorphous oxide semiconductors are formed by deposition methods such as the spray method, roll coating method, and mist CVD method. Therefore, a transistor in which an amorphous oxide semiconductor is used for a channel formation region can be provided. Such a semiconductor device can be manufactured with high productivity.

[0141] Note that the oxide semiconductor may be a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or The mixed film may be a film having two or more kinds of amorphous oxide semiconductors. The region of the crystal oxide semiconductor, the region of the microcrystalline oxide semiconductor, the region of the polycrystalline oxide semiconductor, the region of the CAA In addition, the mixed film may have two or more regions, for example, For example, an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, In some cases, the nanotube may have a laminated structure of two or more of the CAAC-OS and CAAC-OS regions.

[0142] The oxide semiconductor may have a single crystal structure. These are called crystalline oxide semiconductors.

[0143] Single-crystal oxide semiconductors have a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. The transistors used in the formation region may rarely have normally-on electrical characteristics. In addition, since the density of defect states in a single crystal oxide semiconductor is low, the density of trap states is also low. Therefore, a transistor in which a single crystal oxide semiconductor is used for a channel formation region may In this case, the change in electrical characteristics may be small, resulting in a highly reliable transistor.

[0144] For example, the oxide semiconductor has a high density when it has few defects. For example, higher crystallinity leads to higher density. In addition, oxide semiconductors can be easily oxidized by impurities such as hydrogen. For example, a single-crystal oxide semiconductor has a higher density than a CAAC-OS. For example, the CAAC-OS has a higher density than a microcrystalline oxide semiconductor. In addition, for example, a polycrystalline oxide semiconductor may have a higher conductivity than a microcrystalline oxide semiconductor. In addition, for example, a microcrystalline oxide semiconductor may have a higher density than an amorphous oxide semiconductor. may also be denser.

[0145] Next, the semiconductor layer 307 is processed into desired regions to form island-shaped semiconductor layers 308a, 30 In addition, the semiconductor layers 308a, 308b, 308c, and 308d are formed. The formation of 308d is performed by forming a mask by a second patterning in a desired area, and the mask The etching can be performed by etching the areas not covered by the mask. For this purpose, dry etching, wet etching, or a combination of both may be used. (See Fig. 6(A), (B), and (C)). In this way, the island-shaped semiconductor layer 308d is formed by processing the semiconductor layer 307 into a desired region, No additional steps are required, resulting in fewer total steps, lower costs and reduced throughput. You can give a put.

[0146] Next, a first heat treatment is preferably performed. The first heat treatment is performed at a temperature of 250° C. or higher and 650° C. or higher. ℃ or less, preferably 300 ℃ to 500 ℃, in an inert gas atmosphere, an oxidizing gas atmosphere The first heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine or under reduced pressure. The atmosphere is an inert gas atmosphere, and then an oxidizing gas is introduced to replenish the oxygen that has been removed. The first heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine. , 308b, 308c, and 308d, and the crystallinity of the oxide semiconductor is improved. Hydrogen, water, etc. are released from the semiconductor layers 308a, 308b, 308c, and 308d. Before processing the oxide semiconductor into islands, the first heating The process may be carried out.

[0147] In order to provide a transistor with an oxide semiconductor channel with stable electrical characteristics, The present invention relates to a method for making an oxide semiconductor intrinsic or substantially intrinsic by reducing the impurity concentration in the oxide semiconductor. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is 1 ×10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 Being less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0148] In addition, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and a metal element other than the main component For example, hydrogen and nitrogen form donor levels and increase the carrier density. In addition, silicon forms an impurity level in the oxide semiconductor. The levels become traps and may degrade the electrical characteristics of a transistor.

[0149] In order to make an oxide semiconductor intrinsic or substantially intrinsic, it is necessary to determine whether the oxide semiconductor is intrinsic or substantially intrinsic in the SIMS analysis. The silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm 3 less than 1×10 18 atoms / cm 3 Less than. The hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 ato ms / cm 3 Less than or equal to 1×10 19atoms / cm 3 The following is more preferable: 5×10 18 atoms / cm 3 The nitrogen concentration is 5×10 19 at oms / cm 3 Less than 5 x 10 18 atoms / cm 3 More preferably, 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0150] In addition, when the oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the oxide In order to prevent the crystallinity of an oxide semiconductor from being reduced, , silicon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 ato ms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, the carbon concentration is set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 at oms / cm 3 less than 1×10 18 atoms / cm 3 Less than stomach.

[0151] In addition, a transistor using the purified oxide semiconductor for a channel formation region as described above can be fabricated. The off-state current of the transistor is extremely small, and the off-state current normalized by the channel width of the transistor is several It is possible to reduce the resistance from yA / μm to several zA / μm.

[0152] Next, a conductive layer is formed on the insulating layer 306 and the semiconductor layers 308a, 308b, 308c, and 308d. A layer 309 is formed (see Figures 7(A), (B) and (C)).

[0153] The conductive layer 309 may be made of a conductive material such as aluminum, titanium, chromium, nickel, From copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten The metal may be a single metal or an alloy containing the metal as a main component, and may be used as a single layer or a multilayer structure. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a titanium film on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film; It is made of titanium or titanium nitride film and aluminum layered on top of the titanium or titanium nitride film. A titanium or copper film is laminated on top of the titanium or titanium nitride film. A layer structure, a molybdenum film or a molybdenum nitride film, and the molybdenum film or the molybdenum nitride film An aluminum film or a copper film is laminated on the silicon film, and a molybdenum film or There are three-layer structures that form a molybdenum nitride film. Alternatively, a transparent conductive material containing zinc oxide may be used as the conductive layer 309. It can be formed by using a tarring method.

[0154] Next, the conductive layer 309 is processed into a desired region to form conductive layers 310a, 310b, and 311. In addition, the conductive layers 310a, 310c, 310d, 310e, 310f, and 310g are formed. The formation of 10b, 310c, 310d, 310e, 310f, and 310g is performed in the desired area. A mask is formed by patterning in step 3, and the area not covered by the mask is etched. By this technique, the formation of the void can be achieved (see FIGS. 8(A), (B), and (C)).

[0155] In this embodiment, the conductive layers 310a, 310b, 310f, and 310g are semiconductor The insulating layer 306 and the semiconductor layer 308a and 308c are formed on the insulating layer 306 and the semiconductor layer 308a and 308c. It may be formed as follows.

[0156] Next, the insulating layer 306, the semiconductor layers 308a, 308c and the conductive layers 310a, 310b, An insulating layer 311 is formed to cover the layers 10c, 310d, 310e, 310f, and 310g. (See Figures 9(A), (B), and (C)).

[0157] The insulating layer 311 is used as the semiconductor layers 308a, 308b, 308c, and 308d. In order to improve the interface characteristics with the oxide semiconductor, it is necessary to use an inorganic insulating material that contains oxygen. The insulating layer 311 can be formed by using, for example, a PE-CVD method. can.

[0158] An example of the insulating layer 311 is a silicon oxide film having a thickness of 150 nm or more and 400 nm or less. A silicon oxynitride film, an aluminum oxide film, or the like can be used. For the insulating layer 311, a silicon oxynitride film having a thickness of 300 nm is used.

[0159] Next, the insulating layer 311 is processed into desired regions to form openings 372a and 372b. Moreover, the insulating layer 311 becomes the insulating layer 312 in which the openings 372a and 372b are formed. The insulating layer 312 and the openings 372a and 372b are formed in a desired region. A mask is formed by patterning, and the area not covered by the mask is etched. By doing so, it is possible to form the pores (see Figs. 10(A), (B), and (C)).

[0160] The opening 372a is formed so as to expose the insulating layer 305. 2b is formed so as to expose the semiconductor layer 308d. As a method, for example, a dry etching method can be used. The method for forming 2a and 372b is not limited to this, and may be a wet etching method, or A combination of dry etching and wet etching may also be used. When forming an island-shaped semiconductor layer 308d, the semiconductor layer 307 is processed into a desired region. Instead of forming the semiconductor layer 307 by using another semiconductor layer (e.g., ITO In the case where the opening 372b is formed by processing the opening 372b, it is possible to omit the opening 372b. In the case where the island-shaped semiconductor layer 308d and the insulating layer 313 are not in contact with each other, the opening It is also possible to not provide 372b. Alternatively, it is not necessary to form the island-shaped semiconductor layer 308d. If there is no opening 372b, the opening 372b may not be provided.

[0161] Next, the insulating layer 313 is formed on the insulating layers 305 and 312 and the semiconductor layer 308d (FIG. 11(A), (B), and (C)).

[0162] The insulating layer 313 is formed to prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc. The film is formed of a material that prevents diffusion of the impurities into the oxide semiconductor layer and further contains hydrogen. Therefore, when hydrogen in the insulating layer 313 diffuses into the semiconductor layer 308d, In this way, hydrogen bonds with oxygen, generating electrons as carriers. The layer d becomes a conductive layer having high electrical conductivity and light transmitting properties.

[0163] In this embodiment, hydrogen is released from the insulating layer 313 in contact with the semiconductor layer 308d. The method of introduction is not limited to the above. For example, the channel of a transistor A mask is placed on the portion to be the hole formation region, and hydrogen is introduced into the region not covered by the mask. For example, hydrogen may be introduced into the semiconductor layer 308d using an ion doping device or the like. In addition, a light-transmitting conductive film, for example, In this case, a light-transmitting conductive film may be formed on the opening 372. On the insulating layer 312 where b is not provided (i.e., between the insulating layer 312 and the insulating layer 313), It may be formed.

[0164] An example of the insulating layer 313 is an insulating film containing hydrogen with a thickness of 150 nm to 400 nm. For example, a silicon nitride film, a silicon oxynitride film, or the like can be used. In this example, a silicon nitride film having a thickness of 150 nm is used as the insulating layer 313 .

[0165] In addition, the silicon nitride film is preferably formed at a high temperature in order to enhance blocking properties. Preferably, the substrate temperature is 100° C. or higher and lower than the distortion point of the substrate, more preferably 300° C. or higher and 400° C. or higher. It is preferable to form the film by heating at a temperature of 00°C or less. Oxygen is released from the oxide semiconductors used as the dielectric layers 308a, 308b, and 308c, and the carriers are Therefore, the temperature should be set so that this phenomenon does not occur. do.

[0166] Next, the insulating layer 313 is processed into desired regions to form openings 374a, 374b, The insulating layer 313 also has openings 374a, 374b, and 374c. The insulating layer 314 is formed with 374b, 374c, 374d, and 374e. 4, and openings 374a, 374b, 374c, 374d, and 374e are provided for the first A mask is formed by patterning in step 5, and the area not covered by the mask is etched. The formation can be achieved by performing the above-mentioned steps (see Figs. 12(A), (B), and (C)).

[0167] The openings 374a and 374c are formed so as to expose the conductive layers 304b and 304c. The openings 374b, 374d, and 374e are formed by the conductive layers 310c, 310d, and 31 In the region where the opening 374c is to be formed, Similar to the opening 372a, an opening is formed by removing a part of the insulating layers 306 and 312. Good too.

[0168] The openings 374a, 374b, 374c, 374d, and 374e can be formed by For example, a dry etching method can be used. The method for forming 374b, 374c, 374d, and 374e is not limited to the above, and may be a wet etching method. A method using a combination of dry etching and wet etching. It is also possible to use the following.

[0169] Next, the insulating layer 314 covers the openings 374a, 374b, 374c, 374d, and 374e. In this manner, a conductive layer 315 is formed on the insulating layer 314 (see FIGS. 13(A), (B), and (C)). ).

[0170] The conductive layer 315 may be formed of indium oxide containing tungsten oxide, tungsten oxide, or the like. Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide A conductive material with light-transmitting properties, such as indium tin oxide doped with silicon oxide, is used. The conductive layer 315 can be formed by, for example, a sputtering method. It is possible.

[0171] Next, the conductive layer 315 is processed into a desired region, so that the conductive layers 316a, 316b, and 31 The conductive layers 316a, 316b, and 316c are formed in the desired regions. A mask is formed by patterning in step 6, and the area not covered by the mask is etched. The formation can be achieved by performing a step of cutting (see FIGS. 14(A), (B), and (C)).

[0172] The driver circuit portion 104 having the transistors formed on the substrate 302 by the above steps and the pixel The element portion 102 can be formed on the same substrate. In the process, the first to sixth patterning steps, i.e., the driving circuit section, the transistor section, and the like are formed using six masks. A transistor, a capacitance element, etc. can be formed at the same time.

[0173] Next, the structure formed on the substrate 342 provided opposite the substrate 302 will be described below. Provide an explanation.

[0174] First, a substrate 342 is prepared. The substrate 342 is made of the same material as that of the substrate 302. Next, a light-shielding layer 344 and a colored layer 346 are formed on the substrate 342 (FIG. 1). 5(A), (B), (C)).

[0175] The light-shielding layer 344 may be made of a metal or other material as long as it has a function of blocking light in a specific wavelength range. Alternatively, an organic insulating film containing a black pigment or the like can be used.

[0176] The color layer 346 may have a function of transmitting light of a specific wavelength band. For example, For example, a red (R) color filter transmits light in the red wavelength range, and a green (G) color filter transmits light in the green wavelength range. A green (G) color filter transmits light in the blue wavelength range, and a blue (B) color filter transmits light in the blue wavelength range. Each color filter can be printed using various materials. method, inkjet method, and etching method using photolithography technology, respectively. Form in desired location.

[0177] Next, an insulating layer 348 is formed on the light-shielding layer 344 and the colored layer 346 (FIG. 16(A), (See (B) and (C)).

[0178] The insulating layer 348 may be an organic insulating film made of, for example, acrylic resin. By forming the insulating layer 348, for example, impurities contained in the color layer 346 can be removed. It is possible to suppress the diffusion of the liquid crystal layer 320 toward the liquid crystal layer 320. However, the insulating layer 348 must be It is not necessary to form the insulating layer 348, and a structure in which the insulating layer 348 is not formed may be used.

[0179] Next, a conductive layer 350 is formed on the insulating layer 348 (see FIGS. 17(A), (B), and (C)). The conductive layer 350 can be made of the same material as the conductive layer 315.

[0180] Through the above steps, the structure formed on the substrate 342 can be formed.

[0181] Next, the insulating layer 31 formed on the substrate 302 and the substrate 342, more specifically, on the substrate 302, 4. Conductive layers 316a, 316b, 316c and conductive layer 350 formed on substrate 342 The alignment films 318 and 352 are formed on the substrate 314 and 316, respectively. The substrate 302 and the substrate 342 can be formed by using a photoalignment method, a photoalignment method, or the like. The liquid crystal layer 320 is formed between the liquid crystal layers 320. The liquid crystal layer 320 is formed by a dispenser method (droplet method). or by bonding the substrate 302 and the substrate 342 together and then injecting liquid crystal by using capillary action. An injection technique can be used.

[0182] Through the above steps, the display device shown in FIG. 3 can be manufactured.

[0183] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0184] (Embodiment 3) In this embodiment, a modification of the display device described in the first embodiment will be described with reference to FIGS. This will be explained using 20.

[0185] FIG. 18 shows a modified example of the structure shown in FIG. 3 of the first embodiment. The same parts or parts having the same functions are designated by the same reference numerals and their details are described below. The explanation will be omitted.

[0186] FIG. 18A is a cross-sectional view corresponding to the cross-section taken along dashed line X1-Y1 shown in FIG. 2A. FIG. 18(B) is a cross-section taken along dashed lines X2-Y2 and X3-Y3 shown in FIG. 2(B). 18(C) is a cross-sectional view taken along the dashed line X4-Y4 in FIG. 2(C). A cross-sectional view corresponding to the surface is shown.

[0187] The driving circuit section 104 shown in FIG. 18(A) includes a substrate 302 and a conductive layer formed on the substrate 302. The conductive layers 304a and 304b are formed on the substrate 302 and the conductive layers 304a and 304b. An insulating layer 305, an insulating layer 306 formed on the insulating layer 305, and a A semiconductor layer 308a formed in a position overlapping with the conductive layer 304a, An insulating layer 370 formed on the semiconductor layer 308a and a conductive layer formed on the insulating layer 370 and the semiconductor layer 308a. The conductive layers 310a and 310b, the conductive layer 310c formed on the insulating layer 370, and the semiconductor layer 3 08a, and an insulating layer 312 formed to cover the conductive layers 310a, 310b, and 310c. An insulating layer 314 is formed on the insulating layer 312, and a conductive layer 3 is formed on the insulating layer 314. 16a and

[0188] In the driving circuit section 104 shown in FIG. 18A, the conductive layer 316a is The conductive layer 304b has a function as a wiring that connects the insulating layer 304b and the conductive layer 310c. Through openings formed in layers 305, 306, 312, 314, and 370, conductive layer 310 c is connected by a conductive layer 316a through an opening formed in the insulating layers 312 and 314. can be.

[0189] In the driver circuit portion 104 shown in FIG. 18A, the conductive layer 310a and the conductive layer 3 10b is connected to the semiconductor layer 308a through an opening formed in the insulating layer 370.

[0190] The driving circuit section 104 shown in FIG. 18(B) includes a substrate 302 and a conductive layer formed on the substrate 302. and a conductive layer 304c, 304d, and a conductive layer 304c, 304d formed on the substrate 302 and the conductive layer 304c, 304d. The insulating layer 305 and the conductive layer 304d are formed on the insulating layer 305 so as to overlap with each other. a conductive layer 304d formed over the insulating layer 306 and overlapping with the conductive layer 304d; a semiconductor layer 308b formed over the semiconductor layer 308b at a position overlapping with the conductive layer 304d; The insulating layer 370 is formed on the insulating layer 306, the conductive layer 310d is formed on the insulating layer 306, and the insulating layer 370, the insulating layer 306, and the conductive layers 310d and 310e. an insulating layer 312 formed to cover the insulating layer 312; and an insulating layer 314 formed on the insulating layer 312. In addition, a conductive layer 316b is formed over the insulating layer 314.

[0191] In the driving circuit section 104 shown in FIG. 18B, the conductive layer 316b is The conductive layer 316b has a function as a wiring for connecting the insulating layer 4c and the conductive layer 310d. The openings in the layers 305, 306, 312, 314, and 370 and the insulating layers 312 and 31 4, the conductive layer 310d is connected to the conductive layer 310c through an opening formed in the conductive layer 310d.

[0192] In the driving circuit section 104 shown in FIG. 18(B), similar to the driving circuit section 104 shown in FIG. The electrostatic breakdown inducing region 360 is formed in the first embodiment. The effect is the same as that shown in FIG.

[0193] In the driving circuit section 104 shown in FIG. 18B, the conductive layer 304d and the conductive layer 31 Between 0e, the insulating layer 305, the insulating layer 306, the semiconductor layer 308b, and the insulating layer 370, In addition to the insulating layer 305 and the insulating layer 306, the semiconductor layer 308b and the insulating layer 370 are By forming the conductive layer 304d, the distance between the conductive layer 304d and the conductive layer 310e can be increased. Therefore, it is possible to reduce the parasitic capacitance that may occur between the conductive layer 304d and the conductive layer 310e. In addition, by increasing the distance between the conductive layer 304d and the conductive layer 310e, This can reduce the possibility of short circuiting between the conductive layer 304d and the conductive layer 310e.

[0194] The pixel portion 102 shown in FIG. 18C includes a substrate 302 and a conductive layer formed on the substrate 302. 304e, an insulating layer 305 formed on the substrate 302 and the conductive layer 304e, and an insulating layer 3 05, and a conductive layer 304e formed on the insulating layer 306. The semiconductor layer 308c is formed at a position corresponding to the insulating layer 306. d, an insulating layer 370 formed on the semiconductor layer 308c, and a semiconductor layer 3 08c, the conductive layers 310f and 310g, the insulating layer 370, and the conductive layer 310f An insulating layer 312 is formed so as to cover the semiconductor device 310g. An insulating layer 314 formed on the conductor layer 308d, and a conductive layer 315 formed on the insulating layer 314. and a conductive layer 316c connected to 310g.

[0195] The conductive layer 316c is formed through an opening formed in the insulating layers 312 and 314. Connected to 310g.

[0196] In this way, the display devices shown in FIGS. 18(A), (B), and (C) can be used in the same manner as in FIGS. The display device shown in FIG. 1C is different from the display device shown in FIG. 1 in that an insulating layer 370 is formed. The insulating layer 370 is After the semiconductor layers 308a, 308b, 308c, and 308d are formed, an insulating layer is formed. The insulating layer 370 can be formed by processing the insulating layer 312. The present invention can be formed by any suitable material and method.

[0197] By forming an insulating layer 370, it is possible to cover the semiconductor layers 308a and 308c. The semiconductor layers 308a and 308c are exposed through an opening provided in the insulating layer 370. Conductive layers 310a, 310b, and 310f functioning as source and drain electrodes. When processing the conductive layer that functions as the source electrode and the drain electrode, Therefore, the semiconductor layers 308a and 308c are protected by the insulating layer 370. functions as a so-called channel protective film.

[0198] In the display devices shown in FIGS. 3A, 3B, and 3C, As shown in Fig. 18(A), (B), and (C), it can be fabricated with six masks. In the display device shown in FIG. 1, the number of masks is increased by one, so that the display device can be manufactured using seven masks. .

[0199] In the transistors 131_3 and 131_1 shown in FIG. In the above embodiment, the semiconductor layers 308a and 308c are covered, but the present invention is not limited to this. For example, as shown in FIG. 19, an insulating layer 370 is formed only in the channel formation region of a transistor. However, as shown in FIG. 18, the semiconductor layers 308a and 308c may be provided with a structure in which The insulating layer 370 also covers the periphery, preventing impurities that may penetrate into the semiconductor layers 308a and 308c. Since the insulating layer 370 can protect the device from damage, the structure shown in FIG. is a more preferable structure.

[0200] Next, the display device shown in FIG. 20 will be described below.

[0201] 20(A) and (B) show modified examples of the structure shown in FIG. 3(A) of the first embodiment. , the same parts or parts having the same functions as those in the above embodiments are Reference numerals are given to these components, and detailed explanations thereof are omitted.

[0202] The driving circuit section 104 shown in FIG. 20A has the following features in comparison with the driving circuit section 104 shown in FIG. The method of connecting the conductive layer 304b and the conductive layer 310c is different. In the driving circuit unit 104 shown in FIG. 1, a part of the conductive layer 310c overlaps a part of the conductive layer 304b. The conductive layer 304b and the conductive layer 310c are disposed in a line with each other via the conductive layer 316a. In this manner, a part of the conductive layer 310c is overlapped with a part of the conductive layer 304b. By providing the driver circuit in this way, the area of ​​the driver circuit can be reduced. 1A, when the driver circuit unit 104 shown in FIG. This makes it possible to reduce the area of ​​the gate driver 104a.

[0203] The driving circuit section 104 shown in FIG. 20B has the following features in comparison with the driving circuit section 104 shown in FIG. The insulating layer 370 is formed, and the conductive layer 304b and the conductive layer 310c are connected in a different manner. The insulating layer 370 has the same function and effect as the insulating layer 370 shown in FIG. The conductive layer 304b and the conductive layer 310c are connected in the same manner as shown in FIG. It has the same function and effect.

[0204] As described above, in the display device shown in this embodiment, the electrostatic breakdown inducing region is formed in the driver circuit portion. The electrostatic breakdown inducing region includes a wiring formed in the same process as the gate electrode and a source The thickness of the insulating film formed between the drain electrode and the wiring formed in the same process as the drain electrode is By making it thinner, i.e. shortening the distance between the wiring, the insulating film between other wiring patterns can be In the electrostatic breakdown inducing region, the gate electrode and The shape of the wiring formed in the same process is comb-shaped, so the overcurrent that may occur due to ESD is The structure is easy to flush.

[0205] As described above, one embodiment of the present invention is a display device having an electrostatic breakdown inducing region in a driver circuit portion. By doing so, it is possible to provide a novel display device with improved reliability.

[0206] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0207] (Embodiment 4) In this embodiment, a modification of the electrostatic breakdown inducing region 360 described in the first embodiment is described. This will be explained using FIG.

[0208] In the first embodiment, the electrostatic breakdown inducing region 360 is formed in the drive circuit section 104. In the present embodiment, the electrostatic discharge inductive element is provided on the outer periphery of the display device. A configuration for forming a light emitting region will be described.

[0209] FIG. 21A is a schematic top view of the display device and the peripheral portion of the display device. FIG. 1(B) is a schematic diagram showing an enlarged top view of the electrostatic breakdown inducing region 362a shown in FIG. 21C corresponds to a cross-sectional view taken along the line X5-Y5 shown in FIG. 21B. do.

[0210] FIG. 21A shows a pixel section 102, a gate driver 104a, and a source driver 104. b are formed on the display device 100. In addition, a plurality of A guard ring 362 including wiring is formed. The guard ring 362 is It has area 362a.

[0211] As shown in FIG. 21A, a guard ring 362 is formed on the outer periphery of the display device 100. As a result, the display device 100 is protected against overcurrent caused by ESD or the like that may occur during the manufacturing process of the display device 100. For example, the display device 100 can be protected from damage caused during the manufacturing process of the display device 100. The guard ring 362 acts as an antenna for the excess current, and the excess current is transmitted to the guard ring 362. In this way, by forming the guard ring 362, the display device 10 0 can be protected from overcurrent caused by ESD, etc.

[0212] FIG. 21B is an enlarged view of an electrostatic breakdown inducing region 362a formed in the guard ring 362. 21(A), (B), and (C), the electrostatic breakdown inducing region 362a The following will explain this.

[0213] The electrostatic breakdown inducing region 362a is a region including a substrate 402 and a conductive layer 404 formed on the substrate 402. An insulating layer 405 formed on the substrate 402 and the conductive layer 404; A conductive layer 410 is formed on the insulating layer 406. An insulating layer 412 formed on the conductive layer 410 and an insulating layer 414 formed on the insulating layer 412 and a conductive layer 416 formed on the insulating layer 414.

[0214] The substrate 402 is made of a material that can be used for the substrate 302 shown in the above embodiment. The conductive layer 404 may be formed by the same method as that of the conductive layer 3 shown in the above embodiment. The insulating layer 405 can be made of any of the materials that can be used for the insulating layer 404a. The insulating layer 305 may be formed by using the materials shown in the previous embodiment. The insulating layer 406 can be used as the insulating layer 306 in the above embodiment. The conductive layer 410 may be formed of any of the materials described in the previous embodiment. The materials usable for the conductive layer 310a shown in FIG. The insulating layer 412 may be formed using a material that can be used for the insulating layer 312 shown in the previous embodiment. The insulating layer 414 can be used as the insulating layer 314 shown in the above embodiment. The conductive layer 416 can be formed by using the same material as that described above. The materials that can be used for the conductive layer 316a shown in the embodiment mode can be used. Cut.

[0215] The electrostatic breakdown inducing region 362a has an opening 474a and an opening 474b. The opening 474a is formed by removing a portion of the insulating layers 405, 406, 412, and 414, and forming a conductive layer. In addition, the opening 474b is formed by removing a part of the insulating layers 412 and 414. The conductive layer 410 is exposed through the openings 474a and 474b. Conductive layer 404 and conductive layer 410 are connected by conductive layer 416 formed thereon.

[0216] In this embodiment, the conductive layer 416 is formed on the upper portion of the electrostatic breakdown inducing region 362a. Although a shape covering the entire surface will be described, the present invention is not limited to this. For example, the openings 474a and 47 Alternatively, the conductive layer 416 may be formed only on the portion where the conductive layer 414b is formed. The guard ring 362 and the guard ring 362 may be omitted. The electrostatic breakdown inducing region 362a is formed on the outer periphery of the display device 100. Therefore, the method of connecting the conductive layer 404 and the conductive layer 410 is The shape of the upper surfaces of the conductive layers 404 and 410 may be determined by the practitioner as appropriate. can be selected.

[0217] The effect of the electrostatic breakdown inducing region 362a is the same as that of the electrostatic breakdown inducing region 362 shown in the first embodiment. It has the same effect as trigger area 360.

[0218] In this manner, in the present embodiment, a static electricity breakdown inducing region is formed on the outer periphery of the display device. By doing so, it is possible to provide a novel display device that can have improved reliability.

[0219] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0220] (Embodiment 5) In this embodiment, a circuit that can be used for the pixel circuit portion 108 shown in FIG. The circuit configuration will be described with reference to FIG. 22. The same reference numerals are used for the parts having the same functions, and detailed explanations thereof will be omitted.

[0221] The pixel circuit portion 108 shown in FIG. 22A includes a liquid crystal element 322 and a transistor 131_1. and a capacitor 133_1.

[0222] The potential of one of the pair of electrodes of the liquid crystal element 322 is appropriately set according to the specifications of the pixel circuit unit 108. The alignment state of the liquid crystal element 322 is set by the written data. A common electrode is connected to one of a pair of electrodes of the liquid crystal element 322 included in each of the pixel circuit units 108. A potential (common potential) may be applied to the liquid crystal elements 322 of the pixel circuit unit 108 in each row. A different potential may be applied to one of the pair of electrodes.

[0223] For example, the display device including the liquid crystal element 322 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0224] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be configured by the liquid crystal that exhibits the blue phase. Since it is short and optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0225] In the pixel circuit portion 108 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 322. The gate of the transistor 131_1 is electrically connected to the other of the scan lines GL_ m. The transistor 131_1 is turned on or off. This has the function of controlling the writing of data of the data signal.

[0226] One of a pair of electrodes of the capacitor 133_1 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 322. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 111. The capacitor 133_1 has a function as a storage capacitor for storing written data. do.

[0227] For example, in a display device having a pixel circuit portion 108 shown in FIG. 4a sequentially selects the pixel circuit units 108 in each row and turns on the transistors 131_1. and writes the data of the data signal.

[0228] In the pixel circuit portion 108 to which the data is written, the transistor 131_1 is turned off. By repeating this process row by row, an image can be displayed.

[0229] The pixel circuit portion 108 shown in FIG. 22B includes a transistor 131_2 and a capacitor The pixel circuit 130 includes a pixel 133_2, a transistor 134, and a light-emitting element 135.

[0230] One of the source and drain of the transistor 131_2 is connected to a wiring to which a data signal is applied. (hereinafter, referred to as data line DL_n). Further, the transistor 131 The gate of _2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is given. is connected to.

[0231] The transistor 131_2 is turned on or off to output the data signal. It has a function to control writing of data.

[0232] One of a pair of electrodes of the capacitance element 133_2 is connected to a wiring through which power is supplied (hereinafter, a power supply line VL _a), and the other is electrically connected to the source and drain of the transistor 131_2. The other terminal is electrically connected to the other terminal.

[0233] The capacitor 133_2 has a function as a storage capacitor for storing written data. .

[0234] One of the source and drain of the transistor 134 is electrically connected to the power supply line VL_a. Furthermore, the gate of the transistor 134 is connected to the source and drain of the transistor 131_2. The other of the drains is electrically connected to the other of the drains.

[0235] One of the anode and the cathode of the light emitting element 135 is electrically connected to the power supply line VL_b. The other is electrically connected to the other of the source and drain of the transistor 134 .

[0236] The light-emitting element 135 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light emitting element 135 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0237] A high power supply potential VDD is applied to one of the power supply lines VL_a and VL_b. The other terminal is supplied with a low power supply potential VSS.

[0238] In the display device having the pixel circuit portion 108 in FIG. 22(B), The pixel circuit units 108 in each row are sequentially selected, the transistors 131_2 are turned on, and the data Write the data of the data signal.

[0239] In the pixel circuit unit 108 to which the data is written, the transistor 131_2 is turned off. In addition, the transistor 1 is turned on in response to the potential of the written data signal. The amount of current flowing between the source and drain of the light emitting element 135 is controlled by the amount of current flowing between the source and drain of the light emitting element 34. By performing this process row by row, an image can be displayed.

[0240] In this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element, can be used in various forms or in various Examples of a display element, a display device, a light-emitting element, or a light-emitting device include , EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) ), transistors (transistors that emit light according to electric current), electron-emitting devices, liquid crystal devices, Dye ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), MEMS (Micro Electro Mechanical Systems), Digital Ma Micromirror Device (DMD), DMS (Digital Micro Shutter), MIR ASOL (registered trademark), IMOD (Interference Modulation) element, pressure Electro-magnetic effects in ceramic displays, carbon nanotubes, etc. Some have display media that change in transparency, brightness, reflectance, transmittance, etc. An example of a display device using electron emission elements is an EL display. An example of a display device is a field emission display (FED) or SED type. Flat panel display (SED: Surface-conduction Electr Examples of display devices using liquid crystal elements include Examples include LCDs (transmissive LCDs, semi-transmissive LCDs, reflective LCDs, etc.) LCD displays include projection LCDs, direct-view LCDs, and projection LCDs. An example of a display device using electronic ink or electrophoretic elements is electronic paper. do.

[0241] An example of an EL element is a device that includes an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. One example of an EL layer is a device that uses light emission (fluorescence) from singlet excitons. Those that utilize emission from triplet excitons (phosphorescence), and those that utilize emission from singlet excitons ( those that utilize fluorescence and those that utilize emission from triplet excitons (phosphorescence), Those formed by organic matter, those formed by inorganic matter, those formed by organic matter Materials made of polymeric materials, including materials made of inorganic materials and materials made of inorganic materials. , those containing low molecular weight materials, or those containing high molecular weight materials and low molecular weight materials, etc. However, the present invention is not limited to these, and various EL elements can be used.

[0242] An example of a liquid crystal element is a liquid crystal device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation of the liquid crystal is achieved by applying an electric field (horizontal electric field, vertical electric field or oblique electric field) to the liquid crystal. In addition, a specific example of a liquid crystal element is a chromatic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermo tropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PD LC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, banana type liquid crystal, etc. The following can be mentioned.

[0243] One example of the display method for electronic paper is the molecular display (optical anisotropy, dye molecular orientation, etc.), and those displayed by particles (electrophoresis, particle migration, particle rotation, phase change, etc.) ), those that are displayed by the movement of one edge of the film, and those that are displayed by coloring / phase change of molecules. Some are indicated by the absorption of light by molecules, others by the self-assembled electron and hole combination. The display may be made by emitting light. Specifically, the display may be made of electronic paper. Examples of methods include microcapsule electrophoresis, horizontal migration electrophoresis, and vertical migration electrophoresis. Electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner -, electronic powder, magnetic migration type, magnetic heat sensitive type, electrowetting, light scattering (transparent / White opacity change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic Liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color development and erasure by leuco dye , photochromic, electrochromic, electrodeposition, flexible However, there are various electronic paper and its display methods, including but not limited to these. Various types of electrophoresis can be used. This can solve the aggregation and precipitation of electrophoretic particles. It has advantages such as high reflectance, wide viewing angle, low power consumption, and memory properties.

[0244] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0245] (Embodiment 6) In this embodiment, the pixel portion 102 of the display device shown in FIG. The structure of a transistor that can be used in the driver circuit portion 104 will be described with reference to FIG. The following explanation is provided.

[0246] The transistor shown in FIG. 23A includes a conductive layer 304a formed over a substrate 302 and a Insulating layers 305 and 306 are formed on the plate 302 and the conductive layer 304a, and on the insulating layer 306 The oxide stack 390 formed, the insulating layer 306 and the conductive layer formed on the oxide stack 390 The transistor shown in FIG. A semiconductor device is formed on the transistor, more specifically, on the oxide stack 390 and the conductive layers 310a and 310b. The insulating layers 312 and 314 may be formed on the insulating film 312 .

[0247] Depending on the type of conductive film used for the conductive layers 310a and 310b, the oxide stack 390 3, and removes oxygen from a portion of the oxide stack 390 or forms a mixed layer, forming an n-type region 392 in the oxide stack 390. In FIG. 23A, n-type region 392 may be formed in oxide stack 390. The n-type region 39 may be formed in the region near the interface where the conductive layers 310a and 310b are in contact. 2 can function as a source region and a drain region.

[0248] In the transistor shown in FIG. 23A, the conductive layer 304a functions as a gate electrode. The conductive layer 310a functions as a source electrode or a drain electrode, and the conductive layer 310b functions as a source electrode or a drain electrode. It functions as a source electrode or a drain electrode.

[0249] In addition, in the transistor illustrated in FIG. 23A, the oxide film in the region overlapping with the conductive layer 304a is The distance between the conductive layer 310a and the conductive layer 310b of the layer 390 is called the channel length. The oxide stack 390 includes a conductive layer 304a and a conductive layer 304b. The channel is a region sandwiched between the conductive layer 310a and the conductive layer 310b. In a semiconductor device, the term "internal current" refers to the area through which electric current mainly flows.

[0250] The oxide stack 390 will now be described in detail with reference to FIG.

[0251] FIG. 23B is an enlarged view of the oxide stack 390 shown in FIG. The semiconductor layer 90 includes an oxide semiconductor layer 390a and an oxide layer 390b.

[0252] The oxide semiconductor layer 390a contains at least indium (In), zinc (Zn) and Mn (Al). In-MZ containing elements such as I, Ga, Ge, Y, Zr, Sn, La, Ce or Hf It is preferable that the oxide semiconductor layer 390a includes a layer represented by n-oxide. The oxide semiconductor material or the formation Methods etc. can be used as appropriate.

[0253] The oxide layer 390b is composed of one or more elements that constitute the oxide semiconductor layer 390a. The energy of the conduction band minimum is 0.05 eV or more and 0.07 eV or more higher than that of the oxide semiconductor layer 390a. eV or more, 0.1 eV or more or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 The gate electrode is an oxide film having a potential of 0.4 eV or less, or close to the vacuum level. When an electric field is applied to the conductive layer 304a, the oxide stack 390 is A channel is formed in the oxide semiconductor layer 390a having low energy. By having an oxide layer 390b between the semiconductor layer 390a and the insulating layer 312, The channel of the transistor can be formed in the oxide semiconductor layer 390a that is not in contact with the insulating layer 312. In addition, the oxide layer 390b can be formed from one or more of the elements constituting the oxide semiconductor layer 390a. Therefore, the interface diffusion is performed between the oxide semiconductor layer 390a and the oxide layer 390b. Therefore, the oxide semiconductor layer 390a and the oxide layer 390b are not easily disturbed. In this case, the movement of carriers is not hindered, and thus the field effect mobility of the transistor is increased. In addition, an interface state is unlikely to be formed between the oxide semiconductor layer 390a and the oxide layer 390b. If there is an interface state between the oxide semiconductor layer 390a and the oxide layer 390b, the interface is formed as a channel. A second transistor having a different threshold voltage is formed, and the apparent The threshold voltage may vary. Therefore, by providing the oxide layer 390b, In this way, it is possible to reduce variations in electrical characteristics, such as the threshold voltage, of the transistors.

[0254] The oxide layer 390b is made of In-M-Zn oxide (Al, Ti, Ga, Ge, Y, Zr , Sn, La, Ce, Hf, or other elements) and is higher than the oxide semiconductor layer 390a. Specifically, the oxide layer 390b includes an oxide semiconductor The layer 390a contains at least 1.5 times, preferably at least 2 times, more preferably at least 3 times the above elements. The oxide layer contains indium at an atomic ratio of more than 100 times higher than that of the oxide layer. Therefore, it has a function of suppressing the occurrence of oxygen deficiency in the oxide layer. The layer 390b is an oxide layer in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 390a.

[0255] That is, the oxide semiconductor layer 390a and the oxide layer 390b contain at least indium, zinc When the oxide layer 390b is an In-M-Zn oxide containing M, the oxide layer 390b is In:M:Zn=x1 y1:z1 [atomic ratio], and the oxide semiconductor layer 390a is In:M:Zn=x2:y2:z 2 [atomic ratio], it is preferable that y1 / x1 is greater than y2 / x2. y1 / x1 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, than y2 / x2. At this time, in the oxide semiconductor layer 390a, when y2 is equal to or larger than x2, The electrical characteristics of the transistor can be stabilized. However, y2 must be three or more times larger than x2. Since the field effect mobility of the transistor decreases, y2 is less than three times x2. It is preferable.

[0256] When the oxide semiconductor layer 390a is an In-M-Zn oxide, the number of atoms of In and M is The ratio is preferably 25 atomic % In when the sum of In and M is 100 atomic %. at least 75 atomic %, and more preferably In is 34 atomic % or less. % or more and M is less than 66 atomic %. In the case of Zn oxide, the atomic ratio of In and M is 100 atoms. c%, preferably In is less than 50 atomic % and M is 50 atomic % or more. More preferably, In is less than 25 atomic % and M is 75 atomic % or more. do.

[0257] The oxide semiconductor layer 390a and the oxide layer 390b contain, for example, indium, zinc, and An oxide semiconductor containing gallium can be used. 0a is In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1; In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=3:1:2 or similar The oxide layer 390b may have a composition of In:Ga:Zn =1:3:2 [atomic ratio] In-Ga-Zn oxide, In:Ga:Zn=1:6:4 [ In-Ga-Zn oxide with In:Ga:Zn=1:9:6 [atomic ratio] An n-Ga-Zn oxide or an oxide having a composition close thereto can be used.

[0258] The thickness of the oxide semiconductor layer 390a is 3 nm or more and 200 nm or less, preferably 3 nm or less. m is from 0.1 to 100 nm, and more preferably from 0.1 to 50 nm. The thickness of the layer 390b is 3 nm to 100 nm, preferably 3 nm to 50 nm. do.

[0259] Next, the band structure of the oxide stack 390 will be described with reference to FIGS. do.

[0260] For example, the oxide semiconductor layer 390a may be an I Using n-Ga-Zn oxide, the oxide layer 390b has an energy gap of 3.5 eV. The energy gap is measured using a spectroscopic ellipsometer (H Measurements were performed using ORIBA JOBIN (YVON UT-300).

[0261] Vacuum levels and valence band top energies of the oxide semiconductor layer 390a and the oxide layer 390b The difference (also called the ionization potential) was 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). raviolet Photoelectron Spectroscopy) equipment (U Measurements were performed using a VersaProbe (registered trademark) from LVAC·PHI.

[0262] Therefore, the vacuum level and the conduction band minimum of the oxide semiconductor layer 390a and the oxide layer 390b are The energy difference (also called electron affinity) was 4.85 eV and 4.7 eV, respectively. Ta.

[0263] FIG. 23C shows a schematic diagram of a part of the band structure of the oxide stack 390. In the following, a case will be described in which a silicon oxide film is provided in contact with the oxide stack 390. EcI1 shown in 23(C) indicates the energy of the bottom of the conduction band of the silicon oxide film, and EcS1 indicates the energy of the bottom of the conduction band of the oxide semiconductor layer 390a, and EcS2 indicates the energy of the bottom of the conduction band of the oxide semiconductor layer 390a. b, and EcI2 is the energy of the conduction band of the silicon oxide film. In addition, EcI1 corresponds to the insulating layer 306 in FIG. corresponds to the insulating layer 312 in FIG.

[0264] As shown in FIG. 23C, in the oxide semiconductor layer 390a and the oxide layer 390b, The energy at the bottom of the conduction band changes smoothly without any barrier. In other words, it changes continuously. This is because the oxide stack 390 and the oxide semiconductor layer 390a are made of the same material. and oxygen is transferred between the oxide semiconductor layer 390a and the oxide layer 390b. This can be said to be because a mixed layer is formed by the above-mentioned process.

[0265] As shown in FIG. 23C, the oxide semiconductor layer 390a of the oxide stack 390 serves as a well. In the transistor using the oxide stack 390, the channel region is the oxide semiconductor layer 3 It can be seen that the oxide stack 390 is formed at 90a. Since the temperature changes continuously, the oxide semiconductor layer 390a and the oxide layer 390b are continuously joined. It can also be said that this is the case.

[0266] As shown in FIG. 23C, the oxide layer 390b and the insulating layer 312 are adjacent to each other. In the case of the oxide layer 390b, trap levels due to impurities or defects may be formed. By this, the oxide semiconductor layer 390a can be separated from the trap level. However, when the energy difference between EcS1 and EcS2 is small, the oxide semiconductor layer 390 An electron at a can exceed the energy difference and reach the trap level. When electrons are trapped, negative charges are generated at the interface of the insulating film, lowering the threshold voltage of the transistor. The pressure shifts in the positive direction. Therefore, the energy difference between EcS1 and EcS2 When the threshold voltage of the transistor is set to 0.1 eV or more, preferably 0.15 eV or more, This is preferable because it reduces voltage fluctuations and provides stable electrical characteristics.

[0267] FIG. 23D is a schematic diagram showing a part of the band structure of the oxide stack 390. In this example, a silicon oxide film is placed in contact with the oxide stack 390. The case where the silicon oxide film is provided will be described. EcS1 represents the energy of the conduction band minimum of the oxide semiconductor layer 390a. EcI2 indicates the energy at the bottom of the conduction band of the silicon oxide film. I1 corresponds to the insulating layer 306 in FIG. 23(A), and EcI2 corresponds to In this case, it corresponds to the insulating layer 312 .

[0268] In the transistor shown in FIG. 23A, the conductive layers 310a and 310b are oxidized during formation. The upper part of the oxide stack 390, i.e., the oxide layer 390b, may be etched. The upper surface of the oxide semiconductor layer 390a is the oxide semiconductor layer 390 when the oxide layer 390b is formed. In some cases, a mixed layer of oxide layer 390a and oxide layer 390b may be formed.

[0269] For example, the oxide semiconductor layer 390a is an oxide semiconductor layer having an atomic ratio of In:Ga:Zn=1:1:1. n-Ga-Zn oxide, or In-Ga with In:Ga:Zn=3:1:2 [atomic ratio] -Zn oxide, and the oxide layer 390b has an atomic ratio of In:Ga:Zn=1:3:2. In-Ga-Zn oxide with In:Ga:Zn=1:6:4 [atomic ratio] In the case of Ga-Zn oxide, the amount of Ga in the oxide layer 390b is larger than that in the oxide semiconductor layer 390a. Due to the high content, a GaOx layer or an oxide semiconductor layer is formed on the upper surface of the oxide semiconductor layer 390a. A mixed layer containing more Ga than layer 390a may be formed.

[0270] Therefore, even when the oxide layer 390b is etched, the EcI The energy of the bottom of the conduction band on the 2 side becomes higher, resulting in the band structure shown in Figure 23(D). There are cases.

[0271] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0272] (Embodiment 7) In this embodiment, a touch panel that can be combined with the display device of one embodiment of the present invention is The switch sensor and the display module will be described with reference to FIGS.

[0273] FIG. 24A is an exploded perspective view showing a configuration example of a touch sensor 4500, and FIG. FIG. 25 is a plan view showing an example of the configuration of the electrodes of the touch sensor 4500. 4 is a cross-sectional view showing an example of the configuration of a sensor 4500. FIG.

[0274] The touch sensor 4500 shown in FIGS. 24A and 24B is provided on a substrate 4910 in the X-axis direction. A plurality of conductive layers 4510 arranged in a row and a plurality of conductive layers arranged in a Y-axis direction intersecting an X-axis direction The touch sensor 4500 shown in FIGS. 45, a plan view in which a plurality of conductive layers 4510 are formed and a plan view in which a plurality of conductive layers 4520 are formed are separated. are displayed apart.

[0275] FIG. 25 shows the conductive layer 4510 and the conductive layer 452 of the touch sensor 4500 shown in FIG. 25. As shown in FIG. 25, the conductive layer 4510 and the conductive layer 45 At the intersection of 20, a capacitance 4540 is formed.

[0276] The conductive layers 4510 and 4520 have a structure in which a plurality of quadrilateral-shaped conductive films are connected. The conductive layers 4510 and the conductive layers 4520 are formed in a quadrilateral shape of the conductive film. The conductive layers 4510 and 4520 are arranged so as not to overlap each other. In the portion, an insulating film is provided between the conductive layer 4510 and the conductive layer 4520 so that they do not come into contact with each other. There are.

[0277] FIG. 26 shows the conductive layer 4510 and the conductive layer 452 of the touch sensor 4500 shown in FIG. 4 is a cross-sectional view illustrating an example of a connection structure with a conductive layer 4510 (conductive layers 4510a, 4 A cross-sectional view of the intersection of 510b, 4510c) and 4520 is shown as an example.

[0278] As shown in FIG. 26, the conductive layer 4510 includes a first conductive layer 4510a and a conductive layer 45 10b, and a second conductive layer 4510c on the insulating layer 4810. The conductive layer 4510a and the conductive layer 4510b are connected by the conductive layer 4510c. The conductive layer 4520 is formed of the first conductive film. An insulating layer 4820 is formed covering the insulating layer 10. For example, a silicon oxynitride film may be formed. A base film made of an insulating film may be formed between the electrodes 4710. The base film may be, for example, an oxide film. A silicon nitride film can be formed.

[0279] The conductive layer 4510 and the conductive layer 4520 are formed using a conductive material that transmits visible light. For example, the conductive material having a light-transmitting property is indium tin oxide containing silicon oxide, oxide These include indium tin oxide, zinc oxide, indium zinc oxide, and zinc oxide doped with gallium. do.

[0280] The conductive layer 4510a is connected to an electrode 4710. The electrode 4710 is connected to an FPC. The conductive layer 4520 also constitutes a connection terminal. The electrode 4710 may be formed, for example, from a tungsten film.

[0281] An insulating layer 4820 is formed over the conductive layers 4510, 4520 and 4710. In order to electrically connect the electrode 4710 to the FPC, an insulating layer 4810 on the electrode 4710 and An opening is formed in the insulating layer 4820. A substrate 4920 is attached on the insulating layer 4820. The substrate 4 is attached by adhesive or adhesive film. The touch panel is constructed by attaching the 910 side to the color filter substrate of the display panel. can be.

[0282] Next, a display module in which the display device of one embodiment of the present invention can be used will be described with reference to FIG. 7 will be used for explanation.

[0283] The display module 8000 shown in FIG. 27 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board It has a board 8010 and a battery 8011 .

[0284] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 8006.

[0285] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0286] The backlight unit 8007 includes a light source 8008. Alternatively, the light diffusing plate may be provided at the end of the light unit 8007.

[0287] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0288] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if commercial power is used.

[0289] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0290] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0291] (Embodiment 8) In this embodiment, an example of an electronic device will be described.

[0292] 28(A) to 28(H) and 29(A) to 29(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and a LE. D lamp 5004, operation key 5005 (including power switch or operation switch), connection Terminal 5006, sensor 5007 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance , light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation (including functions to measure flow rate, humidity, gradient, vibration, odor, or infrared rays), 5008, etc.

[0293] FIG. 28(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 28(B) shows a mobile phone equipped with a recording medium. A portable image reproducing device (e.g., a DVD reproducing device) and, in addition to the above, the following devices are also included: The display unit 5002, the recording medium reading unit 5011, etc. In addition to the above, the display includes a second display unit 5002 and a support unit 5012. , earphones 5013, etc. FIG. 28(D) shows a portable game machine. In addition to the above, the recording medium reading unit 5011 and the like can be included. This is a digital camera with a television receiving function, and in addition to the above, it also has an antenna 5014, The mobile phone may have a shutter button 5015, an image receiving unit 5016, etc. This is a slot machine, and in addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, , etc. FIG. 28(G) shows a television receiver, which, in addition to the above, has The portable television receiver may include a tuner, an image processor, etc. In addition to the above, the device includes a charger 5017 capable of transmitting and receiving signals. FIG. 29(A) shows a display, which includes, in addition to the above, a support base 5018, FIG. 29(B) shows a camera, which, in addition to the above, has external connections. The device may have a port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 29(C) shows a computer that, in addition to the above, includes a pointing device 5 020, an external connection port 5019, a reader / writer 5021, etc. FIG. 29(D) shows a mobile phone, which, in addition to the above, includes a transmitting unit, a receiving unit, a mobile phone / transmitter a tuner for one segment partial reception service for mobile terminals, etc.

[0294] The electronic devices shown in FIGS. 28(A) to 28(H) and 29(A) to 29(D) are For example, various information (still images, videos, text images, etc.) can be stored. ) on the display, touch panel function, calendar, date or time display, etc. Functions for controlling processing by various software (programs), wireless communication functions , a function for connecting to various computer networks using wireless communication functions, wireless communication functions A function for transmitting or receiving various data using the Or, the data can be read and displayed on a display unit. In electronic devices having such a display unit, one display unit is used mainly to display image information, and another display unit is used A function that mainly displays text information on one display unit, or a function that takes parallax into consideration on multiple displays By displaying the image, it is possible to provide a function of displaying a stereoscopic image. In electronic devices having an image receiving unit, the functions of taking still images, taking videos, The function of automatically or manually correcting the captured image, and the function of storing the captured image on a recording medium (external or camera) It can have functions such as storing the captured image on the camera (built into the camera), displaying the captured image on the display, etc. In addition, the electronic devices shown in Figs. 28(A) to 28(H) and Figs. 29(A) to 29(D) The functions that the device can have are not limited to these, and the device can have a variety of functions.

[0295] The electronic device described in this embodiment has a display unit for displaying some information. It is characterized by the above.

[0296] Next, application examples of the display device will be described.

[0297] FIG. 29(E) shows an example in which a display device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. The display device is a wall-mounted type that is integrated with the building and requires a certain amount of space to install. It can be installed without requiring a large space.

[0298] FIG. 29(F) shows another example in which a display device is provided inside a building as an integral part of the building. The display module 5026 is attached to the unit bath 5027. The bather can then view the display module 5026.

[0299] In this embodiment, a wall and a unit bath are used as examples of structures. The form is not limited to this, and the display device can be installed in various buildings.

[0300] Next, an example in which the display device is provided integrally with a moving object will be described.

[0301] FIG. 29(G) is a diagram showing an example in which the display device is provided in an automobile. The motor 5028 is attached to a body 5029 of the automobile and is used for controlling the operation of the body or the inside and outside of the vehicle. The information entered from the navigation function can be displayed on demand.

[0043]

[0302] FIG. 29(H) is a diagram showing an example in which a display device is integrated into a passenger airplane. FIG. 29(H) shows a display module 503 mounted on a ceiling 5030 above the seats of a passenger airplane. 5 is a diagram showing the shape of the display module 5031 when it is in use. The ceiling 5030 is attached to the ceiling 5030 via a hinge portion 5032. The expansion and contraction of the display module 503 allows passengers to view the display module 5031. 1 has the function of displaying information when operated by passengers.

[0303] In addition, in this embodiment, examples of the moving body include an automobile body and an aircraft body but are not limited thereto, and can be installed on various things such as motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, and the like.

[0304] In addition, in this specification and the like, in the figures or sentences described in a certain embodiment, it is possible to extract a part thereof to constitute an aspect of the invention. Therefore, when a figure or sentence describing a certain part is described, the content obtained by extracting a part of the figure or sentence thereof is also disclosed as an aspect of the invention and is assumed to be capable of constituting an aspect of the invention. Therefore, for example, in a drawing or sentence in which one or more active elements (such as transistors and diodes), wirings, passive elements (such as capacitive elements and resistive elements), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, devices, operation methods, manufacturing methods, etc. are described, it is assumed that it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitive elements), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors and capacitive elements) to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer and M < N ) elements to constitute an aspect of the invention. (N is an integer) elements to constitute an aspect of the invention.

[0305] In this specification, etc., in a drawing or text described in a certain embodiment, When at least one specific example is described, the generic concept of that specific example must be derived. This is easily understood by those skilled in the art. In the drawings or text, if at least one specific example is described, The concept is also disclosed as an aspect of the invention and may constitute an aspect of the invention. It is possible.

[0306] In this specification, at least the contents shown in the drawings (or even a part of the drawings) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it can be explained in text. Even if there is no such disclosure, the contents are disclosed as one aspect of the invention, and one aspect of the invention is Similarly, even if a part of the figure is taken out, it is possible to construct it as one aspect of the invention. and can constitute one embodiment of the invention.

[0307] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0308] (Embodiment 9) In this embodiment, a semiconductor device including the transistor described in the above embodiment will be described as an example. A radiological image detection apparatus capable of acquiring a radiological image for medical use will be described. Flat-type radiation image detection devices that can directly convert radiation images into digital data are generally flat-type. This is called a Flat Panel Detector (FPD).

[0309] As shown in FIG. 31(A), a radiation image detection device 3601 is used for capturing radiation. The object is placed on a stand 3603 on which the object can be placed, and is exposed to radiation 3607 emitted from a radiation source 3605. The light passes through the subject 3609 and reaches the radiation image detection device 3601. The device 3601 detects radiation 3607 that has passed through a subject 3609 using a radiation detection element. The radiation image detection device 3601 can detect radiation by using the image data. The rays 3607 include X-rays, gamma rays, and the like.

[0310] FIG. 31B shows a block diagram of the radiation image detection device 3601. 3601 is a sensor array 3613 in which pixels 3611 are arranged in a matrix, and a gate The LCD device includes a line driver circuit 3615 , a signal detector circuit 3617 , and an A / D converter circuit 3619 . The radiation image detection device 3601 includes a CPU (Central Processor) (not shown). ssing Unit), ROM (Read Only Memory), RAM (Ra In addition, the radiological imaging system is controlled by a The output device 3601 includes a correction circuit that corrects the data output from the A / D conversion circuit 3619, A storage device or the like for storing data output from the A / D conversion circuit 3619 may be provided.

[0311] The pixel 3611 includes a radiation detection element 3621, a capacitor element 3623, and a transistor 36 25. The radiation detection element 3621 detects radiation energy directly or indirectly. The transistor 3623 converts the charge into an electric charge and stores the electric charge in the capacitor 3623. By switching the capacitor 3625, the charge stored in the capacitor element 3623 is discharged to each pixel 3611. By reading out the radiation image as an electrical signal, a radiation image can be obtained on the output device 3631. Cut.

[0312] The radiation detection element 3621 has a pair of electrodes and a conversion layer provided between the pair of electrodes. One of the pair of electrodes is connected to a power supply 3633. The other of the pair of electrodes is connected to a capacitor. A first electrode of the element 3623 and one of the source and drain electrodes of the transistor 3625 A second electrode of the capacitor 3623 is connected to the common electrode which is at ground potential. The other of the source electrode and the drain electrode of the transistor 3625 is connected to a signal line DL. The gate of the transistor 3625 is connected to the gate line GL. The gate line driver circuit 3615 is connected to the gate line driver circuit 3615.

[0313] Next, a method for detecting radiation will be described. With a voltage applied to the first electrode of 21, radiation is incident on the radiation detection element 3621. The radiation detection element 3621 converts radiation energy into electric charges, and the amount of incident radiation is A charge corresponding to the amount of charge stored in the capacitor 3623 is then generated by the gate line driver circuit 3615. By inputting a signal to the scanning line GL and sequentially turning on the transistors 3625, The charge accumulated in the electrode 3623 is output to the signal detection circuit 3617 via the signal line DL as an analog signal. The signal detection circuit 3617 amplifies the analog signal and outputs it as an A / D The conversion circuit 3619 performs A / D conversion to generate a digital signal. is output to an output device 3631 such as a display device, and a radiation image is It will be displayed.

[0314] The radiation image detection device 3601 and the output device 3631 can be connected by a cable. In addition, a transmission / reception circuit is provided in each of the radiation image detection device 3601 and the output device 3631. The image detected by the radiation image detection device 3601 is wirelessly output to the output device 3631. This can be done.

[0315] Radiation image detection devices are classified into direct conversion type and indirect conversion type. The radiation detection element 3621 included in the image detection device detects radiation energy using a photoconductive material. The radiation detection element 3 included in the indirect conversion type radiation image detection device directly converts the 621 converts radiation energy into light using a fluorescent material or the like, and converts the light into a light source such as a photodiode. Converted into an electric charge using an electrical conversion element.

[0316] Next, the structure of each radiation detection element will be described with reference to FIG.

[0317] FIG. 32A is a cross-sectional view of a pixel of a direct conversion type radiation image detection device. Here, we will explain using X-rays as the radiation.

[0318] The transistor 3625 and the capacitor 3623 shown in the above embodiment are formed over a substrate 3641. , and a radiation detection element 3621 are provided. The radiation detection element 3621 is 43, a conversion layer 3645, and a conductive film 3647. The conductive film 3643 connected to one of the source electrode and the drain electrode of the radiation detection element 3621 It functions as an electrode and an electrode of the capacitor 3623.

[0319] The conductive film 3643 is a light-transmitting conductive film which functions as a pixel electrode described in the above embodiment. The same materials as those for the membrane can be used as appropriate.

[0320] The conversion layer 3645 is formed using a material that absorbs radiation and generates an electric charge. Materials that can absorb and generate a charge include amorphous selenium and lead iodide. , mercury iodide, gallium arsenide, CdTe, CdZn, etc.

[0321] The conductive film 3647 is a gate electrode, a source electrode, and a drain electrode of the transistor 3625. The same materials as those of the electrode and the conductive film 3643 can be used as appropriate.

[0322] When a voltage is applied to the conductive film 3647, radiation is incident on the radiation detection element 3621. When the electrons are incident on the conductive film 3645, charges (electrons and holes) are excited in the conversion layer 3645. Depending on the polarity of the voltage applied to 3647, the charge transfers to the conductive film 3643 and is transferred to the capacitor element 3623. Electricity is stored.

[0323] The radiation detection element 3621 used in the direct conversion type radiation image detection device is a conductive film 364 By applying a high voltage to 7, it is possible to increase the linearity of the charge generated in the conversion layer 3645. This reduces the transfer of charges to the radiation detection elements in the adjacent pixels. As a result, it is possible to increase the resolution of the radiation image detection device.

[0324] FIG. 32B is a cross-sectional view of a pixel of a radiation image detection device of an indirect conversion type. .

[0325] The transistor 3625 and the capacitor 3623 shown in the above embodiment are formed over a substrate 3641. , and a radiation detection element 3621 are provided. A phosphor layer 3657, typically a chiller, is provided.

[0326] The radiation detection element 3621 is made up of a conductive film 3651, a conversion layer 3653, and a conductive film 3655. The source electrode of the transistor 3625 may be a photodiode. The conductive film 3651 connected to one of the drain electrodes is an electrode of the radiation detection element 3621. The second electrode 3623 also serves as an electrode of the capacitor 3623 .

[0327] The conductive film 3651 is a light-transmitting conductive film which functions as a pixel electrode shown in the above embodiment. The same materials as those for the membrane can be used as appropriate.

[0328] The conversion layer 3653 is formed using a material that absorbs light and generates a charge. Materials that can generate electric charge include inorganic semiconductor materials such as silicon, quinacrine, The conversion layer 3653 may be a pn type or a pi type. It is preferable to form an n-type junction. When the phosphor layer 3657 is formed using the phosphor layer 3657, the visible light emitted by the phosphor layer 3657 can be detected with high sensitivity. This is preferable.

[0329] The conductive film 3655 can be formed using a material similar to that of the conductive film 3643 .

[0330] When radiation is incident on the phosphor layer 3657, the phosphor layer 3657 absorbs the radiation energy and emits light. It is made of a material that emits visible light. It can absorb radiation energy and emit visible light. Possible materials include cesium iodide, thallium doped cesium iodide, GOS( Gd2O2S:Tb), sodium iodide doped with thallium, etc. The layer 3657 is made of columnar crystals that have grown in the direction connecting the radiation incident surface and the light exit surface. This makes it possible to suppress the lateral diffusion of light generated in the phosphor layer 3657. As a result, it is possible to increase the resolution of the radiation image detection device.

[0331] In order to prevent electrical continuity between the conductive film 3651 and the conductive film 3655, An insulating film 3652 is provided over the layer 3653. By providing an insulating film 3654 on the conversion layer 3653, impurities from the outside are prevented from diffusing into the conversion layer 3653. This can be prevented.

[0332] The phosphor layer 3657 absorbs the incident radiation and emits visible light. When the visible light is incident on the conversion layer 3653 with a voltage (reverse bias) applied, the conversion Charges (electrons and holes) are excited in the conductive layer 3653. The charges are transferred to the conductive film 3651. and is stored in the capacitor 3623.

[0333] The radiation detection element 3621 used in the indirect conversion type radiation image detection device has a phosphor layer 36 In order to detect the visible light converted by 57, a conductive film 3655 of the radiation detection element 3621 is printed with It is possible to reduce the applied voltage.

[0334] In this case, the radiation image detection device 3601 installed on the stand 3603 will be used for explanation. However, it may be possible to use a cassette type radiation image detection device as appropriate. Cut.

[0335] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used. EXAMPLES

[0336] In this embodiment, a conductive layer (hereinafter, referred to as a first conductive layer) is formed in the same process as the gate electrode. ) and a conductive layer formed in the same process as the source electrode and the drain electrode (hereinafter, the second conductive layer ) and the layer between the first conductive layer and the second conductive layer by changing the composition of the interlayer film between The dielectric breakdown voltage of the interlayer was evaluated.

[0337] First, the TEG (Test Element Group) pattern for evaluation used in this embodiment The line will be described with reference to FIG.

[0338] FIG. 33(A) shows a top view of the evaluation TEG, and FIG. 33(B) shows the top view of FIG. 6 is a cross-sectional view corresponding to the cut surfaces taken along dashed dotted lines X6-Y6 and X7-Y7 shown in FIG.

[0339] The evaluation TEG of this embodiment includes a first conductive layer 504a formed on a substrate 502 and a first An interlayer film 506 formed on the first conductive layer 504a and a second conductive film formed on the interlayer film 506. A second conductive layer 510a, an insulating layer 512 formed on the second conductive layer 510a, and a second insulating layer 512 formed on the insulating layer 512. and an insulating layer 514 formed on the insulating layer 514.

[0340] The evaluation TEG also includes a first measurement pad 504b connected to the first conductive layer 504a, and a second measurement pad 510b connected to the second conductive layer 510a. The hole 504b is an opening where a part of the upper interlayer film 506 and the insulating layers 512 and 514 are removed. The second measurement pad 510b has a portion 520. The second measurement pad 510b has a portion 520 of the upper insulating layer 512, 514. The first measurement pad 504b has an opening 522 that is partially removed. By applying a voltage to 510b, a layer formed between the conductive layer 504a and the conductive layer 510a The breakdown voltage of the membrane 506 can be measured.

[0341] The size of the area where the first conductive layer 504a and the second conductive layer 510a intersect is The size of the sample was 10 μm × 10 μm. The measuring device was a Keithley Picore. The measurement conditions were as follows: applied voltage was changed from 0 V to + The voltage was increased in 10V steps up to 500V.

[0342] In this embodiment, samples 1 and 2 were prepared using different materials for the interlayer film 506. Made.

[0343] (Sample 1) The interlayer film 506 of the sample 1 is a two-layer film consisting of a silicon nitride film and a silicon oxynitride film. It has a layered structure.

[0344] (Sample 2) The interlayer film 506 of the sample 2 is a silicon nitride film, a silicon oxynitride film, and an oxide semiconductor film. The structure is a four-layer stack consisting of a conductor film and an oxide film.

[0345] That is, compared to Sample 1, Sample 2 has a structure in which an oxide semiconductor film and an oxide film are stacked. The film formation conditions for each film used in Sample 1 and Sample 2 are shown below.

[0346] (Silicon nitride film) The silicon nitride film was made by stacking three layers of silicon nitride films with different conditions. The deposition conditions for the silicon film were power (RF) = 2000 W, pressure = 100 Pa, SiH4 The second nitrogen gas was deposited at 200 / 2000 / 100 sccm and the film thickness was 50 nm. The deposition conditions for the silicon oxide film were power (RF) = 2000 W, pressure = 100 Pa, Si The gas pressure was H4 / N2 / NH3=200 / 2000 / 2000sccm, and the film thickness was 300nm. The deposition conditions for the third silicon nitride film were: power (RF) = 2000 W, pressure = 100 P a, SiH4 / N2=200 / 5000sccm, film thickness=50nm. The first to third silicon nitride films were all formed using a PE-CVD apparatus at a substrate temperature of 350°C. did.

[0347] (silicon oxynitride film) The deposition conditions for the silicon oxynitride film were: power (RF) = 100 W, pressure = 100 Pa , SiH4 / N2O=20 / 3000sccm, film thickness=50nm. The silicon film was formed using a PE-CVD apparatus with the substrate temperature set at 350°C.

[0348] (Oxide semiconductor film) For the oxide semiconductor film, a target having a composition of In:Ga:Zn=1:1:1 was used. The film was formed by sputtering. The film formation conditions were: power (AC) = 5 kW, pressure = 0 .6Pa, Ar / O2=100 / 100sccm(O2=50%), substrate temperature=170℃ , the film thickness was 35 nm.

[0349] (Oxide film) For the oxide film, a target with a composition of In:Ga:Zn=1:3:2 was used. The deposition conditions were: AC power = 5 kW, pressure = 0.6 P a, Ar / O2=270 / 30sccm (O2=10%), substrate temperature=170℃, film thickness= The thickness was set to 20 nm.

[0350] In addition, both Sample 1 and Sample 2 were annealed at 450° C. in a nitrogen atmosphere before the insulating layer 512 was formed. Heat treatment for 1 hour, followed by heat treatment at 450℃ for 1 hour in a mixed atmosphere of nitrogen and oxygen. went.

[0351] The breakdown voltages of the interlayer films 506 of Samples 1 and 2 are shown in FIG. The vertical axis indicates the voltage, and the vertical axis indicates the current. In FIG. the dashed line 551 indicates the measurement results for sample 1, and the dashed line 552 indicates the measurement results for sample 2.

[0352] In Sample 1 and Sample 2, for example, 1.0×10 -6 When a current of A or more flows, Assuming that the interlayer film 506 is broken down, in the sample 1, the interlayer film 50 is broken down at about 330V. On the other hand, in sample 2, the interlayer film 506 is broken down at about 420 V. do.

[0353] As shown in this embodiment, the interlayer film between the first conductive layer 504a and the second conductive layer 510a By changing the structure or the distance between the first conductive layer 504a and the second conductive layer 510a, It was confirmed that the breakdown voltage differed depending on the material. [Explanation of symbols]

[0354] 100 display device 102 Pixel section 104 Drive circuit section 104a Gate Driver 104b Source Driver 106 Protection circuit 107 Terminal section 108 Pixel circuit section 110 Wiring 111 Pixel circuit 112 Transistor 114 Transistor 116 Wiring 118 Wiring 120 Wiring 122 Wiring 124 Wiring 126 Wiring 128 Transistors 130 Transistor 131_1 Transistor 131_2 Transistor 131_3 Transistor 132 Transistor 133_1 Capacitive element 133_2 Capacitor element 134 Transistor 135 Light emitting element 206 Protection circuit 208 Wiring 212 Transistor 214 Transistor 216 Transistor 218 Transistor 220 Transistors 222 Transistors 224 Wiring 226 Wiring 302 Substrate 304a conductive layer 304b conductive layer 304c conductive layer 304d conductive layer 304e conductive layer 305 Insulation Layer 306 Insulating layer 307 Semiconductor Layer 308a Semiconductor layer 308b Semiconductor layer 308c Semiconductor layer 308d Semiconductor layer 309 Conductive Layer 310a conductive layer 310b conductive layer 310c conductive layer 310d conductive layer 310e conductive layer 310f conductive layer 310g conductive layer 311 Insulating layer 312 Insulating layer 313 Insulating Layer 314 Insulating layer 315 Conductive Layer 316a conductive layer 316b conductive layer 316c conductive layer 318 Orientation Film 320 Liquid crystal layer 322 Liquid crystal element 342 Substrate 344 Light blocking layer 346 colored layer 348 Insulating Layer 350 Conductive layer 352 Orientation Film 360 Electrostatic breakdown induction area 362 Guard Ring 362a Electrostatic breakdown induction area 370 Insulating layer 372a opening 372b opening 374a opening 374b opening 374c opening 374d opening 374e opening 380 areas 382 areas 390 Oxide stack 390a Oxide semiconductor layer 390b Oxide layer 392 n-type region 402 Substrate 404 Conductive layer 405 Insulation Layer 406 Insulating Layer 410 Conductive layer 412 Insulating layer 414 Insulating layer 416 Conductive Layer 474a Opening 474b Opening 502 Substrate 504a Conductive layer 504b Measuring Pad 506 Interlayer Film 510a Conductive layer 510b Measuring Pad 512 Insulating layer 514 Insulating layer 520 Opening 522 Opening 551 Solid Line 552 dashed line 3601 Radiation image detection equipment 3603 units 3605 Radiation source 3607 Radiation 3609 Subject 3611 pixels 3613 Sensor Array 3615 Gate line driver circuit 3617 Signal detection circuit 3619 A / D conversion circuit 3621 Radiation detection element 3623 Capacitor 3625 Transistor 3631 Output Device 3633 Power Supply 3641 Substrate 3643 Conductive film 3645 Conversion Layer 3647 Conductive film 3651 Conductive film 3652 Insulating film 3653 Conversion Layer 3654 Insulating film 3655 Conductive film 3657 Phosphor layer 4500 Touch Sensor 4510 Conductive layer 4510a conductive layer 4510b Conductive layer 4510c conductive layer 4520 Conductive layer 4540 capacity 4710 Electrode 4810 Insulating layer 4820 Insulating layer 4910 Board 4920 Board 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Module 5027 Unit Bath 5028 Display Module 5029 Body 5030 Ceiling 5031 Display module 5032 Hinge part 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. a pixel portion provided with a first transistor, a capacitor, and a pixel electrode; a scanning line driver circuit provided with a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the first transistor includes a first conductive layer, a first insulating layer on the first conductive layer, a first oxide semiconductor layer on the first insulating layer, a second conductive layer on the first oxide semiconductor layer, and a third conductive layer on the first oxide semiconductor layer; the first conductive layer has a region overlapping with the first oxide semiconductor layer, the first conductive layer has a region that functions as a gate electrode; the second conductive layer is electrically connected to the first oxide semiconductor layer; the third conductive layer is electrically connected to the first oxide semiconductor layer; the second conductive layer has a region functioning as one of a source electrode and a drain electrode, the third conductive layer has a region functioning as the other of the source electrode and the drain electrode, a second insulating layer on the first oxide semiconductor layer, the second conductive layer, and the third conductive layer; the second insulating layer has a region in contact with the first oxide semiconductor layer, the second insulating layer has a region in contact with the second conductive layer, the second insulating layer has a region in contact with the third conductive layer, a third insulating layer on the second insulating layer; the third insulating layer has a region in contact with the second insulating layer, the pixel electrode is provided on the third insulating layer, the pixel electrode has a region in contact with the third insulating layer, the pixel electrode has a region in contact with the second insulating layer, the pixel electrode is electrically connected to one of the second conductive layer and the third conductive layer; the capacitive element includes a second oxide semiconductor layer, the third insulating layer on the second oxide semiconductor layer, and the pixel electrode on the third insulating layer; the second oxide semiconductor layer has a region that functions as one electrode of the capacitor, the pixel electrode has a region that functions as the other electrode of the capacitive element, the first oxide semiconductor layer is provided on and in contact with the first insulating layer; the second oxide semiconductor layer is provided on and in contact with the first insulating layer; the second insulating layer has a region in contact with an upper surface of the second oxide semiconductor layer, an area of ​​the second oxide semiconductor layer is larger than an area of ​​the first oxide semiconductor layer in a plan view; The scanning line driving circuit includes: a first conductive portion having a first region, a second region, and a third region arranged branching from a trunk region in a plan view; a second conductive portion having a fourth region, a fifth region, a sixth region, and a seventh region arranged branching from a trunk region in a plan view; having In a plan view, the first region, the second region, and the third region are each arranged to extend along a first direction, In a plan view, the fourth region, the fifth region, the sixth region, and the seventh region are arranged to extend along a second direction opposite to the first direction, the first region is disposed between the fourth region and the fifth region and spaced apart from the fourth region and the fifth region in a plan view; the second region is disposed between the fifth region and the sixth region and spaced apart from the fifth region and the sixth region in a plan view; the third region is disposed between the sixth region and the seventh region and spaced apart from the sixth region and the seventh region in a plan view; one of a source and a drain of the second transistor is disposed in the fourth region; the other of the source and the drain of the second transistor is disposed in the first region; a channel formation region of the second transistor is provided in a third oxide semiconductor layer, one of a source and a drain of the third transistor is disposed in the first region; the other of the source and the drain of the third transistor is disposed in the fifth region; a channel formation region of the third transistor is provided in the third oxide semiconductor layer, one of a source and a drain of the fourth transistor is disposed in the fifth region; the other of the source and the drain of the fourth transistor is disposed in the second region; a channel formation region of the fourth transistor is provided in the third oxide semiconductor layer, one of a source and a drain of the fifth transistor is disposed in the second region; the other of the source and the drain of the fifth transistor is disposed in the sixth region; a channel formation region of the fifth transistor is provided in the third oxide semiconductor layer, one of a source and a drain of the sixth transistor is disposed in the sixth region; the other of the source and the drain of the sixth transistor is disposed in the third region; a channel formation region of the sixth transistor is provided in the third oxide semiconductor layer, one of a source and a drain of the seventh transistor is disposed in the third region; the other of the source and the drain of the seventh transistor is disposed in the seventh region; a channel formation region of the seventh transistor is provided in the third oxide semiconductor layer, one of a source and a drain of the eighth transistor is disposed in the fourth region; the other of the source and the drain of the eighth transistor is disposed in the first region; a channel formation region of the eighth transistor is provided in a fourth oxide semiconductor layer, one of a source and a drain of the ninth transistor is disposed in the first region; the other of the source and the drain of the ninth transistor is disposed in the fifth region; a channel formation region of the ninth transistor is provided in the fourth oxide semiconductor layer, one of a source and a drain of the tenth transistor is disposed in the fifth region; the other of the source and the drain of the tenth transistor is disposed in the second region; a channel formation region of the tenth transistor is provided in the fourth oxide semiconductor layer, one of a source and a drain of the eleventh transistor is disposed in the second region; the other of the source and the drain of the eleventh transistor is disposed in the sixth region; a channel formation region of the eleventh transistor is provided in the fourth oxide semiconductor layer, one of a source and a drain of the twelfth transistor is disposed in the sixth region; the other of the source and the drain of the twelfth transistor is disposed in the third region; a channel formation region of the twelfth transistor is provided in the fourth oxide semiconductor layer, one of a source and a drain of the thirteenth transistor is disposed in the third region; the other of the source and the drain of the thirteenth transistor is disposed in the seventh region; a channel formation region of the thirteenth transistor is provided in the fourth oxide semiconductor layer, the third oxide semiconductor layer is arranged at an interval from the fourth oxide semiconductor layer in a channel width direction of the second to thirteenth transistors.

2. In claim 1, A fourth conductive layer is provided; A display device, wherein gates of the second transistor to the thirteenth transistor are each disposed on the fourth conductive layer.

3. 3. An electronic device comprising the display device according to claim 1.

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