Method for manufacturing semiconductor device

Abstract

To provide a semiconductor device with less variation in transistor characteristics.SOLUTION: A transistor 200 includes: an insulator 216 on an insulator 214; a conductor 205 arranged so as to be embedded in the insulator 214 or the insulator 216; an insulator 222 on the insulator 216 and the conductor 205; an insulator 224 on the insulator 222; an oxide 230a on the insulator 224; an oxide 230b on the oxide 230a; oxides 241 (an oxide 241a and an oxide 241b) and an oxide 230c on the oxide 230b; an oxide 230d on the oxide 230c; a conductor 240a on the oxide 241a; an insulator 271a on the conductor 240a: a conductor 240b on the oxide 241b; an insulator 271b on the conductor 240b; an insulator 250 on the oxide 230d; and a conductor 260 located on the insulator 250 and overlapping with parts of the oxide 230c and the oxide 230d.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention includes forming a first insulator, forming an island-shaped stack by sequentially stacking a first oxide, a second oxide, and a first conductor on the first insulator, forming a second insulator on the first insulator and the stack, forming an opening in the second insulator to expose the stack, removing the area exposed in the opening of the first conductor to expose the top surface of the second oxide, and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process to remove the side surface of the first oxide exposed in the opening and the A first oxide film is formed in contact with the upper and side surfaces of the second oxide and the second oxide, oxygen is added through the first oxide film to the vicinity of the interface between the second oxide and the first oxide film, and then a heat treatment is performed to form a first insulating film and a first conductive film on the first oxide film. After that, a chemical polishing process is performed to remove a portion of the first conductive film, the first insulating film, the first oxide film, and the second insulator to expose the second insulator, and a fourth conductor, a third insulator, and a third oxide are formed in the opening provided in the second insulator.

[0011] One embodiment of the present invention includes forming a first insulator, forming an island-shaped stack by sequentially stacking a first oxide, a second oxide, and a first conductor on the first insulator, forming a second insulator on the first insulator and the stack, forming an opening in the second insulator to expose the stack, removing the area exposed in the opening of the first conductor to expose the top surface of the second oxide, and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process to connect the side of the first oxide exposed in the opening and the top and side surfaces of the second oxide. Then, a first oxide film is formed, a process of adding oxygen through the first oxide film to the vicinity of the interface between the second oxide film and the first oxide film is performed, a second oxide film is formed on the first oxide film, a heat treatment is performed, a first insulating film and a first conductive film are formed on the second oxide film, and then a chemical polishing process is performed to remove a portion of the first conductive film, the second oxide film, the first insulating film, the first oxide film, and the second insulator to expose the second insulator, and a fourth conductor, a third insulator, a third oxide, and a fourth oxide are formed in an opening provided in the second insulator.

[0012] In the above, the oxygen addition treatment is preferably carried out by using an ion implantation method.

[0013] In the above, in claim 1 or claim 2, in the ion implantation method, it is preferable that oxygen ions are incident in the short side direction of the second oxide at an angle θ (45°<θ<135°) with respect to a tangent to the upper surface of the second oxide.

[0014] In the above, the heat treatment is preferably carried out at a temperature of 350° C. or higher and 400° C. or lower.

[0015] In the above, the heat treatment is preferably carried out in an atmosphere containing an oxidizing gas at 1% or more, or 10% or more.

[0016] In the above, the first oxide and the third oxide preferably suppress oxygen diffusion more than the second oxide. Effect of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0019] [Figure 1] Fig. 1A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 1B and Fig. 1C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 2] Fig. 2A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 2B and Fig. 2C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 3] Fig. 3A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 3B and Fig. 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] Fig. 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 4B and Fig. 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 5]Fig. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 5B and Fig. 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] Fig. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 6B and Fig. 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] Fig. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 7B and Fig. 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B and 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 9B and FIG 9C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 10B and FIG 10C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] Fig. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 11B and Fig. 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A, 12B, and 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] Fig. 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 13B and Fig. 13C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14]Fig. 14A is a diagram explaining the classification of IGZO crystal structures. Fig. 14B is a diagram explaining the XRD spectrum of quartz glass. Fig. 14C is a diagram explaining the XRD spectrum of crystalline IGZO. Fig. 14D is a diagram explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. [Figure 15] Fig. 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 15B and Fig. 15C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A and 16B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 17] Fig. 17A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 17B and Fig. 17C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 18B and FIG 18C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] Fig. 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 19B and Fig. 19C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 20B and FIG 20C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] Fig. 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 21B and Fig. 21C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] Fig. 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 22B and Fig. 22C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 23] Fig. 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 23B and Fig. 23C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 24B and FIG 24C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 25] 25A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 25B and FIG 25C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A, 26B, and 26C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 27B and FIG 27C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A and 28B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 30] FIG. 30 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 31] FIG. 31 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 32] FIG. 32 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 33] FIG. 33 is a top view illustrating an apparatus for manufacturing a semiconductor device of one embodiment of the present invention. [Diagram 34] 34A and 34B are a block diagram and a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Diagram 35] 35A to 35H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Diagram 36] FIG. 36 is a diagram showing various storage devices by hierarchy. [Figure 37] 37A and 37B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 38] 38A and 38B are diagrams illustrating an example of an electronic component. [Figure 39] 39A to 39E are schematic diagrams of a memory device according to one embodiment of the present invention. [Diagram 40] 40A to 40H are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, the size, thickness of a layer, or an area may be exaggerated for clarity. Therefore, the scale is not necessarily limited. Note that the drawings are schematic illustrations of one embodiment of the present invention, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0022] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0024] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0026] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0031] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that impurities in a semiconductor refer to, for example, anything other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O :oxygen vacancy) may be formed.

[0034] In this specification and the like, silicon oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and silicon nitride oxide refers to a material having a composition that contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0038] In this specification and the like, normally-off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0040] <Configuration Example 1 of Semiconductor Device> A configuration of a semiconductor device having a transistor 200 will be described with reference to FIG. 1. FIGS. 1A to 1C are a top view and a cross-sectional view of a semiconductor device having a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the top view of FIG. 1A for clarity.

[0041] A semiconductor device of one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282. The insulator 212, the insulator 214, the insulator 280, the insulator 282, and the insulator 283 function as interlayer films.

[0042] The transistor 200 also has a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the transistor 200 and functions as a plug. An insulator 276 (insulator 276a and insulator 276b) is provided in contact with the side surface of the conductor 246 that functions as a plug. A conductor 248 (conductor 248a and conductor 248b) that is electrically connected to the conductor 246 and functions as a wiring is provided on the insulator 283 and the conductor 246. An insulator 286 is provided on the conductor 248 and the insulator 283.

[0043] Specifically, insulator 276a is provided in contact with the inner walls of the openings of insulators 280, 282, and 283, a first conductor of conductor 246a is provided in contact with the side surface of insulator 276a, and a second conductor of conductor 246a is provided further inward. Also, insulator 276b is provided in contact with the inner walls of the openings of insulators 280, 282, and 283, a first conductor of conductor 246b is provided in contact with the side surface of insulator 276b, and a second conductor of conductor 246b is provided further inward.

[0044] 1B, the height of the top surface of the conductor 246 and the height of the top surface of the insulator 283 in the region overlapping with the conductor 248 can be made approximately the same. Note that, in the transistor 200, a configuration in which the first conductor of the conductor 246 and the second conductor of the conductor 246 are stacked is shown, but the present invention is not limited to this. For example, the conductor 246 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be given to indicate the order of formation to distinguish them from one another.

[0045] [Transistor 200] As shown in FIGS. 1A to 1C, the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. 241 (oxide 241a and oxide 241b) and oxide 230c, conductor 240a on oxide 241a, insulator 271a on conductor 240a, conductor 240b on oxide 241b, insulator 271b on conductor 240b, insulator 250 on oxide 230c, and conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with a part of oxide 230c. In addition, oxide 230c contacts the side of oxide 241a, the side of oxide 241b, the side of conductor 240a, the side of conductor 240b, the side of insulator 271a, and the side of insulator 271b.

[0046] 1B and 1C, the upper surface of the conductor 260 is disposed so as to roughly coincide with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Also, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280.

[0047] In the following, the insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0048] An opening is provided in the insulator 280, reaching the oxide 230b. The oxide 230c, the insulator 250, and the conductor 260 are disposed in the opening. In addition, in the channel length direction of the transistor 200, the conductor 260, the insulator 250, and the oxide 230c are provided between the conductor 240a and the oxide 241a and between the conductor 240b and the oxide 241b. The insulator 250 has a region in contact with a side surface of the conductor 260 and a region in contact with a bottom surface of the conductor 260. In addition, in the region overlapping with the oxide 230b, the oxide 230c has a region in contact with the oxide 230b, a region overlapping with a side surface of the conductor 260 via the insulator 250, and a region overlapping with the bottom surface of the conductor 260 via the insulator 250.

[0049] Oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b and at least partially in contact with oxide 230b.

[0050] Note that in the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0051] A transistor using an oxide semiconductor for a channel formation region has an extremely small leakage current in a non-conducting state, and therefore a semiconductor device with low power consumption can be provided. On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to change due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode).

[0052] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities and oxygen vacancies are reduced as the oxide semiconductor for use in a channel formation region of a transistor. Note that in this specification and the like, a high-purity intrinsic oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a substantially high-purity intrinsic oxide semiconductor.

[0053] However, in a transistor including an oxide semiconductor, oxygen from the oxide semiconductor is gradually absorbed by a conductor that constitutes the transistor or a conductor that is used for a plug or a wiring that connects to the transistor, and oxygen vacancies may occur as a type of change over time.

[0054] Therefore, after oxide 230b is made substantially intrinsic with high purity, it is preferable to cover the region of oxide 230b in which the channel is to be formed with oxide 230a, which suppresses oxygen diffusion more than oxide 230b, and oxide 230c.

[0055] Specifically, as shown in the figure, by disposing the oxide 230a under the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b. Also, it is possible to suppress the diffusion of oxygen and impurities from the structure formed below the oxide 230a to the oxide 230b.

[0056] Moreover, by disposing the oxide 230c on the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b, and it is also possible to suppress the diffusion of impurities from a structure formed above the oxide 230c into the oxide 230b.

[0057] Note that the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having such a wide band gap, the off-state current of a transistor can be reduced.

[0058] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0059] Here, the oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. Specifically, the metal oxide used for the oxide 230b preferably has a larger atomic ratio of In to element M than the metal oxide used for the oxide 230a or oxide 230c.

[0060] That is, in the metal oxides used for the oxides 230a and 230c, the atomic ratio of element M to other metal elements that are main components is preferably greater than the atomic ratio of element M to metal elements that are main components in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a and 230c.

[0061] By the oxide 230a and the oxide 230c having a common element other than oxygen (as a main component), the defect level density at each interface between the oxide 230a, the oxide 230b, and the oxide 230c can be reduced. In this case, the main path of carriers is the oxide 230b or its vicinity, for example, the interface between the oxide 230b and the oxide 230c. Since the defect level density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0062] For example, as the oxide 230b, specifically, a metal oxide, indium oxide, or the like having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto may be used.

[0063] Moreover, the oxide 230b is preferably crystalline. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) for the oxide 230b.

[0064] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0065] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. In CAAC-OS, it is difficult to confirm clear grain boundaries even near the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of dense arrangement of oxygen atoms in the ab-plane direction and the change in the bond distance between atoms due to the substitution of metal elements.

[0066] A crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor or a decrease in field-effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0067] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be expressed as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be expressed as an (In, M) layer.

[0068] As described above, the CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (oxygen vacancies Vo, etc.). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0069] On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is said that the decrease in electron mobility caused by grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0070] Furthermore, the region of the oxide 230b where the channel is formed may have a smaller cross-sectional area in the W-width direction than the region of the oxide 230b that functions as the source region or drain region. That is, in the processing step of providing an opening in the insulator 280 or in a cleaning step after the processing step, a part of the surface of the oxide 230b exposed at the bottom of the opening may be removed, and a groove (hereinafter also referred to as a countersink) may be formed in the oxide 230b.

[0071] In addition, it is preferable to fill the grooves of the oxide 230b with the oxide 230c. At this time, the oxide 230c is arranged so as to cover the inner walls (side walls and bottom surface) of the grooves. The thickness of the oxide 230c may be approximately the same as the depth of the grooves.

[0072] With the above structure, even if a damaged region is formed on the surface of the oxide 230b at the bottom of the opening when forming the opening for embedding the conductor 260 or the like, the damaged region can be compensated for, thereby suppressing defects in the electrical characteristics of the transistor 200 caused by the damaged region.

[0073] In FIG. 1B, the side of the opening in which the conductor 260 and the like are embedded is approximately perpendicular to the surface on which the oxide 230b is formed, including the groove of the oxide 230b, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped with a gentle curve. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 230b is formed.

[0074] 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0075] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 240, or smaller than half the length of the region of the oxide 230b that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the curved surface in this shape, the coverage of the groove portion by the insulator 250 and the conductor 260 formed in a later process can be improved. In addition, the length of the region that does not have the curved surface can be prevented from decreasing, and the on-current and mobility of the transistor 200 can be suppressed from decreasing. Therefore, a semiconductor device having good electrical characteristics can be provided.

[0076] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator. The conductor 240a functions as one of a source electrode or a drain electrode, and the conductor 240b functions as the other of the source electrode or the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0077] Note that the conductor 260 and the insulator 250 may be shared between adjacent transistors 200. That is, the conductor 260 of one transistor 200 has a region provided contiguous with the conductor 260 of another transistor 200 adjacent to the transistor 200. The insulator 250 of one transistor 200 has a region provided contiguous with the insulator 250 of another transistor 200 adjacent to the transistor 200.

[0078] It is preferable that insulators 212, 214, 271, 282, 283, and 286 function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from the substrate side or from above transistor 200 into transistor 200.

[0079] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property means a function of suppressing the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

[0080] Therefore, it is preferable that the insulators 212, 214, 271, 282, 283, and 286 are made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. (the impurities are less likely to permeate through them). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through them).

[0081] For example, it is preferable to use silicon nitride or the like as the insulators 212, 283, and 286, and aluminum oxide or the like as the insulators 214, 271, and 282. This can suppress impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulators 224 and the like to the substrate side through the insulators 212 and 214. It is also possible to suppress the diffusion of impurities such as water and hydrogen from the insulators 280, the conductor 248, and the like to the oxide 230. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0082] It may also be preferable to reduce the resistivity of the insulators 212, 283, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 283, and 286 to approximately 1×10 13 By setting the resistivity at Ωcm, the insulator 212, the insulator 283, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 240, the conductor 260, or the conductor 248 in a process using plasma or the like in a semiconductor device manufacturing process. 10 Ωcm or more 1×10 15 Ωcm or less.

[0083] The insulator 216 and the insulator 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as the insulator 216 and the insulator 280 as appropriate.

[0084] Note that the insulators 212, 214, and 216 are preferably formed by a sputtering method. The insulators 212, 214, and 216 formed by a sputtering method preferably have a low hydrogen concentration. The insulators 212, 214, and 216 are preferably formed in succession without exposure to the air environment. By forming the insulators 212, 214, and 216 without exposure to the air environment, impurities or moisture from the air environment can be prevented from adhering to the insulators 212, 214, and 216, and the interface and vicinity of the interface between the insulators 212 and 214, and the interface and vicinity of the interface between the insulators 214 and 216 can be kept clean, which is preferable.

[0085] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0086] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0087] As shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of the region of the oxide 230a and the oxide 230b that does not overlap with the conductor 240a and the conductor 240b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to the region outside the end of the oxide 230a and the oxide 230b that intersects with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator on the outside of the side surface of the oxide 230a and the oxide 230b in the channel width direction. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. In this specification, a structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0088] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0089] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0090] Note that, in the transistor 200, the conductor 205 has a structure in which the conductor 205a and the conductor 205b are stacked, but the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by giving ordinal numbers to the order of formation.

[0091] Here, the conductor 205a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0092] By using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive material. For example, the conductor 205a may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide, and titanium or titanium nitride.

[0093] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material.

[0094] Insulator 222 and insulator 224 function as gate insulators.

[0095] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0096] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the insulator 224 and the oxygen contained in the oxide 230.

[0097] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0098] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate voltage during transistor operation while maintaining the physical film thickness.

[0099] The insulator 224 preferably has a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as the insulator 216 and the insulator 280 as appropriate.

[0100] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0101] An oxide 241 (oxide 241a and oxide 241b) may be provided on oxide 230b.

[0102] The oxide 241 (oxide 241a and oxide 241b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 241 having a function of suppressing oxygen permeation between the conductor 240 functioning as a source electrode or drain electrode and the oxide 230b, the electrical resistance between the conductor 240 and the oxide 230b is reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved. Note that if the electrical resistance between the conductor 240 and the oxide 230b can be sufficiently reduced, the oxide 241 may not be provided.

[0103] A metal oxide having element M may be used as the oxide 241. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 241 preferably has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 241. A metal oxide such as In-M-Zn oxide may be used as the oxide 241. Specifically, in the metal oxide used for the oxide 241, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. The film thickness of the oxide 241 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. The oxide 241 is preferably crystalline. When the oxide 241 is crystalline, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxide 241 has a crystal structure such as a hexagonal crystal structure, the release of oxygen in the oxide 230 may be suppressed.

[0104] It is preferable that the oxide film to be oxide 230a, the oxide film to be oxide 230b, and the oxide film to be oxide 241 are successively formed without exposure to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film to be oxide 230a, the oxide film to be oxide 230b, and the oxide film to be oxide 241, and it is possible to keep the interface and the vicinity of the interface between the oxide film to be oxide 230a and the oxide film to be oxide 230b, and the interface and the vicinity of the interface between the oxide film to be oxide 230b and the oxide film to be oxide 241, clean. An apparatus capable of successive film formation will be described later.

[0105] The conductor 240a is provided over the oxide 241a, and the conductor 240b is provided over the oxide 241b. The conductor 240a and the conductor 240b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0106] As the conductor 240 (conductor 240a and conductor 240b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0107] If the oxide 241 is not provided, contact between the conductor 240 and the oxide 230b or the oxide 230c may cause oxygen in the oxide 230b or the oxide 230c to diffuse into the conductor 240, resulting in oxidation of the conductor 240. The oxidation of the conductor 240 is likely to reduce the conductivity of the conductor 240. The diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 240 can be rephrased as the conductor 240 absorbing the oxygen in the oxide 230b or the oxide 230c.

[0108] In addition, oxygen in the oxide 230b or the oxide 230c may diffuse into the conductor 240a and the conductor 240b, forming layers between the conductor 240a and the oxide 230b, between the conductor 240b and the oxide 230b, or between the conductor 240a and the oxide 230c, and between the conductor 240b and the oxide 230c. Since the layer contains more oxygen than the conductor 240a or the conductor 240b, the layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 240a or the conductor 240b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and can be regarded as a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0109] Note that hydrogen contained in the oxide 230b, the oxide 230c, etc. may diffuse into the conductor 240a or the conductor 240b. In particular, by using a nitride containing tantalum for the conductor 240a and the conductor 240b, hydrogen contained in the oxide 230b, the oxide 230c, etc. may easily diffuse into the conductor 240a or the conductor 240b, and the diffused hydrogen may combine with nitrogen contained in the conductor 240a or the conductor 240b. In other words, hydrogen contained in the oxide 230b, the oxide 230c, etc. may be absorbed by the conductor 240a or the conductor 240b.

[0110] Furthermore, there may be a curved surface between the side surface of the conductor 240 and the top surface of the conductor 240. That is, the end of the side surface and the end of the top surface may be curved. The curved surface has a radius of curvature of, for example, 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductor 240. The absence of corners at the end improves the coverage of the film in the subsequent film formation process.

[0111] The insulator 271 is provided in contact with the upper surface of the conductor 240, and preferably functions as a barrier insulating film against at least oxygen. Therefore, the insulator 271 also preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. As the insulator 271, for example, an insulator containing silicon nitride may be used.

[0112] An insulator may be provided to cover the side surfaces of the oxide 230a, the oxide 230b, the oxide 241, the conductor 240, and the insulator 271. The insulator preferably functions as a barrier insulating film against oxygen. In other words, the insulator preferably has a function of suppressing the diffusion of oxygen. For example, the insulator preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed.

[0113] In particular, it is preferable to form the insulator 271 by forming an aluminum oxide or hafnium oxide film in an atmosphere containing oxygen by a sputtering method. Since the sputtering method does not include a hydrogen atmosphere, it is possible to suppress the inclusion of hydrogen as an impurity.

[0114] By providing the insulator 271, the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240 can be separated from the insulator 280. Therefore, it is possible to suppress the direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240. Therefore, it is possible to prevent the carrier density of the source region and the drain region of the oxide 230 from being reduced due to the supply of excess oxygen to the source region and the drain region. In addition, it is possible to suppress the conductor 240 from being excessively oxidized, which increases the resistivity and reduces the on-current.

[0115] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0116] The insulator 250 is preferably formed using an insulator that releases oxygen when heated, similar to the insulator 224. By providing the insulator that releases oxygen when heated as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, and oxygen vacancies in the channel formation region of the oxide 230b can be reduced. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. Furthermore, similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0117] In addition, although the insulator 250 is illustrated as a single layer in FIG. 1B and FIG. 1C, it may be a laminated structure of two or more layers. When the insulator 250 is a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has a function of suppressing the diffusion of oxygen. By adopting such a configuration, it is possible to suppress the diffusion of oxygen contained in the lower layer of the insulator 250 to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be provided using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be provided using a material similar to that of the insulator 222.

[0118] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate voltage applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0119] Specifically, the upper layer of the insulator 250 may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0120] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0121] It is preferable that the metal oxide has a function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 260a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0122] By including the metal oxide, the on-current of the transistor 200 can be improved without weakening the influence of the electric field from the conductor 260. Furthermore, by maintaining a distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 can be suppressed. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily and appropriately adjusted.

[0123] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B and FIG. 1C, the upper surface of the conductor 260 is substantially aligned with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Note that, although the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIG. 1B and FIG. 1C, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers.

[0124] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0125] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0126] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity for the conductor 260b. For example, the conductor 260b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0127] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 240a and the conductor 240b without alignment.

[0128] As shown in FIG. 1C, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably equal to or lower than the height of the bottom surface of the oxide 230b when the bottom surface of the insulator 222 is used as a reference. The conductor 260, which functions as a gate electrode, is configured to cover the side and upper surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. When the bottom surface of the insulator 222 is used as a reference, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0129] The insulator 280 is provided on the insulator 224, the oxide 230, the conductor 240, and the insulator 271. In addition, the upper surface of the insulator 280 may be planarized.

[0130] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0131] It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. The insulator 280 may have a structure in which the above-mentioned materials are stacked, for example, a stacked structure of silicon oxide formed by sputtering and silicon oxynitride formed by chemical vapor deposition (CVD) on the silicon oxide formed by sputtering. Silicon nitride may also be stacked on top of the silicon oxide.

[0132] The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen transmission. The insulator 282 and the insulator 283 may be, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high blocking property against oxygen, and the insulator 283 may be made of silicon nitride, which has a high blocking property against hydrogen.

[0133] The conductor 246a and the conductor 246b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 246a and the conductor 246b may have a layered structure.

[0134] In addition, when the conductor 246 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 284, the insulator 283, the insulator 282, the insulator 280, and the insulator 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. In addition, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 284 from being mixed into the oxide 230 through the conductor 246a and the conductor 246b.

[0135] As the insulator 276a and the insulator 276b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 276a and the insulator 276b are provided in contact with the insulator 271a, impurities such as water and hydrogen contained in the insulator 280 can be prevented from being mixed into the oxide 230 through the conductor 246a and the conductor 246b. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, it can prevent the oxygen contained in the insulator 280 from being absorbed by the conductor 246a and the conductor 246b.

[0136] Conductor 248 (conductor 248a and conductor 248b) may be disposed to function as wiring in contact with the upper surface of conductor 246a and the upper surface of conductor 246b. Conductor 248 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0137] The insulator 286 is provided on the conductor 248 and on the insulator 283. As a result, the upper surface and the side surface of the conductor 248 are in contact with the insulator 286, and the lower surface of the conductor 248 is in contact with the insulator 283. In other words, the conductor 248 can be configured to be surrounded by the insulators 283 and 286. This configuration can suppress the permeation of oxygen from the outside and prevent the conductor 248 from oxidizing. This is also preferable because it can prevent impurities such as water and hydrogen from conductor 248 from diffusing to the outside.

[0138] <<Metal oxides>> It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 230. Hereinafter, metal oxides that can be applied to the oxide 230 according to the present invention will be described.

[0139] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0140] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, there are cases where the element M may be a combination of multiple elements mentioned above.

[0141] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0142] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0143] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0144] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, may have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it may be structurally more stable when made into small crystals (for example, the above-mentioned nanocrystals) rather than large crystals (here, crystals of several mm or several cm).

[0145] The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0146] Oxide semiconductors (metal oxides) have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0147] As an alternative to the oxide semiconductor, a cloud-aligned composite (CAC)-OS may be used.

[0148] CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the material as a whole has a function as a semiconductor. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) that become carriers, and the insulating function is a function of not flowing electrons that become carriers. By making the conductive function and the insulating function act complementarily, it is possible to impart a switching function (on / off function) to CAC-OS or CAC-metal oxide. By separating the respective functions in CAC-OS or CAC-metal oxide, it is possible to maximize both functions.

[0149] Moreover, the CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected in a cloud shape with a blurred periphery.

[0150] In addition, in the CAC-OS or CAC-metal oxide, the conductive regions and the insulating regions may each be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0151] In addition, the CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, the CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this configuration, when carriers are caused to flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily on the component having the wide gap, and carriers also flow in the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force in the on state of the transistor, that is, a large on-current and a high field effect mobility can be obtained.

[0152] That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[0153] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of crystal structures in oxide semiconductors will be described with reference to Fig. 14A. Fig. 14A is a diagram for explaining the classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0154] As shown in FIG. 14A, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes c-axis aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). Crystalline excludes single crystal, poly crystal, and completely amorphous. Crystal includes single crystal and poly crystal.

[0155] The structure in the bold frame shown in FIG. 14A is an intermediate state between Amorphous and Crystal, and belongs to a new boundary region (New crystalline phase). This structure is in the boundary region between Amorphous and Crystal. In other words, this structure can be said to be a structure that is completely different from Amorphous, which is energetically unstable, or Crystal.

[0156] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) image. Here, XRD spectra of quartz glass and IGZO (also called crystalline IGZO) having a crystal structure classified as Crystalline are shown in Fig. 14B and Fig. 14C. Fig. 14B shows the XRD spectrum of quartz glass, and Fig. 14C shows the XRD spectrum of crystalline IGZO. The composition of the crystalline IGZO shown in Fig. 14C is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the crystalline IGZO shown in Fig. 14C is 500 nm.

[0157] As shown by the arrows in Figure 14B, the shape of the peak in the XRD spectrum of silica glass is almost symmetrical. On the other hand, as shown by the arrows in Figure 14C, the shape of the peak in the XRD spectrum of crystalline IGZO is asymmetrical. The asymmetric shape of the peak in the XRD spectrum clearly indicates the presence of crystals. In other words, if the shape of the peak in the XRD spectrum is not symmetrical, it cannot be said to be amorphous. Note that Figure 14C clearly shows the crystal phase (IGZO crystal phase) at or near 2θ=31°. It is presumed that the reason why the shape of the peak in the XRD spectrum is asymmetrical is due to the crystal phase (microcrystals).

[0158] Specifically, the XRD spectrum of crystalline IGZO shown in FIG. 14C has a peak at or near 2θ=34°. Microcrystals have a peak at or near 2θ=31°. When an oxide semiconductor film is evaluated using an X-ray diffraction image, the spectrum width on the lower angle side is wider than the peak at or near 2θ=34°, as shown in FIG. 14C. This suggests that the oxide semiconductor film contains microcrystals having a peak at or near 2θ=31°.

[0159] The crystal structure of the film can be evaluated from the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Figure 14D shows the diffraction pattern of an IGZO film formed at room temperature on the substrate. The IGZO film shown in Figure 14D was formed by sputtering using an oxide target with an In:Ga:Zn=1:1:1 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction was performed with a probe diameter of 1 nm.

[0160] As shown in Figure 14C, a spot-like pattern, not a halo, is observed in the diffraction pattern of the IGZO film deposited at room temperature. Therefore, it is presumed that the IGZO film deposited at room temperature is in an intermediate state, neither crystalline nor amorphous, and it cannot be concluded that it is in an amorphous state.

[0161] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0162] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Thus, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are included in the channel formation region, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode).

[0163] A transistor using a metal oxide is likely to have normally-on characteristics due to impurities and oxygen vacancies in the metal oxide, and when the transistor is operated in a state where the metal oxide contains excess oxygen that exceeds an appropriate amount, the valence of the excess oxygen atom changes, causing the electrical characteristics of the transistor to change, which may result in poor reliability.

[0164] Therefore, it is preferable to use a metal oxide with a low carrier concentration in the channel formation region of a transistor. In order to reduce the carrier concentration of the metal oxide, it is sufficient to reduce the impurity concentration in the metal oxide and reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. Note that in this specification and the like, a metal oxide with a carrier concentration of 1×10 16 cm -3 The following cases are defined as substantially high purity and authentic:

[0165] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is 1×10 16 cm -3 More preferably, it is 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0166] Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water, which may cause oxygen vacancies in the metal oxide. If oxygen vacancies are present in the channel formation region in the metal oxide, the transistor may have normally-on characteristics. Furthermore, if hydrogen enters an oxygen vacancy in the metal oxide, the oxygen vacancy and hydrogen combine to form a V O H may be formed. A defect in which hydrogen enters an oxygen vacancy (V O Hydrogen can function as a donor and generate electrons, which are carriers. In addition, some of the hydrogen can bond with oxygen, which is bonded to metal atoms, to generate electrons, which are carriers. Therefore, transistors using metal oxides that contain a lot of hydrogen tend to have normally-on characteristics. In addition, hydrogen in metal oxides is easily mobile due to stresses such as heat and electric fields, so if metal oxides contain a lot of hydrogen, the reliability of the transistor may deteriorate.

[0167] In one embodiment of the present invention, V in oxide 230 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. OIn order to obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be obtained.

[0168] A defect in which hydrogen has entered an oxygen vacancy (V O H) can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in the case of metal oxides, the carrier concentration may be used instead of the donor concentration. Therefore, in this specification, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the metal oxide instead of the donor concentration. In other words, the "carrier concentration" described in this specification may be rephrased as the "donor concentration". In addition, the "carrier concentration" described in this specification may be rephrased as the "carrier density".

[0169] Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0170] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0171] Furthermore, when impurities are present in a channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may be reduced, or the crystallinity of an oxide provided in contact with the channel formation region may be reduced. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to be degraded. When the crystallinity of an oxide provided in contact with the channel formation region is low, an interface state may be formed, which may degrade the stability or reliability of the transistor.

[0172] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in the channel formation region of the oxide semiconductor and in its vicinity. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0173] Specifically, the concentration of the impurities in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by SIMS, is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by elemental analysis using EDX, is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0174] Furthermore, since a metal oxide with a reduced impurity concentration has a low defect state density, the trap state density may also be low.

[0175] In addition, when impurities and oxygen vacancies are present in a channel formation region of a transistor including an oxide semiconductor, the resistance of the oxide semiconductor may be reduced and the electrical characteristics may be easily changed, resulting in reduced reliability.

[0176] For example, silicon has a higher bond energy with oxygen than indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, if silicon is mixed into the oxide semiconductor, oxygen contained in the oxide semiconductor may be taken by silicon, resulting in oxygen vacancies being formed near indium or zinc.

[0177] In a transistor using an oxide semiconductor for a channel formation region, when a low-resistance region is formed in the channel formation region, a leakage current (parasitic channel) between the source electrode and the drain electrode of the transistor is likely to occur in the low-resistance region. In addition, the parasitic channel is likely to cause defects in the transistor characteristics, such as a normally-on transistor, an increase in leakage current, and a shift in threshold voltage due to application of stress. In addition, if the processing precision of the transistor is low, the parasitic channel varies from transistor to transistor, causing variation in the transistor characteristics.

[0178] Therefore, it is preferable that the impurities and oxygen vacancies be reduced as much as possible in the channel formation region of the oxide semiconductor and its vicinity.

[0179] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 1A to 1C will be described with reference to FIGS. 2A to 11A, FIGS. 2B to 11B, FIGS. 2C to 11C, and FIGS. 12A to 12C.

[0180] 2A to 11A are top views. Also, FIGS. 2B to 11B are cross-sectional views corresponding to the portion indicated by the dashed dotted line A1-A2 in FIGS. 2A to 11A, and are also cross-sectional views in the channel length direction of the transistor 200. Also, FIGS. 2C to 11C are cross-sectional views corresponding to the portion indicated by the dashed dotted line A3-A4 in FIGS. 2A to 11A, and are also cross-sectional views in the channel width direction of the transistor 200. Note that some elements are omitted in the top views of FIGS. 2A to 11A for clarity.

[0181] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate. The insulator 212 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0182] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0183] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0184] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0185] In addition, the ALD method utilizes the self-regulating nature of atoms and can deposit atoms one layer at a time, which has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD (Plasma Enhanced ALD) method, the use of plasma allows films to be formed at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0186] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0187] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0188] In this embodiment, a silicon nitride film is formed as the insulator 212 by a sputtering method.

[0189] In this way, by using an insulator such as silicon nitride through which copper does not easily permeate as insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below insulator 212, it is possible to suppress the metal from diffusing upward through insulator 212. Furthermore, by using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below insulator 212.

[0190] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited as the insulator 214 by a sputtering method.

[0191] The hydrogen concentration of the insulator 214 is preferably lower than that of the insulator 212. By forming a silicon nitride film by a sputtering method as the insulator 212, silicon nitride with a low hydrogen concentration can be formed. Furthermore, by using aluminum oxide as the insulator 214, the hydrogen concentration can be lower than that of the insulator 212.

[0192] In a subsequent process, the transistor 200 is formed on the insulator 214, and it is preferable that the film close to the transistor 200 has a relatively low hydrogen concentration, and it is preferable that the film with a relatively high hydrogen concentration is placed away from the transistor 200.

[0193] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is deposited as the insulator 216 by a sputtering method.

[0194] Note that the insulator 212, the insulator 214, and the insulator 216 are preferably successively formed under reduced pressure without exposure to the air environment. By forming the films without exposure to the air environment, impurities or moisture from the air environment can be prevented from adhering to the insulators 212, 214, and 216, and the interface and vicinity of the interface between the insulators 212 and 214, and the interface and vicinity of the interface between the insulators 214 and 216 can be kept clean, which is preferable. For example, a multi-chamber film formation apparatus may be used for successive film formation. By forming the films successively, the manufacturing process time of the semiconductor device can be shortened, which is preferable.

[0195] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form the groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0196] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0197] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film may be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0198] In this embodiment, the conductive film that becomes the conductor 205a has a multi-layer structure. First, a tantalum nitride film is formed by sputtering, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used for the conductive film that becomes the conductor 205b described later, the metal can be prevented from diffusing out of the conductor 205a.

[0199] Next, a conductive film that becomes the conductor 205b is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film that becomes the conductor 205b.

[0200] Next, a chemical mechanical polishing (CMP) process is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductor 205a and the conductor 205b remain only in the openings. This makes it possible to form the conductor 205 with a flat upper surface (see FIGS. 2A to 2C). Note that the CMP process may remove a portion of the insulator 216.

[0201] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but the present embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and the insulator 216 may be subjected to CMP treatment to remove a part of the insulator 216 and expose the surface of the conductor 205.

[0202] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium is preferably formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water.

[0203] Because the insulator 222 has barrier properties against hydrogen and water, the hydrogen and water contained in the structures provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0204] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0205] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0206] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 222 as much as possible.

[0207] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a flow rate ratio of nitrogen gas and oxygen gas of 4 slm:1 slm at a temperature of 400° C. for one hour. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment can improve the crystallinity of the insulator 222. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0208] Next, the insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide or silicon oxynitride film is formed as the insulator 224 by an ALD method. The insulator 224 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 becomes the insulator 224 in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0209] Alternatively, plasma treatment containing oxygen may be performed under reduced pressure on the insulator 224. By appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0210] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, a CMP process may be performed until the insulator 224 is reached. By performing the CMP process, the surface of the insulator 224 can be planarized and smoothed. By disposing the aluminum oxide on the insulator 224 and performing the CMP process, it becomes easy to detect the end point of the CMP process. In addition, the CMP process may polish a part of the insulator 224, and the thickness of the insulator 224 may become thin, but the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage rate of the oxide to be formed later and prevent a decrease in the yield of the semiconductor device.

[0211] Next, an oxide film 230A and an oxide film 230B are formed in this order on the insulator 224 (see FIGS. 2A to 2C).

[0212] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0213] For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. When the oxide film is formed by a sputtering method, the above-mentioned In-M-Zn oxide target can be used.

[0214] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0215] Next, the oxide film 241A is formed on the oxide film 230B (see FIGS. 2A to 2C). The oxide film 241A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 241A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 241A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0216] It is preferable that the oxide film 230A, the oxide film 230B, and the oxide film 241A are successively formed under reduced pressure without exposure to the atmospheric environment. By forming the oxide film 230A, the oxide film 230B, and the oxide film 241A without exposure to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A, the oxide film 230B, and the oxide film 241A, and it is preferable to keep the interface between the oxide film 230A and the oxide film 230B and the interface and the vicinity of the interface between the oxide film 230B and the oxide film 241A clean. For example, a multi-chamber type film forming apparatus may be used. By forming the oxide film successively, it is preferable to shorten the manufacturing process time of the semiconductor device.

[0217] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 241A are not polycrystallized, and may be performed at 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0218] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230A, the oxide film 230B, and the oxide film 241A as much as possible.

[0219] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550° C. for 1 hour, followed by another heat treatment in an oxygen atmosphere at 550° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 241A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser and more compact structure. This can reduce the diffusion of oxygen or impurities in the oxide film 230B.

[0220] Next, the conductive film 240A is formed on the oxide film 241A (see FIGS. 2A to 2C). The conductive film 240A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 240A by sputtering. Note that a heat treatment may be performed before the conductive film 240A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 240A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 241A can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 241A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0221] Next, the insulating film 271A is formed on the conductive film 240A (see FIGS. 2A to 2C). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film having a function of suppressing oxygen permeation. For example, the insulating film 271A may be formed of aluminum oxide, hafnium oxide, silicon nitride, or the like by a sputtering method or an ALD method.

[0222] Next, a conductive film 291A is formed over the insulating film 271A (see FIGS. 2A to 2C). The conductive film 291A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film 291A may be, for example, a conductive film similar to the conductive film 240A.

[0223] In this embodiment, the conductive film 240A, the insulating film 271A, and the conductive film 291A are formed by sputtering using tantalum nitride for the conductive film 240A, aluminum oxide for the insulating film 271A, and tantalum nitride for the conductive film 291A.

[0224] Note that the conductive film 240A, the insulating film 271A, and the conductive film 291A are preferably formed successively under reduced pressure without exposure to the air environment. By forming the films without exposure to the air environment, impurities or moisture from the air environment can be prevented from adhering to the conductive film 240A, the insulating film 271A, and the conductive film 291A, and the interface and the vicinity of the interface between the conductive film 240A and the insulating film 271A, and the interface and the vicinity of the interface between the insulating film 271A and the conductive film 291A can be kept clean, which is preferable. For example, a multi-chamber type film forming apparatus may be used. By forming the films successively, the manufacturing process time of the semiconductor device can be shortened, which is preferable.

[0225] Next, the oxide film 230A, the oxide film 230B, the oxide film 241A, the conductive film 240A, the insulating film 271A, and the conductive film 291A are processed into an island shape by using a lithography method to form the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B (see FIGS. 3A to 3C). This processing can be performed by a dry etching method or a wet etching method. Processing by the dry etching method is suitable for fine processing. The oxide film 230A, the oxide film 230B, the oxide film 241A, the conductive film 240A, the insulating film 271A, and the conductive film 291A may be processed under different conditions. In this process, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may be thin.

[0226] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0227] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that will be the hard mask material is formed on the conductive film 240A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. Etching of the conductive film 240A and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching of the conductive film 240A and the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B and the conductive layer 291B are used as the hard mask.

[0228] Moreover, the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B are formed so as to at least partially overlap with the conductor 205. Moreover, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B are approximately perpendicular to the upper surface of the insulator 222. Since the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B are approximately perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when providing a plurality of transistors 200. Alternatively, the angle between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B and the upper surface of the insulator 222 may be low. In this case, the angle between the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, the insulating layer 271B, and the conductive layer 291B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulating film 280A and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0229] Next, the conductive layer 291B is removed by dry etching (see FIGS. 4A to 4C).

[0230] Next, an insulating film that will become the insulator 280 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, and the insulating layer 271B. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0231] For example, the insulating film may be formed by forming a silicon oxide film by a sputtering method, and then forming a silicon oxide film thereon by a PEALD method or a thermal ALD method. The insulating film is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This can reduce the hydrogen concentration in the insulator 280. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the insulator 224 and the surface of the object to be formed can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 241B, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0232] Next, the insulating film is subjected to CMP processing to form an insulator 280 having a flat upper surface (see FIGS. 5A to 5C). As with the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the aluminum oxide reaches the insulator 280.

[0233] Here, a microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. After the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0234] Furthermore, by performing microwave treatment, the film quality of the insulator 280 can be modified, thereby suppressing the diffusion of hydrogen, water, impurities, and the like from the insulator 280 to the oxide 230. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, and the like to the oxide 230 via the insulator 280 by a post-process after the formation of the insulator 280, or by a heat treatment, and the like. Note that, although the embodiment has been described as an example of a form in which microwave treatment is performed from above the insulator 280, this is not limiting. For example, in addition to microwave treatment, plasma treatment or microwave-excited plasma treatment, and the like, may be performed.

[0235] Next, a part of the insulator 280, a part of the insulating layer 271B, a part of the conductive layer 240B, a part of the oxide layer 241B, and a part of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 240a, the conductor 240b, the oxide 241a, and the oxide 241b are formed (see FIGS. 6A to 6C).

[0236] Here, the upper part of the oxide 230b may be removed in the step of forming the opening. By removing a part of the oxide 230b, a groove is formed in the oxide 230b.

[0237] In addition, a part of the insulator 280, a part of the insulating layer 271B, a part of the conductive layer 240B, a part of the oxide layer 241B, and a part of the oxide 230b can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulating layer 271B may be processed by wet etching, and a part of the oxide layer 241B, a part of the conductive layer 240B, and a part of the oxide 230b may be processed by dry etching. In addition, processing of a part of the oxide layer 241B and a part of the conductive layer 240B and processing of a part of the oxide 230b may be performed under different conditions.

[0238] When a part of the oxide 230b is removed by dry etching to form a groove, it is preferable to perform the process with a high bias power. For example, the power density of the bias power is set to 0.02 W / cm 2 Above 0.03W / cm 2 It is preferable to set it to 0.06 W / cm or more. 2 It is more preferable that the dry etching time is set to be equal to or longer than that. The dry etching time may be appropriately set according to the depth of the groove.

[0239] In the above-mentioned opening step, impurities may be generated inside the opening or damaged areas may be generated on the surface of the oxide 230b. The impurities and damaged areas are preferably removed by a cleaning step.

[0240] The impurities include, for example, those originating from components contained in the insulator 280, part of the insulating layer 271B, and the conductive layer 240B, components contained in the members used in the device used to form the opening, components contained in the gas or liquid used in etching, etc. Specifically, the impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0241] In particular, impurities such as aluminum or silicon may inhibit the oxide 230c formed in a later step from becoming a CAAC-OS.

[0242] In metal oxides, regions in which impurities such as aluminum or silicon inhibit the formation of CAAC-OS and the resulting amorphous-like oxide semiconductor (a-like OS) are sometimes called non-CAAC regions. In non-CAAC regions, the density of the crystal structure is reduced, and the V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC regions of the oxide 230b and the oxide 230c are reduced or removed.

[0243] Therefore, it is preferable that impurity elements such as aluminum or silicon attached to the surfaces of the oxide 230a and the oxide 230b, which inhibit the formation of CAAC-OS, are reduced or removed. For example, the concentration of aluminum atoms at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0244] Moreover, it is preferable that the oxide 230b and the oxide 230c have a layered CAAC structure. In particular, it is preferable that the CAAC structure is formed up to the drain lower end of the oxide 230b and the oxide 230c. Here, in the transistor 200, the conductor 240a or the conductor 240b and its vicinity function as the drain. In other words, it is preferable that either one or both of the oxide 230b and the oxide 230c near the lower end of the conductor 240a (conductor 240b) have a CAAC structure. In this way, even at the drain end that significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation of the electrical characteristics of the transistor 200 can be further suppressed. In addition, the reliability of the transistor 200 can be improved.

[0245] The cleaning process may be a wet cleaning process using a cleaning solution, a plasma process using plasma, a heat treatment process, or the like, and may be a combination of the above cleaning processes. Note that the cleaning process may deepen the grooves.

[0246] As the wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Also, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Also, these cleaning methods may be appropriately combined.

[0247] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be called diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0248] In addition, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0249] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0250] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230c formed on the oxide 230b can be improved.

[0251] Furthermore, due to processing such as the dry etching or the cleaning process, the thickness of the insulator 224 in the area that overlaps with the opening but does not overlap with the oxide 230b may become thinner than the thickness of the insulator 224 in the area that overlaps with the oxide 230b.

[0252] Also, a heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at 100° C. or higher and 450° C. or lower, preferably 350° C. or higher and 400° C. or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0253] Next, the oxide film 230C is formed (see FIGS. 7A to 7C). A heat treatment may be performed before the formation of the oxide film 230C, and the heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C.

[0254] Here, it is preferable that the oxide film 230C is provided so as to contact at least the inner wall of the groove formed in the oxide 230b, a part of the side surface of the oxide 241, a part of the side surface of the conductor 240, a part of the side surface of the insulator 271, and a part of the side surface of the insulator 280. By being surrounded by the oxide 241, the insulator 271, and the oxide film 230C, the decrease in conductivity of the conductor 240 due to oxidation in the subsequent steps can be suppressed.

[0255] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as that for the oxide film 230A. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0256] Here, in order to reduce oxygen vacancies in oxide 230b and oxide film 230C and make oxide 230b substantially high-purity and intrinsic, a process of adding oxygen to oxide 230b and oxide film 230C (hereinafter also referred to as oxygen ion implantation process or oxygen doping process) is performed (see Figures 8A to 8C and Figure 12A. Note that Figure 12A is an enlarged view of a portion of Figure 8C).

[0257] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide film 230C, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In particular, since the oxide film 230C is made of the same elements as the oxide 230b, even if a part of the oxide film 230C diffuses into the oxide 230b by the addition treatment, no problems caused by impurities occur.

[0258] 8B, 8C, and 12A, an oxygen implantation process forms an oxygen-added region 292 in the oxide film 230C, the surface of the oxide 230b, the surface of the insulator 280, and the surface of the insulator 224. In particular, it is preferable to provide the region 292 near the interface between the oxide film 230C and the oxide 230b. By adding oxygen to the surface of the oxide 230b, oxygen vacancies in the oxide 230b can be efficiently reduced in a subsequent heat treatment.

[0259] Specifically, oxygen can be added to the oxide film 230C and the oxide 230b by using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like as the oxygen implantation process. 16 O2 or 18Examples of the gas include oxygen gas such as O2, nitrous oxide gas, ozone gas, and other gases containing oxygen. The process of adding oxygen may be performed while heating the substrate.

[0260] For example, the acceleration voltage in the ion doping process is 0.5 kV to 100 kV, preferably 1 kV to 50 kV, more preferably 1 kV to 30 kV, and even more preferably 1 kV to 10 kV. The ion implantation concentration is 1×10 15 atoms / cm 2 More than 2×10 15 atoms / cm 2 More preferably, 5×10 15 atoms / cm 2 More preferably, 1×10 16 atoms / cm 2 More preferably, 2×10 16 atoms / cm 2 That is all.

[0261] The addition of ions by the ion doping process may be performed approximately perpendicular to the sample surface, or may be performed at an angle to the sample surface.

[0262] Here, in Fig. 8B and Fig. 8C, an arrow 290 shows a schematic direction of travel of oxygen ions. As shown by the arrow 290, in the channel width direction of the oxide 230b, it is preferable that one ion is incident at an angle θ (45°<θ<135°) with respect to a tangent to the upper surface of the oxide 230b. In addition, in the L length direction of the oxide 230b, it is preferable that one ion is incident approximately perpendicularly to the upper surface of the oxide 230b. By appropriately adjusting the angle θ, oxygen can be added to the side surface of the oxide 230b and the oxide film 230C formed on the side surface of the oxide 230b.

[0263] Before forming the oxide film 230C, a process of adding oxygen may be performed. When oxygen is added before forming the oxide film 230C, it is preferable that the oxide layer 241B remains in the opening as shown in Fig. 13. When the oxide layer 241B remains on the bottom surface of the opening, it is preferable that the oxide layer 241B and the oxide film 230C are made of the same material and have the same atomic ratio.

[0264] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide layer 241B, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In particular, since the oxide layer 241B is made of the same elements as the oxide 230b, even if a part of the oxide layer 241B diffuses into the oxide 230b by the addition treatment, no problems caused by impurities occur.

[0265] Next, a heat treatment is performed (see FIGS. 9A to 9C, 12B, and 12C. Note that FIGS. 12B and 12C are enlarged views of a part of FIG. 9C).

[0266] The heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230b, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, a heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0267] Specifically, the heat treatment is preferably performed at 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is preferably performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

[0268] The effect of the heat treatment will be described with reference to Fig. 12. As shown in Fig. 12B, the oxygen added to the region 292 by the oxygen implantation process diffuses into the oxide 230b, the insulator 224, and the insulator 280 by the heat treatment. At the same time, as shown in Fig. 12C, the diffused oxygen is supplied to the oxygen vacancies Vo of the oxide film 230C and the oxide 230b by the heat treatment, and becomes a part of the oxide film 230C and the oxide 230b by filling the oxygen vacancies. On the other hand, the oxygen diffused into the insulator 224 and the insulator 280 remains in the insulator 224 and the insulator 280 as excess oxygen.

[0269] By reducing the defect level or oxygen vacancy in the channel formation region, a highly reliable transistor with little fluctuation in electrical characteristics can be provided. In addition, a transistor with normally-off characteristics can be provided.

[0270] On the other hand, when the transistor is operated in a state in which the metal oxide contains excess oxygen that exceeds an appropriate amount, the valence of the excess oxygen atoms changes, and the electrical characteristics of the transistor fluctuate, which may result in reduced reliability.

[0271] Therefore, by covering the channel formation region of the oxide 230b with the oxide 230a having barrier properties and the oxide 230c having barrier properties, it is possible to prevent excess oxygen contained in the insulator 224 from being excessively supplied to the oxide 230b.

[0272] Next, the insulating film 250A is formed (see FIGS. 10A to 10C). A heat treatment may be performed before the formation of the insulating film 250A. It is preferable to perform the heat treatment under reduced pressure and then continuously form the insulating film 250A without exposing it to the air. It is also preferable to perform the heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0273] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230c in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0274] When the insulator 250 has a two-layer laminated structure, it is preferable to continuously deposit the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 without exposing them to the atmospheric environment. By depositing the films without exposing them to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250, and it is possible to keep the vicinity of the interface between the insulating film that will be the lower layer of the insulator 250 and the insulating film that will be the upper layer of the insulator 250 clean.

[0275] Here, after the insulating film 250A is formed, a microwave treatment may be performed in an oxygen-containing atmosphere under reduced pressure. After the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure. By performing the microwave treatment, the film quality of the insulating film 250A and the like is modified, thereby making it possible to suppress the diffusion of hydrogen, water, impurities, and the like. Therefore, the diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide 230b, the oxide 230a, and the like can be suppressed by a post-process such as the formation of a conductive film that becomes the conductor 260, or a post-treatment such as a heat treatment.

[0276] Next, the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 10A to 10C). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is successively formed by a CVD method under reduced pressure without exposure to the atmosphere.

[0277] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see Figures 11A to 11C).

[0278] The CMP process may remove a portion of the insulator 280, including the region 292. By removing the region, the amount of excess oxygen contained in the insulator 280 can be reduced.

[0279] By the above processing, the oxide 230c is arranged so as to cover the opening reaching the oxide 230b and the inner wall (side wall and bottom surface) of the groove of the oxide 230b. The insulator 250 is arranged so as to cover the opening and the inner wall of the groove through the oxide 230c. The conductor 260 is arranged so as to fill the opening and the groove through the oxide 230c and the insulator 250.

[0280] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0281] Next, the insulator 282 is formed on the oxide 230b, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form a film of aluminum oxide by a sputtering method. It is also preferable to form the insulator 282 while heating the substrate. It is also preferable to form the insulator 282 in contact with the upper surface of the conductor 260, because this can suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in a subsequent heat treatment.

[0282] Next, the insulator 283 is formed over the insulator 282. The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed by a sputtering method.

[0283] Next, openings are formed in the insulators 271, 280, 282, and 283, reaching the conductor 240. The openings may be formed by using a lithography method. Note that, although the shape of the openings is circular in top view in FIG. 1A, the shape is not limited to this. For example, the openings may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0284] Next, an insulating film that will become the insulator 276 is formed, and the insulating film is anisotropically etched to form the insulator 276 (insulator 276a and insulator 276b). The insulating film that will become the insulator 276 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulating film that will become the insulator 276, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by the ALD method. Alternatively, it is preferable to form a silicon nitride film by the PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0285] Moreover, for example, a dry etching method may be used as the anisotropic etching of the insulating film that becomes the insulator 276. By providing the insulator 276 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and to prevent the oxidation of the conductor 246a and the conductor 246b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 246a and the conductor 246b.

[0286] Next, a conductive film that becomes the conductor 246a and the conductor 246b is formed. The conductive film that becomes the conductor 246a and the conductor 246b is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 246 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0287] Next, CMP processing is performed to remove parts of the conductive film that will become conductor 246a and conductor 246b, exposing the upper surfaces of insulator 283 and insulator 276. As a result, the conductive film remains only in the openings, forming conductors 246a and 246b with flat upper surfaces. Note that the CMP processing may remove parts of the upper surfaces of insulator 283 and insulator 276.

[0288] Next, a conductive film is formed to become the conductor 248. The conductive film to become the conductor 248 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0289] Next, the conductive film that becomes the conductor 248 is processed by lithography to form the conductor 248a in contact with the top surface of the conductor 246a and the conductor 248b in contact with the top surface of the conductor 246b. At this time, although not shown, a part of the insulator 283 may be removed from the region where the conductor 248a and the conductor 248b do not overlap with the insulator 283.

[0290] Next, an insulator 286 is formed on the conductor 248 and the insulator 283 (see FIGS. 1A to 1C). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be a multi-layer structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by a CVD method.

[0291] Through the above steps, a semiconductor device including the transistor 200 shown in FIGS. 1A to 1C can be manufactured.

[0292] <Modification 1 of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 15A to 15C.

[0293] Fig. 15A shows a top view of the semiconductor device. Fig. 15B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 15A. Fig. 15C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 15A. In the top view of Fig. 15A, some elements are omitted for clarity.

[0294] 15A to 15C, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration Example 1 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0295] The semiconductor device shown in Figures 15A to 15C is a modified example of the semiconductor device shown in Figures 1A to 1C. The semiconductor device shown in Figures 15A to 15C differs from the semiconductor device shown in Figures 1A to 1C in the shapes of the insulator 214, the insulator 282, and the insulator 283. Also, the semiconductor device differs in that it has an insulator 284.

[0296] In the semiconductor device shown in FIG. 15A to FIG. 15C, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 are patterned. The insulator 283 has a structure that covers the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282. That is, the insulator 283 contacts the upper surface and side surface of the insulator 282 and the upper surface of the insulator 212. As a result, the insulators 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282, including the oxide 230, are isolated from the outside by the insulator 283 and the insulator 212. In other words, the transistor 200 is disposed in a region sealed by the insulator 283 and the insulator 212.

[0297] For example, it is preferable to form the insulators 214 and 282 using a material that has a function of capturing and fixing hydrogen, and to form the insulators 212 and 283 using a material that has a function of suppressing the diffusion of hydrogen and oxygen. Typically, the insulators 214 and 282 can be made of aluminum oxide. Typically, the insulators 212 and 283 can be made of silicon nitride.

[0298] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from entering the sealed region.

[0299] 15A to 15C show a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0300] The insulator 284 functions as an interlayer film. The insulator 284 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 284 can be provided using, for example, a material similar to that of the insulator 280.

[0301] <Application example 1 of semiconductor device> 16A and 16B, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those shown in the above <Structural Example 1 of Semiconductor Device> and the above <Variation 1 of Semiconductor Device>, will be described below. Note that in the semiconductor device shown in FIG. 16A and FIG. 16B, structures having the same functions as those of the semiconductor device shown in <Variation 1 of Semiconductor Device> (see FIG. 1A to FIG. 1C) are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural Example 1 of Semiconductor Device> and <Variation 1 of Semiconductor Device> can be used as the materials for forming the transistor 200.

[0302] 16A and 16B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 16A and 16B, this is not the only possible arrangement. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0303] 16A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Thus, a plurality of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0304] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0305] In addition, although Fig. 16A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this. As shown in Fig. 16B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 16B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0306] In this manner, by using a structure in which the multiple transistors 200_1 to 200_n are surrounded by multiple sealing portions, the number of areas in contact with the insulator 283 and the insulator 212 increases, thereby improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the multiple transistors 200_1 to 200_n.

[0307] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0308] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0309] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0310] (Embodiment 2) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0311] Note that structures having similar functions to those of the semiconductor device described in the above embodiment are denoted by the same reference numerals, and therefore the above embodiment can be referred to for structures denoted by the same reference numerals.

[0312] <Configuration Example 2 of Semiconductor Device> A configuration of a semiconductor device having a transistor 200 will be described with reference to FIG. 17. FIGS. 17A to 17C are a top view and a cross-sectional view of a semiconductor device having a transistor 200. FIG. 17A is a top view of the semiconductor device. FIGS. 17B to 17C are cross-sectional views of the semiconductor device. FIG. 17B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 17A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 17C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 17A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the top view of FIG. 17A for clarity.

[0313] A semiconductor device of one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 274 on the transistor 200, an insulator 280 on the insulator 274, an insulator 282 on the insulator 280, and an insulator 283 on the insulator 282. The insulators 212, 214, 274, 280, 282, and 283 function as interlayer films.

[0314] The transistor 200 also includes a conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the transistor 200 and functions as a plug. An insulator 276 (insulator 276a and insulator 276b) is provided in contact with a side surface of the conductor 246 that functions as a plug. A conductor 248 (conductor 248a and conductor 248b) that is electrically connected to the conductor 246 and functions as a wiring is provided on the insulator 283 and the conductor 246. An insulator 286 is provided on the conductor 248 and the insulator 284.

[0315] Specifically, insulator 276a is provided in contact with the inner walls of the openings of insulators 274, 280, 282, and 283, a first conductor of conductor 246a is provided in contact with the side surface of insulator 276a, and a second conductor of conductor 246a is provided further inward. Also, insulator 276b is provided in contact with the inner walls of the openings of insulators 280, 282, and 283, a first conductor of conductor 246b is provided in contact with the side surface of insulator 276b, and a second conductor of conductor 246b is provided further inward.

[0316] 17B, ​​the height of the top surface of the conductor 246 and the height of the top surface of the insulator 283 in the region overlapping with the conductor 248 can be made approximately the same. Note that, in the transistor 200, a configuration in which the first conductor of the conductor 246 and the second conductor of the conductor 246 are stacked is shown, but the present invention is not limited to this. For example, the conductor 246 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be given to indicate the order of formation to distinguish them from one another.

[0317] [Transistor 200] As shown in FIGS. 17A to 17C , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 241 (oxide 242) on the oxide 230b. 1a, and oxide 241b), oxide 230c, oxide 230d on oxide 230c, conductor 240a on oxide 241a, insulator 271a on conductor 240a, conductor 240b on oxide 241b, insulator 271b on conductor 240b, insulator 250 on oxide 230d, and conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with part of oxide 230c and oxide 230d. In addition, oxide 230c is in contact with the side of oxide 241a, the side of oxide 241b, the side of conductor 240a, the side of conductor 240b, the side of insulator 271a, and the side of insulator 271b.

[0318] 17B and 17C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surface of the insulator 250, the oxide 230c, and the upper surfaces of the oxide 230d. Also, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230c, the oxide 230d, and the insulator 280.

[0319] In the following, the insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0320] An opening is provided in the insulator 280, reaching the oxide 230b. The oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 are disposed in the opening. In addition, in the channel length direction of the transistor 200, the conductor 260, the insulator 250, the oxide 230d, and the oxide 230c are provided between the conductor 240a and the oxide 241a and between the conductor 240b and the oxide 241b. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. The oxide 230d is provided between the oxide 230c and the insulator 250. In addition, in the region overlapping with oxide 230b, oxide 230c has a region in contact with oxide 230b, a region overlapping with oxide 230d and the side of conductor 260 via insulator 250, and a region overlapping with the bottom surface of conductor 260 via insulator 250.

[0321] Oxide 230 preferably has oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, oxide 230c disposed on oxide 230b and at least partially in contact with oxide 230b, and oxide 230d disposed on oxide 230c.

[0322] Note that in the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d) including the channel formation region.

[0323] A transistor using an oxide semiconductor for a channel formation region has an extremely small leakage current in a non-conducting state, and therefore a semiconductor device with low power consumption can be provided. On the other hand, the electrical characteristics of a transistor using an oxide semiconductor tend to change due to impurities and oxygen vacancies in the oxide semiconductor, and the transistor tends to have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode).

[0324] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor in which impurities and oxygen vacancies are reduced as the oxide semiconductor for use in a channel formation region of a transistor. Note that in this specification and the like, a high-purity intrinsic oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a substantially high-purity intrinsic oxide semiconductor.

[0325] However, in a transistor including an oxide semiconductor, oxygen from the oxide semiconductor is gradually absorbed by a conductor that constitutes the transistor or a conductor that is used for a plug or a wiring that connects to the transistor, and oxygen vacancies may occur as a type of change over time.

[0326] Therefore, it is preferable to make the oxide 230b substantially high-purity and intrinsic. In order to make the oxide 230b high-purity and intrinsic, it is preferable to perform a process of adding oxygen to the oxide 230b (hereinafter, also referred to as oxygen implantation process or oxygen doping process). Specifically, the oxygen implantation process may be performed by ion implantation, ion doping, plasma immersion ion implantation, or the like.

[0327] On the other hand, when performing a process of adding oxygen using an ion implantation method or the like, physical damage may occur on the surface of the oxide 230b. Therefore, it is preferable to perform a process of adding oxygen to the oxide 230b via the oxide film 230C. Therefore, it is preferable to use the same material for the oxide film 230C as for the oxide 230b.

[0328] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide 230c, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In addition, since the same material is used for the oxide 230b and the oxide 230c, even if a part of the oxide film 230C diffuses into the oxide 230b by the addition treatment, no problems caused by impurities occur.

[0329] Furthermore, after oxide 230b is made substantially intrinsic with high purity, it is preferable to cover the region of oxide 230b in which the channel is to be formed with oxide 230a, which suppresses oxygen diffusion more than oxide 230b, and oxide 230d.

[0330] Specifically, as shown in the figure, by disposing the oxide 230a under the oxide 230b, it is possible to suppress the extraction of oxygen from the oxide 230b. Also, it is possible to suppress the diffusion of oxygen and impurities from the structure formed below the oxide 230a to the oxide 230b.

[0331] Moreover, by disposing the oxide 230d on the oxide 230b and the oxide 230c, it is possible to suppress the extraction of oxygen from the oxide 230b and the oxide 230c. It is also possible to suppress the diffusion of impurities from a structure formed above the oxide 230d into the oxide 230b.

[0332] Note that the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having such a wide band gap, the off-state current of a transistor can be reduced.

[0333] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0334] Here, the oxide 230 preferably has a layered structure of multiple oxide layers with different chemical compositions. Specifically, the metal oxide used for the oxide 230b preferably has a larger atomic ratio of In to element M than the metal oxide used for the oxide 230a or the oxide 230d.

[0335] That is, in the metal oxides used for the oxides 230a and 230d, the atomic ratio of element M to the main metal element is preferably greater than the atomic ratio of element M to the main metal element in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a and 230d.

[0336] By the oxide 230a and the oxide 230d having a common element other than oxygen (as a main component), the defect level density at each interface between the oxide 230a, the oxide 230b, and the oxide 230d can be reduced. At this time, the main path of carriers is the oxide 230b or its vicinity, for example, the interface between the oxide 230b and the oxide 230c. Since the defect level density at the interface between the oxide 230b and the oxide 230c can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0337] For example, as the oxide 230b and the oxide 230c, specifically, a metal oxide, indium oxide, etc., having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=10:1:3 [atomic ratio] or a composition close thereto, may be used.

[0338] Moreover, it is preferable that the oxide 230b and the oxide 230c have crystallinity. In particular, it is preferable that the oxide 230b is made of c-axis aligned crystalline oxide semiconductor (CAAC-OS).

[0339] In one embodiment of the present invention, for example, it is preferable to use silicon nitride or the like as the insulators 212, 282, 283, 274, and 286, and aluminum oxide or the like as the insulators 214 and 271. This can suppress impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulators 212 and 214. It is also possible to suppress diffusion of impurities such as water and hydrogen from the insulator 280, the conductor 248, and the like to the oxide 230. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 274, 282, and 283, which have a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.

[0340] For example, an insulator 274 is provided to cover the side surfaces of the oxide 230a, the oxide 230b, the oxide 241, the conductor 240, and the insulator 271. The insulator 274 preferably functions as a barrier insulating film against oxygen more than the insulator 280. In other words, the insulator preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 274 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.

[0341] The insulator 274 is preferably formed in an atmosphere that does not contain oxygen, particularly in an inert atmosphere. When the insulator 274 is formed in an atmosphere that contains oxygen, oxygen may be added to the surface on which the insulator 274 is formed. When oxygen is added to the insulator 224, the oxygen is likely to diffuse to the channel formation region through the oxide 230c. When excess oxygen diffuses to the channel formation region, it may cause deterioration of the electrical characteristics of the transistor. Therefore, the insulator 274 may be formed using, for example, a nitride such as silicon nitride.

[0342] In particular, it is preferable to form the insulator 274 by a sputtering method. Since the sputtering method does not include a hydrogen atmosphere, it is possible to suppress the inclusion of hydrogen as an impurity.

[0343] By providing the insulator 271 and the insulator 274, the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240 can be separated from the insulator 280. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280 to the oxide 230a, the oxide 230b, the oxide 241, and the conductor 240. This makes it possible to prevent the carrier density of the source region and the drain region of the oxide 230 from being reduced due to the supply of excess oxygen to the source region and the drain region. In addition, it is possible to suppress the conductor 240 from being excessively oxidized, which increases the resistivity and reduces the on-current.

[0344] In addition, when the conductor 246 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 284, the insulator 283, the insulator 282, the insulator 280, and the insulator 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. In addition, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 284 from being mixed into the oxide 230 through the conductor 246a and the conductor 246b.

[0345] In particular, the insulator 282 is preferably formed in an oxygen-free atmosphere and an inert atmosphere, similar to the insulator 274. When the insulator 282 is formed in an oxygen-containing atmosphere, oxygen may be added to the surface on which the insulator 282 is formed. When oxygen is added to the insulator 280, the oxygen is likely to diffuse to the channel formation region through the oxide 230c. When excess oxygen diffuses to the channel formation region, it may cause deterioration of the electrical characteristics of the transistor. Therefore, the insulator 282 may be formed of, for example, a nitride such as silicon nitride.

[0346] Note that when an oxide film with high barrier properties, such as aluminum oxide, is to be used for the insulator 282, the film should be formed under conditions in which oxygen is not injected into the surface on which the film is to be formed.

[0347] The insulator 282 is preferably formed by a sputtering method. Since the sputtering method does not include a hydrogen atmosphere, inclusion of hydrogen as an impurity can be suppressed.

[0348] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 17A to 17C will be described with reference to FIGS. 18A to 25A, FIGS. 18B to 25B, FIGS. 18C to 25C, and FIGS. 26A to 26C.

[0349] 18A to 25A are top views. Also, Fig. 18B to Fig. 25B are cross-sectional views corresponding to the portion indicated by the dashed line A1-A2 in Fig. 18A to Fig. 25A, and are also cross-sectional views in the channel length direction of the transistor 200. Also, Fig. 18C to Fig. 25C are cross-sectional views corresponding to the portion indicated by the dashed line A3-A4 in Fig. 18A to Fig. 25A, and are also cross-sectional views in the channel width direction of the transistor 200. Note that some elements are omitted in the top views of Fig. 18A to Fig. 25A for clarity.

[0350] First, in this embodiment mode, the manufacturing method described with reference to FIGS. 2 to 4 in the previous embodiment mode can be referred to.

[0351] Next, the insulator 274 is deposited over the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 241B, the conductive layer 240B, and the insulating layer 271B.

[0352] The insulator 274 is formed in an atmosphere that does not contain at least oxygen. For example, it is preferable to form the insulator 274 in an inert atmosphere of a rare gas, nitrogen, or the like. Specifically, the insulator 274 may be formed using a nitride such as silicon nitride.

[0353] When a film is formed in an atmosphere containing oxygen, oxygen may be added to the film formation surface. When oxygen is added to the insulator 224, the oxygen is likely to diffuse to the channel formation region through the oxide 230c. When excess oxygen diffuses to the channel formation region, it may cause deterioration of the electrical characteristics of the transistor.

[0354] Next, an insulating film that will become the insulator 280 is formed on the insulator 274. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0355] Next, the insulating film is subjected to CMP processing to form an insulator 280 having a flat upper surface (see FIGS. 18A to 18C). As with the insulator 224, an aluminum oxide film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the aluminum oxide reaches the insulator 280.

[0356] Here, a microwave treatment may be performed. The microwave treatment is preferably performed in an oxygen-containing atmosphere under reduced pressure. After the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower.

[0357] Furthermore, by performing microwave treatment, the film quality of the insulator 280 can be modified, thereby suppressing the diffusion of hydrogen, water, impurities, and the like. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, and the like into the oxide 230 through the insulator 280 by a post-process after the formation of the insulator 280, or by a heat treatment, and the like. Note that, although the embodiment has been described as an example of a form in which microwave treatment is performed from above the insulator 280, this is not limiting. For example, in addition to the microwave treatment, a plasma treatment or a microwave-excited plasma treatment may be performed.

[0358] Next, a part of the insulator 280, a part of the insulator 274, a part of the insulating layer 271B, a part of the conductive layer 240B, a part of the oxide layer 241B, and a part of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 240a, the conductor 240b, the oxide 241a, and the oxide 241b are formed (see FIGS. 19A to 19C).

[0359] Here, the upper part of the oxide 230b may be removed in the step of forming the opening. By removing a part of the oxide 230b, a groove is formed in the oxide 230b.

[0360] In addition, a part of the insulator 280, a part of the insulator 274, a part of the insulating layer 271B, a part of the conductive layer 240B, a part of the oxide layer 241B, and a part of the oxide 230b can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions. For example, a part of the insulator 280 and a part of the insulator 274 may be processed by dry etching, a part of the insulating layer 271B may be processed by wet etching, and a part of the oxide layer 241B, a part of the conductive layer 240B, and a part of the oxide 230b may be processed by dry etching. In addition, processing of a part of the oxide layer 241B and a part of the conductive layer 240B and processing of a part of the oxide 230b may be performed under different conditions.

[0361] When a part of the oxide 230b is removed by dry etching to form a groove, it is preferable to perform the process by increasing the bias power. For example, the power density of the bias power is set to 0.02 W / cm 2 Above 0.03W / cm 2 It is preferable to set it to 0.06 W / cm or more. 2 It is more preferable that the dry etching time is set to be equal to or longer than that. The dry etching time may be appropriately set according to the depth of the groove.

[0362] In the above-mentioned opening step, impurities may be generated inside the opening or damaged areas may be generated on the surface of the oxide 230b. The impurities and damaged areas are preferably removed by a cleaning step.

[0363] Next, the oxide film 230C is formed (see FIGS. 20A to 20C). A heat treatment may be performed before the formation of the oxide film 230C, and the heat treatment is preferably performed under reduced pressure, and the oxide film 230C is formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C.

[0364] Here, it is preferable that the oxide film 230C is provided so as to contact at least the inner wall of the groove formed in the oxide 230b, a part of the side surface of the oxide 241, a part of the side surface of the conductor 240, a part of the side surface of the insulator 271, and a part of the side surface of the insulator 280. By being surrounded by the oxide 241, the insulator 271, and the oxide film 230C, the decrease in conductivity of the conductor 240 due to oxidation in the subsequent steps can be suppressed.

[0365] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film formation method as that for the oxide film 230A. In this embodiment, the oxide film 230C is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0366] Here, in order to reduce oxygen vacancies in oxide 230b and oxide film 230C and make oxide 230b substantially high-purity and intrinsic, a process of adding oxygen to oxide 230b and oxide film 230C (hereinafter also referred to as oxygen implantation process or oxygen doping process) is performed (see Figures 21A to 21C and Figure 26A. Note that Figure 26A is an enlarged view of a portion of Figure 21C).

[0367] By performing oxygen addition treatment on the channel formation region of the oxide 230b through the oxide film 230C, it is possible to suppress the diffusion of impurities or the generation of damaged regions on the surface of the channel formation region. In particular, since the oxide film 230C uses the same material as the oxide 230b, even if a part of the oxide film 230C diffuses into the oxide 230b by the addition treatment, no problems caused by impurities occur.

[0368] 21B, 21C, and 26A, an oxygen implantation process forms an oxygen-added region 292 in the oxide film 230C, the surface of the oxide 230b, the surface of the insulator 280, and the surface of the insulator 224. In particular, it is preferable to provide the region 292 near the interface between the oxide film 230C and the oxide 230b. By adding oxygen to the surface of the oxide 230b, oxygen vacancies in the oxide 230b can be efficiently reduced in a subsequent heat treatment.

[0369] Specifically, oxygen can be added to the oxide film 230C and the oxide 230b by using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like as the oxygen implantation process. 16 O2 or 18 Examples of the gas include oxygen gas such as O2, nitrous oxide gas, ozone gas, and other gases containing oxygen. The process of adding oxygen may be performed while heating the substrate.

[0370] For example, the acceleration voltage in the ion doping process is 0.5 kV to 100 kV, preferably 1 kV to 50 kV, more preferably 1 kV to 30 kV, and even more preferably 1 kV to 10 kV. The ion implantation concentration is 1×10 15 atoms / cm 2 More than 2×10 15 atoms / cm 2 More preferably, 5×10 15 atoms / cm 2 More preferably, 1×10 16 atoms / cm 2 More preferably, 2×10 16 atoms / cm 2 That is all.

[0371] The addition of ions by the ion doping process may be performed approximately perpendicular to the sample surface, or may be performed at an angle to the sample surface.

[0372] Here, in Figures 21B and 21C, an arrow 290 typically indicates the direction of travel of oxygen ions. As indicated by the arrow 290, in the channel width direction of the oxide 230b, it is preferable that one ion is incident at an angle θ (45°<θ<135°) with respect to a tangent to the upper surface of the oxide 230b. In addition, in the L length direction of the oxide 230b, it is preferable that one ion is incident approximately perpendicularly to the upper surface of the oxide 230b. By appropriately adjusting the angle θ, oxygen can be added to the side surface of the oxide 230b and the oxide film 230C formed on the side surface of the oxide 230b.

[0373] Next, an oxide film 230D is formed on the oxide film 230C (see FIGS. 22A to 22C). The oxide film 230D preferably has a higher barrier property against oxygen and impurities than the oxide 230b and the oxide film 230C.

[0374] By disposing the oxide film 230D on the oxide 230b and the oxide film 230C, it is possible to suppress the extraction of oxygen from the oxide 230b and the oxide film 230C. In addition, it is possible to suppress the diffusion of impurities into the oxide 230b from a structure formed above the oxide film 230D.

[0375] Next, a heat treatment is performed (see FIGS. 23A to 23C, 26B, and 26C. Note that FIGS. 26B and 26C are enlarged views of a part of FIG. 23C).

[0376] The heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230b, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, a heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0377] Specifically, the heat treatment is preferably performed at 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is preferably performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

[0378] The effect of the heat treatment will be described with reference to FIG. 26. As shown in FIG. 26B, the oxygen added to the region 292 by the oxygen implantation process diffuses into the oxide 230b, the insulator 224, and the insulator 280 by the heat treatment. At the same time, as shown in FIG. 26C, the diffused oxygen is supplied to the oxygen vacancies Vo of the oxide film 230C and the oxide 230b by the heat treatment, and becomes a part of the oxide film 230C and the oxide 230b by filling the oxygen vacancies. On the other hand, the oxygen diffused into the insulator 224 and the insulator 280 remains in the insulator 224 and the insulator 280 as excess oxygen.

[0379] By reducing the defect levels or oxygen vacancies in the channel formation region, a highly reliable transistor with little fluctuation in electrical characteristics can be provided. In addition, the transistor can have normally-off characteristics.

[0380] On the other hand, when the transistor is operated in a state in which the metal oxide contains excess oxygen that exceeds an appropriate amount, the valence of the excess oxygen atoms changes, and the electrical characteristics of the transistor fluctuate, which may result in reduced reliability.

[0381] Therefore, by covering the channel formation region of the oxide 230b with the oxide 230a having barrier properties and the oxide 230d having barrier properties, it is possible to prevent excess oxygen contained in the insulator 224 from being excessively supplied to the oxide 230b.

[0382] Next, the insulating film 250A is formed (see FIGS. 24A to 24C). A heat treatment may be performed before the formation of the insulating film 250A. It is preferable to perform the heat treatment under reduced pressure and then continuously form the insulating film 250A without exposing it to the air. It is also preferable to perform the heat treatment in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230D can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230D can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0383] Next, the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 24A to 24C). The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by an ALD method, and the conductive film 260B is successively formed by a CVD method under reduced pressure without exposure to the atmosphere.

[0384] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the oxide 230d, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see Figures 25A to 25C).

[0385] The CMP process may remove a portion of the insulator 280, including the region 292. By removing the region, the amount of excess oxygen contained in the insulator 280 can be reduced.

[0386] By the above processing, the oxide 230c is arranged so as to cover the opening reaching the oxide 230b and the inner wall (side wall and bottom surface) of the groove of the oxide 230b. The insulator 250 is arranged so as to cover the opening and the inner wall of the groove through the oxide 230c. The conductor 260 is arranged so as to fill the opening and the groove through the oxide 230c and the insulator 250.

[0387] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0388] Next, the insulator 282 is formed over the oxide 230d, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0389] The insulator 282 is formed in an atmosphere that does not contain at least oxygen. For example, it is preferable to form the insulator 282 in an inert atmosphere of a rare gas, nitrogen, or the like. Specifically, the insulator 282 may be formed using a nitride such as silicon nitride.

[0390] When a film is formed in an atmosphere containing oxygen, oxygen may be added to the film formation surface. When oxygen is added to the insulator 280, the oxygen is likely to diffuse to the channel formation region through the oxide 230c. When excess oxygen diffuses to the channel formation region, it may cause degradation of the electrical characteristics of the transistor.

[0391] Next, the insulator 283 is formed on the insulator 282 .

[0392] Next, openings reaching the conductor 240 are formed in the insulators 271 , 280 , 282 , and 283 .

[0393] Next, an insulating film that will become the insulator 276 is formed, and the insulating film is anisotropically etched to form the insulator 276 (insulator 276a and insulator 276b).

[0394] Next, a conductive film to become the conductor 246a and the conductor 246b is formed. The conductive film to become the conductor 246a and the conductor 246b preferably has a layered structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.

[0395] Next, CMP processing is performed to remove parts of the conductive film that will become conductor 246a and conductor 246b, exposing the upper surfaces of insulator 283 and insulator 276. As a result, the conductive film remains only in the openings, forming conductors 246a and 246b with flat upper surfaces. Note that the CMP processing may remove parts of the upper surfaces of insulator 283 and insulator 276.

[0396] Next, a conductive film that will become the conductor 248 is formed.

[0397] Next, the conductive film that becomes the conductor 248 is processed by lithography to form the conductor 248a in contact with the top surface of the conductor 246a and the conductor 248b in contact with the top surface of the conductor 246b.

[0398] Next, an insulator 286 is deposited over the conductor 248 and the insulator 283 (see Figures 17A to 17C).

[0399] Through the above steps, a semiconductor device including the transistor 200 illustrated in FIGS. 17A to 17C can be manufactured.

[0400] <Modification 2 of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 27A to 27C.

[0401] Fig. 27A shows a top view of the semiconductor device. Fig. 27B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 27A. Fig. 27C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 27A. In the top view of Fig. 27A, some elements are omitted for clarity.

[0402] 27A to 27C, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Example 2 of Semiconductor Device> are denoted by the same reference numerals. Note that, in this section as well, the materials described in detail in <Configuration Example 2 of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0403] The semiconductor device shown in Figures 27A to 27C is a modified example of the semiconductor device shown in Figures 17A to 17C. The semiconductor device shown in Figures 27A to 27C differs from the semiconductor device shown in Figures 17A to 17C in the shapes of the insulator 214, the insulator 282, and the insulator 283. Also, the semiconductor device differs in that it has an insulator 284.

[0404] In the semiconductor device shown in FIG. 27A to FIG. 27C, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282 are patterned. The insulator 283 has a structure that covers the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282. That is, the insulator 283 contacts the upper surface and side surface of the insulator 282 and the upper surface of the insulator 212. As a result, the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 280, and the insulator 282, including the oxide 230, are isolated from the outside by the insulator 283 and the insulator 212. In other words, the transistor 200 is disposed in a region sealed by the insulator 283 and the insulator 212.

[0405] For example, it is preferable to form the insulator 214 using a material that has a function of capturing and fixing hydrogen, and to form the insulators 212, 282, and 283 using a material that has a function of suppressing the diffusion of hydrogen and oxygen. Typically, aluminum oxide can be used as the insulator 214. Typically, silicon nitride can be used as the insulators 212, 282, and 283.

[0406] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from entering the sealed region.

[0407] 27A to 27C show a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0408] The insulator 284 functions as an interlayer film. The insulator 284 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 284 can be provided using, for example, a material similar to that of the insulator 280.

[0409] <Application example 2 of semiconductor device> 28A and 28B, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those shown in the above <Structural Example 2 of Semiconductor Device> and the above <Variation 2 of Semiconductor Device>, will be described below. Note that in the semiconductor device shown in FIG. 28A and FIG. 28B, structures having the same functions as those of the semiconductor device shown in <Variation 2 of Semiconductor Device> (see FIG. 17A to FIG. 17C) are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural Example 2 of Semiconductor Device> and <Variation 2 of Semiconductor Device> can be used as the materials for forming the transistor 200.

[0410] 28A and 28B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 28A and 28B, this is not the only possible arrangement. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0411] 28A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Thus, a plurality of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0412] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0413] In addition, although Fig. 28A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this. As shown in Fig. 28B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 28B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0414] In this manner, by using a structure in which the multiple transistors 200_1 to 200_n are surrounded by multiple sealing portions, the number of areas in contact with the insulator 283 and the insulator 212 increases, thereby improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the multiple transistors 200_1 to 200_n.

[0415] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0416] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0417] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0418] (Embodiment 3) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0419] [Storage device 1] 29 and 30 show an example of a semiconductor device (memory device) according to one embodiment of the present invention. The semiconductor device according to one embodiment of the present invention includes a transistor 200, a transistor 300, and a capacitor 100. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0420] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0421] 29 and 30, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0422] Moreover, the memory devices shown in FIGS. 29 and 30 can be arranged in a matrix to form a memory cell array.

[0423] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0424] Here, in the transistor 300 shown in FIG. 29 and FIG. 30, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and upper surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0425] Note that the transistor 300 shown in FIGS. 29 and 30 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0426] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

[0427] For example, the conductor 112 and the conductor 110 over the conductor 246 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0428] 29 and 30 show a single-layer structure for the conductor 112 and the conductor 110, but the present invention is not limited to this configuration and may be a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0429] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0430] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0431] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0432] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0433] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0434] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0435] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0436] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 29 and Fig. 30, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Also, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0437] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0438] Here, similarly to the insulator 271 shown in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 211, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 211, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0439] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulators 211, 212, 214, and 222, it is possible to prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0440] The insulator 217 can be formed by a method similar to that of the insulator 271. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0441] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0442] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0443] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen has been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0444] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, and 350 can be made of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0445] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0446] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0447] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0448] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0449] 29 and 30, for example, an insulator 271 may be provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 246. By providing the insulator 271 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0450] In other words, the insulator 271 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 246. Furthermore, the insulator 271 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 246.

[0451] As the insulator 271, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, may be used. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0452] As in the above embodiment, the transistor 200 is preferably sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 284, 150, and the like into the insulator 280 and the like.

[0453] Here, the conductor 246 penetrates the insulator 283 and the insulator 282, and the conductor 218 penetrates the insulator 214, the insulator 212, and the insulator 211, but as described above, the insulator 271 is provided in contact with the conductor 246, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 212, 214, 282, and 283 through the conductor 246 and the conductor 218. In this way, the transistor 200 can be more reliably sealed with the insulators 212, 214, 282, 283, 271, and 217, and it is possible to reduce impurities such as hydrogen contained in the insulator 284, etc. from being mixed in from the outside.

[0454] Furthermore, the insulators 216, 224, 280, 250, and 284 are preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed, as described in the above embodiment, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 284.

[0455] In this manner, the hydrogen concentration in the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0456] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0457] 29 and 30, for example, it is preferable to design the area where the insulator 283 and the insulator 212 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 282, 280, 224, 222, 216, and 214 near the area that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0458] That is, the insulator 212 and the insulator 283 are in contact with each other through the openings provided in the insulators 282, 280, 224, 222, 216, and 214. The insulators 212 and 283 can be made of the same material and by the same method to improve adhesion. For example, it is preferable to use silicon nitride.

[0459] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0460] This structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0461] In the memory device shown in Figures 29 and 30, the shape of the capacitor 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Figures 31 and 32. In the memory device shown in Figure 32, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Figure 31.

[0462] 31 and 32 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0463] The conductor 115 functions as the lower electrode of the capacitance element 100, the conductor 125 functions as the upper electrode of the capacitance element 100, and the insulator 145 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface in the openings of the insulators 150 and 142, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0464] The insulator 152 may be made of an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be made of an insulator that can be used for the insulator 214.

[0465] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. With such a configuration, the occupation area of ​​a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0466] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably approximately coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be, for example, a conductor that can be used for the conductor 205.

[0467] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0468] Moreover, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0469] Examples of insulators made of high dielectric constant (high-k) materials (materials with high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 145 is made thick. By making the insulator 145 thick, the leakage current occurring between the conductor 115 and the conductor 125 can be suppressed.

[0470] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon nitride (SiN x ) in that order can be used. By using such an insulator having a high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0471] The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0472] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0473] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0474] (Embodiment 4) In this embodiment, an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0475] When manufacturing a semiconductor device according to one embodiment of the present invention, it is preferable to use a so-called multi-chamber apparatus having a plurality of treatment chambers in which different types of films can be successively formed. In each treatment chamber, a film formation process such as sputtering, CVD, or ALD can be performed. For example, when one treatment chamber is a sputtering chamber, a gas supply device, a gas purification device connected to the gas supply device, a vacuum pump, a target, and the like can be connected to the sputtering chamber.

[0476] In each treatment chamber, a cleaning treatment, a plasma treatment, a reverse sputtering treatment, an etching treatment, an ashing treatment, a heating treatment, etc. may be performed. By appropriately performing different treatments in each treatment chamber, an insulator, a conductor, and a semiconductor film can be formed without exposure to the atmosphere.

[0477] A typical example of a semiconductor film used in one embodiment of the present invention is an oxide semiconductor film. In particular, an oxide semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) can be used to manufacture a transistor with excellent electrical characteristics. Here, a semiconductor film having a low impurity concentration and a low density of defect states is referred to as a highly pure intrinsic film or a substantially highly pure intrinsic film.

[0478] A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film can have a low carrier density because there are few carrier generation sources. Therefore, a transistor in which a channel formation region is formed in the oxide semiconductor film rarely has electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low. In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has an extremely small off-state current and a channel width of 1×10 6 Even if the device has a channel length L of 10 μm and a width of 1 μm, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10-13 It is possible to obtain a characteristic of A or less.

[0479] Typical examples of impurities in an oxide semiconductor film include water and hydrogen. In this specification and the like, reducing or removing water and hydrogen from an oxide semiconductor film may be referred to as dehydration or dehydrogenation. Adding oxygen to an oxide semiconductor film may be referred to as oxygen addition, and a state in which oxygen is added and the oxide semiconductor film has more oxygen than the stoichiometric composition may be referred to as an excess oxygen state.

[0480] Here, by successively depositing different types of films, that is, an oxide semiconductor, an insulator or conductor located below the oxide semiconductor, and an insulator or conductor located above the oxide semiconductor, without exposure to the air, it is possible to form a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly hydrogen and water) is reduced.

[0481] First, a structural example of an apparatus that can be used for manufacturing a semiconductor device of one embodiment of the present invention will be described in detail with reference to Fig. 33. By using the apparatus shown in Fig. 33, a semiconductor film, an insulator or a conductor located under the semiconductor film, and an insulator or a conductor located over the semiconductor film can be successively formed. Therefore, impurities (particularly hydrogen and water) that may enter the semiconductor film can be suppressed.

[0482] FIG. 33 is a schematic top view of a single-wafer type multi-chamber apparatus 4000.

[0483] The apparatus 4000 has an atmosphere-side substrate supply chamber 4010, an atmosphere-side substrate transfer chamber 4012 for transferring substrates from the atmosphere-side substrate supply chamber 4010, a load lock chamber 4020a for transferring substrates and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 4020b for transferring substrates and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 4029 and a transfer chamber 4039 for transferring substrates in a vacuum, a transfer chamber 4030a and a transfer chamber 4030b connecting the transfer chamber 4029 and the transfer chamber 4039, and treatment chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e for performing film formation or heating.

[0484] The multiple processing chambers can each perform different processes in parallel. Therefore, a stacked structure of different film types can be easily fabricated. Parallel processing can be performed up to the number of processing chambers. For example, the apparatus 4000 shown in FIG. 33 has seven processing chambers. Therefore, seven film formation processes can be performed consecutively using one apparatus (also referred to as in-situ in this specification) without being exposed to the atmosphere.

[0485] On the other hand, in a laminated structure, the number of layers that can be produced without exposing to the atmosphere is not necessarily the same as the number of processing chambers. For example, if the desired laminated structure has multiple layers of the same material, the layers can be provided in one processing chamber, so that a laminated structure with a greater number of layers than the number of processing chambers installed can be produced.

[0486] The atmosphere side substrate supply chamber 4010 also includes a cassette port 4014 for accommodating substrates, and an alignment port 4016 for aligning the substrates. Note that a configuration may be provided with a plurality of cassette ports 4014 (for example, three in FIG. 33).

[0487] The atmosphere side substrate transfer chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4024a, and the processing chamber 4024b. The transfer chamber 4030a and the transfer chamber 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039. The transfer chamber 4039 is connected to the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.

[0488] A gate valve 4028 or a gate valve 4038 is provided at the connection between the chambers, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 4010 and the atmosphere side substrate transfer chamber 4012. The atmosphere side substrate transfer chamber 4012 has a transfer robot 4018. The transfer chamber 4029 has a transfer robot 4026, and the transfer chamber 4039 has a transfer robot 4036. The transfer robot 4018, the transfer robot 4026, and the transfer robot 4036 each have a plurality of movable parts and an arm that holds a substrate, and can transfer a substrate to each chamber.

[0489] The number of transfer chambers, processing chambers, load lock chambers, unload lock chambers and transport chambers is not limited to the above, and an optimum number can be provided depending on the installation space and process conditions.

[0490] In particular, when there are multiple transfer chambers, it is preferable to have two or more transfer chambers between one transfer chamber and another transfer chamber. For example, as shown in Fig. 33, when there are transfer chambers 4029 and 4039, it is preferable to arrange transfer chambers 4030a and 4030b in parallel between transfer chambers 4029 and 4039.

[0491] By arranging the transfer chamber 4030a and the transfer chamber 4030b in parallel, for example, a step in which the transfer robot 4026 carries a substrate into the transfer chamber 4030a and a step in which the transfer robot 4036 carries a substrate into the transfer chamber 4030b can be performed simultaneously. Also, a step in which the transfer robot 4026 carries a substrate out of the transfer chamber 4030b and a step in which the transfer robot 4036 carries a substrate out of the transfer chamber 4030a can be performed simultaneously. In other words, by driving multiple transfer robots simultaneously, production efficiency is improved.

[0492] 33 shows an example in which one transfer chamber has one transfer robot and is connected to multiple processes, but this is not limited to the structure. One transfer chamber may have multiple transfer robots.

[0493] In addition, one or both of the transfer chamber 4029 and the transfer chamber 4039 are connected to a vacuum pump and a cryopump via valves. Therefore, the transfer chamber 4029 and the transfer chamber 4039 are evacuated from atmospheric pressure to a low or medium vacuum (several hundred Pa to about 0.1 Pa) using a vacuum pump, and then the valve is switched and the cryopump is used to evacuate from the medium vacuum to a high or ultra-high vacuum (0.1 Pa to 1×10 -7 It is possible to evacuate to a pressure of approximately 10 Pa.

[0494] Also, for example, two or more cryopumps may be connected in parallel to one transfer chamber. By having multiple cryopumps, even if one cryopump is in regeneration, it is possible to use the other cryopumps to pump air. Note that regeneration is the process of releasing molecules (or atoms) that have accumulated in the cryopump. If a cryopump accumulates too many molecules (or atoms), its pumping capacity will decrease, so it is a good idea to regenerate it periodically.

[0495] The processing chambers 4024a, 4024b, 4034a, 4034b, 4034c, 4034d, and 4034e can each perform different processes in parallel. That is, in each processing chamber, a film formation process using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, a heat treatment, or a plasma treatment can be performed on a substrate placed therein. In addition, a film formation process may be performed in the processing chamber after a heat treatment or a plasma treatment is performed.

[0496] The apparatus 4000 has multiple processing chambers, and thus can transport the substrate between processing steps without exposing it to the atmosphere, thereby preventing impurities from being adsorbed on the substrate. In addition, since each processing chamber can perform a film formation process for different types of films, a heat treatment process, or a plasma treatment process, the order of film formation, heat treatment, etc. can be freely determined.

[0497] Each processing chamber may be connected to a vacuum pump via a valve. As the vacuum pump, for example, a dry pump, a mechanical booster pump, or the like can be used.

[0498] Each processing chamber may be connected to a power source capable of generating plasma. The power source may be a DC power source, an AC power source, or a high-frequency (RF, microwave, etc.) power source. A pulse generator may be connected to the DC power source.

[0499] The processing chamber may be connected to a gas purification device via a gas supply device. The gas supply devices and gas purification devices may be provided in the same number as the number of gas types.

[0500] For example, when a film formation process by sputtering is performed in a process chamber, the process chamber may include a target, a backing plate connected to the target, a cathode arranged facing the target via the backing plate, an adhesion prevention plate, a substrate stage, etc. Also, for example, the substrate stage may include a substrate holding mechanism for holding a substrate, a back surface heater for heating the substrate from the back surface, etc.

[0501] The substrate stage is held in a generally vertical position relative to the floor during film formation, and is held in a generally horizontal position relative to the floor during substrate transfer. By holding the substrate stage generally vertical to the floor, the probability that dust or particles that may be mixed in during film formation will adhere to the substrate can be reduced more than if the substrate stage were held horizontal. However, if the substrate stage is held vertical (90°) relative to the floor, there is a risk that the substrate will fall, so the angle of the substrate stage relative to the floor is preferably 80° or more and less than 90°.

[0502] The configuration of the substrate stage is not limited to the above. For example, the substrate stage may be configured to be approximately horizontal with respect to the floor surface. In this configuration, the target may be placed below the substrate stage, and the substrate may be placed between the target and the substrate stage. The substrate stage may also include a jig for fixing the substrate so that the substrate does not fall, or a mechanism for fixing the substrate.

[0503] Furthermore, by providing an adhesion prevention plate in the processing chamber, it is possible to prevent the particles sputtered from the target from accumulating in unnecessary areas. It is also desirable to process the adhesion prevention plate so that the accumulated sputtered particles do not peel off. For example, a blasting process may be performed to increase the surface roughness, or the surface of the adhesion prevention plate may be provided with irregularities.

[0504] The backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.

[0505] Note that the target may be a conductor, an insulator, or a semiconductor. For example, when the target is an oxide semiconductor such as a metal oxide, an oxide semiconductor film can be formed in the treatment chamber. Even when the target is a metal oxide, an oxynitride semiconductor film can be formed by using nitrogen gas as a film formation gas.

[0506] Each processing chamber may be connected to a gas supply device via a gas heating mechanism. The gas heating mechanism is connected to a gas purification device via a gas supply device. The gas introduced into the processing chamber may have a dew point of -80°C or less, preferably -100°C or less, and more preferably -120°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used. The gas heating mechanism may heat the gas introduced into the processing chamber to 40°C or more and 400°C or less, preferably 50°C or more and 200°C or less. The gas heating mechanism, gas supply device, and gas purification device may be provided in the same number as the number of gas types.

[0507] Each processing chamber may be connected to a turbo molecular pump and a vacuum pump via a valve, and each processing chamber may be provided with a cryotrap.

[0508] A cryotrap is a mechanism capable of adsorbing molecules (or atoms) with a relatively high melting point, such as water. A turbomolecular pump is excellent in productivity because it stably pumps large-sized molecules (or atoms) and requires little maintenance, but has a low pumping capacity for hydrogen and water. Therefore, a cryotrap can be used to improve the pumping capacity for water and the like. The temperature of the cryotrap refrigerator is 100K or less, preferably 80K or less. In addition, when a cryotrap has multiple refrigerators, it is preferable to change the temperature of each refrigerator, since this allows for efficient pumping. For example, the temperature of the first-stage refrigerator may be 100K or less, and the temperature of the second-stage refrigerator may be 20K or less.

[0509] The exhaust method of the processing chamber is not limited to this, and may be the same as the exhaust method of the connected transfer chamber (exhaust method of a cryopump and a vacuum pump). The exhaust method of the transfer chamber may be the same as the exhaust method of the processing chamber (exhaust method of a turbo molecular pump and a vacuum pump).

[0510] In particular, a combination of a vacuum pump and a cryotrap may be used as an exhaust means for the treatment chamber in which the oxide semiconductor film is formed. It is preferable that an exhaust means provided in the treatment chamber in which the oxide semiconductor film is formed has a function of adsorbing at least water molecules.

[0511] In addition, the partial pressure of hydrogen molecules in the treatment chamber for forming the oxide semiconductor film was 1×10 -2 Pa or less, and the partial pressure of water molecules is 1×10 -4 In addition, the pressure in the treatment chamber in which the oxide semiconductor film is formed in a standby state is preferably 8.0×10 Pa or less. -5 Pa or less, preferably 5.0×10 -5 Pa or less, more preferably 1.0×10 -5 The partial pressure of hydrogen molecules and the partial pressure of water molecules are values ​​when the processing chamber in which sputtering is performed is in a standby state and in a film forming state (plasma is in a discharging state) as described above.

[0512] The total pressure and partial pressure of the process chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0513] When the partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state in the treatment chamber are set to the above ranges, the impurity concentration in the oxide semiconductor film to be formed can be low.

[0514] In particular, by using each treatment chamber for a film formation process by sputtering, part of the configuration of the transistor 200 described in the above embodiment can be manufactured to have a stacked structure in which films are successively formed in situ.

[0515] In a method for manufacturing the transistor 200, the insulator 212, the insulator 214, and the insulator 216 are successively formed using an apparatus 4000. The oxide film 230A, the oxide film 230B, and the oxide film 243A are successively formed using the apparatus 4000. The conductive film 242A, the insulating film 271A, and the conductive film 248A are successively formed using the apparatus 4000.

[0516] That is, the insulator 212, the insulator 214, and the insulator 216 can be formed successively without exposure to the atmosphere. Also, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be formed successively without exposure to the atmosphere. Also, the conductive film 242A, the insulating film 271A, and the conductive film 248A can be formed successively without exposure to the atmosphere.

[0517] With the above-mentioned configuration, it is possible to form a laminated film from which impurities (typically, water, hydrogen, etc.) are thoroughly eliminated. In addition, since each interface of the laminated film is not exposed to the atmosphere, the impurity concentration is reduced.

[0518] Furthermore, for example, when heat treatment is performed in a treatment chamber, the treatment chamber may include a plurality of heating stages capable of storing substrates. The heating stages may be configured in multiple stages. By increasing the number of heating stages, a plurality of substrates can be simultaneously heat-treated, thereby improving productivity.

[0519] The heating mechanism that can be used in the processing chamber may be, for example, a heating mechanism that uses a resistance heating element for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTAs (Rapid Thermal Anneals) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTAs heat the workpiece by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. GRTAs perform heat treatment using high-temperature gas. An inert gas is used as the gas.

[0520] The load lock chamber 4020a may include a substrate transfer stage, a backside heater for heating the substrate from the backside, etc. The load lock chamber 4020a increases the pressure from a reduced pressure state to the atmosphere, and when the pressure in the load lock chamber 4020a reaches atmospheric pressure, the substrate transfer stage receives the substrate from the transfer robot 4018 provided in the atmosphere side substrate transfer chamber 4012. Thereafter, the load lock chamber 4020a is evacuated to a reduced pressure state, and then the transfer robot 4026 provided in the transfer chamber 4029 receives the substrate from the substrate transfer stage.

[0521] The load lock chamber 4020a is connected to a vacuum pump and a cryopump via valves. The unload lock chamber 4020b may have the same configuration as the load lock chamber 4020a.

[0522] The atmosphere side substrate transfer chamber 4012 has a transfer robot 4018, so that the transfer robot 4018 can transfer substrates between the cassette port 4014 and the load lock chamber 4020a. A mechanism for suppressing the intrusion of dust or particles, such as a HEPA filter (High Efficiency Particulate Air Filter), may be provided above the atmosphere side substrate transfer chamber 4012 and the atmosphere side substrate supply chamber 4010. The cassette port 4014 can store a plurality of substrates.

[0523] By using the above-described apparatus 4000 to successively form an insulating film, a semiconductor film, and a conductive film without exposure to the atmosphere, it is possible to suitably suppress the intrusion of impurities into the semiconductor film.

[0524] As described above, by using the apparatus according to one embodiment of the present invention, a stacked structure including a semiconductor film can be manufactured by successive film formation. Therefore, impurities such as hydrogen and water that are taken into the semiconductor film can be suppressed, and a semiconductor film with a low density of defect states can be manufactured.

[0525] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0526] (Embodiment 5) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter may be referred to as an OS transistor) and a memory device including a capacitor (hereinafter may be referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 34A, 34B, and 35A to 35H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0527] <Storage device configuration example> 34A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0528] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0529] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0530] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0531] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0532] 34A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 34B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0533] 35A to 35H will be used to explain examples of the configuration of a memory cell that can be applied to the above-mentioned memory cell MC.

[0534] [DOSRAM] 35A to 35C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 35A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0535] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring CAL.

[0536] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0537] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 35B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 35C.

[0538] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0539] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0540] [NOSRAM] 35D to 35G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 35D has a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply called a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be called a nonvolatile oxide semiconductor RAM (NOSRAM).

[0541] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0542] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while holding data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0543] Here, the memory cell 1474 shown in Fig. 35D corresponds to the memory device shown in Fig. 37. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0544] Moreover, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 35E. For example, the memory cell MC may be configured such that the transistor M2 has a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 35F. For example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 35G.

[0545] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very small. As a result, written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is very small, multi-level data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0546] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. By using a Si transistor as the transistor M3, the transistor M2 can be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0547] In addition, the transistor M3 may be an OS transistor. When the transistors M2 and M3 are OS transistors, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0548] FIG. 35H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 35H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

[0549] The transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. The backgate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have to have a backgate.

[0550] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0551] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0552] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary.

[0553] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 36 shows various storage devices by hierarchy. The higher the storage device, the faster the access speed is required, while the lower the storage device, the larger the storage capacity and the higher the recording density are required. Figure 36 shows, from the top layer, memories embedded as registers in arithmetic processing devices such as CPUs, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), and 3D NAND memories.

[0554] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0555] SRAM is used, for example, in caches. A cache has the function of storing a copy of some of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0556] DRAM is used, for example, as a main memory. The main memory has a function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 It is.

[0557] 3D NAND memory is used, for example, in storage. Storage has the function of holding data that needs to be stored for a long time and various programs used in processing units. Therefore, storage requires a larger memory capacity and a higher recording density than the operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 It is.

[0558] The storage device of one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device of one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 including both a hierarchical level where a cache is located and a hierarchical level where a main memory is located. The storage device of one embodiment of the present invention can be suitably used as a storage device located in a boundary area 902 including both a hierarchical level where a main memory is located and a hierarchical level where a storage is located.

[0559] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0560] (Embodiment 6) In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to Figures 37A and 37B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0561] As shown in FIG. 37A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0562] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 37B. In addition, a plurality of bumps 1202 are provided on the back side of the first surface of PCB 1201 and are connected to a motherboard 1203.

[0563] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be the DOSRAM described in the above embodiment. For example, the flash memory 1222 may be the NOSRAM described in the above embodiment.

[0564] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing and multiplication and accumulation. By providing the GPU 1212 with an image processing circuit or a multiplication and accumulation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiplication and accumulation with low power consumption.

[0565] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0566] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0567] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0568] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0569] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0570] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0571] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be referred to as a GPU module 1204.

[0572] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0573] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or examples.

[0574] (Embodiment 7) This embodiment mode describes an example of an electronic component or electronic device in which the memory device or the like described in the above embodiment mode is incorporated.

[0575] <Electronic components> First, an example of an electronic component incorporating a memory device 720 will be described with reference to FIGS. 38A and 38B.

[0576] Fig. 38A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in Fig. 38A has memory device 720 in mold 711. Part of electronic component 700 is omitted in Fig. 38A to show the inside of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0577] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0578] 38B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 720 provided on interposer 731.

[0579] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). Also, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0580] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0581] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0582] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0583] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0584] In addition, in SiPs and MCMs that use silicon interposers, reliability is less likely to decrease due to differences in the expansion coefficient between the integrated circuit and the interposer. In addition, because the surface of the silicon interposer is highly flat, connection defects are less likely to occur between the integrated circuit mounted on the silicon interposer and the silicon interposer. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0585] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0586] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 38B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0587] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as Staggered Pin Grid Array (SPGA), Land Grid Array (LGA), Quad Flat Package (QFP), Quad Flat J-leaded package (QFJ), and Quad Flat Non-leaded package (QFN).

[0588] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0589] (Embodiment 8) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording and reproducing devices, navigation systems, and the like). Note that the computer here includes a large computer such as a server system, in addition to tablet computers, notebook computers, and desktop computers. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). FIGS. 39A to 39E are schematic diagrams showing some configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0590] 39A is a schematic diagram of a USB memory. A USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like.

[0591] FIG. 39B is a schematic diagram of the appearance of an SD card, and FIG. 39C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0592] FIG. 39D is a schematic diagram of the appearance of an SSD, and FIG. 39E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0593] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes or examples.

[0594] (Embodiment 9) A semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIG.

[0595] <Electronic equipment and systems> The GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, and audio playback devices. Moreover, by providing the GPU or chip according to one embodiment of the present invention in an electronic device, it is possible to mount artificial intelligence on the electronic device.

[0596] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0597] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0598] An electronic device according to one embodiment of the present invention can have various functions. For example, the electronic device can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc. Examples of electronic devices are shown in Fig. 40A to Fig. 40H.

[0599] [Information terminal] 40A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0600] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5102 and displays them on the display unit 5102, and an application that performs biometric authentication such as fingerprints and voiceprints.

[0601] 40B illustrates a notebook type information terminal 5200. The notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0602] The notebook type information terminal 5200 can execute an application using artificial intelligence by applying a chip according to one embodiment of the present invention, similar to the above-described information terminal 5100. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. In addition, the notebook type information terminal 5200 can be used to develop new artificial intelligence.

[0603] In the above description, a smartphone and a notebook type information terminal are illustrated in Fig. 40A and Fig. 40B as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0604] [Game consoles] FIG. 40C illustrates a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. When the connection unit 5305 of the housing 5301 is attached to another housing (not shown), a video displayed on the display unit 5304 can be displayed on another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows a plurality of players to play a game at the same time. The chips described in the above embodiments can be incorporated in the chips provided on the substrates of the housings 5301, 5302, and 5303.

[0605] 40D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0606] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0607] Furthermore, by applying a GPU or a chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0608] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5300, it becomes possible to express things that are not limited to the program of the game. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0609] In addition, when playing a game on the portable game console 5300 that requires multiple players, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0610] 40C and 40D show a portable game machine and a stationary game machine as examples of game machines, but the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0611] [Mainframe computers] The GPU or chip of one embodiment of the present invention can be applied to a large computer.

[0612] 40E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 40F is a diagram showing a rack-mounted calculator 5502 included in the supercomputer 5500.

[0613] A supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the board.

[0614] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. In scientific and technological calculations, huge amounts of calculations need to be processed at high speed, and therefore power consumption is high and chips generate a lot of heat. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0615] 40E and 40F show a supercomputer as an example of a large computer, but the large computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of large computers to which the GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).

[0616] [Mobile object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0617] Fig. 40G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body, Fig. 40G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0618] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a...

Claims

1. depositing a first insulator; forming an island-shaped laminate on the first insulator by sequentially laminating a first oxide, a second oxide, and a first conductor; forming a second insulator on the first insulator and the stack; forming a third insulator on the second insulator; forming openings in the second insulator and the third insulator to expose the stack; removing a region of the first conductor exposed in the opening to expose an upper surface of the second oxide and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process; forming a first oxide film in contact with the side surface of the first oxide and the upper surface and side surface of the second oxide exposed in the opening; performing a process of adding oxygen through the first oxide film to the vicinity of the interface between the second oxide film and the first oxide film, and then performing a heat treatment; A method for manufacturing a semiconductor device, comprising: forming a first insulating film and a first conductive film on the first oxide film; and then removing parts of the first conductive film, the first insulating film, the first oxide film, the second insulator, and the third insulator by a chemical polishing process to expose the third insulator; and forming a fourth conductor, a fourth insulator, and a third oxide in the opening provided in the third insulator.

2. depositing a first insulator; forming an island-shaped laminate on the first insulator by sequentially laminating a first oxide, a second oxide, and a first conductor; forming a second insulator on the first insulator and the laminate; forming a third insulator on the second insulator; forming openings in the second insulator and the third insulator to expose the stack; removing a region of the first conductor exposed in the opening to expose an upper surface of the second oxide and forming a second conductor and a third conductor disposed on the second oxide, and then performing a cleaning process; forming a first oxide film in contact with a side surface of the first oxide and an upper surface and a side surface of the second oxide exposed in the opening; performing a process of adding oxygen through the first oxide film to the vicinity of the interface between the second oxide film and the first oxide film, and then performing a heat treatment; forming a first insulating film and a first conductive film on the first oxide film, and then removing a portion of the first conductive film, the first insulating film, the first oxide film, the second insulator, and the third insulator by a chemical polishing process to expose the third insulator, and forming a fourth conductor, a fourth insulator, and a third oxide in the opening provided in the third insulator; The method for manufacturing a semiconductor device, wherein the first oxide is an indium oxide.

3. In claim 1 or 2, The oxygen addition process is a method for manufacturing a semiconductor device using an ion implantation method.

4. In claim 3, In the ion implantation method, oxygen ions are incident in a short side direction of the second oxide at an angle θ (45°<θ<135°) with respect to a tangent to an upper surface of the second oxide.

5. In any one of claims 1 to 4, The heat treatment is performed at a temperature of 350° C. or higher and 400° C. or lower.

6. In any one of claims 1 to 5, The method for manufacturing a semiconductor device, wherein the heat treatment is performed in an atmosphere containing an oxidizing gas at 1% or more, or 10% or more.

7. In any one of claims 1 to 6, A method for manufacturing a semiconductor device, wherein the first oxide and the third oxide suppress oxygen diffusion more than the second oxide.

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