Delay based comparator

Abstract

To provide a high-speed latching comparator and a delay circuit.SOLUTION: In an analog-to-digital converter (ADC), a comparator 104 includes a pair of back-to-back negative-AND (NAND) gates 254 / 260 / 264 and 256 / 262 / 266 and delay circuits 202 and 204 coupled to the pair of back-to-back NAND gates 254 / 260 / 264 and 256 / 262 / 266. The delay circuits are configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates 254 / 260 / 264 and 256 / 262 / 266 is configured to receive a delayed clock signal 226a or 226b and generate a comparator output signal on the basis of the delayed clock signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] Analog comparators are relatively common electronic circuits used in a wide variety of applications to compare the amplitudes of two signals. A latched comparator is a type of comparator that uses positive feedback to maintain the output state of the comparator. For example, a latched comparator's output state change may be triggered by a transition or state of a clock signal. After the output state change, the comparator's output state is maintained by the positive feedback, and the remainder of the comparator circuitry may operate at a reduced power level. Latched comparators are often used in event-driven or power-sensing applications, such as analog-to-digital converters (ADCs). Summary of the Invention

[0002] In accordance with at least one embodiment of the present description, a comparator includes a pair of back-to-back NAND gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a trigger clock signal with an input voltage to generate a delayed clock signal having a delay based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.

[0003] Another aspect of the present disclosure is a delay circuit including a first inverter, a second inverter, and a pair of cross-coupled capacitors. The first inverter is coupled to a first transistor and a second transistor. The first inverter is configured to receive a first intermediate delayed clock signal and generate a positive delayed clock signal to be received by a first NAND gate of a comparator. The second inverter is coupled to a third transistor and a fourth transistor. The second inverter is configured to receive a second intermediate delayed clock signal and generate a negative delayed clock signal to be received by a second NAND gate of a comparator. The pair of cross-coupled capacitors is coupled to the first and second inverters.

[0004] Yet another aspect of the present disclosure is a comparator including a differential input pair of transistors and a delay circuit. The differential input pair of transistors includes a first input transistor and a second input transistor. The delay circuit includes a first inverter, a second inverter, and a pair of cross-coupled capacitors. The first inverter is coupled to the first transistor and the second transistor. The first inverter is configured to receive the first intermediate delayed clock signal and generate a positive delayed clock signal to be received by the first input transistor. The second inverter is coupled to the third transistor and the fourth transistor. The second inverter is configured to receive the second intermediate delayed clock signal and generate a negative delayed clock signal to be received by the second input transistor. The pair of cross-coupled capacitors is coupled to the first and second inverters. [Brief description of the drawings]

[0005] [Figure 1] 1 illustrates an example block diagram of an ADC in accordance with various examples.

[0006] [Diagram 2] 1 illustrates an example circuit diagram of a comparator in accordance with various examples.

[0007] [Diagram 3] 4 illustrates an example circuit diagram for a comparator delay circuit in accordance with various examples.

[0008] [Figure 4A] 4 illustrates an example timing diagram of various signals in a comparator delay circuit in accordance with various examples.

[0009] [Figure 4B] 4 illustrates an example timing diagram of various signals in a comparator delay circuit in accordance with various examples.

[0010] [Diagram 5] 1 illustrates an example block diagram of a flash ADC comparison circuit in accordance with various examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In this description, the term "coupled" means either an indirect or direct connection. Thus, if a first device couples to a second device, the connection may be through a direct connection or through an indirect connection via connections with other devices. Also, in this description, "based on" means "based at least in part on." Thus, if X is based on Y, X may be based on Y and any number of other factors.

[0012] ADCs are used to convert analog signals into digital representations of the same signal. ADCs are used in a wide range of applications ranging from medicine and entertainment to communications (both voice and data). One key design block of any ADC is the comparator. A comparator generates a digital output signal based on the comparison of an analog input signal with a reference voltage.

[0013] For example, in a SAR ADC, a comparator compares the sampled analog input signal with the analog output of an internal DAC and outputs a digital output signal to a SAR circuit that generates a digital code of the analog input signal voltage fed to the DAC. The SAR circuit is initialized with its most significant bit (MSB) equal to a digital 1. This digital code is output to the DAC, which converts the digital code to its analog equivalent based on a reference signal. The analog output of the DAC is received by the comparator. If the analog input signal has a voltage greater than the voltage of the analog output of the DAC, the comparator outputs a HIGH signal (so the SAR keeps the MSB at 1). However, if the analog signal has a voltage less than the voltage of the analog output of the DAC, the comparator outputs a LOW signal (so the SAR resets with the MSB at 0). Each bit of the SAR is tested in a similar manner against the analog input signal by the comparator until each bit is set. The resulting code is output as a digital output signal representative of the analog input signal. Comparators are equally important in sigma-delta modulated ADCs, flash ADCs, high-speed radio frequency (RF) sampling converters, and more.

[0014] Since the comparator is essential to the ADC, the speed of the comparator affects the overall speed of the ADC. In other words, by increasing the speed of the comparator, the speed of the ADC can also be increased. Conventional high-speed ADCs include a comparator that requires input information (e.g., an analog input signal and a reference signal) before the comparator provides a valid decision (e.g., generates an output signal). In 65 nm technology, the time for the comparator to make a decision is usually greater than 100 μs. Therefore, ADCs using conventional comparators typically require an amplifier driving the comparator to hold the input for at least 100 μs. In other words, conventional systems require an amplifier driving the comparator to hold the input signal for a relatively long period of time. Therefore, the operation of the ADC is slowed. Also, because the input signal is held for a relatively long period of time, timing complexity is introduced into these conventional systems.

[0015] According to various embodiments, a relatively high speed latched comparator is provided. Such a comparator includes, in various examples, a voltage controlled delay circuit that converts input voltage information into time information. The input clock (LATP) of the comparator is delayed by the delay circuit in proportion to the input voltage. Thus, the delayed input signal (which may include a pair of differential delayed input signals (INPD and INMD)) contains the input information (e.g., input voltage) in the time domain. Depending on whether the signal INPD or INMD arrives at the latch first, the latch is triggered, allowing the comparator to generate an output signal. For such a comparator, the delay generated by the delay circuit is relatively small (e.g., about 25 μs). Also, the behavior of the input voltage (e.g., a change in the input voltage) after the signals INPD and INMD are generated does not affect the decision of the comparator (e.g., does not affect the output signal). Thus, the input information is not needed when the comparator is making a decision. In this way, the speed of the comparator is increased and the timing complexity is reduced. Also, the input information is not corrupted during processing.

[0016] 1 illustrates an example block diagram of an ADC 100 in accordance with various examples. The ADC 100, in one embodiment, includes a comparison circuit 102, a DAC 110, and a summing circuit 106. The summing circuit 106 is configured to receive an analog input signal 122 (e.g., a time-varying analog voltage) and an analog feedback signal 134, which is an analog version of the comparison circuit output signal 130. The summing circuit 106 is further configured to sum the analog input signal 122 and the analog feedback signal 134 to generate a summed analog signal 126.

[0017] The comparison circuit 102 includes at least one comparator 104. For example, the comparator 104 may be configured to compare the summed analog input signal 126 with the reference signal 124 and generate a digital comparison circuit output signal 130. So, for example, if the summed analog input signal 126 corresponding to the analog input signal 122 has a voltage greater than the voltage of the reference signal 124, the comparator 104 outputs a HIGH signal as the digital comparison circuit output signal 130, but if the summed analog input signal 126 has a voltage less than the voltage of the reference signal 124, the comparator 104 outputs a LOW signal as the digital comparison circuit output signal 130. The DAC 110 receives the digital comparison circuit output signal 130 and generates an analog version of the digital comparison circuit output signal 130 as the analog feedback signal 134.

[0018] As mentioned above, the comparator 104 may be one of multiple comparators in the comparison circuit 102. So, for example, the comparison circuit 102 may include multiple comparators that generate individual bits of the digital comparison circuit output signal 130.

[0019] 2 illustrates an exemplary circuit diagram of the comparator 104 according to various examples. The comparator 104 includes, in one example, a pair of back-to-back NAND gates (NANDs) configured with a differential input pair of transistors 260-262 and regeneration transistors 254-256 and 264-266. For example, one NAND gate may include transistors 254, 260, and 264, while a second NAND gate may include transistors 256, 262, and 266. The comparator 104 also includes timing transistors 252 and 258 configured to receive the trigger clock signal LATP and delay elements 202-204. The delay elements 202-204 are coupled to the back-to-back NAND gates and configured to modulate the trigger clock signal LATP with an input voltage to generate a delayed clock signal having a delay based on the input voltage. For example, the input voltage received by the comparator 104 can be a differential signal composed of a positive input signal (INP) 222a and a negative input signal (INM) 222b. More specifically, the delay element 202 is configured to receive the INP 222a, and the delay element 204 is configured to receive the INM 222b. In addition, the delay elements 202-204 are configured to receive a reference signal, which in one example is a differential signal composed of a positive reference signal (REFP) 224a and a negative reference signal (REFP) 224b. More specifically, the delay element 202 is configured to receive the REFM 224b, and the delay element 204 is configured to receive the REFP 224a. In some examples, the reference signals REFP 224a and REFM 224b are set such that the threshold of the comparator 104 is equal to the voltage of REFP 224a minus the voltage of REFM 224b.

[0020] The delay element 202 is configured to generate a positive delayed clock signal (INPD) 226a whose delay is proportional to the voltage level of INP 222a. In other words, the input transistor 260 receives a delayed version of the trigger clock signal LATP, whose delay is proportional to INP 222a. The delay element 204 is configured to generate a negative delayed clock signal (INMD) 226b whose delay is proportional to the voltage level of INM 222b. In other words, the input transistor 262 receives a delayed version of the trigger clock signal LATP, whose delay is proportional to INM 222b. In this way, the delay of the delayed clock signal is proportional to the input voltage. In other words, the input voltage signal is converted into time information before being processed by the back-to-back NAND gates.

[0021] FIG. 3 illustrates an example circuit diagram for a delay circuit 300 of the comparator 104, according to various examples. The delay circuit 300 may include the delay elements 202-204 shown in FIG. 2. The delay circuit 300 includes, in one example, transistors 302-318, inverters 322-324, and a pair of cross-coupled capacitors including capacitors 326-328. In some examples, the transistors 302-312 are n-channel metal oxide semiconductor field effect (n-MOS) transistors. However, in other examples, the transistors 302-312 can be p-channel metal oxide semiconductor field effect (PMOS) transistors, bipolar junction transistors (BJT), or any combination thereof (e.g., a combination of NMOS and PMOS transistors). The transistors 314-318 are PMOS transistors in one example. However, transistors 314-318 may be NMOS transistors, BJTs, or any combination thereof (eg, a combination of NMOS and PMOS transistors).

[0022] The transistors 302-304 are configured to receive a trigger clock signal LATP, which is provided to the transistors 306-312. More specifically, the transistors 306-308 are in parallel with each other, and the transistors 310-312 are in parallel with each other. The transistor 306 is configured to receive at its gate INP222a. The resistance of the transistor 306 is therefore proportional to the voltage level of the input 222a. The transistor 308 is configured to receive at its gate REFM224b. The resistance of the transistor 308 is therefore proportional to the voltage level of REFM224b. The transistor 310 is configured to receive at its gate INM222b. The resistance of the transistor 310 is therefore proportional to the voltage level of INM222b. The transistor 312 is configured to receive at its gate REFP224a. The resistance of the transistor 312 is therefore proportional to the voltage level of REFP224a.

[0023] For example, the parallel transistors 306-308 receive the trigger clock signal LATP and generate an intermediate delayed clock signal 352a (a delayed version of the LATP) based on the resistance of the parallel transistors 306-308 (and thus based on the voltage levels of INP 222a and REFM 224b). Thus, if the resistance of the parallel transistors 306-308 is relatively large, the delay in the LATP will be relatively large in the resulting intermediate delayed clock signal 352a. However, if the resistance of the parallel transistors 306-308 is relatively small, the delay in the LATP will be relatively small in the resulting intermediate delayed clock signal 352a. Thus, the resistance of the parallel transistors 306-308 (caused by the voltage levels of INP 222a and REFM 224b) determines the delay in the intermediate delayed clock signal 352a, and therefore in the INPD 226a.

[0024] Similarly, the parallel transistors 310-312 receive the trigger clock signal LATP and generate an intermediate delayed clock signal 352b (a delayed version of LATP) based on the resistance of the parallel transistors 310-312 (and therefore based on the voltage levels of INM 222b and REFP 224a). Thus, if the resistance of the parallel transistors 310-312 is relatively large, the delay in the LATP will be relatively large in the resulting intermediate delayed clock signal 352b. However, if the resistance of the parallel transistors 310-312 is relatively small, the delay in the LATP will be relatively small in the resulting intermediate delayed clock signal 352b. In this manner, the resistance of the parallel transistors 310-312 (caused by the voltage levels of INM 222b and REFP 224a) determines the delay in the intermediate delayed clock signal 352b, and therefore in INMD 226b.

[0025] The delay difference between the intermediate delayed clock signal 352a and the intermediate delayed clock signal 352b can be relatively small, and therefore, a cross-coupled capacitor pair including capacitors 326-328 is included in some examples to provide more resolution in the delay difference between INPD2 26a and INMD2 26b. For example, inverter 322 is configured in one example to receive intermediate delayed clock signal 352a from parallel transistors 306-308 and invert intermediate delayed clock signal 352a to generate INPD2 26a. Similarly, inverter 324 is configured in one example to receive intermediate delayed clock signal 352b from parallel transistors 310-312 and invert intermediate delayed clock signal 352b to generate INMD2 26b. Because capacitors 326-328 are in a cross-coupled configuration, if INPD2 26a transitions HIGH before INMD2 26b transitions HIGH, the transition of INMD2 26b to HIGH is delayed. Similarly, if INMD 226b transitions HIGH before INPD 226a transitions HIGH, the transition of INPD 226a to HIGH is delayed. Higher resolution in the delay difference between INPD 226a and INMD 226b allows the comparator 104 to provide accurate decisions as its output signal.

[0026] In one embodiment for generating a high resolution differential delay between INPD226a and INMD226b, the drains of transistors 306-308 are connected to an input terminal of inverter 322 and a first terminal of capacitor 326. Thus, a first terminal of capacitor 326 is connected to an input terminal of inverter 322. The drains of transistors 310-312 are connected to an input terminal of inverter 324 and a first terminal of capacitor 328. Thus, a first terminal of capacitor 328 is connected to an input terminal of inverter 324. A second terminal of capacitor 326 is connected to an output terminal of inverter 324 and thus, connected to INMD226b. A second terminal of capacitor 328 is connected to an output terminal of inverter 322 and thus, connected to INPD226a.

[0027] 4A illustrates an example timing diagram 400 of the LATP, INPD 226a, and INMD 226b in the delay circuit 300 of the comparator 104, according to various examples. More specifically, the timing diagram 400 illustrates the timing of the signals LATP, INPD 226a, and INMD 226b when the voltage of INP 222a minus the voltage of INM 222b is greater than the voltage of REFP 224a minus the voltage of REFM 224b (i.e., (INP-INM)>(REFP-REFM)). Thus, as illustrated in FIG. 4A, when (INP-INM)>(REFP-REFM), INPD 226a triggers before INMD 226b triggers.

[0028] 4B illustrates an example timing diagram 450 of LATP, INPD 226a, and INMD 226b in the delay circuit 300 of the comparator 104, according to various examples. More specifically, the timing diagram 450 illustrates the timing of the signals LATP, INPD 226a, and INMD 226b when the voltage of INP 222a minus the voltage of INM 222b is less than the voltage of REFP 224a minus the voltage of REFM 224b (i.e., (INP-INM)<(REFP-REFM)). Thus, as shown in FIG. 4B, when (INP-INM)<(REFP-REFM), INMD 226b triggers before INPD 226a triggers.

[0029] 5 illustrates an example block diagram of a flash ADC comparison circuit 102 in accordance with various examples. The example comparison circuit 102 includes, in one example, delay circuits 300, 500, and 550, first level comparators 502-504 and 554, interpolating comparators 506-518, and dummy comparators 520-528 and 556-558. The comparators 502-528 and 554-556 are, in one example, similar to the comparator 104 from FIG. 2 without the delay elements 202-204. The delay circuits 500 and 550 are, in one example, similar to the delay circuit 300, except for one or more different input signals. For example, delay circuit 300 receives INP222a, INM222b, REFP224a, and REFM224b, delay circuit 500 receives a different reference signal (e.g., REFP574a and REFM574b) in addition to INP222a and INM222b, and delay circuit 550 receives trigger clock signal LATP-IN as its only input.

[0030] The comparators 554-558 are configured to generate trigger clock signals for successive levels of comparators, each level being delayed from the previous level. For example, the clock signal LATP_IN is used as a trigger clock signal for the comparators 502-504 of the first level, LATP1 is used as a trigger clock signal for the second level of comparators including the interpolating comparator 506 and the dummy comparators 520-522, the trigger clock signal LATP2 is used as a trigger clock signal for the third level of comparators including the interpolating comparators 508-510 and the dummy comparators 524-528, and the trigger clock signal LATP3 is used as a trigger clock signal for the fourth level of comparators including the interpolating comparators 512-518.

[0031] The first level comparator 502 compares the positive delayed clock signal generated by the delay circuit 500 with the negative delayed clock signal generated by the delay circuit 500 and generates a differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). Similarly, the first level comparator 504 compares the positive delayed clock signal generated by the delay circuit 300 with the negative delayed clock signal generated by the delay circuit 300 and generates a differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). The interpolating comparator 506 receives the negative comparator output signal from the comparator 504 and the positive comparator output signal from the comparator 502 and generates a second level differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal). Dummy comparators 520-522 are utilized to match the timing difference generated by the interpolating comparator 506 for the third level of comparators.

[0032] The third level of comparators functions similarly to the second level of comparators, except that there are now two interpolating comparators (e.g., interpolating comparators 508-510). For example, the interpolating comparator 508 receives the negative comparator output signal from the interpolating comparator 506 and the positive comparator output signal from the dummy comparator 522, and generates a third level of differential comparator output signals (e.g., a positive comparator output signal and a negative comparator output signal). The interpolating comparator 510 receives the positive comparator output signal from the interpolating comparator 506 and the negative comparator output signal from the dummy comparator 520, and generates a third level of differential comparator output signals (e.g., a positive comparator output signal and a negative comparator output signal). The dummy comparators 524-528 are utilized to match the timing difference generated by the interpolating comparators 508-510 to the fourth level of comparators.

[0033] The fourth level of comparators functions similarly to the second level of comparators and the third level of comparators, except that there are now four interpolating comparators (e.g., interpolating comparators 512-518). For example, the interpolating comparator 512 receives the negative comparator output signal from the dummy comparator 524 and the positive comparator output signal from the interpolating comparator 510, and generates a single-bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that constitutes a single bit of the comparison circuit 102 output signal 130. The interpolating comparator 514 receives the negative comparator output signal from the interpolating comparator 510 and the positive comparator output signal from the dummy comparator 526, and generates a single-bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that constitutes a single bit of the comparison circuit 102 output signal 130. The interpolating comparator 516 receives the negative comparator output signal from the dummy comparator 526 and the positive comparator output signal from the interpolating comparator 508, and generates a single-bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that constitutes a single bit of the comparison circuit 102 output signal 130. The interpolating comparator 518 receives the negative comparator output signal from the interpolating comparator 508 and the positive comparator output signal from the dummy comparator 528, and generates a single-bit differential comparator output signal (e.g., a positive comparator output signal and a negative comparator output signal) that constitutes a single bit of the comparison circuit 102 output signal 130.

[0034] Therefore, the input information (INP222a, INM222b, REFP224a, REFP224b, REFP574a, and REFM574b) is only needed for the duration of the delay elements of the delay circuits 300 and 500 to modulate the input trigger clock LATP_IN. The entire conversion can continue in asynchronous operation, so that only one input trigger clock is needed. Also, when the last level of comparators (e.g., the fourth level of comparators) is in the decision phase, the first level of comparators can start processing the next input sample. Also, since each level of interpolation provides a gain for the next level of comparators, not all comparators need to be designed for noise.

[0035] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A comparator comprising: A pair of back-to-back negative AND (NAND) gates; a delay circuit coupled to the pair of back-to-back NAND gates; Including, the delay circuit is configured to modulate a trigger clock signal with an input voltage to generate a delayed clock signal with a delay based on the input voltage; a comparator, each of the back-to-back NAND gates configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal;

2. 2. A comparator as claimed in claim 1, A comparator, wherein the delay of the delayed clock signal is proportional to the input voltage.

3. 2. A comparator as claimed in claim 1, A comparator, wherein the input voltage is a differential signal including a positive input signal and a negative input signal.

4. 4. A comparator according to claim 3, The delay circuit further comprises a comparator configured to receive a differential reference signal including a positive reference signal and a negative reference signal.

5. 5. A comparator according to claim 4, The delay circuit is a first transistor configured to receive the positive input signal; a second transistor in parallel with the first transistor, the second transistor configured to receive the negative reference signal; a third transistor configured to receive the negative input signal; and a fourth transistor in parallel with the third transistor, the fourth transistor configured to receive the positive reference signal; Including, a comparator.

6. 6. A comparator according to claim 5, the delays of the delayed clock signals include a positive delayed clock signal and a negative delayed clock signal; a resistance of the first transistor in parallel with the second transistor determines a delay of the positive delayed clock signal; A comparator, the resistance of a third transistor in parallel with the fourth transistor determining the delay of the negative delayed clock signal.

7. 7. A comparator according to claim 6, a resistance of the first transistor proportional to the voltage level of the positive input signal, a resistance of the second transistor proportional to the voltage level of the negative reference signal, a resistance of the third transistor proportional to the voltage level of the negative input signal, and a resistance of the fourth transistor proportional to the voltage level of the positive reference signal.

8. 7. A comparator according to claim 6, The delay circuit is a first inverter configured to receive a first intermediate delayed clock signal from the first transistor and the second transistor; a second intermediate delayed clock signal from the third transistor and the fourth transistor; a second inverter configured to receive a pair of cross-coupled capacitors coupled to the first and second inverters; The comparator further includes:

9. 9. A comparator as claimed in claim 8, The pair of cross-coupled capacitors a first capacitor including a first terminal and a second terminal; a second capacitor including a third terminal and a fourth terminal; Including, a comparator, the first terminal being connected to an input of the first inverter, the third terminal being connected to an input of the second inverter, the second terminal being connected to an output of the second inverter, and the fourth terminal being connected to an output of the first inverter.

10. 10. A comparator as claimed in claim 9, a comparator, wherein the output of the first inverter is the positive delayed clock signal and the output of the second inverter is the negative delayed clock signal.

11. A delay circuit comprising: a first inverter coupled to the first transistor and the second transistor, the first inverter configured to receive the first intermediate delayed clock signal and generate a positive delayed clock signal that is received by a first negative product (NAND) gate of a comparator; a second inverter coupled to the third transistor and the fourth transistor, the second inverter configured to receive the second intermediate delayed clock signal and generate a negative delayed clock signal that is received by the second NAND gate of the comparator; and a pair of cross-coupled capacitors coupled to the first inverter and the second inverter; A delay circuit including:

12. 12. The delay circuit according to claim 11, the first transistor is connected in parallel to the second transistor; the third transistor is connected in parallel with a fourth transistor; a resistance of the first transistor in parallel with the second transistor determines a delay of the positive delayed clock signal; A delay circuit, wherein a resistance of a third transistor in parallel with the fourth transistor determines a delay of the negative delayed clock signal.

13. 13. A delay circuit according to claim 12, comprising:

11. A delay circuit, comprising: a first transistor including a first gate configured to receive a positive input signal; a second transistor including a second gate configured to receive a negative reference signal; a third transistor including a third gate configured to receive a negative input signal; and a fourth transistor including a fourth gate configured to receive a positive reference signal.

14. 14. A delay circuit according to claim 13, comprising: a resistance of the first transistor proportional to the voltage level of the positive input signal, a resistance of the second transistor proportional to the voltage level of the negative reference signal, a resistance of the third transistor proportional to the voltage level of the negative input signal, and a resistance of the fourth transistor proportional to the voltage level of the positive reference signal.

15. 14. A delay circuit according to claim 13, comprising: the first inverter includes a first input terminal and a first output terminal, the second inverter includes a second input terminal and a second output terminal; the pair of cross-coupled capacitors includes a first capacitor and a second capacitor; a delay circuit, the first input terminal being connected to a first terminal of the first capacitor, the second output terminal being connected to a second terminal of the first capacitor, the second input terminal being connected to a third terminal of the second capacitor, and the first output terminal being connected to a fourth terminal of the second capacitor.

16. 16. A delay circuit according to claim 15, the first transistor further includes a first drain, the second transistor further includes a second drain, the third transistor further includes a third drain, and the fourth transistor further includes a fourth drain; a delay circuit, the first input terminal being connected to the first drain and the second drain, and the second input terminal being connected to the third drain and the fourth drain;

17. A comparator comprising: a differential input pair of transistors including a first input transistor and a second input transistor; and Delay circuit, Including, The delay circuit is a first inverter coupled to a first transistor and a second transistor, the first inverter configured to receive a first intermediate delayed clock signal and generate a positive delayed clock signal that is received by the first input transistor; a second inverter coupled to a third transistor and the fourth transistor, the second inverter configured to receive a second intermediate delayed clock signal and generate a negative delayed clock signal that is received by the second input transistor; a pair of cross-coupled capacitors coupled to the first inverter and the second inverter; Including, a comparator.

18. 18. A comparator as claimed in claim 17, comprising: the first inverter includes a first input terminal and a first output terminal, the second inverter includes a second input terminal and a second output terminal; the pair of cross-coupled capacitors includes a first capacitor and a second capacitor; a comparator, the first input terminal being connected to a first terminal of the first capacitor, the second output terminal being connected to a second terminal of the first capacitor, the second input terminal being connected to a third terminal of the second capacitor, and the first output terminal being connected to a fourth terminal of the second capacitor.

19. 20. A comparator as claimed in claim 18, comprising: the first transistor includes a first drain, the second transistor includes a second drain, the third transistor includes a third drain, and the fourth transistor includes a fourth drain; a comparator, the first input terminal being connected to the first drain and the second drain, and the second input terminal being connected to the third drain and the fourth drain.

20. 20. A comparator as claimed in claim 19, comprising: the first transistor includes a first gate configured to receive a positive input signal, the second transistor includes a second gate configured to receive a negative reference signal, the third transistor includes a third gate configured to receive a negative input signal, and the fourth transistor includes a fourth gate configured to receive a positive reference signal; a resistance of the first transistor proportional to the voltage level of the positive input signal, a resistance of the second transistor proportional to the voltage level of the negative reference signal, a resistance of the third transistor proportional to the voltage level of the negative input signal, and a resistance of the fourth transistor proportional to the voltage level of the positive reference signal.

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