Protection circuit and electronic apparatus

Abstract

To provide a protection circuit capable of preventing continuation of an overload current without using a physical fuse in the case where an overload current occurs due to a short circuit or the like.SOLUTION: In an electronic apparatus 10, a protection circuit 24 comprises: a switch element 26 that connects or disconnects a power supply 22 and a loading 14; a power supply monitoring circuit 28 that outputs a first signal (high-level) when a voltage value of the power supply is larger than a voltage threshold value, and outputs a second signal (low-level) when the voltage value of the power supply is smaller than the voltage threshold value; a storage circuit 30 that outputs a third signal (high-level) in response to supply of power from the power supply, and outputs a fourth signal (low-level) after the signal output from the power supply monitoring circuit has changed from the first signal to the second signal; and a determination circuit 32 that supplies an on-signal to the switch element in the case where the first signal is output from the power supply monitoring circuit and the third signal is output from the storage circuit, and supplies an off-signal to the switch element in the case where the fourth signal is output from the storage circuit or the second signal is output from the power supply monitoring circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a protection circuit and an electronic device. [Background technology]

[0002] Patent Document 1 shows a medicinal liquid administration device as an electronic device. This medicinal liquid administration device includes a pump that supplies medicinal liquid stored in a reservoir to a needle, a control unit that controls the pump, and a battery that supplies power to the control unit. The medicinal liquid administration device is attached to the human body and administers medicinal liquid to the human body. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-63105 A Summary of the Invention [Problem to be solved by the invention]

[0004] There is a risk of an overcurrent occurring in the circuit of a drug solution administration device due to a short circuit or the like. If the overcurrent continues, the temperature of the drug solution administration device will rise. This will cause discomfort to a user wearing the drug solution administration device. The continuation of the overcurrent can be prevented by providing a physical fuse in the circuit of the drug solution administration device. However, there is a need for a technology that can prevent the continuation of the overcurrent without using a physical fuse.

[0005] The present invention aims to solve the above-mentioned problems. [Means for solving the problem]

[0006] (1) A protection circuit of a first invention includes a switch element that electrically connects a power supply and a load when an on signal is supplied and electrically disconnects the power supply and the load when an off signal is supplied; a first circuit that outputs a first signal from a first output terminal when a voltage value of the power supply is greater than a voltage threshold and outputs a second signal different from the first signal from the first output terminal when the voltage value of the power supply is less than the voltage threshold; and a third signal that outputs a third signal from a second output terminal in response to the supply of power from the power supply, and the signal output from the first output terminal of the first circuit is different from the first signal. a second circuit that outputs a fourth signal different from the third signal from the second output terminal after the first signal has changed from the first output terminal of the first circuit and the third signal is output from the second output terminal of the second circuit, and a third circuit that supplies the on signal to the switch element when the first signal is output from the first output terminal of the first circuit and the third signal is output from the second output terminal of the second circuit, and supplies the off signal to the switch element when the fourth signal is output from the second output terminal of the second circuit or the second signal is output from the first output terminal of the first circuit.

[0007] The protection circuit operates as follows. When an overcurrent or the like occurs in the load, the voltage value of the power supply becomes smaller than the voltage threshold. When the voltage value of the power supply is smaller than the voltage threshold, the first circuit outputs a second signal from the first output terminal. After the signal output from the first output terminal of the first circuit changes to the second signal, the second circuit outputs a fourth signal from the second output terminal. When the fourth signal is output from the second output terminal of the second circuit, the third circuit supplies an off signal to the switch element. Alternatively, when the second signal is output from the first output terminal of the first circuit, the third circuit also supplies an off signal to the switch element. As a result, the switch element electrically disconnects the power supply from the load.

[0008] In this way, when an overcurrent occurs in the load due to a short circuit or the like, the protection circuit electrically disconnects the power supply and the load by the switch element, which prevents the overcurrent in the load from continuing and prevents the temperature of the electronic device from rising.

[0009] In the protection circuit, a switch element, rather than a physical fuse, switches between electrical connection and disconnection between the power supply and the load. The series resistance of the switch element is smaller than that of the physical fuse. Therefore, the protection circuit can suppress a large voltage drop in the switch element. Therefore, the protection circuit can prevent the voltage range of the power supply that can be used by the load from narrowing.

[0010] Even if the voltage of the power supply recovers after the power supply and the load are electrically disconnected, the switch element maintains the off state, and therefore the protection circuit can prevent the recurrence of an overcurrent in the load.

[0011] (2) In the protection circuit described in the above item (1), the switch element may be a PMOS semiconductor element having a gate terminal, the first circuit may be a reset circuit having a reset output terminal as the first output terminal, the second circuit may be a latch circuit having a data input terminal, a clock terminal, and an inverted output terminal as the second output terminal, the third circuit may be a NAND circuit having a first input terminal, a second input terminal, and a NAND output terminal, the reset output terminal of the reset circuit is connected to the clock terminal of the latch circuit and the first input terminal of the NAND circuit, the inverted output terminal of the latch circuit is connected to the data input terminal of the latch circuit and the second input terminal of the NAND circuit, and the NAND output terminal of the NAND circuit may be connected to the gate terminal of the PMOS semiconductor element.

[0012] (3) In the protection circuit described in the above item (2), the reset circuit outputs a high-level signal, which is the first signal, from the reset output terminal when the voltage value of the power supply is greater than the voltage threshold, and outputs a low-level signal, which is the second signal, from the reset output terminal when the voltage value of the power supply is less than the voltage threshold, and the latch circuit outputs a high-level signal, which is the third signal, from the inverting output terminal in response to the supply of power from the power supply, and outputs a low-level signal, which is the fourth signal, from the inverting output terminal after the signal supplied from the first circuit changes from a high-level signal to a low-level signal. the NAND circuit may supply a low level signal, which is the on signal, from the NAND output terminal to the gate terminal of the PMOS semiconductor element when a high level signal is output from the reset output terminal of the reset circuit and a high level signal is output from the inverted output terminal of the latch circuit, and may supply a high level signal, which is the off signal, from the NAND output terminal to the gate terminal of the PMOS semiconductor element when a low level signal is output from the inverted output terminal of the latch circuit or a low level signal is output from the reset output terminal of the reset circuit.

[0013] (4) In the protection circuit described in the above item (1), the switch element may be an NMOS semiconductor element having a gate terminal, the first circuit may be a reset circuit having a reset output terminal as the first output terminal, the second circuit may be a latch circuit having a data input terminal, a clock terminal, and an inverted output terminal as the second output terminal, the third circuit may be an AND circuit having a first input terminal, a second input terminal, and an AND output terminal, the reset output terminal of the reset circuit is connected to the clock terminal of the latch circuit and the first input terminal of the AND circuit, the inverted output terminal of the latch circuit is connected to the data input terminal of the latch circuit and the second input terminal of the AND circuit, and the AND output terminal of the AND circuit may be connected to the gate terminal of the NMOS semiconductor element.

[0014] (5) In the protection circuit described in the above item (4), the reset circuit outputs a high-level signal, which is the first signal, from the reset output terminal when the voltage value of the power supply is greater than the voltage threshold, and outputs a low-level signal, which is the second signal, from the reset output terminal when the voltage value of the power supply is less than the voltage threshold, and the latch circuit outputs a high-level signal, which is the third signal, from the inverting output terminal in response to the supply of power from the power supply, and after the signal supplied from the first circuit changes from a high-level signal to a low-level signal, outputs a low-level signal, which is the fourth signal, from the inverting output terminal. the AND circuit may supply a high-level signal, which is the on signal, to the gate terminal of the NMOS semiconductor element from the AND output terminal when a high-level signal is output from the reset output terminal of the reset circuit and a high-level signal is output from the inverting output terminal of the latch circuit, and supply a low-level signal, which is the off signal, to the gate terminal of the NMOS semiconductor element from the AND output terminal when a low-level signal is output from the inverting output terminal of the latch circuit or a low-level signal is output from the reset output terminal of the reset circuit.

[0015] (6) An electronic device according to a second aspect of the present invention includes the protection circuit according to any one of the above items (1) to (5). Effect of the Invention

[0016] According to the present invention, it is possible to provide a technique for preventing the continuation of an overcurrent without using a physical fuse. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a circuit block diagram of an electronic device. [Diagram 2] FIG. 2 is a specific circuit diagram of the power supply device according to the first embodiment. [Diagram 3] 3A to 3F are timing charts of the various parts of the power supply device when starting up an electronic device. [Figure 4] 4A to 4F are timing charts of the various parts of the power supply device before and after an overcurrent occurs in the load device. [Diagram 5] FIG. 5 is a specific circuit diagram of the power supply device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] [1 Configuration of electronic device 10] 1 is a circuit block diagram of electronic device 10. Electronic device 10 includes a power supply device 12 and a load device 14. In this specification, electronic device 10 is assumed to be a medicinal liquid administration device. However, electronic device 10 is not limited to a medicinal liquid administration device.

[0019] The load device 14 includes a microcomputer 16, a driver circuit 18, and a motor 20. The microcomputer 16 is connected to the power supply device 12. The motor 20 is connected to the power supply device 12 via the driver circuit 18. The microcomputer 16 and the motor 20 are each supplied with power from the power supply device 12. The microcomputer 16 supplies a control signal to the driver circuit 18 to control the operation of the motor 20. When the electronic device 10 is a drug solution administration device, the drug solution in the reservoir is administered to the human body via a cannula when the motor 20 operates.

[0020] The power supply device 12 includes a power supply 22 and a protection circuit 24. The power supply 22 is, for example, a small low-voltage (several volts) battery. The protection circuit 24 electrically connects the power supply 22 to the load device 14. In addition, the protection circuit 24 electrically disconnects the power supply 22 from the load device 14 when an overcurrent occurs in the load device 14.

[0021] While the protection circuit 24 has the function of a physical fuse, it has the following advantages over a physical fuse. Since the power source 22 is a small battery, the smaller the breaking current value of the physical fuse is set, the larger the series resistance value of the physical fuse among the series resistance values ​​from the power source 22 to the load device 14. This means that the voltage drops significantly at the physical fuse under high load. As a result, the voltage range of the power source 22 that can be used in the load device 14 becomes narrower. In other words, the use of a physical fuse is an obstacle to lowering the voltage of the power source 22. In contrast, the protection circuit 24 can switch between electrical connection and disconnection between the power source 22 and the load device 14 by switching the switch element 26 on and off. The series resistance value of the switch element 26 is smaller than the series resistance value of the physical fuse. In this way, the protection circuit 24 does not have a circuit element (physical fuse) that has a relatively large series resistance value between the power source 22 and the load device 14. Therefore, the protection circuit 24 can widen the voltage range of the power source 22 that can be used in the load device 14 compared to a physical fuse. In other words, the use of the protection circuit 24 contributes to lowering the voltage of the power supply 22.

[0022] The protection circuit 24 includes a switch element 26, a power supply monitoring circuit 28 (first circuit), a memory circuit 30 (second circuit), and a determination circuit 32 (third circuit). The switch element 26 is capable of switching between electrical connection and interruption between the power supply 22 and the load device 14.

[0023] The power supply monitoring circuit 28 monitors the voltage value of the positive terminal 22p of the power supply 22. The power supply monitoring circuit 28 outputs a high-level signal (first signal) from the output terminal 28o (first output terminal) when the voltage value of the positive terminal 22p of the power supply 22 is equal to or higher than the voltage threshold Vth. The power supply monitoring circuit 28 outputs a low-level signal (second signal) different from the high-level signal from the output terminal 28o when the voltage value of the positive terminal 22p of the power supply 22 is lower than the voltage threshold Vth.

[0024] The memory circuit 30 stores information previously supplied and outputs the stored information at a predetermined timing. The memory circuit 30 outputs a high-level signal (third signal) from the output terminal 30o (second output terminal) in response to the supply of power from the power source 22. After the signal output from the output terminal 28o provided in the power supply monitoring circuit 28 changes from a high-level signal to a low-level signal, the memory circuit 30 outputs a low-level signal (fourth signal) different from the high-level signal from the output terminal 30o.

[0025] The determination circuit 32 determines whether to turn the switch element 26 on or off based on the signal output from the power supply monitoring circuit 28 and the signal output from the memory circuit 30. The determination circuit 32 supplies an on signal to the switch element 26 when a high level signal is output from the output terminal 28o of the power supply monitoring circuit 28 and a high level signal is output from the output terminal 30o of the memory circuit 30. The determination circuit 32 supplies an off signal to the switch element 26 when a low level signal is output from the output terminal 30o of the memory circuit 30. The determination circuit 32 also supplies an off signal to the switch element 26 when a low level signal is output from the output terminal 28o of the power supply monitoring circuit 28.

[0026] In this specification, the signal value of a high level signal (H level signal) is called a high level value (H level value). The high level value may be illustrated using "H". Furthermore, the signal value of a low level signal (L level signal) is called a low level value (L level value). The low level value may be illustrated using "L".

[0027] The electronic device 10 includes an insulating unit (not shown) between the power source 22 and the load device 14. The insulating unit insulates the power source 22 from the load device 14 when the electronic device 10 is unused. When using the electronic device 10, the user can release the state of insulation between the power source 22 and the load device 14 provided by the insulating unit. When the state of insulation between the power source 22 and the load device 14 provided by the insulating unit is released, the electronic device 10 starts up.

[0028] [2 Specific examples of power supply unit 12] FIG. 2 is a specific circuit diagram of the power supply device 12 according to the first embodiment. The protection circuit 24 shown in FIG. 2 is an example of the protection circuit 24 according to the present invention. For example, a PMOS semiconductor element 36 is used as the switch element 26. For example, a reset circuit 38 (also called a reset IC) is used as the power supply monitoring circuit 28. For example, a latch circuit 40 (also called a D flip-flop circuit) is used as the memory circuit 30. For example, a NAND circuit 42 is used as the determination circuit 32. Note that the power supply device 12 may be realized by circuits other than the reset circuit 38, the latch circuit 40, the NAND circuit 42, and the like.

[0029] The PMOS semiconductor element 36 includes a gate terminal 36g, a source terminal 36s, and a drain terminal 36d. The reset circuit 38 includes a reset input terminal 38i, a reset output terminal 38o, and a GND terminal 38g. The latch circuit 40 includes a reset terminal 40r, a data input terminal 40d, a clock terminal 40c, a non-inverting output terminal 40o1, an inverting output terminal 40o2, and a GND terminal 40g. The NAND circuit 42 includes a first input terminal 42i1, a second input terminal 42i2, a third input terminal 42i3, a NAND output terminal 42o, and a GND terminal 42g.

[0030] A source terminal 36s of the PMOS semiconductor element 36 is connected to a positive terminal 22p of the power supply 22. A drain terminal 36d of the PMOS semiconductor element 36 is connected to a positive terminal (not shown) of the load device 14. In this manner, the PMOS semiconductor element 36 is interposed between the power supply 22 and the load device 14.

[0031] The positive terminal 22p of the power supply 22 and the source terminal 36s of the PMOS semiconductor element 36 are connected to a reset input terminal 38i of the reset circuit 38, a reset terminal 40r of the latch circuit 40, and a third input terminal 42i3 of the NAND circuit 42, via a fuse 44. The fuse 44 is not interposed between the power supply 22 and the load device 14. Therefore, the fuse 44 does not affect the voltage range of the power supply 22 that can be used by the load device 14.

[0032] A reset output terminal 38o of the reset circuit 38 is connected to a clock terminal 40c of the latch circuit 40 and a first input terminal 42i1 of the NAND circuit 42. An inverted output terminal 40o2 of the latch circuit 40 is connected to a data input terminal 40d of the latch circuit 40 and a second input terminal 42i2 of the NAND circuit 42. A NAND output terminal 42o of the NAND circuit 42 is connected to a gate terminal 36g of the PMOS semiconductor element 36.

[0033] A negative terminal 22n of the power supply 22 is connected to ground. Similarly, a GND terminal 38g of the reset circuit 38, a GND terminal 40g of the latch circuit 40, a GND terminal 42g of the NAND circuit 42, and a negative terminal (not shown) of the load device 14 are each connected to ground.

[0034] The reset circuit 38 outputs a high-level signal from the reset output terminal 38o when the voltage value of the reset input terminal 38i (the voltage value of the power supply 22) is equal to or higher than the voltage threshold Vth. The reset circuit 38 outputs a low-level signal from the reset output terminal 38o when the voltage value of the reset input terminal 38i (the voltage value of the power supply 22) is lower than the voltage threshold Vth.

[0035] The latch circuit 40 stores a low-level value at startup. That is, immediately after startup, the latch circuit 40 outputs a low-level signal from the non-inverting output terminal 40o1 and a high-level signal from the inverting output terminal 40o2. The latch circuit 40 can switch the stored value in synchronization with the falling edge (negative edge trigger) of the clock signal.

[0036] [Operation of protection circuit 24] [Operation of protection circuit 24 at startup] Figures 3A to 3F are timing charts of each part of the power supply device 12 when the electronic device 10 is starting up. Figure 3A shows the transition of the voltage value of the positive terminal 22p provided in the power supply 22. Figure 3B shows the transition of the signal value output from the reset output terminal 38o provided in the reset circuit 38. Figure 3C shows the transition of the signal value supplied to the data input terminal 40d provided in the latch circuit 40. Figure 3D shows the transition of the signal value output from the non-inverting output terminal 40o1 provided in the latch circuit 40. Figure 3E shows the transition of the signal value output from the inverting output terminal 40o2 provided in the latch circuit 40. Figure 3F shows the transition of the signal value output from the NAND output terminal 42o provided in the NAND circuit 42.

[0037] At time point ta1, the user releases the insulation state between the power supply 22 and the load device 14 by an insulating part (not shown). Then, as shown in Figure 3A, the voltage value of the positive terminal 22p provided in the power supply 22 rises from 0 to a predetermined V1 from time point ta1 to time point ta3. The voltage value of the positive terminal 22p provided in the power supply 22 becomes equal to or higher than the voltage threshold Vth (0 < Vth < V1) at time point ta2 (ta1 < ta2 < ta3).

[0038] At time ta1, the voltage value of the reset input terminal 38i of the reset circuit 38 is less than the voltage threshold Vth. In this state, as shown in FIG. 3B, the reset circuit 38 outputs a low-level signal from the reset output terminal 38o. At time ta2, the voltage value of the reset input terminal 38i of the reset circuit 38 becomes equal to or greater than the voltage threshold Vth. At this timing (time ta2), as shown in FIG. 3B, the reset circuit 38 increases the signal value output from the reset output terminal 38o from a low-level value. Between time ta2 and time ta3, the reset circuit 38 switches the signal output from the reset output terminal 38o from a low-level signal to a high-level signal.

[0039] At time ta1, the latch circuit 40 transitions to the initial state in response to an increase in the voltage value of the reset terminal 40r. That is, the latch circuit 40 stores a low level value that is an initial value. As shown in FIG. 3D, from time ta1 to time ta3, the latch circuit 40 outputs a low level signal from the non-inverting output terminal 40o1. As shown in FIG. 3E, from time ta1 to time ta3, the latch circuit 40 switches the signal output from the inverting output terminal 40o2 from a low level signal to a high level signal. As shown in FIG. 3C, from time ta1 to time ta3, the signal supplied to the data input terminal 40d switches from a low level signal to a high level signal in accordance with a change in the signal output from the inverting output terminal 40o2. As a result, at time ta3, the latch circuit 40 stores the signal value (high level value) of the high level signal supplied to the data input terminal 40d.

[0040] At time ta3, the signals output from the reset output terminal 38o and the inverted output terminal 40o2 both become high-level signals. Then, as shown in FIG. 3F, at time ta3, the NAND circuit 42 outputs a low-level signal from the NAND output terminal 42o. As a result, the voltage of the gate terminal 36g of the PMOS semiconductor element 36 becomes a low-level value. Then, in the PMOS semiconductor element 36, the voltage value of the gate terminal 36g becomes lower than the voltage value of the source terminal 36s. Therefore, the PMOS semiconductor element 36 is turned on. In this way, the power supply 22 and the load device 14 are electrically connected.

[0041] [Operation of Protection Circuit 24 Before and After Overcurrent Occurrence] FIGS. 4A to 4F are timing charts of each part of the power supply device 12 before and after overcurrent occurrence in the load device 14. FIG. 4A shows the transition of the voltage value of the plus terminal 22p provided in the power supply 22. FIG. 4B shows the transition of the signal value output from the reset output terminal 38o provided in the reset circuit 38. FIG. 4C shows the transition of the signal value supplied to the data input terminal 40d provided in the latch circuit 40. FIG. 4D shows the transition of the signal value output from the non-inverted output terminal 40o1 provided in the latch circuit 40. FIG. 4E shows the transition of the signal value output from the inverted output terminal 40o2 provided in the latch circuit 40. FIG. 4F shows the transition of the signal value output from the NAND output terminal 42o provided in the NAND circuit 42.

[0042] At time ts1, an overcurrent (short circuit) occurs in the load device 14. Then, as shown in FIG. 4A, the voltage value of the plus terminal 22p provided in the power supply 22 decreases from V1 from time ts1 to time ts3. The voltage value of the plus terminal 22p provided in the power supply 22 becomes less than the voltage threshold Vth at time ts2 (ts1 < ts2 < ts3).

[0043] At time ts1, the voltage value of the reset input terminal 38i of the reset circuit 38 is equal to or higher than the voltage threshold Vth. In this state, as shown in FIG. 4B, the reset circuit 38 outputs a high-level signal from the reset output terminal 38o. At time ts2, the voltage value of the reset input terminal 38i of the reset circuit 38 becomes lower than the voltage threshold Vth. At this timing (time ts2), as shown in FIG. 4B, the reset circuit 38 lowers the signal value output from the reset output terminal 38o from a high-level value. Between time ts2 and time ts3, the reset circuit 38 switches the signal output from the reset output terminal 38o from a high-level signal to a low-level signal.

[0044] At time ts2, the latch circuit 40 detects the falling edge of the signal (signal output from the reset output terminal 38o) supplied to the clock terminal 40c. Then, the latch circuit 40 outputs the stored high level value. That is, as shown in FIG. 4D, from time ts2 to time ts3, the latch circuit 40 switches the signal output from the non-inverting output terminal 40o1 from a low level signal to a high level signal. As shown in FIG. 4E, from time ts2 to time ts3, the latch circuit 40 switches the signal output from the inverting output terminal 40o2 from a high level signal to a low level signal. As shown in FIG. 4C, from time ta2 to time ta3, the signal supplied to the data input terminal 40d switches from a high level signal to a low level signal in accordance with the change in the signal output from the inverting output terminal 40o2. As a result, at time ts3, the latch circuit 40 stores the signal value (low level value) of the low level signal supplied to the data input terminal 40d.

[0045] At time point ts3, the signals output from the reset output terminal 38o and the inverted output terminal 40o2 both become low-level signals. Then, as shown in FIG. 4F, at time point ts3, the NAND circuit 42 switches the signal output from the NAND output terminal 42o from a low-level signal to a high-level signal. As a result, the voltage of the gate terminal 36g of the PMOS semiconductor element 36 becomes a high-level value. Then, in the PMOS semiconductor element 36, the potential difference between the gate terminal 36g and the source terminal 36s becomes small. Therefore, the PMOS semiconductor element 36 is turned off.

[0046] When the PMOS semiconductor element 36 is turned off, the voltage value of the positive terminal 22p provided in the power supply 22 rises again. As shown in FIG. 4A, from time point ts3 to time point ts6, the voltage value of the positive terminal 22p provided in the power supply 22 rises from less than the voltage threshold Vth to a predetermined V1. The voltage value of the positive terminal 22p provided in the power supply 22 becomes equal to or higher than the voltage threshold Vth (0 < Vth < V1) at time point ts4 (ts3 < ts4 < ts6).

[0047] At time point ts3, the voltage value of the reset input terminal 38i provided in the reset circuit 38 is less than the voltage threshold Vth. In this state, as shown in FIG. 4B, the reset circuit 38 outputs a low-level signal from the reset output terminal 38o. At time point ts4, the voltage value of the reset input terminal 38i provided in the reset circuit 38 becomes equal to or higher than the voltage threshold Vth. At this timing (time point ts4), the reset circuit 38 raises the signal value output from the reset output terminal 38o from a low-level value. From time point ts4 to time point ts5 (ts4 < ts5 < ts6), the reset circuit 38 switches the signal output from the reset output terminal 38o from a low-level signal to a high-level signal.

[0048] After time ts3, the latch circuit 40 does not detect the falling edge of the signal supplied to the clock terminal 40c (the signal output from the reset output terminal 38o). Therefore, as shown in Fig. 4D, after time ts3, the latch circuit 40 continues to output a high-level signal from the non-inverting output terminal 40o1. Similarly, as shown in Fig. 4E, after time ts3, the latch circuit 40 continues to output a low-level signal from the inverting output terminal 40o2.

[0049] After time ts3, the signal output from the inverting output terminal 40o2 of the latch circuit 40 maintains a low level value. Therefore, as shown in FIG. 4F, after time ta3, the NAND circuit 42 continues to output a high level signal from the NAND output terminal 42o. As a result, the voltage value of the gate terminal 36g of the PMOS semiconductor element 36 maintains a high level value. Then, in the PMOS semiconductor element 36, the potential difference between the gate terminal 36g and the source terminal 36s maintains a small voltage value. Therefore, the PMOS semiconductor element 36 maintains an off state.

[0050] [4. Effects of the protection circuit 24] The protection circuit 24 operates as follows. When an overcurrent or the like occurs in the load device 14, the voltage value of the power supply 22 becomes smaller than the voltage threshold value Vth. When the voltage value of the power supply 22 is smaller than the voltage threshold value Vth, the reset circuit 38 (power supply monitoring circuit 28) outputs a low-level signal from the reset output terminal 38o (output terminal 28o). After the signal output from the reset output terminal 38o provided in the reset circuit 38 changes to a low-level signal, the latch circuit 40 (storage circuit 30) outputs a low-level signal from the inverted output terminal 40o2 (output terminal 30o). When a low-level signal is output from the inverted output terminal 40o2 provided in the latch circuit 40, the NAND circuit 42 (determination circuit 32) supplies an off signal to the PMOS semiconductor element 36 (switch element 26). As a result, the PMOS semiconductor element 36 electrically disconnects the power supply 22 and the load device 14.

[0051] In this way, according to the protection circuit 24, when an overcurrent occurs in the load device 14 due to a short circuit or the like, the PMOS semiconductor element 36 electrically disconnects the power supply 22 from the load device 14. This prevents the overcurrent in the load device 14 from continuing, and makes it possible to prevent the temperature of the electronic device 10 from increasing.

[0052] In the protection circuit 24, a PMOS semiconductor element 36 (switch element 26), rather than a physical fuse, switches between electrical connection and disconnection between the power supply 22 and the load device 14. The series resistance value of the PMOS semiconductor element 36 is smaller than the series resistance value of a physical fuse. Therefore, the protection circuit 24 can suppress a large voltage drop in the PMOS semiconductor element 36. Therefore, the protection circuit 24 can prevent the voltage range of the power supply 22 that can be used in the load device 14 from narrowing.

[0053] Even if the voltage value of the positive terminal 22p of the power supply 22 recovers after the power supply 22 and the load device 14 are electrically disconnected, the PMOS semiconductor element 36 maintains the off state. Therefore, the protection circuit 24 can prevent the recurrence of an overcurrent in the load device 14.

[0054] [5 Alternative forms of protection circuit 24] 5 is a specific circuit diagram of the power supply device 12 according to the second embodiment. A protection circuit 24 including a switch element 26 may be formed between the negative terminal 22n of the power supply 22 and the ground. In this protection circuit 24, an NMOS semiconductor element 46 may be used as the switch element 26. Also, in this protection circuit 24, an AND circuit 48 may be used as the determination circuit 32.

[0055] A source terminal 46s of the NMOS semiconductor element 46 is connected to a negative terminal 22n of the power supply 22. A drain terminal 46d of the NMOS semiconductor element 46 is connected to the ground. In this manner, the NMOS semiconductor element 46 is interposed between the power supply 22 and the load device 14 via the ground.

[0056] A reset output terminal 38o of the reset circuit 38 is connected to a clock terminal 40c of the latch circuit 40 and a first input terminal 48i1 of the AND circuit 48.

[0057] The inverting output terminal 40o2 of the latch circuit 40 is connected to a data input terminal 40d of the latch circuit 40 and a second input terminal 48i2 of the AND circuit .

[0058] A third input terminal 48i3 of the AND circuit 48 is connected to the positive terminal 22p of the power supply 22 via the fuse 44. An AND output terminal 48o of the AND circuit 48 is connected to a gate terminal 46g of the NMOS semiconductor element 46.

[0059] A GND terminal 38g of the reset circuit 38, a GND terminal 40g of the latch circuit 40, and a GND terminal 48g of the AND circuit 48 are each connected to a negative terminal 22n of the power supply 22 and a source terminal 46s of the NMOS semiconductor element 46.

[0060] When a high level signal is output from the reset output terminal 38o of the reset circuit 38 and a high level signal is output from the inverted output terminal 40o2 of the latch circuit 40, the AND circuit 48 supplies a high level signal, which is an on signal, from the AND output terminal 48o to the gate terminal 46g of the NMOS semiconductor element 46. When a low level signal is output from the inverted output terminal 40o2 of the latch circuit 40, the AND circuit 48 supplies a low level signal, which is an off signal, from the AND output terminal 48o to the gate terminal 46g of the NMOS semiconductor element 46. Even when a low level signal is output from the reset output terminal 38o of the reset circuit 38, the AND circuit 48 supplies a low level signal, which is an off signal, from the AND output terminal 48o to the gate terminal 46g of the NMOS semiconductor element 46.

[0061] The protection circuit 24 in the second embodiment provides the same effects as the protection circuit 24 in the first embodiment.

[0062] The present invention is not limited to the above disclosure, and various configurations can be adopted without departing from the gist of the present invention. [Explanation of symbols]

[0063] 10...Electronic equipment 14...Load device (load) 22…Power supply 24…Protection circuit 26... Switch element 28... Power supply monitoring circuit (first circuit) 28o...output terminal (first output terminal) 30...memory circuit (second circuit) 30o...output terminal (second output terminal) 32...judgment circuit (third circuit) 36...PMOS semiconductor element 36g, 46g...Gate terminal 38...Reset circuit 38o...Reset output terminal 40...Latch circuit 40c...Clock terminal 40d...Data input terminal 40o2...Inverted output terminal 42...NAND circuit 42i1, 48i1...First input terminal 42i2, 48i2: Second input terminal 42o: NAND output terminal 46...NMOS semiconductor element 48...AND circuit 48o...AND output terminal

Claims

1. a switch element that electrically connects a power supply and a load when an on signal is supplied, and electrically disconnects the power supply and the load when an off signal is supplied; a first circuit that outputs a first signal from a first output terminal when a voltage value of the power supply is greater than a voltage threshold, and outputs a second signal different from the first signal from the first output terminal when the voltage value of the power supply is less than the voltage threshold; a second circuit that outputs a third signal from a second output terminal in response to a supply of power from the power source, and outputs a fourth signal different from the third signal from the second output terminal after a signal output from the first output terminal of the first circuit changes from the first signal to the second signal; a third circuit that supplies the ON signal to the switch element when the first signal is output from the first output terminal of the first circuit and the third signal is output from the second output terminal of the second circuit, and supplies the OFF signal to the switch element when the fourth signal is output from the second output terminal of the second circuit or the second signal is output from the first output terminal of the first circuit; A protection circuit comprising:

2. 2. The protection circuit according to claim 1, the switch element is a PMOS semiconductor element having a gate terminal; the first circuit is a reset circuit having a reset output terminal as the first output terminal, the second circuit is a latch circuit including a data input terminal, a clock terminal, and an inverted output terminal serving as the second output terminal; the third circuit is a NAND circuit having a first input terminal, a second input terminal, and a NAND output terminal; the reset output terminal of the reset circuit is connected to the clock terminal of the latch circuit and to the first input terminal of the NAND circuit; the inverting output terminal of the latch circuit is connected to the data input terminal of the latch circuit and the second input terminal of the NAND circuit; the NAND output terminal of the NAND circuit is connected to the gate terminal of the PMOS semiconductor element,

3. 3. The protection circuit according to claim 2, the reset circuit outputs a high-level signal, which is the first signal, from the reset output terminal when the voltage value of the power supply is greater than the voltage threshold, and outputs a low-level signal, which is the second signal, from the reset output terminal when the voltage value of the power supply is less than the voltage threshold; the latch circuit outputs a high-level signal, which is the third signal, from the inverting output terminal in response to a supply of power from the power supply, and outputs a low-level signal, which is the fourth signal, from the inverting output terminal after the signal supplied from the first circuit changes from a high-level signal to a low-level signal; the NAND circuit supplies a low level signal, which is the on signal, from the NAND output terminal to the gate terminal of the PMOS semiconductor element when a high level signal is output from the reset output terminal of the reset circuit and a high level signal is output from the inverting output terminal of the latch circuit, and supplies a high level signal, which is the off signal, from the NAND output terminal to the gate terminal of the PMOS semiconductor element when a low level signal is output from the inverting output terminal of the latch circuit or a low level signal is output from the reset output terminal of the reset circuit.

4. 2. The protection circuit according to claim 1, the switch element is an NMOS semiconductor element having a gate terminal; the first circuit is a reset circuit having a reset output terminal as the first output terminal, the second circuit is a latch circuit including a data input terminal, a clock terminal, and an inverted output terminal serving as the second output terminal; the third circuit is an AND circuit having a first input terminal, a second input terminal, and an AND output terminal; the reset output terminal of the reset circuit is connected to the clock terminal of the latch circuit and to the first input terminal of the AND circuit; the inverting output terminal of the latch circuit is connected to the data input terminal of the latch circuit and the second input terminal of the AND circuit; the AND output terminal of the AND circuit is connected to the gate terminal of the NMOS semiconductor element,

5. 5. The protection circuit according to claim 4, the reset circuit outputs a high-level signal, which is the first signal, from the reset output terminal when the voltage value of the power supply is greater than the voltage threshold, and outputs a low-level signal, which is the second signal, from the reset output terminal when the voltage value of the power supply is less than the voltage threshold; the latch circuit outputs a high-level signal, which is the third signal, from the inverting output terminal in response to a supply of power from the power supply, and outputs a low-level signal, which is the fourth signal, from the inverting output terminal after the signal supplied from the first circuit changes from a high-level signal to a low-level signal; the AND circuit supplies a high-level signal, which is the on signal, from the AND output terminal to the gate terminal of the NMOS semiconductor element when a high-level signal is output from the reset output terminal of the reset circuit and a high-level signal is output from the inverting output terminal of the latch circuit, and supplies a low-level signal, which is the off signal, from the AND output terminal to the gate terminal of the NMOS semiconductor element when a low-level signal is output from the inverting output terminal of the latch circuit or a low-level signal is output from the reset output terminal of the reset circuit.

6. An electronic device comprising the protection circuit according to any one of claims 1 to 5.

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