Image processing apparatus

Abstract

To provide an image processing apparatus that can reduce the delay time of an output video signal relative to an input video signal.SOLUTION: An image processing apparatus includes: a memory that, upon input of a video signal, writes the video signal therein, and reads out the written video signal at the timing of a read-out clock and outputs the video signal as an output video signal; a horizontal synchronization detection circuit that detects a horizontal synchronization signal from the video signal; a phase comparator that generates a phase difference signal indicating the phase difference between the phase of the horizontal synchronization signal and the phase of a divided frequency clock signal; a lock circuit that generates a reference clock signal obtained by shifting the phase of a free-running clock signal by the phase difference indicated by the phase difference signal; a PLL that generates an oscillation signal having the dot frequency of the video signal, and locks the phase of the oscillation signal to the phase of the reference clock signal to generate a read-out clock signal; and a frequency divider that supplies, to the phase comparator, a clock signal obtained by dividing the frequency of the read-out clock signal as the divided frequency clock signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an image processing device that synchronizes and outputs a video signal. [Background technology]

[0002] 2. Description of the Related Art In recent years, vehicles such as automobiles are equipped with display systems having a camera that captures images outside the vehicle and a display device that displays images based on video signals captured by the camera.

[0003] The display device is provided with an image processing device that adjusts the input video signal to match its own timing (see, for example, Patent Document 1). In making such adjustments, the image processing device uses a frame memory as a buffer memory. For example, the synchronization timing of the video signal is adjusted by writing the video signal to the frame memory and reading the video signal from the frame memory at a predetermined timing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-71066 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the read speed for the frame memory is faster than the write speed, the frame memory may become empty. Therefore, in order to avoid such a situation, the image processing device writes one or two frames of input video signal before reading it. As a result, the output video signal is supplied to the display device after a delay of one or two frames from the input video signal, which causes a problem of a large time lag in image display relative to the input video signal.

[0006] SUMMARY OF THE PRESENT DISCLOSURE An object of the present invention is to provide an image processing device capable of reducing the delay time of an output video signal relative to an input video signal. [Means for solving the problem]

[0007] The image processing device of the present invention includes a memory that writes a video signal when the video signal is input, reads the written video signal at the timing of a read clock signal, and outputs the video signal as an output video signal, a horizontal synchronization detection circuit that detects a horizontal synchronizing signal from the video signal, a phase comparator that generates a phase difference signal indicating the phase difference between the phase of the horizontal synchronizing signal and the phase of a divided clock signal, a lock circuit that receives a free-running clock signal and generates a reference clock signal by shifting the phase of the free-running clock signal by the phase difference indicated by the phase difference signal, a PLL that generates an oscillation signal having a dot frequency and locks the phase of the oscillation signal to the phase of the reference clock signal as the read clock signal, and a frequency divider that supplies a clock signal obtained by dividing the read clock signal to the phase comparator as the divided clock signal.

[0008] Moreover, an image processing device according to the present invention includes a memory which writes a video signal when the video signal is input, reads out the written video signal at the timing of a read clock signal, and outputs the video signal as an output video signal; a horizontal synchronization detection circuit which detects a horizontal synchronization signal from the video signal; a multiplication circuit which generates a signal having a frequency of the horizontal synchronization signal multiplied by N (N is a real number equal to or greater than 2) as a horizontal synchronization multiplied signal; a phase comparator which generates a phase difference signal which indicates the phase difference between the phase of the horizontal synchronization multiplied signal and the phase of a divided clock signal; a lock circuit which receives a free-running clock signal and generates a reference clock signal by shifting the phase of the free-running clock signal by the phase difference which is indicated by the phase difference signal; a PLL which generates an oscillation signal having a dot frequency and locks the phase of the oscillation signal to the phase of the reference clock signal as the read clock signal; and a frequency divider which supplies a clock signal obtained by dividing the read clock signal to the phase comparator as the divided clock signal. Effect of the Invention

[0009] In the present invention, when an input video signal is written into a memory while being read out and output as an output video signal, a read clock signal is generated that is phase-synchronized with the horizontal synchronization signal of the input video signal, and the video signal is read out from the memory at the timing of this read clock signal.

[0010] This makes it possible to make the delay time of the output video signal relative to the input video signal less than the display period of one frame. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a configuration of a video system 100 including an image processing device according to the present invention. [Diagram 2] 2 is a block diagram showing an example of the internal configuration of an image processing device 20. FIG. [Diagram 3] 4 is a time chart showing an example of waveforms of a horizontal synchronization signal HD and a frequency-divided clock signal CKd. [Figure 4] 4 is a time chart showing a delay state of an output video signal VDX output by an image processing device 20 in response to an input video signal VD. [Diagram 5] 4 is a block diagram showing another example of the internal configuration of the image processing device 20. FIG. [Figure 6] 4 is a time chart showing an example of waveforms of a horizontal synchronization multiplied signal HDm and a frequency-divided clock signal CKE. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0013] FIG. 1 is a block diagram showing the configuration of a video system 100 including an image processing device according to the present invention.

[0014] As shown in FIG. 1, a video system 100 includes a video signal generating device 10, an image processing device 20, and a display device 30.

[0015] The video signal generating device 10 is composed of, for example, a DVD or Blu-ray player (recorder), a TV tuner, a camera, etc., and supplies a video signal acquired or reproduced by itself as a video signal VD to the image processing device 20. Note that the video signal VD includes, for each pixel constituting the screen of the display device 30, a series of pixel data pieces indicating the luminance level of that pixel.

[0016] When the image processing device 20 receives a video signal VD from the video signal generating device 10, the image processing device 20 generates, based on the video signal VD, an output clock signal CLKX as a clock signal used on the display device 30 side, and an output video signal VDX synchronized with the phase of the output clock signal CLKX. Then, the image processing device 20 outputs the output clock signal CLKX and the output video signal VDX to the display device 30.

[0017] The display device 30 is, for example, a display using liquid crystal or organic EL, and receives the output video signal VDX in synchronization with the output clock signal CLKX, and displays an image based on the output video signal VDX.

[0018] FIG. 2 is a block diagram showing an example of the internal configuration of the image processing device 20. As shown in FIG.

[0019] As shown in FIG. 2, the image processing device 20 includes a horizontal synchronization detection circuit 201, a phase comparator 202, an input detection circuit 203, a lock circuit 204, a PLL (Phase Locked Loop) 205, a frequency divider 206, a frame memory 207, and a clock buffer 208.

[0020] The horizontal synchronization detection circuit 201 detects a horizontal synchronization signal from the video signal VD, and supplies this to a phase comparator 202 as a horizontal synchronization signal HD.

[0021] The phase comparator 202 compares the phase of the horizontal synchronization signal HD with the phase of a frequency-divided clock signal CKd supplied from a frequency divider 206 , and supplies a phase difference signal PH indicating the phase difference between the two to a lock circuit 204 .

[0022] 3, when the rising edge of the divided clock signal CKd (indicated by a white triangle) is delayed by dW from the rising edge of the horizontal synchronizing signal HD (indicated by a white triangle) that appears every horizontal synchronizing period H, the phase comparator 202 supplies a phase difference signal PH representing a phase difference of (-dW) to the locking circuit 204. When the rising edge of the divided clock signal CKd is advanced by dW from the rising edge of the horizontal synchronizing signal HD, the phase comparator 202 supplies a phase difference signal PH representing a phase difference of (dW) to the locking circuit 204.

[0023] When the input detection circuit 203 receives a video signal VD, that is, when a video signal is input, the input detection circuit 203 generates an input detection signal ID indicating "input present", and when the video signal VD is not input, that is, when there is no input, the input detection circuit 203 generates an input detection signal ID indicating "no input". The input detection circuit 203 supplies the generated input detection signal ID to the lock circuit 204.

[0024] The lock circuit 204 receives the phase difference signal PH, the input sense signal ID, and a free-running clock signal CLKF, which is generated by the oscillation of an oscillator circuit (not shown) provided outside the image processing device 20, for example.

[0025] When the input detection signal ID indicates “input present”, the lock circuit 204 shifts the phase of the free-running clock signal CLKF by the phase difference indicated by the phase difference signal PH to generate a reference clock signal CKr locked to the phase of the video signal VD and supplies this to the PLL 205.

[0026] On the other hand, when the input detection signal ID indicates "no input", the lock circuit 204 supplies the free-running clock signal CLKF to the PLL 205 as the reference clock signal CKr.

[0027] The PLL 205 generates an oscillation signal having the dot frequency of the input video signal VD, locks the phase of the oscillation signal to the phase of the reference clock signal CKr, and supplies this to the frequency divider 206, the frame memory 207, and the clock buffer 208 as a read clock signal CKrd.

[0028] The frequency divider 206 divides the frequency of the read clock signal CKrd to generate a clock signal having a horizontal sync frequency, and supplies this to the phase comparator 202 as a divided clock signal CKd.

[0029] When a video signal VD is input, the frame memory 207 sequentially takes in and writes each of the pixel data pieces contained in the video signal VD, and reads out the written pixel data pieces in the order in which they were written, at the timing of the read clock signal CKrd, and outputs the read out data to the display device 30 as an output video signal VDX.

[0030] The clock buffer 208 outputs a signal obtained by amplifying the read clock signal CKrd to the display device 30 as the above-mentioned output clock signal CLKX.

[0031] With this configuration, when a video signal VD is input, the image processing device 20 writes it into the frame memory 207, and outputs the written video signal VDX, which is read out at a timing phase-synchronized with the horizontal synchronizing signal HD of the input video signal VD, to the display device 30. Furthermore, together with the output video signal VDX, the image processing device 20 outputs an output clock signal CLKX phase-synchronized with the horizontal synchronizing signal HD of the video signal VD to the display device 30. On the other hand, when the video signal VD is not input, the image processing device 20 outputs an output clock signal CLKX phase-synchronized with the free-running clock signal CLKF to the display device 30.

[0032] Therefore, by the operation of the image processing device 20 described above, it is possible to make the delay time DL of the output video signal VDX supplied to the display device 30 shorter than one frame display period F with respect to the input video signal VD, as shown in FIG.

[0033] 2 is employed as the image processing device 20, a phase comparison between the horizontal synchronization signal HD of the video signal VD and the frequency-divided clock signal CKd is performed once every horizontal scanning period H, as shown in Fig. 3. At this time, the more phase comparisons are performed per unit time, the higher the accuracy of phase synchronization can be. For example, the dot frequency of the pixel data pieces in the video signal VD, that is, the sampling frequency, is increased.

[0034] However, when high-speed video signals conforming to standards such as LVDS (Low Voltage Differential Signaling) and MIPI (Mobile Industry Processor Interface) are input, it becomes difficult to increase the sampling frequency without degrading the sampling accuracy.

[0035] FIG. 5 is a block diagram showing another example of the internal configuration of an image processing device 20 capable of generating an output video signal VDX that is phase-synchronized with an input video signal VD with high accuracy, even when such a high-speed video signal is input.

[0036] In addition, in the configuration shown in FIG. 5, a multiplication circuit 210 is newly added, and a phase comparator 202a and a frequency divider 206a are adopted instead of the phase comparator 202 and the frequency divider 206. Other configurations are the same as those shown in FIG.

[0037] Therefore, the operation of the image processing device 20 having the configuration shown in FIG. 5 will be described below, focusing on the multiplier circuit 210, the phase comparator 202a, and the frequency divider 206a.

[0038] The multiplication circuit 210 receives the horizontal synchronization signal HD detected by the horizontal synchronization detection circuit 201, and supplies a signal obtained by multiplying the frequency of the horizontal synchronization signal HD by N (N is a positive real number other than 0) to the phase comparator 202 as a horizontal synchronization multiplied signal HDm.

[0039] The frequency divider 206a divides the read clock signal CKrd output from the PLL 205 so that the frequency after division is N (N is a positive real number other than 0) times the horizontal synchronization frequency, and supplies the divided clock signal CKE to the phase comparator 202a.

[0040] The phase comparator 202 compares the phase of the horizontal sync multiplied signal HDm with the phase of the frequency-divided clock signal CKE, and supplies a phase difference signal PH representing the phase difference between the two to a lock circuit 204 .

[0041] In other words, as shown in FIG. 6, the phase comparator 202a supplies to the lock circuit 204 a phase difference signal PH representing the phase difference between the rising edge portion (indicated by a white triangle) of the divided clock signal CKE and the rising edge portion (indicated by a white triangle) of the horizontal synchronization signal HDm that appears N times within each horizontal synchronization period H.

[0042] Therefore, according to the configuration shown in FIG. 5, the number of phase comparisons performed within each horizontal scanning period H is N times that in the case of employing the configuration shown in FIG. 2, so that it is possible to generate an output video signal VDX that is phase-synchronized with high accuracy with respect to a high-speed input video signal that complies with standards such as LVDS and MIPI.

[0043] In the configuration shown in FIG. 2 or FIG. 5, the read clock signal CKrd and the output clock signal CLKX are generated using an externally supplied free-running clock signal CLKF, but an oscillator circuit for generating this free-running clock signal CLKF may be provided within the image processing device 20. [Explanation of symbols]

[0044] 20 Image processing device 201 Horizontal sync detection circuit 202, 202a phase comparator 203 Input detection circuit 204 Lock Circuit 205 PLL 206, 206a frequency divider 207 Frame Memory 210 Multiplication circuit

Claims

1. a memory for writing a video signal when the video signal is input, reading the written video signal at the timing of a read clock signal, and outputting the read video signal as an output video signal; a horizontal synchronization detection circuit for detecting a horizontal synchronization signal from the video signal; a phase comparator for generating a phase difference signal indicating a phase difference between the horizontal synchronizing signal and a frequency-divided clock signal; a lock circuit for receiving a free-running clock signal and generating a reference clock signal by shifting the phase of the free-running clock signal by the phase difference indicated by the phase difference signal; a PLL that generates an oscillation signal having a dot frequency and locks the phase of the oscillation signal to the phase of the reference clock signal to generate the read clock signal; a frequency divider that divides the frequency of the read clock signal and supplies the divided clock signal to the phase comparator.

2. a memory for writing a video signal when the video signal is input, reading the written video signal at the timing of a read clock signal, and outputting the read video signal as an output video signal; a horizontal synchronization detection circuit for detecting a horizontal synchronization signal from the video signal; a multiplication circuit that generates a signal obtained by multiplying the frequency of the horizontal synchronization signal by N (N is a real number equal to or greater than 2) as a horizontal synchronization multiplied signal; a phase comparator for generating a phase difference signal indicating a phase difference between the phase of the horizontal sync multiplied signal and the phase of a frequency-divided clock signal; a lock circuit for receiving a free-running clock signal and generating a reference clock signal by shifting the phase of the free-running clock signal by the phase difference indicated by the phase difference signal; a PLL that generates an oscillation signal having a dot frequency and locks the phase of the oscillation signal to the phase of the reference clock signal to generate the read clock signal; a frequency divider that divides the frequency of the read clock signal and supplies the divided clock signal to the phase comparator.

3. an input detection circuit that detects whether the video signal is input and generates an input detection signal indicating the presence or absence of an input; 3. The image processing device according to claim 1, wherein the lock circuit generates the reference clock signal by shifting the phase of the free-running clock signal by the phase difference indicated by the phase difference signal when the input detection signal indicates the presence of an input, and uses the free-running clock signal as the reference clock signal when the input detection signal indicates the absence of an input.

4. 3. The image processing apparatus according to claim 1, wherein the memory is a frame memory.

5. 3. The image processing apparatus according to claim 1, further comprising a clock buffer for outputting the read clock signal to an external device as an output clock signal.

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