Image sensor and image processing apparatus including the same

Abstract

To provide an image sensor and an image processing apparatus including the same.SOLUTION: In an image sensor in which a plurality of pixels are arranged, each pixel includes: a first sub-pixel that shares a first floating diffusion node (FD1); a second sub-pixel that shares a second floating diffusion node (FD2); a first rolling shutter operation circuit that reads photocharges accumulated in the FD1 by a rolling shutter method; a second rolling shutter operation circuit that reads photocharges accumulated in the FD2 by the rolling shutter method; a global selection switch circuit that is connected between the first rolling shutter operation circuit and the second rolling shutter operation circuit, and includes at least one transistor; and a global shutter operation circuit that is connected to the global selection switch circuit and reads photocharges accumulated in the FD1 and FD2 by the global shutter method.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an image sensor and an image processing device including the same, and more particularly to an image sensor capable of operating in either a global shutter mode or a rolling shutter mode. [Background technology]

[0002] Image sensors, which capture images and convert them into electrical signals, are used not only in consumer electronic devices such as digital cameras, cell phone cameras and portable camcorders, but also in cameras mounted on automobiles, security devices and robots.

[0003] The image sensor may adjust the exposure time to determine the amount of photocharge on which an electrical signal is based. The image sensor may adjust the exposure time using a rolling shutter method or a global shutter method. In this case, the rolling shutter method controls the accumulation time of photocharge to be different for each row of a pixel array, and the global shutter method controls the accumulation time of photocharge to be the same for different rows of the pixel array. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENTS An object of the present invention is to provide an image sensor capable of simultaneously outputting adjacent pixels in a rolling shutter manner and also outputting the adjacent pixels in a global shutter manner. [Means for solving the problem]

[0005] In order to achieve the above technical objectives, an image sensor according to the technical concept of the present invention is disclosed.

[0006] In an image sensor including a pixel array in which a plurality of pixels are arranged, each of the plurality of pixels may include: a first sub-pixel sharing a first floating diffusion node; a second sub-pixel sharing a second floating diffusion node; a first rolling shutter operation circuit configured to read out photocharges accumulated in the first floating diffusion node by a rolling shutter manner; a second rolling shutter operation circuit configured to read out photocharges accumulated in the second floating diffusion node by the rolling shutter manner; a global selection switch circuit connected between the first rolling shutter operation circuit and the second rolling shutter operation circuit and including at least one transistor; and a global shutter operation circuit connected to one end of the global selection switch circuit and configured to read out photocharges accumulated in the first floating diffusion node and the second floating diffusion node by the global shutter manner.

[0007] In order to achieve the above technical objectives, an image sensor according to the technical concept of the present invention is disclosed.

[0008] The image sensor may include a first sub-pixel including at least two first photodiodes, a second sub-pixel including at least two second photodiodes, a first floating diffusion node storing charges accumulated by the first photodiodes, a second floating diffusion node storing charges accumulated by the second photodiodes, a first source follower transistor amplifying a voltage stored in the first floating diffusion node, a second source follower transistor amplifying a voltage stored in the second floating diffusion node, a first rolling select transistor connected in series with the first source follower transistor, a second rolling select transistor connected in series with the second source follower transistor, and a global selection switch transistor connected between an output terminal of the first source follower transistor and an output terminal of the second source follower transistor.

[0009] In order to achieve the above technical object, an image processing apparatus according to the technical idea of ​​the present invention is disclosed.

[0010] The image processing device includes an image sensor including a pixel array in which a plurality of pixels are arranged in a matrix, the image sensor generating image data based on an optical signal received by the pixel array, and an application processor receiving the image data from the image sensor, processing the image data, and providing a mode setting signal to the image sensor, and each of the plurality of pixels includes a first sub-pixel sharing a first floating diffusion node, a second sub-pixel sharing a second floating diffusion node, and a first sub-pixel configured to read out photocharges accumulated in the first floating diffusion node by a rolling shutter method. the first rolling shutter operation circuit and the second rolling shutter operation circuit configured to read out the photocharges accumulated in the second floating diffusion node by a rolling shutter method; a global selection switch circuit connected between the first rolling shutter operation circuit and the second rolling shutter operation circuit and including at least one transistor; and a global shutter operation circuit connected to one end of the global selection switch circuit and configured to read out the photocharges accumulated in the first floating diffusion node and the second floating diffusion node by a global shutter method. Effect of the Invention

[0011] According to an image sensor according to the technical idea of ​​the present disclosure, it is possible to simultaneously output adjacent pixels in a rolling shutter mode, and also possible to output the adjacent pixels in a global shutter mode.

[0012] According to an image sensor according to the technical concept of the present disclosure, a hybrid image sensor capable of both the rolling shutter method and the global shutter method can be provided.

[0013] The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly derived and understood by a person having ordinary skill in the art to which the exemplary embodiments of the present disclosure belong from the following description of the exemplary embodiments of the present disclosure. In other words, unintended effects by implementing the exemplary embodiments of the present disclosure can also be derived from the exemplary embodiments of the present disclosure by a person having ordinary skill in the art. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 2A] FIG. 4 is a timing diagram showing the operation of a global shutter mode. [Figure 2B] FIG. 4 is a timing diagram showing the operation in a rolling shutter mode. [Diagram 3] FIG. 2 is a block diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. [Figure 5A] FIG. 13 illustrates a rolling shutter mode readout operation of a pixel according to an exemplary embodiment of the present disclosure. [Figure 5B] FIG. 13 illustrates a global shutter mode readout operation of a pixel according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 2 is a diagram for explaining the arrangement of components included in a pixel according to an exemplary embodiment of the present disclosure. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. [Figure 8] FIG. 2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 2 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure. [Figure 10]4 is a flow chart illustrating a method of operating a pixel according to an exemplary embodiment of the present disclosure. [Figure 11] 4 is a flow chart illustrating a method of operating a pixel according to an exemplary embodiment of the present disclosure. [Figure 12] 4 is a flow chart illustrating a method of operating a pixel according to an exemplary embodiment of the present disclosure. [Figure 13A] FIG. 2 illustrates a stack structure of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 13B] FIG. 2 illustrates a stack structure of an image sensor according to an exemplary embodiment of the present disclosure. [Figure 14A] FIG. 1 is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure. [Figure 14B] FIG. 1 is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure. [Figure 15] FIG. 1 is a block diagram that generally illustrates an electronic device including an image sensor according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0016] FIG. 1 is a block diagram of an image sensor according to an exemplary embodiment of the present disclosure.

[0017] The image sensor 100 may be mounted in an electronic device having an image sensing function or an optical sensing function. For example, the image sensor 100 may be mounted in electronic devices such as a camera, a smartphone, a wearable device, an Internet of things (IoT) device, a home appliance, a tablet PC (personal computer), a PDA (personal digital assistant), a PMP (portable multimedia player), a navigation device, a drone, and an advanced driver-assistance system (ADAS). The image sensor 100 may also be mounted in electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring devices, and the like.

[0018] 1, the image sensor 100 may include a pixel array 110, a row driver 120, a ramp signal generator 130, an analog-to-digital conversion circuit (hereinafter, referred to as an "ADC circuit") 140, a data output circuit 170, and a timing controller 180. The image sensor 100 may further include a signal processing unit 190. A configuration including the ramp signal generator 130, the ADC circuit 140, and the data output circuit 170 may be referred to as a readout circuit.

[0019] The pixel array 110 may include a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix.

[0020] Each of the pixels PX may include a plurality of photoelectric conversion elements, and the pixel PX may sense light using the photoelectric conversion elements and output an image signal, which is an electrical signal based on the sensed light. For example, the photoelectric conversion elements may include a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0021] Each of the pixels PX may be sensitive to light in a particular spectral region. For example, the pixels PX may include a red pixel for converting light in a red spectral region into an electrical signal, a green pixel for converting light in a green spectral region into an electrical signal, and a blue pixel for converting light in a blue spectral region into an electrical signal. However, without being limited thereto, the pixels may further include a white pixel. As another example, the pixels may include pixels combined with other color configurations, for example, a yellow pixel, a cyan pixel, and a magenta pixel.

[0022] A color filter array for transmitting light in a specific spectral region is disposed on the upper portion of the pixels PX, and the color filter disposed on the upper portion of each of the pixels PX may determine the hue that the pixel may sense. However, the present disclosure is not limited thereto. In some embodiments, the specific photoelectric conversion element may convert light in a specific wavelength band into an electrical signal depending on the level of the electrical signal applied to the photoelectric conversion element.

[0023] In one embodiment, each of the pixels PX has a pixel structure that can be operated by a global shutter mode and a rolling shutter mode, and the pixel array 110 can be operated by a global shutter mode or a rolling shutter mode. According to the global shutter mode, the exposure start time and exposure period of the pixels PX of the pixel array 110 are the same, and after the exposure period, the rows of the pixel array 110 are read sequentially, and according to the rolling shutter mode, the rows of the pixel array 110 are exposed sequentially and then read sequentially.

[0024] In an embodiment, each of the pixels PX may have a dual conversion gain. The dual conversion gain may include a low conversion gain and a high conversion gain. Here, the conversion gain refers to a ratio at which charges accumulated in the floating diffusion nodes FD1 and FD2 (FIG. 4) are converted into a voltage. Charges generated in the photoelectric conversion element are transferred to and accumulated in the floating diffusion nodes, and the charges accumulated in the floating diffusion nodes may be converted into a voltage by the conversion gain. At this time, the conversion gain may vary depending on the capacitance of the floating diffusion node, and if the capacitance increases, the conversion gain may decrease, and if the capacitance decreases, the conversion gain may increase.

[0025] In one embodiment, each of the multiple pixels PX may include at least two photodiodes, and the image sensor 100 may provide an autofocus function (AF) based on a pixel signal corresponding to the photocharges output from the at least two photodiodes.

[0026] The pixel PX according to the present disclosure may include a plurality of sub-pixels, and each sub-pixel may be connected to a corresponding floating diffusion node. According to an example, the pixel PX according to the present disclosure may simultaneously output the results of each of the sub-pixels operating in a rolling shutter manner, or may operate in a global shutter manner, bin the sub-pixels, and output them to separate output lines. The pixel structure of the pixels PX according to the technical idea of ​​the present disclosure will be described in detail with reference to FIG. 3 and subsequent figures.

[0027] The row driver 120 drives the pixel array 110 on a row-by-row basis. The row driver 120 may decode a row control signal (e.g., an address signal) received from the timing controller 180, and may select at least one row line constituting the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 may generate a selection signal for selecting one of a plurality of rows. The pixel array 110 may output a pixel signal, e.g., a pixel voltage, from a row selected by the selection signal provided by the row driver 120. The pixel signal may include a reset signal and an image signal. The row driver 120 may transmit a control signal for outputting the pixel signal to the pixel array 110, and the pixel PX may output the pixel signal by operating in response to the control signal.

[0028] The ramp signal generator 130 may generate a ramp signal (e.g., a ramp voltage) whose level rises and falls at a predetermined slope under the control of the timing controller 180. The ramp signal RAMP may be provided to each of a plurality of correlated double sampling (CDS) circuits 150 included in the ADC circuit 140.

[0029] The ADC circuit 140 may include a plurality of CDS circuits 150 and a plurality of counters 160. The ADC circuit 140 may convert pixel signals (e.g., pixel voltages) input from the pixel array 110 into pixel values ​​that are digital signals. Each pixel signal received via each of the plurality of column lines CL is converted into a pixel value that is a digital signal by the CDS circuit 150 and the counter 160.

[0030] The CDS circuit 150 may compare a pixel signal, e.g., a pixel voltage, received via a column line CL with a ramp signal RAMP, and output the comparison result as a comparison result signal. When the level of the ramp signal RAMP is the same as the level of the pixel signal, the CDS circuit 150 may output a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low). The point in time at which the level of the comparison signal transitions may be determined by the level of the pixel signal. Hereinafter, in this disclosure, for convenience of explanation, the first level will be represented as a high level, and the second level will be represented as a low level.

[0031] The CDS circuit 150 may sample a pixel signal provided from the pixel PX by a correlated double sampling (CDS) method. The CDS circuit 150 may sample a reset signal received as a pixel signal, compare the reset signal with a ramp signal RAMP, and generate a comparison signal according to the reset signal. Then, the CDS circuit 150 may sample an image signal correlated with the reset signal, compare the image signal with the ramp signal RAMP, and generate a comparison signal according to the image signal.

[0032] The counter 160 may count the time points of level transition of the comparison result signal output from the CDS circuit 150 based on a counting clock CNT_CLK provided by the timing controller 180, and output a count value.

[0033] In some embodiments, the counter 160 may be implemented by an up-counter whose count value is incremented sequentially based on a counting clock CNT_CLK, an arithmetic circuit, an up-down counter, or a bit-wise inversion counter.

[0034] In some embodiments, the image sensor 100 may further include a counting code generator that generates a counting code (e.g., Gray code) whose value changes periodically and provides the counting code to a plurality of counters 160, each of which may include a latch circuit and an arithmetic circuit. The latch circuit may latch a code value of the counting code at a time point when the level of the counting comparison signal transitions. The latch circuit may latch a code value corresponding to a reset signal, e.g., a reset value, and a code value corresponding to an image signal, e.g., an image signal value. The arithmetic circuit may perform an arithmetic operation between the reset value and the image signal value, and generate an image signal value from which the reset level of the pixel PX is removed. The counter 160 may output the image signal value from which the reset level is removed as a pixel value.

[0035] The data output circuit 170 may temporarily store and then output pixel values ​​output from the ADC circuit 140. The data output circuit 170 may include a plurality of column memories 171 (also referred to as buffers BF) and a column decoder 172. The column memories 171 store pixel values ​​received from the corresponding counters 160. In some embodiments, each of the plurality of column memories 171 may be included in the counter 160. The plurality of pixel values ​​stored in the plurality of column memories 171 may be output as image data IDTA under the control of the column decoder 171.

[0036] The timing controller 180 may output control signals to each of the row driver 120, the ramp signal generator 130, the ADC circuit 140, and the data output circuit 170, and control the operation or timing of the row driver 120, the ramp signal generator 130, the ADC circuit 140, and the data output circuit 170.

[0037] The signal processor 190 may perform noise reduction, gain adjustment, waveform shaping, interpolation, white balance, gamma adjustment, edge enhancement, binning, etc. on the image data IDTA. In some embodiments, the signal processor 190 may be included in an external processor located outside the image sensor 100.

[0038] 2A and 2B are timing diagrams illustrating the global shutter mode of operation and the rolling shutter mode of operation.

[0039] 1 and 2A, the image sensor 100 may operate in a global shutter mode.

[0040] One frame period FP may include a first period P1 and a second period P2, in which a plurality of pixels PX of the pixel array 110, in other words a plurality of rows (e.g., the first row R1 to the nth row Rn) of the pixel array 110 simultaneously perform a reset operation, an exposure operation, and a global signal dumping operation, in the first period P1, and a plurality of rows of the pixel array 110 may sequentially perform a read operation in the second period P2. The second period P2 may be referred to as a frame read-out period.

[0041] The first period P1 may include a reset period, an integration period, and a global signal dumping period (GSDP). The pixels PX perform a reset operation to remove charges accumulated in the photodiodes (and floating diffusion nodes) during the reset period, and perform an integration operation to generate and accumulate photocharges corresponding to the received optical signal in the photodiodes during the integration period. During the global signal dumping period (GSDP), the pixels PX may store a reset signal according to a reset level of the floating diffusion node and an image signal corresponding to the photocharges accumulated in the photodiodes in at least two capacitors provided therein.

[0042] In the second period P2, a rolling readout operation may be performed in which the readout operations performed during the readout period are performed sequentially by row. For example, after the readout operation for the first row R1 of the pixel array 110 is performed, the readout operation for the second row R2 may be performed. Then, after the readout operation for the second row R2 is performed, the readout operation for the third row R3 may be performed. During the readout operation, the reset signal and the image signal stored in at least two capacitors may be output from each pixel PX as a pixel signal during a global signal dumping period (GSDP).

[0043] 1 and 2B, the image sensor 100 may operate in a rolling shutter mode.

[0044] During one frame period FP, a number of rows (eg, the first row R1 through the n-th row Rn) of the pixel array 110 may sequentially perform a reset operation, an exposure operation, and a read-out operation.

[0045] The pixels PX of one row may perform a reset operation during the reset period, perform an accumulation operation during the accumulation period, and output a reset signal (e.g., reset voltage) corresponding to a reset level of the floating diffusion node and an image signal (e.g., image voltage) corresponding to photocharges generated in the photodiode as pixel signals during the readout period. The readout periods of the multiple rows of the pixel array 110 are not overlapped. After the readout period, the pixels PX of one row may further perform a reset operation after a waiting period. In one embodiment, the waiting period may be set so that the readout period in the next frame period of at least one row (e.g., the first row R1, the second row R2, etc.) that is read out early in the frame period FP does not overlap with the readout period in the current frame period of at least another row (e.g., the (n-1)th row Rn-1, the nth row Rn, etc.) that is read out late in the frame period FP.

[0046] As described above, the image sensor 100 according to the present disclosure may selectively operate in a global shutter mode or a rolling shutter mode. In one embodiment, an electronic device (e.g., an image processing device) in which the image sensor 100 is mounted may operate in a global shutter mode during high-speed video capture and in a rolling shutter mode during high-quality still image capture or low-speed video capture (in other words, when generating high-quality images). In one embodiment, the image sensor may operate in a rolling shutter mode in a high-illumination environment and in a global shutter mode in a low-illumination environment.

[0047] FIG. 3 is a block diagram illustrating a pixel according to an exemplary embodiment of the present disclosure.

[0048] The pixel PX in FIG. 3 may include a first subpixel 111, a second subpixel 112, a first rolling shutter operation circuit 113, a second rolling shutter operation circuit 114, a global selection switch circuit 115, and a global shutter operation circuit .

[0049] The first sub-pixel 111 may include a plurality of photoelectric conversion elements. According to an example, the plurality of photoelectric conversion elements included in the first sub-pixel 111 may be connected to a first floating diffusion node. The second sub-pixel 112 may include a plurality of photoelectric conversion elements. According to an example, the plurality of photoelectric conversion elements included in the second sub-pixel 112 may be connected to a second floating diffusion node. The first sub-pixel 111 and the second sub-pixel 112 may be disposed adjacent to each other.

[0050] In the present disclosure, at least one pair of photoelectric conversion elements and one pair of transfer transistors corresponding to the pair of photoelectric conversion elements may be referred to as one subpixel. For example, the first and second photodiodes, and the first and second transfer transistors may constitute a first subpixel 111, and the third and fourth photodiodes, and the third and fourth transfer transistors may constitute a second subpixel 112. In the present disclosure, each subpixel (the first subpixel 111, the second subpixel 112) may share a global selection switch circuit 115 and a global shutter operation circuit 116, as described later. Note that, in the present disclosure, the pixel PX is illustrated as including two subpixels (the first subpixel 111, the second subpixel 112), but is not limited thereto.

[0051] The first sub-pixel 111 and the second sub-pixel 112 included in the pixel PX of FIG. 3 may simultaneously operate in the rolling shutter mode. The first rolling shutter operation circuit 113 is connected to the first sub-pixel 111 and may operate the first sub-pixel 111 in the rolling shutter mode, and the second rolling shutter operation circuit 114 is connected to the second sub-pixel 112 and may operate the second sub-pixel 112 in the rolling shutter mode. According to an example, the first rolling shutter operation circuit 113 may include a first source follower transistor and a first rolling selection transistor. According to an example, the second rolling shutter operation circuit 114 may include a second source follower transistor and a second rolling selection transistor. The first rolling shutter operation circuit 113 and the second rolling shutter operation circuit 114 may each operate independently. The first rolling shutter operation circuit 113 may be connected to a first output line Vout1, and the second rolling shutter operation circuit 114 may be connected to a second output line Vout2. According to the present disclosure, the first rolling shutter operation circuit 113 and the second rolling shutter operation circuit 114 may output pixel signals according to their respective rolling shutter operations via separate output lines.

[0052] The global selection switch circuit 115 may be connected between the first rolling shutter operation circuit 113 and the second rolling shutter operation circuit 114. The global selection switch circuit 115 may include at least one transistor. According to the present disclosure, the global selection switch circuit 115 may be controlled to operate in a global shutter mode by turning on a transistor included in the global selection switch circuit 115. According to an example, the pixel PX of FIG. 3 may bin the first sub-pixel 111 and the second sub-pixel 112 and operate in the global shutter mode. The pixel PX according to the present disclosure may be used as a path that can operate in the global shutter mode via the global selection switch circuit 115.

[0053] The global shutter operation circuit 116 may be connected to an output terminal of the global selection switch circuit 115. The global shutter operation circuit 116 may control transistors included in the global shutter operation circuit 116 to operate in a global shutter mode when at least one transistor included in the global selection switch circuit 115 is turned on. The global shutter operation circuit 116 may be connected to a third output line Vout3. The global shutter operation circuit 116 may output a pixel signal based on the global shutter operation via the third output line Vout3.

[0054] The pixel PX according to the present disclosure may have a structure in which, in a binning mode scheme, an output line by a rolling shutter operation and an output line by a global shutter operation are formed by a total of three lines. According to one example, the pixel according to the present disclosure may have a total of three output lines, two output lines by two rolling shutter operations and one output line by a global shutter operation.

[0055] The pixel PX according to the present disclosure can operate in either a global shutter mode or a rolling shutter mode through the control of a plurality of transistors included in the pixel PX. The pixel PX according to the present disclosure can simultaneously output adjacent left and right pixels through separate output lines in a rolling shutter mode when one transfer control line is selected. The pixel PX according to the present disclosure can collectively read out the outputs of adjacent left and right pixels through a binning mode in a global shutter mode. According to the present disclosure, operation is possible without adding a transfer control line during full mode readout in the rolling shutter mode. That is, according to the present disclosure, adjacent photodiodes connected to one transfer control line can be simultaneously read out, which is economical and can perform various rolling shutter readout functions.

[0056] The circuit structure of a specific pixel PX according to the present disclosure will be described in detail below.

[0057] FIG. 4 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure.

[0058] 4, the pixel PXa may include a first sub-pixel 111a, a second sub-pixel 112a, a first rolling shutter operation circuit 113a, a second rolling shutter operation circuit 114a, a global selection switch circuit 115a, and a global shutter operation circuit 116a. According to an example, control signals are applied to a plurality of transistors included in the first rolling shutter operation circuit 113a, the second rolling shutter operation circuit 114a, the global selection switch circuit 115a, and the global shutter operation circuit 116a, and at least some of the control signals may be generated by the row driver 120.

[0059] Each of the first subpixel 111a and the second subpixel 112a may include a plurality of photodiodes. The first subpixel 111a may include eight photodiodes, and the second subpixel 112a may include eight photodiodes. The plurality of photodiodes PD may generate photocharges that vary according to the intensity of light. For example, the photodiode PD may generate charges, i.e., electrons that are negative charges and holes that are positive charges, in proportion to the amount of incident light. The number of photodiodes included in each of the first subpixel 111a and the second subpixel 112a is not limited to that shown in FIG. 4, and each of the first subpixel 111a and the second subpixel 112a may include two or more photodiodes.

[0060] Although not shown in FIG. 4, a transfer transistor may be connected to each of the photodiodes PD included in the first subpixel 111a and the second subpixel 112a. According to an example, the first transfer transistor may be connected between the photodiodes PD included in the first subpixel 111a and a first floating diffusion node FD1. A first terminal of the first transfer transistor may be connected to an output terminal of the photodiode PD, and a second terminal of the first transfer transistor may be connected to the first floating diffusion node FD1. The first transfer transistor may be turned on or off in response to a transfer control signal received from the row driver 120. When the first transfer transistor is turned on, it may transfer photocharges generated in the photodiode PD to the first floating diffusion node FD1. The number of first transfer transistors included in the first subpixel 111a may correspond to the number of photodiodes PD included in the first subpixel 111a.

[0061] According to an example, the second transfer transistor may be connected between the photodiodes PD included in the second sub-pixel 112a and a second floating diffusion node FD2. A first terminal of the second transfer transistor may be connected to an output terminal of the photodiode PD, and a second terminal of the second transfer transistor may be connected to the second floating diffusion node FD2. The second transfer transistor may be turned on or off in response to a transfer control signal received from the row driver 120. The second transfer transistor may be turned on to transfer photocharges generated in the photodiode PD to the second floating diffusion node FD2. The number of second transfer transistors included in the second sub-pixel 112a may correspond to the number of photodiodes PD included in the second sub-pixel 112a.

[0062] The first rolling shutter operation circuit 113a may include a first reset transistor RX1, a first conversion gain control transistor DCG1, a second conversion gain control transistor DCG2, a first source follower transistor SF1, and a first rolling selection transistor RSEL1. The first reset transistor RX1 may reset charges accumulated in a first floating diffusion node FD1. A pixel voltage VPIX may be applied to a first terminal of the first reset transistor RX1, and a second terminal of the first reset transistor RX1 may be connected to a first terminal of the second conversion gain control transistor DCG2. The first reset transistor RX1 may be turned on or off in response to a reset control signal received from the row driver 120. When the first reset transistor RX1, the first conversion gain control transistor DCG1, and the second conversion gain control transistor DCG2 are turned on, charges accumulated in the first floating diffusion node FD1 may be discharged and the first floating diffusion node FD1 may be reset.

[0063] The first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2 may adjust the conversion gain of the first sub-pixel 111a. Here, the conversion gain refers to a ratio at which the charge accumulated in the first floating diffusion node FD1 is converted into a voltage. The conversion gain varies depending on the capacitance of the first floating diffusion node FD1, and if the capacitance increases, the conversion gain may be lower, and if the capacitance decreases, the conversion gain may be higher.

[0064] The first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2 are turned on or off in response to a gain control signal, and when the first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2 are turned on, the capacitance of the first floating diffusion node FD1 increases and the conversion gain may be low, and when the first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2 are turned off, the capacitance of the first floating diffusion node FD1 decreases and the conversion gain may be high. Therefore, depending on whether the first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2 are turned on or off, the first subpixel 111a may operate in a high conversion gain HCG mode or a low conversion gain LCG mode. In other words, the first subpixel 111a operates in a dual conversion gain mode, and the conversion gain mode can be determined by turning on / off the first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2.

[0065] A pixel voltage VPIX may be applied to a first terminal of the first source follower transistor SF1, and a second terminal of the first source follower transistor SF1 may be connected to a first output node N1. The first source follower transistor SF1 may be a buffer amplifier and may buffer a signal according to the amount of charge stored in the first floating diffusion node FD1. The potential of the first floating diffusion node FD1 may change according to the amount of charge stored in the first floating diffusion node FD1, and the first source follower transistor SF1 may amplify the potential change in the first floating diffusion node FD1 and output it to the first output node N1. The first source follower transistor SF1 may operate as a source follower and output a voltage corresponding to the voltage of the first floating diffusion node FD1 to the first output node N1.

[0066] A first terminal of the first rolling selection transistor RSEL1 may be connected to the first source follower transistor SF1, and a second terminal of the first rolling selection transistor RSEL1 may be connected to a first output line Vout1. The first rolling selection transistor RSEL1 may be turned on or off in response to a first rolling selection control signal. When the first rolling selection transistor RSEL1 is turned on, a voltage corresponding to the first output node N1 may be output to the first output line Vout1. At this time, the output voltage may be output in a rolling shutter manner.

[0067] The second rolling shutter operation circuit 114a may include a second reset transistor RX2, a third conversion gain control transistor DCG3, a fourth conversion gain control transistor DCG4, a second source follower transistor SF2, and a second rolling selection transistor RSEL2. The operation of the second reset transistor RX2 may correspond to the operation of the first reset transistor RX1, and the operations of the third conversion gain control transistor DCG3 and the fourth conversion gain control transistor DCG4 may correspond to the operations of the first conversion gain control transistor DCG1 and the second conversion gain control transistor DCG2. The operation of the second source follower transistor SF2 may correspond to the operation of the first source follower transistor SF1, and the operation of the second rolling selection transistor RSEL2 may correspond to the operation of the first rolling selection transistor RSEL1, so that overlapping explanations will be omitted.

[0068] The first rolling shutter operation circuit 113a may control the output of the photodiode included in the first subpixel 111a to be output in a shutter operation mode, and the second rolling shutter operation circuit 114a may control the output of the photodiode included in the second subpixel 112a to be output in a shutter operation mode. The first rolling shutter operation circuit 113a may output the output of the photodiode included in the first subpixel 111a through a first output line Vout1, and the second rolling shutter operation circuit 114a may output the output of the photodiode included in the second subpixel 112a through a second output line Vout2. The first rolling shutter operation circuit 113a and the second rolling shutter operation circuit 114a according to the present disclosure may output the outputs of the subpixels connected to the respective rolling shutter operation circuits through separate output lines Vout1 and Vout2, and may simultaneously output the rolling shutter mode operation results between adjacent subpixels. That is, according to the present disclosure, the output lines of the first rolling shutter operation circuit 113a and the second rolling shutter operation circuit 114a can be separated to simultaneously output the processing results of adjacent sub-pixels.

[0069] The global selection switch circuit 115a may be disposed between the first rolling shutter operation circuit 113a and the second rolling shutter operation circuit 114a. The global selection switch circuit 115a may be connected between a first output node N1 of the first rolling shutter operation circuit 113a and a second output node N2 of the second rolling shutter operation circuit 114a. The first output node N1 is a node between the first source follower transistor SF1 and the first rolling selection transistor RSEL1. The second output node N2 is a node between the second source follower transistor SF2 and the second rolling selection transistor RSEL2. The global selection switch circuit 115a may include a first global selection switch transistor GSS1 and a second global selection switch transistor GSS2. One end of the first global selection switch transistor GSS1 may be connected to the first output node N1, and the other end of the first global selection switch transistor GSS1 may be connected to a third output node N3 of the global shutter operation circuit 116a. One end of the second global selection switch transistor GSS2 may be connected to the second output node N2, and the other end of the second global selection switch transistor GSS2 may be connected to the third output node N3 of the global shutter operation circuit 116a. The first global selection switch transistor GSS1 and the second global selection switch transistor GSS2 may be operated by the same control signal. According to an example, the first global selection switch transistor GSS1 and the second global selection switch transistor GSS2 may be turned on or off in response to a global selection control signal. When the first global selection switch transistor GSS1 and the second global selection switch transistor GSS2 are turned on, the first output node N1 and the second output node N2 may be connected to the third output node N3 of the global shutter operation circuit 116a, and the output of the first sub-pixel 111a and the output of the second sub-pixel 112a may be controlled to be read out by a global shutter operation.

[0070] The global shutter operation circuit 116a may include a precharge transistor PCX. A first terminal of the precharge transistor PCX may be connected to a third output node N3, and a second terminal of the precharge transistor PCX may be connected to a precharge selection transistor PSX. The third output node N3 is a node where the global shutter operation circuit 116a and the global selection switch circuit 115a are connected. The precharge transistor PCX may precharge the third output node N3 in response to a precharge control signal PC received from the row driver 120.

[0071] The global shutter operation circuit 116a may include a precharge selection transistor PSX. A first terminal of the precharge selection transistor PSX may be connected to the precharge transistor PCX, and a ground voltage may be applied to a second terminal of the precharge selection transistor PSX. The precharge selection transistor PSX may be turned on or off in response to a precharge selection control signal PCSEL received from the row driver 120, and may reset the third output node N3. The precharge transistor PCX and the precharge selection transistor PSX may be connected in series. According to an example, the precharge transistor PCX and the precharge selection transistor PSX are a precharge circuit.

[0072] The global shutter operation circuit 116a may include a first sampling transistor SMP1. A first terminal of the first sampling transistor SMP1 may be coupled to a third output node N3, and a second terminal of the first sampling transistor SMP1 may be coupled to a first capacitor C1. In response to a first sampling control signal received from the row driver 120, the first sampling transistor SMP1 may be turned on or off to couple the first capacitor C1 to the third output node N3.

[0073] A pixel voltage VPIX may be applied to a first terminal of the first capacitor C1, and a second terminal of the first capacitor C1 may be connected to the first sampling transistor SMP1. Charge may be stored in the first capacitor C1 due to a switching operation of the first sampling transistor SMP1. For example, charge may be stored in the first capacitor C1 due to a reset operation in which the first floating diffusion node FD1 and / or the second floating diffusion node FD2 are reset.

[0074] The global shutter operation circuit 116a may include a second sampling transistor SMP2. A first terminal of the second sampling transistor SMP2 may be coupled to a third output node N3, and a second terminal of the second sampling transistor SMP2 may be coupled to a second capacitor C2. In response to a second sampling control signal received from the row driver 120, the second sampling transistor SMP2 may be turned on or off to couple the second capacitor C2 to the third output node N3.

[0075] A pixel voltage VPIX may be applied to a first terminal of the second capacitor C2, and a second terminal of the second capacitor C2 may be connected to the second sampling transistor SMP2. Charges may be stored in the second capacitor C2 by a switching operation of the second sampling transistor SMP2. For example, charges may be stored in the second capacitor C2 by a photocharge accumulation operation in which photocharges generated in the photodiode PD are accumulated in the first floating diffusion node FD1 and / or the second floating diffusion node FD2.

[0076] The global shutter operation circuit 116a may include a third sampling transistor SMP3. A first terminal of the third sampling transistor SMP3 may be coupled to a third output node N3, and a second terminal of the third sampling transistor SMP3 may be coupled to a third capacitor C3. In response to a third sampling control signal received from the row driver 120, the third sampling transistor SMP3 may be turned on or off to couple the third capacitor C3 to the third output node N3.

[0077] A pixel voltage VPIX may be applied to a first terminal of the third capacitor C3, and a second terminal of the third capacitor C3 may be connected to the third sampling transistor SMP3. A charge may be stored in the third capacitor C3 by a switching operation of the third sampling transistor SMP3. For example, charges due to an AF operation of the first sub-pixel 111a and the second sub-pixel 112a may be stored in the third capacitor C3. According to an example, a signal corresponding to a photodiode located on the left side of the first sub-pixel 111a and the second sub-pixel 112a may be primarily transferred to the global shutter operation circuit 116a, and a signal corresponding to a photodiode located on the right side of the first sub-pixel 111a and the second sub-pixel 112a may be secondarily transferred to the global shutter operation circuit 116a, thereby sampling AF signals corresponding to the left / right directions, respectively. According to one example, a transfer transistor corresponding to a photodiode located on the left side of the first subpixel 111a and the second subpixel 112a may be controlled to be turned on to store a left AF signal, and a transfer transistor corresponding to a photodiode located on the right side of the first subpixel 111a and the second subpixel 112a may be controlled to be turned on to store a right AF signal.

[0078] According to an example, the first sampling transistor SMP1, the second sampling transistor SMP2, the third sampling transistor SMP3, the first capacitor C1, the second capacitor C2, and the third capacitor C3 may operate as a sampling circuit for sampling a voltage output via the third output node N3 when the pixel PXa operates in a global shutter mode. According to an example, the first sampling transistor SMP1, the second sampling transistor SMP2, the third sampling transistor SMP3, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are the sampling circuit.

[0079] The global shutter operation circuit 116a may include a third source follower transistor SF3 and a global selection transistor GSEL. A pixel voltage VPIX may be applied to a first terminal of the third source follower transistor SF3, and a second terminal of the third source follower transistor SF3 may be connected to the global selection transistor GSEL. The third source follower transistor SF3 may amplify and output a potential change at a third output node N3.

[0080] A first terminal of the global selection transistor GSEL may be coupled to the third source follower transistor SF3, and a second terminal of the global selection transistor GSEL may be coupled to a third output line Vout3. The global selection transistor GSEL may be turned on or off in response to a selection control signal received from the row driver 120. When the global selection transistor GSEL is turned on, a reset signal corresponding to a reset operation, an image signal corresponding to a charge accumulation operation, or an AF signal corresponding to an AF operation may be output to the third output line Vout3.

[0081] That is, the third source follower transistor SF3 and the global selection transistor GSEL output a pixel signal due to a potential change at the third output node N3 to the third output line Vout3, and may output a pixel signal corresponding to one of the amount of charge stored in the first capacitor C1, the amount of charge stored in the second capacitor C2, and the amount of charge stored in the third capacitor C3 via the third output line Vout3.

[0082] 5A and 5B illustrate the global shutter mode and rolling shutter mode readout operations of a pixel according to an exemplary embodiment of the present disclosure.

[0083] 5A, when the pixel PXa operates in a rolling shutter mode, during a readout period, the first rolling selection transistor RSEL1 may be turned on, the second rolling selection transistor RSEL2 may be turned on, and the first global selection switch transistor GSS1 and the second global selection switch transistor GSS2 may be turned off, so that the charges accumulated in the first floating diffusion node FD1 and the charges accumulated in the second floating diffusion node FD2 may be simultaneously outputted through the first output line Vout1 and the second output line Vout2, respectively.

[0084] 5B, when pixel PXa operates in the global shutter mode, the first rolling selection transistor RSEL1 may be turned off, the second rolling selection transistor RSEL2 may be turned off, and the first global selection switch transistor GSS1 and the second global selection switch transistor GSS2 may be turned on, so that the reset voltage, the image voltage, and the AF voltage stored in the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be output as a pixel signal to the third output line Vout3 via the global selection transistor GSEL during the global signal dumping period.

[0085] According to one example, when the pixel PXa operates in the global shutter mode, the outputs of the photodiodes included in the first subpixel 111a and the second subpixel 112a may be binned, and outputs corresponding to all the photodiodes included in the pixel PXa may be output in the global shutter mode. According to one example, the pixel PXa may operate in the 4-SUM mode. According to one example, the pixel PXa may operate in the 2-SUM mode. According to one example, when the pixel PXa includes two subpixels as in the present disclosure, binning the two subpixels and operating in the global shutter mode may mean operating in the 2-SUM mode. According to another example, when the pixel PXa includes four subpixels, binning the four subpixels and operating in the global shutter mode may mean operating in the 4-SUM mode.

[0086] FIG. 6 is a diagram for explaining an arrangement structure of components included in a pixel according to an exemplary embodiment of the present disclosure.

[0087] In FIG. 6, the description of the parts that overlap with those described in FIG. 4 will be omitted. Referring to FIG. 6, the first rolling shutter operation circuit 113a and the global selection switch circuit 115a may be connected via metal-to-metal bonding (C2C: chip-to-chip). Referring to FIG. 6, the second rolling shutter operation circuit 114a and the global selection switch circuit 115a may be connected via metal-to-metal bonding (C2C). According to an example, the metal may be copper (Cu). However, the metal is not limited to Cu.

[0088] 6, the first substrate Sub1 and the second substrate Sub2 may be separated based on metal-to-metal bonding (C2C). The first substrate Sub1 and the second substrate Sub2 may be electrically connected through metal-to-metal bonding (C2C). The first substrate Sub1 and the second substrate Sub2 are stacked on top of each other.

[0089] Referring to FIG. 6, based on metal-to-metal bonding (C2C), components in the upper direction may be disposed on a first substrate Sub1, and components in the lower direction may be disposed on a second substrate Sub2.

[0090] According to one example, the first subpixel 111a, the second subpixel 112a, the first rolling shutter operation circuit 113a, and the second rolling shutter operation circuit 114a may be arranged on a first substrate Sub1, and the global selection switch circuit 115a and the global shutter operation circuit 116a may be arranged on a second substrate Sub2.

[0091] In the description of FIG. 6, the configuration of the metal-to-metal bonding (C2C) is not a circuit component included in the pixel circuit, but for convenience of description, it will be described as being included in the pixel circuit diagram in FIG. 7 to FIG. 9 described later. The meaning of the metal-to-metal bonding (C2C) illustrated in the circuit diagrams of FIG. 7 to FIG. 9 described later may mean that the components disposed on both ends of the metal-to-metal bonding (C2C) are disposed on different substrates based on the metal-to-metal bonding (C2C) component. Also, it may mean that the components disposed on different substrates may be electrically connected through the metal-to-metal bonding (C2C). In the present disclosure, the metal-to-metal bonding (C2C) may be expressed as a C2C structure.

[0092] Fig. 7 is a circuit diagram showing a pixel according to an exemplary embodiment of the present disclosure. In the description of Fig. 7, the same configuration as that of the circuit described in Fig. 4 will be omitted. Referring to pixel PXb in Fig. 7, the configuration of global selection switch circuit 115b is different from that in Fig. 4.

[0093] The global selection switch circuit 115b may include a first global selection switch transistor GSS3 and a second global selection switch transistor GSS4. One end of the first global selection switch transistor GSS3 may be connected to the first output node N1, and the other end of the first global selection switch transistor GSS3 may be connected to the third output node N3. One end of the second global selection switch transistor GSS4 may be connected to the second output node N2, and the other end of the second global selection switch transistor GSS4 may be connected to the third output node N3. According to an example, the first global selection switch transistor GSS3 and the second global selection switch transistor GSS4 may be turned on or off by different control signals.

[0094] 7, the global selection switch circuit 115b may be disposed on the first substrate Sub1, and the global shutter operation circuit 116b may be disposed on the second substrate Sub2. Since the global selection switch circuit 115b is disposed on the first substrate Sub1, only one metal-to-metal bonding (C2C) is provided to be connected to the output terminal of the global selection switch circuit 115b, and the number of metal-to-metal bonding (C2C) may be reduced compared to the embodiment of FIG.

[0095] FIG. 8 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure.

[0096] In the description of Fig. 8, description will be omitted for configurations that are the same as those of the circuits described in Fig. 4. Referring to pixel PXc in Fig. 8, the configuration of a global selection switch circuit 115c is different from that in Fig. 4.

[0097] 8 may include a global select switch transistor GSS5. One end of the global select switch transistor GSS5 may be coupled to a first output node N1, and the other end of the global select switch transistor GSS5 may be coupled to a second output node N2. The global select switch transistor GSS5 may be turned on or off by a global select control signal.

[0098] 8, the global select switch circuit 115c may include only one global select switch transistor, and according to the embodiment of FIG 8, only one metal-to-metal bonding (C2C) may be provided that is connected to the output terminal of the global select switch circuit 115c.

[0099] FIG. 9 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present disclosure.

[0100] In the description of Fig. 9, description will be omitted for configurations that are the same as those of the circuits described in Fig. 4. Referring to pixel PXd in Fig. 9, the configuration of a global shutter operation circuit 116d is different from that in Fig. 4.

[0101] The global shutter operating circuit 116d may further include a capacitor control transistor CTR. According to an example, the capacitor control transistor CTR may be connected between a third output node N3 and a fourth output node N4. According to an example, the fourth output node N4 is a node to which the first sampling transistor SMP1, the second sampling transistor SMP2, and the third sampling transistor SMP3 are all connected.

[0102] The capacitor control transistor CTR may be turned on or off to reset the fourth output node N4 in response to a capacitor control signal received from the row driver 120. The fourth output node N4 may have a parasitic capacitance.

[0103] 9, pixel PXd is illustrated as including one capacitor adjustment transistor CTR, but the present disclosure is not so limited. Pixel PXd may include various numbers of capacitor adjustment transistors CTR as transistors for resetting fourth output node N4.

[0104] 10-12 are flow charts illustrating a method of operating a pixel according to an exemplary embodiment of the present disclosure.

[0105] 10, in operation S100, the image sensor may receive a mode setting signal. According to one example, the mode setting signal may be received from an application processor AP of FIG. 14A, which will be described later.

[0106] In step S200, based on the received mode setting signal, the image sensor may operate in a global shutter mode or a rolling shutter mode during the readout period. According to one example, the image sensor may operate in a global shutter mode and read out pixels, or may operate in a rolling shutter mode and read out pixels.

[0107] In step S300, the image sensor may output a readout result according to the global shutter mode or the rolling shutter mode determined in step S200.

[0108] The flowcharts shown in Figures 11 and 12 are steps that may be included in step S200 of Figure 10. Figure 11 is a flowchart when the image sensor operates in a rolling shutter mode. Figure 12 is a flowchart when the image sensor operates in a global shutter mode.

[0109] Referring to step S210 of FIG. 11, the image sensor may be determined to operate in the rolling shutter mode according to the received mode setting signal. Referring to step S211, the readout circuit may generate a control signal for turning on a first rolling selection transistor included in the first rolling shutter operating circuit and a second rolling selection transistor included in the second rolling shutter operating circuit, and apply the control signal to the pixel. Thereby, the outputs of the first sub-pixel connected to the first rolling shutter operating circuit and the second sub-pixel connected to the second rolling shutter operating circuit may be read out in the rolling shutter mode. Referring to step S212, the readout circuit may generate a control signal for turning off a transistor included in the global selection switch circuit, and apply the control signal to the pixel. Thereby, the image sensor may be blocked from operating in the global shutter mode. Referring to step S213, an output of a first rolling shutter operating circuit, for example, a reset voltage, an image voltage, or an AF voltage, may be output as a pixel signal to a first output line, and an output of a second rolling shutter operating circuit, for example, a reset voltage, an image voltage, or an AF voltage, may be output as a pixel signal to a second output line, respectively, at the same time.

[0110] Referring to step S220 of FIG. 12, the image sensor may be determined to operate in the global shutter mode according to the received mode setting signal. Referring to step S221, the readout circuit may generate a control signal for turning off a first rolling selection transistor included in the first rolling shutter operation circuit and a second rolling selection transistor included in the second rolling shutter operation circuit, and apply the control signal to the pixel. Through this, the image sensor may be blocked from operating in the rolling shutter mode. Referring to step S222, the readout circuit may generate a control signal for turning on a transistor included in the global selection switch circuit, and apply the control signal to the pixel. Through this, the image sensor may operate in the global shutter mode and read out a result output of binning the first sub-pixel and the second sub-pixel. Referring to step S223, the output of the global shutter operation circuit, for example, a reset voltage, an image voltage, or an AF voltage, may be output as a pixel signal through a third output line.

[0111] According to the present disclosure, in an image sensor including a pixel operable in each of a global shutter mode and a rolling shutter mode, a hybrid readout may be possible by separately processing output lines when operating in the global shutter mode and when operating in the rolling shutter mode. According to one example, the pixel of the present disclosure includes at least two or more sub-pixels, and in the global shutter mode, it operates in a binning mode in which the outputs of the two or more sub-pixels are combined, and in the rolling shutter mode, it may output the outputs of the sub-pixels separately through output lines connected to each other.

[0112] 13A and 13B show a stack structure of an image sensor according to an exemplary embodiment of the present disclosure.

[0113] 13A, the image sensor 1 may include an upper chip 40 and a lower chip 50. The upper chip 40 may include a sensing area SA in which a plurality of pixels PX are provided, a circuit area LC in which elements for driving the plurality of pixels PX are provided, and a pad area PA1 around the sensing area SA and the circuit area LC. A plurality of upper pads PAD may be arranged in the pad area PA1, and the plurality of upper pads PAD may be connected to elements provided in the lower chip 50 through vias or the like.

[0114] The lower chip 50 includes a circuit region LC and a pad region PA2 around the circuit region LC. In the circuit region LC, peripheral circuits of the pixel array 110 (FIG. 1), such as the row driver 120, the ADC circuit 140, the ramp signal generator 130, the timing controller 180, and the signal processing unit 190, may be formed. In one embodiment, the lower chip 50 may include a memory region and a dummy region. The memory region may include memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices. However, the memory devices in the memory region are not limited to DRAM devices or SRAM devices. The dummy region may support the upper chip 40, but may not store data. According to one embodiment, the upper chip 40 and the lower chip 50 may be connected by metal-to-metal bonding (C2C).

[0115] 13B, the image sensor 2 may include a plurality of stacked chips. For example, the pixel array 110 may be formed in the upper chip 40 and the middle chip 50, and the peripheral circuit of the pixel array 110 or a memory may be formed in the lower chip 60. According to an example, a first subpixel, a second subpixel, a first rolling shutter operating circuit, and a second rolling shutter operating circuit of a pixel may be formed in the upper chip 40, and a global selection switch circuit and a global shutter operating circuit may be formed in the middle chip 50. According to an example, the upper chip 40 and the middle chip 50 may be connected by metal-to-metal bonding (C2C). The lower chip 60 may include a circuit region LC, and the peripheral circuit of the pixel array 110 (FIG. 1) may be formed in the circuit region LC. In an embodiment, the lower chip 60 may include a memory region and a dummy region.

[0116] In one embodiment, the top chip 40 and the middle chip 50 may be stacked together at the wafer level, and the bottom chip 60 may be attached to the bottom of the middle chip 50 at the chip level.

[0117] 14A and 14B are block diagrams illustrating an electronic device according to an exemplary embodiment of the present disclosure.

[0118] 14A and 14B, an electronic device 1000a, 1000b may include an image sensor 1100 and an application processor (AP) 1200. According to one example, the electronic device is an image processing device.

[0119] The application processor 1200 may transmit a control signal to the image sensor 1000 for controlling the operation of the image sensor 1100. The control signal may include, for example, setting information SET_IF for setting an operation mode, a shuttering mode, a conversion gain mode, etc. of the image sensor 1100. The setting information SET_IF may be a mode setting signal. The transmission of the control signal may be performed based on an interface based on, for example, I2C (Inter-Integrated Circuit). The control signal may further include configuration data of the image sensor 1100, such as a lens shading correction value, a crosstalk coefficient, an analog gain, a digital gain, and a frame rate setting value.

[0120] The image sensor 1100 may capture an object based on the received control signal and generate image data IDTA. The image data IDTA may include still images and moving images. The image sensor 1100 may perform signal processing such as image quality compensation, binning, and downsizing on the image data IDTA. The image quality compensation may include signal processing such as black level compensation, lens shading compensation, crosstalk compensation, and bad pixel correction.

[0121] The pixel array 110 (FIG. 1) of the image sensor 1100 may operate in a global shutter mode or a rolling shutter mode. The pixel array 110 may also operate in a high conversion gain mode, a low conversion gain mode, or a dual conversion gain mode. In one embodiment, at least some of the pixels of the pixel array 110 may be focus pixels for generating autofocus data. The focus pixels may include a pair of photodiodes.

[0122] In one embodiment, each of the pixels of the pixel array 110 may include a plurality of sub-pixels. Each of the sub-pixels may include a pair of photodiodes and a pair of transfer transistors coupled to each of the pair of photodiodes. The pixel array 110 may operate in a binning mode or a full mode, and may shutter using a global shutter scheme when operating in the binning mode, and may shutter using a rolling shutter scheme when operating in the full mode.

[0123] In one embodiment, sub-pixels included in each of the multiple pixels of the pixel array 110 may be shuttered by a rolling shutter method, and outputs resulting from the shuttering may be simultaneously output through output lines connected separately to each other.

[0124] The image sensor 1100 may transmit the image data IDTA or the signal-processed image data IDTA to the application processor 1200. The transmission of the image data IDTA may be performed using, for example, a camera serial interface (CSI) based on a Mobile Industry Processor Interface (MIPI), but the present embodiment is not limited thereto.

[0125] The application processor 1200 may perform image processing such as bad pixel correction, 3A adjustment (auto-focus correction, auto-white balance, auto-exposure), noise reduction, sharpening, gamma control, remosaic, demosaic, and resolution scaling (video / preview) on the received image data IDTA.

[0126] In addition, the application processor 1200 can perform high dynamic range (HDR) processing on a plurality of image data IDTAs having different luminance levels to generate an image having a high dynamic range.

[0127] 14B, the electronic device 1000b may further include an illuminance sensor 1300. The illuminance sensor 1300 may sense the ambient illuminance of the electronic device 1000b and transmit information related to the ambient illuminance to the application processor 1200.

[0128] The application processor 1200 may determine the operation mode, shuttering mode, conversion gain mode, etc., of the image sensor 1100 based on the illuminance information. For example, the application processor 1200 may determine that the image sensor 1100 operates in a global shutter mode when the illuminance is less than a reference value, and may determine that the image sensor 1100 operates in a rolling shutter mode when the illuminance is equal to or greater than the reference value. For example, the application processor 1200 may determine that the image sensor 1100 operates in a binning mode when the illuminance is less than a reference value, and may determine that the image sensor 1100 operates in a full mode when the illuminance is equal to or greater than the reference value.

[0129] In one embodiment, sub-pixels included in each of a plurality of pixels of a pixel array 110 included in the image sensor 1100 may be shuttered using a rolling shutter method, and the resulting outputs may be output simultaneously via output lines connected separately to each other.

[0130] 15 is a block diagram illustrating an electronic device including an image sensor according to an exemplary embodiment of the present disclosure. The electronic device 2000 of FIG. 15 may be a portable terminal.

[0131] 15, the electronic device 2000 may include an application processor 2100, a camera module 2200, a display device 2600, a working memory 2300, a storage 2400, and a user interface 2500. The electronic device 2000 may further include other general-purpose components, such as a communication module, a sensor module, and the like.

[0132] The application processor 2100 may be implemented as a system-on-chip (SoC) that controls the overall operation of the electronic device 2000 and runs an application program, an operating system (OS), etc. The application processor 2100 may provide image data provided from the camera module 2200 to the display device 2600 or store the image data in the storage 2400. In one embodiment, the application processor 2100 includes an image processing circuit and may perform image processing such as image quality adjustment, data format conversion, and high dynamic range (HDR) processing on the image data received from the camera module 2200.

[0133] The camera module 2200 may include a plurality of cameras, for example, a first camera 2210 and a second camera 2220. The first camera 2210 and the second camera 2210 may each include an image sensor (a first image sensor 2211 and a second image sensor 2221). At least one of the first image sensor 2211 and the second image sensor 2221 may be implemented by the image sensor described with reference to FIGS. 1 to 9. At least one of the first image sensor 2211 and the second image sensor 2221 may selectively perform shuttering in a rolling shutter manner (rolling shutter mode) or a global shutter manner (global shutter mode). At least one of the first image sensor 2211 and the second image sensor 2221 may operate in a binning mode or a full mode, and may perform shuttering in the global shutter manner when operating in the binning mode, and may perform shuttering in the rolling shutter manner when operating in the full mode.

[0134] In one embodiment, sub-pixels included in each of a plurality of pixels of the pixel array 110 included in at least one of the first image sensor 2211 and the second image sensor 2221 may be shuttered using a rolling shutter method, and the resulting outputs may be output simultaneously through output lines connected separately to each other.

[0135] The working memory 2300 may be implemented by a volatile memory such as a DRAM or an SRAM, or a non-volatile resistive memory such as a ferroelectric random access memory (FeRAM), a resistive random access memory (RRAM), or a phase-change random access memory (PRAM). The working memory 2300 may store programs and / or data to be processed or executed by the application processor 2100.

[0136] The storage 2400 may be implemented by a non-volatile memory device such as a NAND flash or a resistive memory, and may be provided as a memory card (MMC, eMMC, SD, micro SD), etc. The storage 2400 may store image data provided by the camera module 2200.

[0137] The user interface 2700 may be embodied by a variety of devices capable of receiving user input, such as a keyboard, a curtain key panel, a touch panel, a fingerprint sensor, a microphone, etc. The user interface 2700 may receive the user input and provide a signal corresponding to the received user input to the application processor 2100.

[0138] As above, exemplary embodiments have been disclosed with the drawings and the specification. In this specification, specific terms are used to describe the embodiments, but they are only used for the purpose of describing the technical idea of ​​the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure is defined by the technical idea of ​​the claims. [Explanation of symbols]

[0139] 100,1100 Image sensor 110 pixel array 111 1st subpixel 112 2nd subpixel 113 First rolling shutter operating circuit 114 Second rolling shutter operating circuit 115 Global selection switch circuit 116 Global shutter operation circuit 120 Row Driver 130 Ramp Signal Generator 140 Analog-to-Digital Conversion Circuit 150 CDS circuit 160 Counter 170 Data output circuit 171 Column Memory 172 Column Decoder 180 Timing Controller 190 Signal Processing Section 1000a,1000b,2000 Electronic equipment 1200,2100 Application Processor 1300 Light Sensor 2200 Camera Module 2210,2220 Camera 2300 Working Memory 2400 Storage 2500 User Interface 2600 display station PX

Claims

1. In an image sensor including a pixel array in which a plurality of pixels are arranged, Each of the plurality of pixels comprises: a first sub-pixel sharing a first floating diffusion node; a second sub-pixel sharing the second floating diffusion node; a first rolling shutter operation circuit configured to read out the photocharges accumulated in the first floating diffusion node by a rolling shutter method; a second rolling shutter operation circuit configured to read out the photocharges accumulated in the second floating diffusion node by a rolling shutter method; a global selection switch circuit coupled between the first rolling shutter operating circuit and the second rolling shutter operating circuit, the global selection switch circuit including at least one transistor; a global shutter operation circuit connected to one end of the global selection switch circuit and configured to read out the photocharges accumulated in the first floating diffusion node and the second floating diffusion node in a global shutter manner.

2. the first rolling shutter operating circuit is connected to a first output line; the second rolling shutter operating circuit is connected to a second output line; The image sensor of claim 1 , wherein the global shutter operating circuit is coupled to a third output line.

3. The first rolling shutter operation circuit includes: a first source follower transistor that amplifies and outputs a voltage of the first floating diffusion node; a first rolling select transistor connected in series with the first source follower transistor; The second rolling shutter operation circuit includes: a second source follower transistor that amplifies and outputs a voltage of the second floating diffusion node; 2. The image sensor of claim 1, further comprising: a second rolling select transistor coupled in series with the second source follower transistor.

4. The global selection switch circuit comprises: The image sensor of claim 3 , further comprising: a first node included in the first rolling shutter operation circuit and a second node included in the second rolling shutter operation circuit, the first node being coupled between the first node and the second node.

5. the first node is a node between the first source follower transistor and the first rolling select transistor; The image sensor of claim 4 , wherein the second node is a node between the second source follower transistor and the second rolling select transistor.

6. The transistors included in the global selection switch circuit include The image sensor according to claim 4 , configured to be connected with the first node at one end and the second node at the other end.

7. The global selection switch circuit comprises: a first global selection switch transistor connected to the first node as one end; 5. The image sensor of claim 4, further comprising: a second global selection switch transistor having one end connected to the second node.

8. 8. The image sensor of claim 7, wherein the other end of the first global selection switch transistor and the other end of the second global selection switch transistor are connected to the global shutter operating circuit.

9. 9. The image sensor of claim 8, wherein the control signal input to the gate of the first global selection switch transistor and the gate of the second global selection switch transistor are the same signal.

10. 9. The image sensor of claim 8, wherein the control signals input to the gate of the first global select switch transistor and the gate of the second global select switch transistor are different signals.

11. The global shutter operation circuit includes: a precharge circuit connected to an output terminal of the global selection switch circuit; 2. The image sensor of claim 1, further comprising: a sampling circuit coupled to an output terminal of the global selection switch circuit, the sampling circuit comprising one or more capacitors.

12. The global shutter operation circuit includes:

12. The image sensor of claim 11, further comprising a capacitor adjustment transistor coupled between the sampling circuit and the precharge circuit.

13. The image sensor includes a first substrate and a second substrate connected in a C2C structure, the first sub-pixel and the second sub-pixel, and the first rolling shutter operation circuit and the second rolling shutter operation circuit are formed on the first substrate; The image sensor of claim 1 , wherein the global selection switch circuit and the global shutter operation circuit are formed on the second substrate.

14. The image sensor includes a first substrate and a second substrate connected in a C2C structure, the first sub-pixel, the second sub-pixel, the first rolling shutter operating circuit, the second rolling shutter operating circuit, and the global selection switch circuit are formed on the first substrate; The image sensor according to claim 1 , wherein the global shutter operation circuit is formed on the second substrate.

15. a first subpixel including at least two first photodiodes; a second subpixel including at least two second photodiodes; a first floating diffusion node for storing charge accumulated by the first photodiode; a second floating diffusion node for storing charge accumulated by the second photodiode; a first source follower transistor amplifying a voltage stored in the first floating diffusion node; a second source follower transistor amplifying a voltage stored at the second floating diffusion node; a first rolling select transistor connected in series with the first source follower transistor; a second rolling select transistor connected in series with the second source follower transistor; a global select switch transistor coupled between an output terminal of the first source follower transistor and an output terminal of the second source follower transistor.

16. The global select switch transistor a first global selection switch transistor connected to an output terminal of the first source follower transistor; 16. The image sensor of claim 15, further comprising: a second global select switch transistor coupled to an output terminal of the second source follower transistor.

17. One end of the first global selection switch transistor and one end of the second global selection switch transistor 17. The image sensor of claim 16, further comprising a global shutter operating circuit configured to read out the photocharges stored in the first and second floating diffusion nodes in a global shutter manner.

18. one end of the first rolling selection transistor is connected to a first output line; one end of the second rolling selection transistor is connected to a second output line; 20. The image sensor of claim 17, wherein one end of a global selection transistor included in the global shutter operating circuit is coupled to a third output line.

19. In an image processing device, an image sensor including a pixel array in which a plurality of pixels are arranged in a matrix, the image sensor generating image data based on optical signals received by the pixel array; an application processor that receives and processes the image data from the image sensor and provides a mode setting signal to the image sensor; Each of the plurality of pixels comprises: a first sub-pixel sharing a first floating diffusion node; a second sub-pixel sharing the second floating diffusion node; a first rolling shutter operation circuit configured to read out the photocharges accumulated in the first floating diffusion node by a rolling shutter method; a second rolling shutter operation circuit configured to read out the photocharges accumulated in the second floating diffusion node by a rolling shutter method; a global selection switch circuit coupled between the first rolling shutter operating circuit and the second rolling shutter operating circuit, the global selection switch circuit including at least one transistor; a global shutter operation circuit connected to one end of the global selection switch circuit and configured to read out the photocharges accumulated in the first floating diffusion node and the second floating diffusion node in a global shutter manner.

20. The image processing device of claim 19 , wherein the pixel array of the image sensor selectively operates in a global shutter mode or a rolling shutter mode based on the mode setting signal received from the application processor.

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