Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the corrosion of metal used for a terminal structure is suppressed.SOLUTION: A semiconductor substrate 1 includes: a plurality of first terminal semiconductor layers 12 of a first conductivity type provided on a surface layer on a first main surface S1 side of a drift layer 10 in a first terminal region 22; and a second terminal semiconductor layer 13 of a second conductivity type provided on the surface layer on the first main surface S1 side of the drift layer 10 at an end part of the semiconductor substrate 1 in a second terminal region 23. The semiconductor device 10 includes: a first insulating layer 2 provided on the first main surface S1 in the first terminal region 22; a plurality of first terminal electrode layers 5 provided on the first main surface S1 and electrically connected to the first terminal semiconductor layers 12; a second terminal electrode layer 6 provided on the first main surface S1 and electrically connected to the second terminal semiconductor layer 13; a second insulating layer 3 provided on the first main surface S1 and in contact with the outermost first terminal semiconductor layer 12 and the second terminal semiconductor layer 13; and a sealing material 9 in contact with an upper surface of the second insulating layer 3.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices, a resistive field plate (RFP) is often used to increase the breakdown voltage of the termination region. The RFP promotes the expansion of the depletion layer at the edge of the pn junction located in the termination region, and relieves electric field concentration. This makes it possible to prevent edge breakdown of the pn junction (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-150025 A Summary of the Invention [Problem to be solved by the invention]

[0004] Recently, the applications of semiconductor products, including power modules, have become more diverse with the aim of reducing carbon emissions and saving energy, and high reliability is required in a variety of environments according to user needs. In particular, the required level tends to become higher in the Temperature Humidity Bias (THB) test. In the THB test, there is a problem that the metal used in the termination structure corrodes, causing breakdown or an increase in withstand voltage leakage.

[0005] The present disclosure has been made to solve the above problems, and has an object to suppress corrosion of metals used in termination structures in semiconductor devices. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a semiconductor substrate which is divided in a plan view into an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region, and which has a first main surface and a second main surface which is a main surface opposite to the first main surface, the semiconductor substrate including a drift layer of a second conductivity type, a plurality of first termination semiconductor layers of the first conductivity type provided in a surface layer on the first main surface side of the drift layer in the first termination region, and a second termination semiconductor layer of the second conductivity type provided in a surface layer on the first main surface side of the drift layer at an end of the semiconductor substrate in the second termination region. the first insulating layer provided on the first main surface in the first termination region, a plurality of first termination electrode layers provided on the first main surface and conductive with the plurality of first termination semiconductor layers through openings in the first insulating layer, a second termination electrode layer provided on the first main surface and conductive with the second termination semiconductor layer, a second insulating layer provided on the first main surface, one end of which contacts the outermost first termination semiconductor layer of the plurality of first termination semiconductor layers and the other end of which contacts the second termination semiconductor layer, and a sealing material in direct contact with the top surface of the second insulating layer. Effect of the Invention

[0007] According to the semiconductor device of the present disclosure, the encapsulant is in direct contact with the upper surface of the second insulating layer. Therefore, when ions generated in the outermost first or second termination semiconductor layer in the THB test move along the upper surface of the second insulating layer, they are dispersed in the encapsulant. Therefore, corrosion of the metal used in the first or second termination electrode layer is suppressed. [Brief description of the drawings]

[0008] [Figure 1] 1 is a top view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 11 is a top view showing a configuration of a semiconductor device according to a second embodiment. [Figure 4] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. [Diagram 5] 11 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment, showing a second insulating layer in which a non-reference surface is formed by a recess. FIG. [Figure 6] 13 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment, showing a second insulating layer in which a part of a non-reference surface formed by a convex portion extends under the second electrode layer and the third electrode layer. FIG. [Figure 7] 11 is a cross-sectional view showing a second insulating layer having a triangular cross section in a non-reference plane. FIG. [Figure 8] FIG. 4 is a cross-sectional view showing a second insulating layer whose non-reference surface has a tapered shape. [Figure 9] FIG. 4 is a cross-sectional view showing a second insulating layer whose non-reference surface is a curved surface. [Figure 10] 11 is a cross-sectional view showing a second insulating layer in which the non-reference surface is formed by both a convex portion and a concave portion. FIG. [Figure 11] 4 is an enlarged view of region B in FIG. 3 when the concave-convex pattern on the top surface of the second insulating layer is a stripe pattern. [Figure 12] 4 is an enlarged view of region B in FIG. 3 when the concave-convex pattern on the top surface of the second insulating layer is a discontinuous stripe pattern. [Figure 13] 4 is an enlarged view of region B in FIG. 3 when the concavo-convex pattern on the top surface of the second insulating layer is a checkered pattern. [Figure 14] 4 is an enlarged view of region B in FIG. 3 when the concave-convex pattern on the top surface of the second insulating layer is a dot pattern. [Figure 15] 13 is a top view showing the configuration of a semiconductor device according to a second embodiment, in which the concave and convex areas of the second insulating layer are provided only at the chip corners. FIG. [Figure 16] 13 is a top view showing the configuration of a semiconductor device according to a second embodiment, in which the density of the concave-convex pattern of the second insulating layer at the chip corners is higher than the density of the concave-convex pattern of the second insulating layer in other regions. FIG. [Figure 17] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment. [Figure 19] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment. [Figure 20]It is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2. [Figure 21] It is a cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2. [Figure 22] It is a cross-sectional view of the main part of the semiconductor device according to Embodiment 3. [Diagram 23] It is a cross-sectional view of the semiconductor device according to Embodiment 4.

Embodiments for Carrying Out the Invention

[0009] In the following description, the conductivity type of the semiconductor is described as the first conductivity type or the second conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0010] <A. Embodiment 1> <A-1. Configuration> FIG. 1 is a top view of the semiconductor device 101 according to Embodiment 1. As shown in FIG. 1, in a plan view, the semiconductor device 101 is divided into an active region 21 in the central portion, a first terminal region 22 surrounding the active region 21, and a second terminal region 23 surrounding the first terminal region 22.

[0011] FIG. 2 is a cross-sectional view of the semiconductor device 101 taken along the line A-A' of FIG. 1. The semiconductor device 101 includes a semiconductor substrate 1, a first insulating layer 2, a second insulating layer 3, an active region electrode layer 4, a first terminal electrode layer 5, a second terminal electrode layer 6, a back surface electrode 8, and a sealing material 9.

[0012] The semiconductor substrate 1 has a first main surface S1 and a second main surface S2 which is the main surface on the side opposite to the first main surface S1. The semiconductor substrate 1 is a substrate with a thickness of 50 μm to several hundred μm made of silicon, silicon carbide, gallium nitride, or the like. The semiconductor substrate 1 includes a drift layer 10, an active region semiconductor layer 11, a first terminal semiconductor layer 12, a second terminal semiconductor layer 13, and a buffer layer 7.

[0013] The semiconductor substrate 1 includes a drift layer 10 of a second conductivity type. An active region semiconductor layer 11 of a first conductivity type, a plurality of first termination semiconductor layers 12 of a first conductivity type, and a second termination semiconductor layer 13 of a second conductivity type are locally formed on the surface layer of the drift layer 10 on the first main surface S1 side. The active region semiconductor layer 11 is formed in an active region 21, the plurality of first termination semiconductor layers 12 are formed in a first termination region 22, and the second termination semiconductor layer 13 is formed at an end of the semiconductor substrate 1 in a second termination region 23. The plurality of first termination semiconductor layers 12 concentrically surround the active region semiconductor layer 11. The active region semiconductor layer 11 and the plurality of first termination semiconductor layers 12 control the extension of a depletion layer from the center to the end of the semiconductor device 101, thereby contributing to maintaining a breakdown voltage. The second termination semiconductor layer 13 is provided by ion implantation or the like.

[0014] A first insulating layer 2 and a second insulating layer 3 are provided on the first main surface S1 of the semiconductor substrate 1. The first insulating layer 2 is provided in the active region 21 and the first termination region 22. The second insulating layer 3 is provided in the second termination region 23. One end of the second insulating layer 3 contacts the outermost first termination semiconductor layer 12, and the other end of the second insulating layer 3 contacts the second termination semiconductor layer 13. The first insulating layer 2 has an opening above the first termination semiconductor layer 12.

[0015] The active region electrode layer 4 is provided on the first main surface S1 of the semiconductor substrate 1 in the active region 21, and is an electrode through which a main current of the semiconductor device 101 flows. The active region electrode layer 4 contacts the active region semiconductor layer 11 through an opening in the first insulating layer 2. An IGBT (Insulated Gate Bipolar Transistor) or a diode may be provided on the semiconductor substrate 1 of the active region 21 in contact with the active region electrode layer 4.

[0016] The multiple first termination electrode layers 5 are provided on the first main surface S1 of the semiconductor substrate 1 in the first termination region 22, separated from the active region electrode layer 4. The first termination electrode layers 5 are electrically isolated from each other. Each first termination electrode layer 5 contacts the first termination semiconductor layer 12 through an opening in the first insulating layer 2. The multiple first termination electrode layers 5 are field plates that contribute to maintaining the breakdown voltage of the semiconductor device 101.

[0017] The second terminal electrode layer 6 is provided separately from the active region electrode layer 4 and the first terminal electrode layer 5 on the first main surface S1 of the semiconductor substrate 1 in the second terminal region 23. A second insulating layer 3 is provided between the outermost first terminal electrode layer 5 and the second terminal electrode layer 6. One end of the second insulating layer 3 is in contact with the outermost first terminal electrode layer 5, and the other end is in contact with the second terminal electrode layer 6. The second terminal electrode layer 6 is electrically connected to the first terminal semiconductor layer 12. The plurality of first terminal electrode layers 5 and the second terminal electrode layer 6 are made of a metal such as Al.

[0018] A buffer layer 7 of the second conductivity type is provided on the surface layer on the second main surface S2 side of the semiconductor substrate 1. The surface of the buffer layer 7 constitutes the second main surface S2. A back surface electrode 8 is provided on the second main surface S2 of the semiconductor substrate 1. Note that a semiconductor layer of the first conductivity type or a semiconductor layer of the second conductivity type may be provided between the buffer layer 7 and the back surface electrode 8. For example, when the semiconductor device 101 is an IGBT, a collector layer of the first conductivity type is disposed between the buffer layer 7 and the back surface electrode 8. When the semiconductor device 101 is a diode, a cathode layer of the second conductivity type is disposed between the buffer layer 7 and the back surface electrode 8.

[0019] The upper surfaces of the active region electrode layer 4, the first terminal electrode layer 5, the second terminal electrode layer 6, the first insulating layer 2, and the second insulating layer 3 are in direct contact with the encapsulant 9. The encapsulant 9 is made of an insulating material such as, for example, silicone gel or an epoxy resin.

[0020] <A-2. Effect> The semiconductor device 101 according to Embodiment 1 is divided in a plan view into an active region 21, a first termination region 22 surrounding the active region 21, and a second termination region 23 surrounding the first termination region 22. The semiconductor device 101 has a first main surface S1 and a second main surface S2 which is the main surface on the side opposite to the first main surface S1. The semiconductor substrate 1 includes a drift layer 10 of a second conductivity type, a plurality of first termination semiconductor layers 12 of a first conductivity type provided on the surface layer on the first main surface S1 side of the drift layer 10 in the first termination region 22, and a second termination semiconductor layer 13 of a second conductivity type provided on the surface layer on the first main surface S1 side at the end of the semiconductor substrate 1 in the second termination region 23. The semiconductor device 101 includes a first insulating layer 2 provided on the first main surface S1 in the first termination region 22, a plurality of first termination electrode layers 5 provided on the first main surface S1 and conducting with the plurality of first termination semiconductor layers 12 through an opening of the first insulating layer 2, a second termination electrode layer 6 provided on the first main surface S1 and in contact with the second termination semiconductor layer 13, a second insulating layer 3 provided on the first main surface S1, with one end in contact with the outermost first termination semiconductor layer 12 among the plurality of first termination semiconductor layers 12 and the other end in contact with the second termination semiconductor layer 13, and a sealing material 9 in direct contact with the upper surface of the second insulating layer 3.

[0021] With the above configuration, when ions generated in the outermost first termination electrode layer 5 or second termination electrode layer 6 move on the surface of the second insulating layer 3, they are dispersed in the sealing material 9. Therefore, corrosion of the metal used for the first termination electrode layer 5 or second termination electrode layer 6 is suppressed. In addition, since the step of forming a protective film between the second insulating layer 3 and the sealing material 9 becomes unnecessary, the manufacturing cost is reduced.

[0022] <B. Embodiment 2> <B-1. Configuration> FIG. 3 is a top view of the semiconductor device 102 according to Embodiment 2. FIG. 4 is a cross-sectional view of the semiconductor device 102 taken along the line A-A' in FIG. 3. The semiconductor device 102 is different from the semiconductor device 101 according to Embodiment 1 in that the upper surface of the second insulating layer 3 has an uneven region 30 with an uneven shape. In FIG. 3, the uneven region 30 is provided with satin hatching.

[0023] Specifically, the upper surface of the second insulating layer 3 is composed of a reference surface 31 having the same height as the upper surface of the first insulating layer 2 and a non-reference surface 32 formed by convex portions protruding from the reference surface 31. The upper surface of the second insulating layer 3 has an uneven shape due to the reference surface 31 and the non-reference surface 32. The region with the uneven shape on the upper surface of the second insulating layer 3 is referred to as an uneven region 30. Note that the second insulating layer 3 needs to have a film thickness such that it can maintain insulation from the semiconductor substrate 1 at the reference surface 31.

[0024] As shown in FIG. 3, the uneven region 30 exists over the entire region of the second terminal region 23 so as to surround the first terminal region 22.

[0025] <B-2. Uneven Shape of the Second Insulating Layer> Various shapes are assumed for the uneven shape of the second insulating layer 3. In FIG. 4, the non-reference surface 32 was formed by convex portions protruding from the reference surface 31. However, as shown in FIG. 5, the non-reference surface 32 may be formed by concave portions recessed from the reference surface 31. In this case, the second insulating layer 3 needs to have a film thickness such that it can maintain insulation from the semiconductor substrate 1 at the non-reference surface 32.

[0026] When the non-reference surface 32 is formed by convex portions protruding from the reference surface 31, as shown in FIG. 6, the convex portions located at both ends of the second insulating layer 3 may enter under the outermost first terminal electrode layer 5 and second terminal electrode layer 6.

[0027] In FIGS. 4 to 6, the cross-sectional shape of the non-reference surface 32 of the second insulating layer 3 was rectangular. However, the cross-sectional shape of the non-reference surface 32 may be triangular as shown in FIG. 7, or may be tapered as shown in FIG. 8. Also, as shown in FIG. 9, the non-reference surface 32 may be a curved surface. In FIG. 9, the non-reference surface 32 is formed from both convex and concave portions with respect to the reference surface 31. FIG. 10 shows an example in which the non-reference surface 32 is formed from both convex and concave portions with respect to the reference surface 31, and the convex or concave portion forming the non-reference surface 32 is rectangular in cross-sectional view.

[0028] <B-3. Arrangement Pattern of the Non-reference Surface> In the uneven region 30, there are a reference plane 31 and a non-reference plane 32. In the uneven region 30, the non-reference plane 32 can be arranged in various patterns. In FIG. 3, a part of the uneven region 30 is shown as region B. FIG. 11 is an enlarged view of region B in FIG. 3. In FIG. 11, the non-reference plane 32 is arranged in a stripe pattern. Here, the thickness, length, number, and interval of the stripe pattern are not limited to those shown in the figure.

[0029] As shown in FIG. 12, the non-reference plane 32 may be arranged in a pattern in which a part of the stripe pattern in FIG. 11 is missing, that is, a so-called incomplete stripe pattern. In FIG. 12, among the four patterns of the non-reference plane 32, three patterns excluding the leftmost pattern are not completely continuous patterns in the vertical direction of the figure and are interrupted at least at one location. The missing locations of these patterns of the non-reference plane 32 are not limited to those shown in FIG. 12.

[0030] As shown in FIG. 13, the non-reference plane 32 may be arranged in a rectangular dot pattern. The size of the dots or the positional relationship between adjacent patterns is not limited to those shown in FIG. 13. In FIG. 13, adjacent patterns of the non-reference plane 32 are in contact, and the reference plane 31 is surrounded by four patterns of the non-reference plane 32. However, adjacent patterns of the non-reference plane 32 do not have to be in contact. Also, the shape of the dot pattern is not limited to a rectangle and may be a polygon.

[0031] As shown in FIG. 14, the non-reference plane 32 may be arranged in a circular dot pattern. Also, an elliptical dot pattern may be used instead of the circular dot pattern. The size of the dots or the positional relationship between adjacent patterns is not limited to those shown in FIG. 14. In FIG. 14, adjacent patterns of the non-reference plane 32 are not in contact, but they may be in contact.

[0032] <B-4. Arrangement of the uneven region> In FIG. 3, the concavo-convex region 30 existed over the entire region of the second terminal region 23 so as to surround the first terminal region 22. However, the concavo-convex region 30 may be provided only in a partial region of the second terminal region 23. For example, as shown in FIG. 15, the concavo-convex region 30 may be provided only at the corner portion of the semiconductor device 102 in the second terminal region 23. By providing the concavo-convex region 30 at the corner portion where a high electric field is likely to be generated, the destruction by the THB test or the increase in leakage current can be effectively suppressed and delayed. Note that the concavo-convex region 30 may be provided at a location other than the corner portion as long as it is a location where a high electric field is likely to be generated.

[0033] As shown in FIG. 16, after arranging the concavo-convex region 30 over the entire region of the second terminal region 23, the corner portion may be made into a high-density concavo-convex region 30a having a higher concavo-convex pattern density than other concavo-convex regions 30. Note that the high-density concavo-convex region 30a may be provided at a location other than the corner portion as long as it is a location where a high electric field is likely to be generated.

[0034] <B-5. Manufacturing Process> The formation process of the second insulating layer 3 having the non-reference surface 32 formed by the convex portion with respect to the reference surface 31 shown in FIG. 4 and its periphery will be described below.

[0035] First, as shown in FIG. 17, a first terminal semiconductor layer 12 and a second terminal semiconductor layer 13 are formed on the surface layer of the first main surface S1 of the semiconductor substrate 1 having the drift layer 10. Thereafter, a second insulating layer 3 is formed on the first main surface S1 of the semiconductor substrate 1. Note that the second insulating layer 3 may be formed before the formation of the first terminal semiconductor layer 12 and the second terminal semiconductor layer 13.

[0036] Next, as shown in FIG. 18, a resist film 14 having an arbitrary opening is formed on the second insulating layer 3. In the case of forming the second insulating layer 3 having the non-reference surface 32 formed by the concave portion with respect to the reference surface 31, the pattern of the resist film 14 shown in FIG. 18 may be inverted.

[0037] Thereafter, as shown in FIG. 19, a part of the thickness of the second insulating layer 3 in the opening of the resist film 14 is removed. At this time, the second insulating layer 3 in the opening of the resist film 14 needs to have a remaining film thickness that can maintain insulation from the semiconductor substrate 1. This process is a general half-etch or etch-back, and can be either wet or dry. By this process, the upper surface of the second insulating layer 3 in the opening of the resist film 14 becomes the reference surface 31, and the upper surface of the second insulating layer 3 immediately below the resist film 14 becomes the non-reference surface 32.

[0038] Next, by removing the resist film 14, the configuration shown in FIG. 20 is obtained.

[0039] Thereafter, by forming the first terminal electrode layer 5 and the second terminal electrode layer 6 respectively, the configuration shown in FIG. 21 is obtained.

[0040] The above flow is the simplest method of forming the concavo-convex shape on the upper surface of the second insulating layer 3. Alternatively, although the man-hour increases, it is possible to form the concavo-convex shape of the second insulating layer 3 using the LOCOS (LOCal Oxidation of Silicon) flow. Further, according to the deposition process of forming a rough surface on the second insulating layer 3, or the process of roughening the once-formed flat second insulating layer 3 by etching, although a deep concavo-convex shape cannot be obtained, it is possible to easily form the concavo-convex shape of the second insulating layer 3.

[0041] <B-6. Effect> In the semiconductor device 102 according to the second embodiment, the upper surface of the second insulating layer 3 has a concavo-convex region 30 that is concavo-convex in a cross-sectional view. Therefore, according to the semiconductor device 102, in addition to the effects of the semiconductor device 101 according to the first embodiment, the following effects are obtained. That is, since the upper surface of the second insulating layer 3 is concavo-convex, the melt that has corroded and ionized at the outermost first terminal electrode layer 5 or second terminal electrode layer 6 due to the test load during the THB test moves between the outermost first terminal electrode layer 5 and the second terminal electrode layer 6 due to the voltage bias. The distance becomes longer. Thereby, the destruction or increase in leakage current due to the THB test can be suppressed and delayed.

[0042] <C. Embodiment 3> <C-1. Configuration> As shown in FIG. 3, the top view of the semiconductor device 103 according to Embodiment 3 is the same as that of the semiconductor device 102 according to Embodiment 2. FIG. 22 is a cross-sectional view of the semiconductor device 103 taken along the line A-A' in FIG. 3. The semiconductor device 103 is different from the semiconductor device 102 according to Embodiment 2 in that a plurality of third insulating layers 15 are discretely formed on the flat upper surface of the second insulating layer 3. That is, in the semiconductor device 103, an uneven shape is formed by the flat upper surface of the second insulating layer 3 and the plurality of third insulating layers 15. Here, a plurality of third insulating layers 15 are used, but another insulating layer may be provided separately from the third insulating layers 15 on the flat upper surface of the second insulating layer 3. Also, another insulating layer may be in contact with the third insulating layers 15 and provided in multiple layers. The number of types of insulating layers to be used may be determined by comparing the merit of improving the withstand voltage in the THB test and the demerit of increasing the number of processes.

[0043] <C-2. Effect> In the semiconductor device 103 according to Embodiment 3, the upper surface of the second insulating layer 3 is flat, and a plurality of third insulating layers are discretely provided on the upper surface of the second insulating layer 3. With this configuration, since an uneven shape is formed by the upper surface of the second insulating layer 3 and the third insulating layers, the same effect as that of the semiconductor device 102 according to Embodiment 2 in which the upper surface of the second insulating layer 3 has an uneven shape can be obtained.

[0044] <D. Embodiment 4> <D-1. Configuration> As shown in FIG. 3, the top view of the semiconductor device 104 according to Embodiment 4 is the same as that of the semiconductor device 102 according to Embodiment 2. FIG. 23 is a cross-sectional view of the semiconductor device 104 taken along line A-A' in FIG. 3. The semiconductor device 104 is different from the semiconductor device 102 according to Embodiment 2 in that the first insulating layer 2 has convex portions 16 on the upper surface between the active region electrode layer 4 and the first terminal electrode layer 5 and between adjacent first terminal electrode layers 5. The number of the convex portions 16 of the first insulating layer 2 is not limited to that shown in FIG. 23. It is not necessary to provide the convex portions 16 in all of the spaces between the active region electrode layer 4 and the first terminal electrode layer 5 and between adjacent first terminal electrode layers 5.

[0045] <D-2. Effect> In the semiconductor device 104 according to Embodiment 4, the semiconductor substrate 1 includes a first-conductivity-type active region semiconductor layer 11 provided on the surface layer on the first main surface S1 side of the drift layer 10 in the active region 21. The semiconductor device 104 includes an active region electrode layer 4 provided on the first main surface S1 and electrically connected to the active region semiconductor layer 11. The upper surface of the first insulating layer 2 has convex portions 16 in at least one of the spaces between the active region electrode layer 4 and the first terminal electrode layer 5 and between adjacent first terminal electrode layers 5. According to the above configuration, the distance between the active region electrode layer 4 and the first terminal electrode layer 5 or the distance between the first terminal electrode layers 5 can be defined by the width of the convex portions 16 of the first insulating layer 2. These distances are important design parameters for maintaining the breakdown voltage. When these distances become smaller, the bridging of corrosive substances is accelerated. However, since the upper surface of the second insulating layer 3 has an uneven shape, the THB withstand voltage can be maintained or improved. Therefore, in the first terminal region 22, the dimensional design can be freely performed with a focus on maintaining the breakdown voltage.

[0046] Although the preferred embodiments etc. have been described in detail above, the present invention is not limited to the above-described embodiments etc., and various modifications and substitutions can be made to the above-described embodiments etc. without departing from the scope described in the claims.

[0047] Hereinafter, aspects of the present disclosure will be summarized as appendices.

[0048] (Appendix 1) In a plan view, the semiconductor device is divided into an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region; A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The semiconductor substrate is A drift layer of a second conductivity type; a plurality of first termination semiconductor layers of a first conductivity type provided on a surface layer on the first main surface side of the drift layer in the first termination region; a second termination semiconductor layer of a second conductivity type provided in a surface layer on the first main surface side of the drift layer at an end of the semiconductor substrate in the second termination region, a first insulating layer disposed on the first major surface in the first termination region; a plurality of first termination electrode layers provided on the first main surface and electrically connected to the plurality of first termination semiconductor layers through openings in the first insulating layer; a second termination electrode layer provided on the first major surface and electrically connected to the second termination semiconductor layer; a second insulating layer provided on the first major surface, one end of which contacts an outermost first termination semiconductor layer of the plurality of first termination semiconductor layers and the other end of which contacts the second termination semiconductor layer; and a sealant in direct contact with the top surface of the second insulating layer. Semiconductor device.

[0049] (Appendix 2) The upper surface of the second insulating layer has an uneven region having an uneven shape in a cross-sectional view. 2. The semiconductor device according to claim 1.

[0050] (Appendix 3) the uneven region includes a reference surface that is flush with the upper surface of the first insulating layer, and a non-reference surface that is formed by a convex portion protruding from the reference surface. 3. The semiconductor device according to claim 2.

[0051] (Appendix 4) the uneven region includes a reference surface that is at the same height as the first insulating layer, and a non-reference surface that is formed by a recess that is recessed from the reference surface. 3. The semiconductor device according to claim 2.

[0052] (Appendix 5) the protrusions located at both ends of the second insulating layer are embedded under an outermost first termination electrode layer of the plurality of first termination electrode layers and under the second termination electrode layer; 4. The semiconductor device according to claim 3.

[0053] (Appendix 6) The cross-sectional shape of the non-reference surface is rectangular. 6. The semiconductor device according to claim 3,

[0054] (Appendix 7) The cross-sectional shape of the non-reference surface is triangular. 6. The semiconductor device according to claim 3,

[0055] (Appendix 8) The cross-sectional shape of the non-reference surface is tapered. 6. The semiconductor device according to claim 3,

[0056] (Appendix 9) The non-reference surface is a curved surface. 6. The semiconductor device according to claim 3,

[0057] (Appendix 10) the non-reference surfaces are arranged in a striped pattern; 10. The semiconductor device according to claim 3,

[0058] (Appendix 11) the non-reference surfaces are arranged in an incomplete stripe pattern; 10. The semiconductor device according to claim 3,

[0059] (Appendix 12) the non-reference surfaces are arranged in a polygonal dot pattern; 10. The semiconductor device according to claim 3,

[0060] (Appendix 13) The non-reference surfaces are arranged in a circular or elliptical dot pattern. 10. The semiconductor device according to claim 3,

[0061] (Appendix 14) The uneven area is provided only at the corners of the second termination area. The semiconductor device according to any one of claims 2 to 13.

[0062] (Appendix 15) the concave-convex region is provided over the entire second terminal region, The concave-convex region provided at the corner portion of the second termination region is a high-density concave-convex region having a concave-convex pattern with a higher density than the other concave-convex regions. The semiconductor device according to any one of claims 2 to 13.

[0063] (Appendix 16) The upper surface of the second insulating layer is flat, Further comprising a plurality of third insulating layers discretely provided on an upper surface of the second insulating layer. 2. The semiconductor device according to claim 1.

[0064] (Appendix 17) the semiconductor substrate includes an active region semiconductor layer of a first conductivity type provided in a surface layer of the drift layer on the first main surface side in the active region, an active region electrode layer provided on the first main surface and electrically connected to the active region semiconductor layer; an upper surface of the first insulating layer has a convex portion between the active region electrode layer and the first termination electrode layer and / or between adjacent first termination electrode layers; 17. The semiconductor device according to claim 1,

[0065] (Appendix 18) 1. A method for manufacturing a semiconductor device, the semiconductor device being divided into an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region in a plan view, the method comprising: preparing a semiconductor substrate having a drift layer of a second conductivity type and having a first main surface and a second main surface that is a main surface opposite to the first main surface; forming a plurality of first termination semiconductor layers of a first conductivity type on a surface layer on the first main surface side of the drift layer in the first termination region; forming a second termination semiconductor layer of a second conductivity type on a surface layer of the drift layer on the first main surface side at an end of the semiconductor substrate in the second termination region; forming a first insulating layer on the first major surface in the first termination region; forming a plurality of first termination electrode layers on the first main surface and electrically connected to the plurality of first termination semiconductor layers through the openings in the first insulating layer; forming a second termination electrode layer on the first major surface, the second termination electrode layer being electrically connected to the second termination semiconductor layer; forming a second insulating layer on the first main surface, the second insulating layer having one end in contact with an outermost first termination semiconductor layer of the plurality of first termination semiconductor layers and the other end in contact with the second termination semiconductor layer; sealing the upper surface of the second insulating layer with a sealing material; A method for manufacturing a semiconductor device. [Explanation of symbols]

[0066] REFERENCE SIGNS LIST 1 semiconductor substrate, 2 first insulating layer, 3 second insulating layer, 4 active region electrode layer, 5 first termination electrode layer, 6 second termination electrode layer, 8 back electrode, 9 sealing material, 10 drift layer, 11 active region semiconductor layer, 12 first termination semiconductor layer, 13 second termination semiconductor layer, 14 resist film, 15 third insulating layer, 16 convex portion, 21 active region, 22 first termination region, 23 second termination region, 30 uneven region, 31 reference surface, 32 non-reference surface, 101-104 semiconductor device.

Claims

1. In a plan view, the semiconductor device is divided into an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region; A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, The semiconductor substrate is A drift layer of a second conductivity type; a plurality of first termination semiconductor layers of a first conductivity type provided on a surface layer on the first main surface side of the drift layer in the first termination region; a second termination semiconductor layer of a second conductivity type provided in a surface layer on the first main surface side of the drift layer at an end of the semiconductor substrate in the second termination region, a first insulating layer disposed on the first major surface in the first termination region; a plurality of first termination electrode layers provided on the first major surface and electrically connected to the plurality of first termination semiconductor layers through openings in the first insulating layer; a second termination electrode layer provided on the first major surface and electrically connected to the second termination semiconductor layer; a second insulating layer provided on the first major surface, one end of which contacts an outermost first termination semiconductor layer of the plurality of first termination semiconductor layers and the other end of which contacts the second termination semiconductor layer; a sealant in direct contact with the top surface of the second insulating layer; Semiconductor device.

2. The upper surface of the second insulating layer has an uneven region having an uneven shape in a cross-sectional view. The semiconductor device according to claim 1 .

3. the uneven region includes a reference surface that is at the same height as the upper surface of the first insulating layer, and a non-reference surface that is formed by a convex portion protruding from the reference surface. The semiconductor device according to claim 2 .

4. the uneven region includes a reference surface having the same height as the first insulating layer, and a non-reference surface formed by a recess recessed from the reference surface. The semiconductor device according to claim 2 .

5. the protrusions located at both ends of the second insulating layer are embedded under an outermost first termination electrode layer of the plurality of first termination electrode layers and under the second termination electrode layer; The semiconductor device according to claim 3 .

6. The cross-sectional shape of the non-reference surface is rectangular. The semiconductor device according to claim 3 .

7. The cross-sectional shape of the non-reference surface is triangular. The semiconductor device according to claim 3 .

8. The cross-sectional shape of the non-reference surface is tapered. The semiconductor device according to claim 3 .

9. The non-reference surface is a curved surface. The semiconductor device according to claim 3 .

10. the non-reference surfaces are arranged in a striped pattern; The semiconductor device according to claim 3 .

11. the non-reference surfaces are arranged in an incomplete stripe pattern; The semiconductor device according to claim 3 .

12. the non-reference surfaces are arranged in a polygonal dot pattern; The semiconductor device according to claim 3 .

13. The non-reference surfaces are arranged in a circular or elliptical dot pattern. The semiconductor device according to claim 3 .

14. The uneven region is provided only at a corner portion of the second termination region. The semiconductor device according to claim 2 .

15. the concave-convex region is provided over the entire second terminal region, the concave-convex region provided at the corner portion of the second termination region is a high-density concave-convex region having a concave-convex pattern with a higher density than the other concave-convex regions; The semiconductor device according to claim 2 .

16. The upper surface of the second insulating layer is flat, The semiconductor device further includes a plurality of third insulating layers provided discretely on an upper surface of the second insulating layer. The semiconductor device according to claim 1 .

17. the semiconductor substrate includes an active region semiconductor layer of a first conductivity type provided in a surface layer of the drift layer on the first main surface side in the active region, an active region electrode layer provided on the first major surface and electrically connected to the active region semiconductor layer; an upper surface of the first insulating layer has a convex portion between the active region electrode layer and the first termination electrode layer and / or between adjacent first termination electrode layers; The semiconductor device according to claim 1 .

18. 1. A method for manufacturing a semiconductor device, the semiconductor device being divided into an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region in a plan view, the method comprising the steps of: preparing a semiconductor substrate having a drift layer of a second conductivity type and having a first main surface and a second main surface that is a main surface opposite to the first main surface; a first termination semiconductor layer having a first conductivity type is formed on a surface layer of the drift layer on the first main surface side in the first termination region; a second termination semiconductor layer of a second conductivity type is formed on a surface layer of the drift layer on the first main surface side at an end of the semiconductor substrate in the second termination region; forming a first insulating layer on the first major surface in the first termination region; forming a plurality of first termination electrode layers on the first main surface and electrically connected to the plurality of first termination semiconductor layers through the openings in the first insulating layer; forming a second termination electrode layer on the first major surface and in electrical communication with the second termination semiconductor layer; a second insulating layer is formed on the first main surface, the second insulating layer having one end in contact with an outermost first termination semiconductor layer of the plurality of first termination semiconductor layers and the other end in contact with the second termination semiconductor layer; sealing the upper surface of the second insulating layer with a sealing material; A method for manufacturing a semiconductor device.

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