Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that can be made smaller in size than a conventional surface mount package and has higher reliability than a conventional CSP.SOLUTION: A semiconductor device includes a semiconductor chip having rewiring, a lead frame having a die pad on which the semiconductor chip is mounted and leads connected to the die pad, in which the rewiring and the die pad are electrically connected by solder or a conductive adhesive, and a sealing member that seals the semiconductor chip.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The disclosed technology relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The following techniques are known as techniques relating to semiconductor devices. Patent Document 1 describes a semiconductor device in which an oscillator is mounted on a first surface of a lead frame, an integrated circuit is mounted on a second surface of the lead frame, and the oscillator and the integrated circuit are connected to the lead frame by bonding wires.

[0003] Patent document 2 describes a semiconductor device including a semiconductor element, at least one electrode portion arranged on one surface of the semiconductor element, an insulating layer formed to cover the one surface of the semiconductor element except for the electrode portion, wiring provided on the insulating layer, and an external terminal formed on the wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-232544 A [Patent Document 2] JP 2011-60805 A Summary of the Invention [Problem to be solved by the invention]

[0005] A surface mount type semiconductor package such as a small outline package (SOP) and a quad flat package (QFP) includes a semiconductor chip, a lead frame, and a sealing member. The lead frame has a die pad and leads. The semiconductor chip is mounted on the lead frame, and the semiconductor chip and the leads are connected via bonding wires. In such a surface mount type package, the size of the package is significantly larger than the size of the semiconductor chip because bonding wires are used to connect the semiconductor chip and the leads. In addition, the inductance component of the bonding wire may affect the electrical characteristics. Furthermore, there is a risk of the bonding wire breaking or peeling off.

[0006] CSP (chip size package) is known as a package that solves the above problems. CSP is a semiconductor package that does not have bonding wires and has a package size that is approximately the same as the size of the semiconductor chip. In CSP, the semiconductor chip is exposed, which raises concerns about reliability and also poses the problem of being difficult to handle.

[0007] The disclosed technology has been made in consideration of the above points, and aims to make the size smaller than that of conventional surface mount packages and to make the reliability higher than that of conventional CSPs. [Means for solving the problem]

[0008] The semiconductor device related to the disclosed technology includes a semiconductor chip having rewiring, a lead frame having a die pad on which the semiconductor chip is mounted and leads connected to the die pad, the rewiring and the die pad being electrically connected by solder or a conductive adhesive, and a sealing member that seals the semiconductor chip.

[0009] A manufacturing method for a semiconductor device according to the disclosed technology includes the steps of preparing a semiconductor chip having rewiring, connecting the die pad and the rewiring of a lead frame having a die pad and a lead connected to the die pad with solder or a conductive adhesive, and sealing the semiconductor chip with a sealing member. Effect of the Invention

[0010] According to the disclosed technology, it is possible to make the package smaller than conventional surface mount packages and to increase the reliability compared to conventional CSPs. [Brief description of the drawings]

[0011] [Figure 1] 1 is a perspective view showing an example of a configuration of a semiconductor device; [Diagram 2] FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. [Diagram 3] 1 is a plan view showing an example of a configuration of a lead frame according to an embodiment of the disclosed technique; [Figure 4] 1 is a cross-sectional view showing an example of a configuration of a semiconductor chip according to an embodiment of the disclosed technique. [Figure 5A] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5B] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5C] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5D] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5E] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5F] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5G] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5H] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a semiconductor device according to an embodiment of the disclosed technique. [Figure 6] 1 is a cross-sectional view comparing the sizes of a semiconductor device according to an embodiment of the disclosed technique and a surface-mount type semiconductor device according to a comparative example. [Figure 7A] 11 is a cross-sectional view showing another configuration example of a semiconductor device according to an embodiment of the disclosed technique. [Figure 7B] 11 is a cross-sectional view showing another configuration example of a semiconductor device according to an embodiment of the disclosed technique. [Figure 7C] 11 is a cross-sectional view showing another configuration example of a semiconductor device according to an embodiment of the disclosed technique. [Figure 7D] 11 is a cross-sectional view showing another configuration example of a semiconductor device according to an embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are given the same reference numerals, and duplicated descriptions will be omitted.

[0013] Fig. 1 is a perspective view showing an example of the configuration of a semiconductor device 10 according to an embodiment of the disclosed technique. Fig. 2 is a cross-sectional view taken along line 2-2 in Fig. 1. The semiconductor device 10 has a semiconductor chip 20, a lead frame 30, and a sealing member 40. Fig. 3 is a plan view showing an example of the configuration of the lead frame 30. Fig. 4 is a cross-sectional view showing an example of the configuration of the semiconductor chip 20.

[0014] As shown in Fig. 4, the semiconductor chip 20 has a semiconductor substrate 21 on which a circuit element 22 is formed, an insulating film 23 covering the semiconductor substrate 21, and an electrode 24 provided on the insulating film 23 and connected to the circuit element 22. The semiconductor substrate 21 is, for example, a silicon substrate. The circuit element 22 is, for example, a transistor, a diode, a resistor, or a capacitor. The insulating film 23 is made of an insulator such as SiO2. The electrode 24 is connected to the circuit element 22 through a via 25 that penetrates the insulating film 23. The via 25 and the electrode 24 are made of a conductor such as Al.

[0015] The semiconductor chip 20 has a rewiring layer 50 provided on an insulating film 23. The rewiring layer 50 has the same size as the planar size of the semiconductor substrate 21. The rewiring layer 50 has an insulating film 51 made of an insulator such as polyimide or PBO (polybenzoxazole), and rewirings 52 provided on the surface of the insulating film 51. The rewirings 52 are connected to the electrodes 24 exposed in openings formed in the insulating film 51. The rewirings 52 are made of a conductor such as Cu.

[0016] The surface of the rewiring layer 50 is covered with an insulating film 53 made of an insulator such as a photosensitive resin. The terminal pads 54 are connected to the rewirings 52 exposed at openings formed in the insulating film 53. A plurality of connection terminals 55 are provided on the surface of the terminal pads 54. The connection terminals 55 may have the form of solder balls. The rewirings 52 and the terminal pads 54 are made of a conductor such as Cu.

[0017] The semiconductor chip 20 has a rewiring layer 50 having the same size as the planar size of the semiconductor substrate 21, and is a BGA (Ball Grid Array) type chip component in the form of a CSP.

[0018] As shown in Fig. 2, the semiconductor chip 20 is mounted on a lead frame 30. The lead frame 30 is produced by progressive precision pressing (punching, drawing, bending) of a thin plate made of a Cu alloy-based material or an Fe alloy-based material, which has excellent electrical conductivity, mechanical strength, thermal conductivity, and corrosion resistance. The lead frame 30 has a die pad 31 on which the semiconductor chip 20 is mounted, and leads 33 connected to the die pad 31. In Fig. 3, the rectangular area indicated by a dotted line is the area of ​​the die pad 31, which is the mounting area for the semiconductor chip 20.

[0019] The die pad 31 has a plurality of electrically separated divided pieces 32 corresponding to the plurality of connection terminals 55 of the semiconductor chip 20. Each of the plurality of connection terminals 55 is connected to a corresponding divided piece 32 among the plurality of divided pieces 32. In FIG. 3, the connection portion with the connection terminal 55 is indicated by a circular dotted line. The connection terminal 55 is constituted by a solder ball. That is, the rewiring 52 of the semiconductor chip 20 and the die pad 31 of the lead frame 30 are electrically connected by solder. In the semiconductor device 10 according to this embodiment, a bonding wire is not used for the electrical connection between the semiconductor chip 20 and the lead frame 30. It is also possible to apply a form in which the connection terminal 55 is not constituted by a solder ball. In this case, for example, the rewiring 52 and the die pad 31 may be connected using a solder paste or a conductive adhesive supplied onto the die pad 31.

[0020] The sealing member 40 seals the die pad 31 and the semiconductor chip 20. That is, the die pad 31 and the semiconductor chip 20 are embedded inside the sealing member 40. The sealing member 40 is made of a thermosetting epoxy resin. The leads 33 connected to each of the divided pieces 32 of the die pad 31 extend to the outside of the sealing member 40.

[0021] The semiconductor device 10 according to this embodiment has a QFP configuration in which the leads 33 are arranged along each of the four sides of the rectangular shaped sealing member 40. As shown in Fig. 3, the leads 33 are formed into a desired shape.

[0022] A method for manufacturing the semiconductor device 10 will be described below with reference to FIGS. 5A to 5H. First, a circuit element 22 such as a transistor, a diode, a resistor, or a capacitor is formed on a semiconductor substrate 21 using a known semiconductor manufacturing process (FIG. 5A). Then, an insulating film 23 made of an insulator such as SiO2 is formed on the circuit formation surface of the semiconductor substrate 21 using a CVD (Chemical Vapor Deposition) method (FIG. 5A). Then, a contact hole is formed at a predetermined position of the insulating film 23 using a photolithography technique. Then, a conductive film made of a conductor such as Al is formed on the surface of the insulating film 23 using a sputtering method. As a result, a conductor is embedded in the contact hole formed in the insulating film 23, and a via 25 connected to the circuit element 22 is formed. Then, the conductive film is patterned using a photolithography technique to form an electrode 24 connected to the via 25 (FIG. 5A).

[0023] Next, a resin such as polyimide or PBO is applied onto the insulating film 23, and then the resin is cured to form an insulating film 51 (FIG. 5B).

[0024] Next, an opening is formed in the insulating film 51 using photolithography technology. The electrode 24 is exposed in the opening. Next, a conductive film made of a conductor such as Cu is formed to cover the surface of the insulating film 51 using plating technology. Subsequently, the conductive film is patterned using photolithography technology. As a result, the rewiring 52 connected to the electrode 24 is formed (FIG. 5C). The planar size of the rewiring layer 50 made up of the insulating film 51 and the rewiring 52 is the same as the planar size of the semiconductor substrate 21.

[0025] Next, a photosensitive resin is applied to the surface of the insulating film 51, and then the photosensitive resin is cured to form the insulating film 53 (FIG. 5D).

[0026] Next, an opening is formed in the insulating film 53 using photolithography technology. The rewiring 52 is partially exposed in the opening. Next, a conductive film made of a conductor such as Cu is formed by plating to cover the surface of the insulating film 53. Subsequently, the conductive film is patterned using photolithography technology to form terminal pads 54 connected to the rewiring 52 (FIG. 5E). Next, connection terminals 55 made of solder balls are formed on the terminal pads 54 (FIG. 5E). Through the above steps, the semiconductor chip 20 is manufactured.

[0027] Next, the semiconductor chip 20 is mounted on the die pad 31 of the lead frame 30, and a reflow process is performed (FIG. 5F). As a result, the semiconductor chip 20 and the lead frame 30 are connected by the solder balls that form the connection terminals 55. That is, the semiconductor chip 20 is connected to the lead frame 30 in the form of a flip-chip connection. Each of the multiple connection terminals 55 of the semiconductor chip 20 is connected to a corresponding one of the multiple divided pieces 32 of the die pad 31. The rewiring 52 provided on the semiconductor chip 20 is electrically connected to the divided pieces 32 and leads of the die pad 31.

[0028] Next, the die pad 31 and the semiconductor chip 20 are sealed with a sealing member 40 (FIG. 5G). The sealing member 40 is molded, for example, by a transfer method. The transfer method is a sealing method in which a lead frame with a semiconductor chip mounted thereon is set in a molding die, and molten resin is filled into the cavity of the die and allowed to harden. The die pad 31 and the semiconductor chip 20 are embedded inside the sealing member 40. The leads 33 connected to each of the divided pieces 32 of the die pad 31 extend to the outside of the sealing member 40 (FIG. 5H).

[0029] As described above, the semiconductor device 10 of this embodiment includes a semiconductor chip 20 having rewiring 52, a lead frame 30 having a die pad 31 on which the semiconductor chip 20 is mounted and leads 33 connected to the die pad 31, the rewiring 52 and the die pad 31 being electrically connected by solder or a conductive adhesive, and a sealing member that seals the semiconductor chip 20.

[0030] The semiconductor chip 20 has a semiconductor substrate 21 on which a circuit element 22 is formed, an insulating film 23 covering the semiconductor substrate 21, electrodes 24 provided on the insulating film 23 and connected to the circuit element 22 and also connected to rewirings 52, and a connection terminal 55 connected to the rewirings 52. The rewirings 52 are provided in a rewiring layer 50 having the same size as the planar size of the semiconductor substrate 21.

[0031] FIG. 6 is a cross-sectional view comparing the sizes of the semiconductor device 10 according to this embodiment and a surface-mount type semiconductor device 10X according to a comparative example.

[0032] The semiconductor device 10X according to the comparative example includes a semiconductor chip 20X, a lead frame 30X, and a sealing member 40X. The lead frame 30X has a die pad 31X and a lead 33X. The semiconductor chip 20X is mounted on the lead frame 30X, and the semiconductor chip 20X and the lead 33X are connected via a bonding wire 60X. In such a surface mount package, the size of the package is significantly larger than the size of the semiconductor chip 20X due to the use of the bonding wire 60X for connecting the semiconductor chip 20X and the lead 33X. In addition, the inductance component of the bonding wire 60X may affect the electrical characteristics. Furthermore, there is a risk of the bonding wire 60X being broken or peeled off.

[0033] CSPs are known as a package that solves the above problems. CSPs are semiconductor packages that do not have bonding wires and have a package size that is approximately the same as the size of the semiconductor chip. In CSPs, the semiconductor chip is exposed, which raises concerns about reliability and makes it difficult to handle.

[0034] On the other hand, according to the semiconductor device 10 according to the embodiment of the disclosed technology, since no bonding wire is used to connect the semiconductor chip 20 and the lead frame 30, the package size can be significantly smaller than that of the semiconductor device 10X according to the comparative example, as shown in Fig. 6. In addition, no inductance component is formed due to the bonding wire. Furthermore, it is possible to avoid the risk of the bonding wire being broken or peeled off.

[0035] Furthermore, although the semiconductor chip 20 according to this embodiment has the form of a CSP, the semiconductor chip 20 is sealed with the sealing member 40, and therefore the reliability and handling problems associated with conventional CSPs are eliminated.

[0036] Various modifications can be made to the configuration of the semiconductor device 10. Figures 7A to 7D are cross-sectional views showing other configuration examples of the semiconductor device 10. As shown in Figure 7A, the side surface of the semiconductor chip 20 may be exposed from the sealing member 40. This makes it possible to reduce the amount of resin used, which is the material of the sealing member 40, while ensuring reliability.

[0037] 7B, the semiconductor device 10 may have a QFN (Quad Flat Non-leaded package) form. In the QFN, electrode pads 34 are used as connection terminals instead of leads. By using the QFN package form, it is possible to make the package size smaller than that of the QFP.

[0038] 7C, the semiconductor device 10 may have a BGA form. In a BGA, solder balls 35 are arranged in a lattice pattern on the back surface of the package instead of leads. By using a BGA as the package form, it is possible to make the package size smaller than that of a QFP.

[0039] 7D, the semiconductor device 10 may have a plurality of semiconductor chips 20. The plurality of semiconductor chips 20 are each mounted on a lead frame 30 and sealed with a sealing member 40.

[0040] The following supplementary notes are further disclosed regarding the above embodiment. (Appendix 1) a semiconductor chip having rewiring; a lead frame including a die pad on which the semiconductor chip is mounted and a lead connected to the die pad, the rewiring and the die pad being electrically connected by solder or a conductive adhesive; a sealing member for sealing the semiconductor chip; A semiconductor device comprising:

[0041] (Appendix 2) The semiconductor chip comprises: A semiconductor substrate on which circuit elements are formed; an insulating film covering a semiconductor substrate; an electrode provided on the insulating film, connected to the circuit element and connected to the rewiring; A connection terminal connected to the rewiring; having The rewiring is provided in a rewiring layer having the same size as the planar size of the semiconductor substrate. 2. The semiconductor device according to claim 1.

[0042] (Appendix 3) the semiconductor chip has a plurality of connection terminals connected to the rewiring; the die pad has a plurality of electrically isolated divided pieces corresponding to the plurality of connection terminals, Each of the plurality of connection terminals is connected to a corresponding one of the plurality of segments. 3. The semiconductor device according to claim 1 or 2.

[0043] (Appendix 4) A side surface of the semiconductor chip is exposed from the sealing member. 4. The semiconductor device according to claim 1,

[0044] (Appendix 5) A plurality of the semiconductor chips are mounted on the lead frame; The sealing member seals a plurality of semiconductor chips. 5. The semiconductor device according to claim 1,

[0045] (Appendix 6) providing a semiconductor chip having redistribution lines; a step of connecting the die pad and the rewiring of a lead frame having a die pad and a lead connected to the die pad by solder or a conductive adhesive; encapsulating the semiconductor chip with an encapsulating material; A method for manufacturing a semiconductor device comprising the steps of: [Explanation of symbols]

[0046] 10 Semiconductor device 20. Semiconductor Chips 21 Semiconductor substrate 22 Circuit elements 23 Insulating film 24 electrodes 30 Lead Frame 31 Die pad 32 Split piece 33 Lead 40 Sealing member 50 redistribution layer 52 Rewiring 55 Connection terminal

Claims

1. A semiconductor chip having rewiring; a lead frame including a die pad on which the semiconductor chip is mounted and a lead connected to the die pad, the rewiring and the die pad being electrically connected by solder or a conductive adhesive; a sealing member for sealing the semiconductor chip; A semiconductor device comprising:

2. The semiconductor chip comprises: A semiconductor substrate on which circuit elements are formed; an insulating film covering a semiconductor substrate; an electrode provided on the insulating film, connected to the circuit element and connected to the rewiring; A connection terminal connected to the rewiring; having The rewiring is provided in a rewiring layer having the same size as the planar size of the semiconductor substrate. The semiconductor device according to claim 1 .

3. the semiconductor chip has a plurality of connection terminals connected to the rewiring; the die pad has a plurality of electrically isolated divided pieces corresponding to the plurality of connection terminals, Each of the plurality of connection terminals is connected to a corresponding one of the plurality of segments. The semiconductor device according to claim 1 .

4. A side surface of the semiconductor chip is exposed from the sealing member. The semiconductor device according to claim 1 .

5. A plurality of the semiconductor chips are mounted on the lead frame; The sealing member seals a plurality of semiconductor chips. The semiconductor device according to claim 1 .

6. providing a semiconductor chip having redistribution lines; a step of connecting the die pad and the rewiring of a lead frame having a die pad and a lead connected to the die pad by solder or a conductive adhesive; encapsulating the semiconductor chip with an encapsulating material; A method for manufacturing a semiconductor device comprising the steps of:

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