Oscillation circuit

Abstract

To suppress the power supply voltage dependency of an oscillation frequency.SOLUTION: An oscillation circuit includes a first circuit that switches the level of an output signal depending on whether the voltage level of a first node at which a charging voltage of the capacitor is output is equal to or higher than a threshold, and a second circuit that switches between charging and discharging the capacitor depending on the level of the output signal of the first circuit. The first circuit switches the level of the output signal only on the basis of the potential difference between the first node and a ground line, not on the potential difference between a power supply line and the first node.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed technology relates to an oscillator circuit. [Background technology]

[0002] The following techniques are known as techniques related to oscillator circuits. Patent Document 1 describes an oscillator circuit that includes a Schmitt circuit that includes two CMOS inverters with different thresholds, which outputs a high-level signal when an input signal becomes smaller than the threshold of the first CMOS inverter and outputs a low-level signal when the input signal becomes larger than the threshold of the second CMOS inverter, a level exchange circuit that has a threshold that increases when the difference between the thresholds of the two CMOS inverters included in the Schmitt circuit becomes smaller and decreases when the difference between the thresholds of the two CMOS inverters included in the Schmitt circuit becomes larger, subtracts the threshold from the high-level signal output from the Schmitt circuit and adds it to the low-level output signal, and outputs the result, and a capacitor that is charged via a resistor by the output voltage of the level exchange circuit and provides an input voltage to the Schmitt circuit.

[0003] Patent Document 2 describes an ultra-low power RC oscillator including: a current generating unit including a current source that generates a current; and a variable resistor whose magnitude is variably set and which is configured by combining resistance elements having mutually opposing characteristics with respect to temperature changes in a predetermined ratio, and which adjusts the magnitude of the current by the variable resistor; a startup circuit unit connected to the current generating unit and fixing the current generating unit at a constant bias operating point so that the current generating unit can stably generate a current; a charge / discharge circuit unit including a variable capacitor whose magnitude is variably set and a plurality of transistors, and which charges and discharges the variable capacitor using a current generated in the current generating unit and the plurality of transistors; an oscillation signal output unit connected to the charge / discharge circuit unit, which includes a plurality of inverters, and outputs an oscillation signal whose frequency is determined by the resistance value of the variable resistor and the capacitance value of the variable capacitor; and an inverter driving power supply unit that mirrors the current generated from the current generating unit and provides the mirrored current as a driving power supply for the plurality of inverters. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 5-183336 [Patent Document 2] JP 2007-325273 A Summary of the Invention [Problem to be solved by the invention]

[0005] A possible configuration of a CR oscillation circuit is one that has a first inverter that switches the level of an output signal depending on whether the voltage level of a first node, at which the charging voltage of the capacitor is output, is equal to or higher than a threshold value, and a second inverter that switches between charging and discharging the capacitor depending on the level of the output signal of the first inverter.

[0006] The first inverter and the second inverter may each be constituted by a CMOS (Complementary Metal-Oxide-Semiconductor) inverter having an n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) (hereinafter referred to as n-MOS) and a p-channel MOSFET (hereinafter referred to as p-MOS).

[0007] However, when the first inverter and the second inverter include p-MOS, the oscillation frequency becomes more dependent on the power supply voltage. That is, when the power supply voltage changes, the threshold of the p-MOS constituting the first inverter changes, and the oscillation frequency changes. Also, when the power supply voltage fluctuates, the output current from the p-MOS of the second inverter, i.e., the charging current of the capacitor, changes, and the oscillation frequency changes.

[0008] The disclosed technology has been made in consideration of the above-mentioned points, and aims to suppress the power supply voltage dependency of the oscillation frequency in an oscillation circuit. [Means for solving the problem]

[0009] An oscillator circuit according to a first aspect of the disclosed technology includes a first circuit that switches the level of an output signal depending on whether the voltage level of a first node at which a charging voltage of a capacitor is output is equal to or higher than a threshold, and a second circuit that switches between charging and discharging of the capacitor depending on the level of the output signal of the first circuit, wherein the first circuit switches the level of the output signal based only on the potential difference between a power supply line and the first node and the potential difference between the first node and a ground line.

[0010] An oscillator circuit according to a second aspect of the disclosed technique includes a first circuit that switches the level of an output signal depending on whether the voltage level of a first node at which a charging voltage of a capacitor is output is equal to or higher than a threshold value, and a second circuit that switches between charging and discharging of the capacitor depending on the level of the output signal of the first circuit, wherein the second circuit includes a constant current circuit that is independent of a power supply voltage and supplies an output current of the constant current circuit as a charging current for the capacitor.

[0011] An oscillator circuit according to a third aspect of the disclosed technique includes a first circuit that switches the level of an output signal depending on whether the voltage level of a first node at which a charging voltage of a capacitor is output is equal to or higher than a threshold value, and a second circuit that switches between charging and discharging of the capacitor depending on the level of the output signal of the first circuit, wherein the first circuit switches the level of the output signal based only on the latter of the potential difference between a power supply line and the first node and the potential difference between the first node and a ground line, and the second circuit includes a constant current circuit that is independent of the power supply voltage and supplies an output current of the constant current circuit as a charging current for the capacitor. Effect of the Invention

[0012] According to the disclosed technique, it is possible to suppress the power supply voltage dependency of the oscillation frequency in an oscillation circuit. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram illustrating an example of a configuration of an oscillator circuit according to an embodiment of the disclosed technique. [Diagram 2] 1 is a time chart showing an example of operational waveforms of each part of an oscillator circuit according to an embodiment of the disclosed technique. [Diagram 3] FIG. 1 is a diagram illustrating a configuration of an oscillator circuit according to a comparative example. [Figure 4] FIG. 13 is a diagram illustrating an example of a configuration of an oscillator circuit according to another embodiment of the disclosed technique. [Diagram 5] FIG. 13 is a diagram illustrating an example of a configuration of an oscillator circuit according to another embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are given the same reference numerals, and duplicated descriptions will be omitted.

[0015] [First embodiment] 1 is a diagram showing an example of a configuration of an oscillator circuit 10 according to a first embodiment of the disclosed technique. The oscillator circuit 10 includes a first circuit 11, a second circuit 12, a CR circuit 13, an inverter 14, and a frequency divider circuit 15.

[0016] The CR circuit 13 has a resistive element 41 and a capacitor 42. One end of the resistive element 41 is connected to the second circuit 12, and the other end is connected to one end of the capacitor 42. The other end of the capacitor 42 is connected to the ground line. A charging voltage of the capacitor 42 is output from a first node n1 which is a connection point between the resistive element 41 and the capacitor 42. The resistive element 41 may be a variable resistor. By configuring the resistive element 41 with a variable resistor, it becomes possible to adjust the frequency of the oscillator circuit 10 by setting the resistance value of the variable resistor.

[0017] The first circuit 11 has a resistive element 21 and an n-MOS 22. The n-MOS 22 has a gate connected to a first node n1, a source connected to a ground line, and a drain connected to one end of the resistive element 21. The other end of the resistive element 21 is connected to a power supply line. A power supply voltage is supplied from the power supply line, and a ground voltage is supplied from the ground line. The first circuit 11 functions as an inverter that inverts the logical value of an input signal and outputs it. The first circuit 11 switches the level of an output signal depending on whether the voltage level of the first node n1, which outputs the charging voltage of the capacitor 42, is equal to or higher than a threshold value. The first circuit 11 outputs a low-level output signal when the voltage level of the first node n1 (i.e., the potential difference between the first node n1 and the ground line) is equal to or higher than the threshold value of the n-MOS 22, and outputs a high-level output signal when the voltage level of the first node n1 is lower than the threshold value of the n-MOS 22. Since the first circuit 11 does not have a p-MOS, the level of the output signal is switched based only on the potential difference between the first node n1 and the power supply line and the potential difference between the first node n1 and the ground line. The output signal of the first circuit 11 is output from the second node n2, which is the drain node of the n-MOS 22.

[0018] The inverter 14 has an input terminal connected to the second node n2 and an output terminal connected to a third node n3 which is the node of the input terminal of the second circuit 12. The inverter 14 inverts the logical value of the output signal of the first circuit 11 and outputs the inverted logical value. The inverter 14 may be configured by, for example, a CMOS inverter.

[0019] The second circuit 12 is composed of a CMOS inverter having a p-MOS 31 and an n-MOS 32. The p-MOS 31 has a source connected to a power supply line, a gate connected to a third node n3, and a drain connected to the drain of the n-MOS 32. The n-MOS 32 has a drain connected to the drain of the p-MOS 31, a gate connected to the third node n3, and a source connected to a ground line. A fourth node n4, which is a node of the drain of the p-MOS 31 and the drain of the n-MOS 32, is used as the output terminal of the second circuit 12. One end of a resistor element 41 constituting a CR circuit 13 is connected to the fourth node n4.

[0020] The second circuit 12 inverts the logical value of the output signal of the inverter 14 and outputs it. The second circuit 12 switches between charging and discharging the capacitor 42 according to the level of the output signal of the first circuit 11 (inverter 14). Specifically, when a low-level signal is input to the third node n3, the p-MOS 31 is turned on, the capacitor 42 of the CR circuit 13 is charged, and the voltage level of the first node n1 rises. On the other hand, when a high-level signal is input to the third node n3, the n-MOS 32 is turned on, the capacitor 42 of the CR circuit 13 is discharged, and the voltage level of the first node n1 drops.

[0021] The frequency divider circuit 15 includes a flip-flop. The flip-flop has a clock input terminal CK connected to the third node n3 and a data input terminal D connected to the inverted data output terminal Q-bar. The frequency divider circuit 15 outputs a signal from the data output terminal Q, which is half the frequency of the signal at the third node n3 input to the clock input terminal CK. The logical value of the signal output from the data output terminal Q is inverted by an inverter 16, and the signal is output as the output signal S of the oscillation circuit 10. OUT is output from the output terminal 17.

[0022] The operation of the oscillator circuit 10 will be described below with reference to Fig. 2. Fig. 2 is a time chart showing an example of the operating waveforms of each part of the oscillator circuit 10. Fig. 2 shows voltage waveforms of a first node n1 which is a node at the input end of the first circuit 11, a node n2 which is a node at the output end of the first circuit 11, and a fourth node n4 which is a node at the output end of the second circuit 12.

[0023] At time t0 when the output signal of the second circuit 12 (signal of the fourth node n4) transitions to a high level, charging of the capacitor 42 starts, and the voltage level of the first node n1 rises. At time t1 when the voltage level of the first node n1 reaches the threshold of the first circuit 11, the n-MOS 22 of the first circuit 11 turns on, and the output signal of the first circuit 11 (signal of the second node n2) transitions to a low level. Accordingly, when the voltage level of the third node n3 (not shown) transitions to a high level, the n-MOS 32 of the second circuit 12 turns on, and at time t2, the output signal of the second circuit 12 (signal of the fourth node n4) transitions to a low level. The period from time t1 to time t2 is a delay time in signal transmission. When the n-MOS 32 turns on, discharging of the capacitor 42 starts, and the voltage level of the first node n1 drops.

[0024] At time t3 when the voltage level of the first node n1 falls below the threshold of the first circuit 11, the n-MOS 22 of the first circuit 11 turns off, and the output signal of the first circuit 11 (signal of the second node n2) transitions to a high level. In response to this, when the voltage level of the third node n3 (not shown) transitions to a low level, the p-MOS 31 of the second circuit 12 turns on, and at time t4, the output signal of the second circuit 12 (signal of the fourth node n4) transitions to a high level. This starts charging the capacitor 42. By repeating the above operations, the oscillator circuit 10 outputs an output signal S having a predetermined oscillation frequency. OUT is output from output terminal 17.

[0025] 3 is a diagram showing a configuration of an oscillator circuit 10X according to a comparative example. The oscillator circuit 10X according to the comparative example differs from the oscillator circuit 10 according to the embodiment of the disclosed technique described above in that a first circuit 11X is configured by a CMOS inverter having a p-MOS 23 and an n-MOS 24.

[0026] In the first circuit 11X according to the comparative example, when the potential difference between the power supply line and the first node n1 becomes larger than the gate-source threshold of the p-MOS 23, the p-MOS 23 turns on, and the output signal of the first circuit 11X transitions to a high level. In the first circuit 11X according to the comparative example, the p-MOS 23 is involved in the output of a high level signal, so the voltage level of the first node n1 for the output signal of the first circuit 11X to transition to a high level (i.e., the threshold of the first circuit 11X) changes depending on the level of the power supply voltage supplied to the power supply line. When the threshold of the first circuit 11X changes with the change in the level of the power supply voltage, the charging and discharging time of the capacitor 42 changes, and thus the oscillation frequency of the oscillation circuit 10X changes. That is, according to the oscillation circuit 10X according to the comparative example in which the first circuit 11X includes the p-MOS 23, the dependence of the oscillation frequency on the power supply voltage increases.

[0027] On the other hand, in the first circuit 11 according to the embodiment of the disclosed technique, when the potential difference between the first node n1 and the ground line becomes smaller than the gate-source threshold of the n-MOS 22, the n-MOS 22 turns off and the output signal of the first circuit 11 transitions to a high level. Also, when the potential difference between the first node n1 and the ground line becomes larger than the gate-source threshold of the n-MOS 22, the n-MOS 22 turns on and the output signal of the first circuit 11 transitions to a low level.

[0028] In the first circuit 11 according to the embodiment of the disclosed technology, the p-MOS is not involved in the output of a high-level signal, so the voltage level of the first node n1 for the output signal of the first circuit 11 to transition to a high level (i.e., the threshold of the first circuit 11) is not affected by the power supply voltage supplied to the power supply line. The same is true when the output signal of the first circuit 11 transitions to a low level. That is, the first circuit 11 according to the embodiment of the disclosed technology switches the level of the output signal based only on the potential difference between the power supply line and the first node n1 and the potential difference between the first node n1 and the ground line. According to the oscillation circuit 10 according to the embodiment of the disclosed technology, the threshold of the first circuit 11 is not affected by the power supply voltage, so it is possible to suppress the power supply voltage dependency of the oscillation frequency.

[0029] [Second embodiment] 4 is a diagram showing an example of the configuration of an oscillator circuit 10A according to the second embodiment of the disclosed technique. The oscillator circuit 10A differs from the oscillator circuit 10X (see FIG. 3) according to the comparative example described above in that the configuration of a second circuit 12A of the oscillator circuit 10A is different. The second circuit 12A includes a constant current circuit 33 that does not depend on the power supply voltage. The second circuit 12A supplies the output current of the constant current circuit 33 as a charging current for the capacitor 42. The second circuit 12A includes a CMOS inverter having a p-MOS 31 and an n-MOS 32, similar to the second circuit 12 according to the first embodiment.

[0030] The constant current circuit 33 is a constant current circuit that is not affected by the power supply voltage. The constant current circuit 33 generates a current that is independent of the power supply voltage. The p-MOS 34, which is an output transistor of the constant current circuit 33, has a source connected to a power supply line and a drain connected to the source of the p-MOS 31 that constitutes a CMOS inverter. When the p-MOS 31 is turned on, the output current of the constant current circuit 33 is supplied as a charging current for the capacitor 42. Note that the configuration of the constant current circuit 33 shown in FIG. 4 is merely an example, and any constant current circuit that can supply a constant current that is independent of the power supply voltage can be applied.

[0031] 3, the charging current of the capacitor 42 depends on the power supply voltage supplied to the power line. When the charging current of the capacitor 42 changes with a change in the level of the power supply voltage, the charging and discharging time of the capacitor 42 changes, and the oscillation frequency of the oscillation circuit 10X also changes. That is, in the oscillation circuit 10X according to the comparative example in which the charging current is affected by the power supply voltage, the power supply voltage dependency of the oscillation frequency becomes large.

[0032] On the other hand, in the oscillator circuit 10A according to the second embodiment of the disclosed technique, the second circuit 12A includes a constant current circuit 33 that does not depend on the power supply voltage, and the output current of the constant current circuit 33 is supplied as a charging current for the capacitor 42. Since the charging current for the capacitor 42 is not affected by the power supply voltage, it is possible to suppress the power supply voltage dependency of the oscillation frequency of the oscillator circuit 10A.

[0033] [Third embodiment] 5 is a diagram showing an example of the configuration of an oscillator circuit 10B according to a third embodiment of the disclosed technology. The oscillator circuit 10B includes a first circuit 11 according to the first embodiment and a second circuit 12A according to the second embodiment. That is, in the oscillator circuit 10B, the first circuit 11 switches the level of the output signal based only on the potential difference between the power supply line and the first node n1 and the potential difference between the first node n1 and the ground line. In the oscillator circuit 10B, the second circuit 12A includes a constant current circuit 33 that does not depend on the power supply voltage, and supplies the output current of the constant current circuit 33 as a charging current for the capacitor 42.

[0034] According to the oscillator circuit 10B according to the third embodiment of the disclosed technique, it is possible to further enhance the effect of suppressing the power supply voltage dependency of the oscillation frequency. [Explanation of symbols]

[0035] 10, 10A, 10B Oscillator Circuit 11 First Circuit 12, 12A second circuit 33 Constant current circuit 42 Capacitor

Claims

1. a first circuit that switches a level of an output signal depending on whether a voltage level of a first node, at which a charging voltage of a capacitor is output, is equal to or higher than a threshold; a second circuit that switches between charging and discharging the capacitor in response to a level of the output signal of the first circuit; Including, The first circuit switches the level of the output signal based only on the potential difference between a power supply line and the first node and the potential difference between the first node and a ground line. Oscillator circuit.

2. The first circuit includes: an n-channel MOSFET having a gate connected to the first node and a source connected to a ground line; a resistor element provided between a power supply line and the drain of the n-channel MOSFET.

2. The oscillator circuit according to claim 1.

3. a first circuit that switches a level of an output signal depending on whether a voltage level of a first node, at which a charging voltage of a capacitor is output, is equal to or higher than a threshold; a second circuit that switches between charging and discharging the capacitor in response to a level of the output signal of the first circuit; Including, The second circuit includes a constant current circuit that does not depend on a power supply voltage, and supplies an output current of the constant current circuit as a charging current for the capacitor. Oscillator circuit.

4. a first circuit that switches a level of an output signal depending on whether a voltage level of a first node, at which a charging voltage of a capacitor is output, is equal to or higher than a threshold; a second circuit that switches between charging and discharging the capacitor in response to a level of the output signal of the first circuit; Including, the first circuit switches a level of the output signal based only on a potential difference between a power supply line and the first node and a potential difference between the first node and a ground line; The second circuit includes a constant current circuit that does not depend on a power supply voltage, and supplies an output current of the constant current circuit as a charging current for the capacitor. Oscillator circuit.

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