Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of reducing carbon vacancies in a silicon carbide layer and a manufacturing method thereof.SOLUTION: A semiconductor device includes a silicon carbide layer having an element region and a termination region surrounding the element region, and including a first semiconductor portion of a first conductivity type having a first portion in the element region, and a second semiconductor portion provided on the first semiconductor portion in a first direction and adjacent to the first portion in a second direction perpendicular to the first direction, a gate electrode facing the second semiconductor portion in the element region, a first insulating film provided between the gate electrode and the silicon carbide layer, and a second insulating film provided on the first portion of the first semiconductor portion and thicker than the first insulating film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In semiconductor devices using silicon carbide (SiC), a problem can occur in which high-temperature heat treatment for activating a region into which impurities that impart a conductivity type have been introduced causes carbon to be desorbed and vacancies to be generated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-176992 A [Non-patent literature]

[0004] [Non-Patent Document 1] Koutarou Kawahara; Jun Suda; Tsunenobu Kimoto, "Analytical model for reduction of deep levels in SiC by thermal oxidation", Journal of Applied Physics 111, 053710 (2012); doi: 10.1063 / 1.3692766 Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments provide a semiconductor device capable of reducing carbon vacancies in a silicon carbide layer and a manufacturing method thereof. [Means for solving the problem]

[0006] According to an embodiment, a semiconductor device comprises a silicon carbide layer having an element region and a termination region surrounding the element region, the silicon carbide layer having a first semiconductor portion of a first conductivity type having a first portion in the element region, and a second semiconductor portion provided on the first semiconductor portion in a first direction and adjacent to the first portion in a second direction perpendicular to the first direction, a gate electrode facing the second semiconductor portion in the element region, a first insulating film provided between the gate electrode and the silicon carbide layer, and a second insulating film provided on the first portion of the first semiconductor portion and thicker than the first insulating film. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a schematic plan view of a silicon carbide layer in the semiconductor device shown in FIG. [Diagram 3] 3(a) and 3(b) are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. [Figure 4] 3(a) and 3(b) are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. [Diagram 5] 3(a) and 3(b) are schematic cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment. [Figure 6] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. In each drawing, the same components are given the same reference numerals. In the following embodiments, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0009] [First embodiment] As shown in Fig. 1, the semiconductor device 1 of the first embodiment includes a silicon carbide layer 10. The silicon carbide layer 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in a first direction Z. The first direction Z is a direction that connects the first surface 10A and the second surface 10B in the shortest distance. Two directions perpendicular to the first direction Z are defined as a second direction X and a third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0010] 2, silicon carbide layer 10 has an element region R1 and a termination region R2. In a plan view, termination region R2 continuously surrounds element region R1. The area of ​​element region R1 is larger than the area of ​​termination region R2.

[0011] The silicon carbide layer 10 has an n-type first semiconductor portion 11 and a p-type second semiconductor portion 12 provided on the first semiconductor portion 11 in the first direction Z. The silicon carbide layer 10 further has an n-type third semiconductor portion 13, a p-type fourth semiconductor portion 14, and a p-type fifth semiconductor portion 15. The third semiconductor portion 13 and the fifth semiconductor portion 15 are provided on the surface of the second semiconductor portion 12. The fourth semiconductor portion 14 is a SiC substrate, and the first semiconductor portion 11 is epitaxially grown on the SiC substrate. The n-type impurity concentration of the third semiconductor portion 13 is higher than the n-type impurity concentration of the first semiconductor portion 11. The p-type impurity concentration of the fourth semiconductor portion 14 and the p-type impurity concentration of the fifth semiconductor portion 15 are higher than the p-type impurity concentration of the second semiconductor portion 12.

[0012] 1 is a cross-sectional view of the element region R1. At least the first semiconductor portion 11 and the fourth semiconductor portion 14 are provided continuously in the element region R1 and the termination region R2.

[0013] The semiconductor device 1 further includes an upper electrode 21 provided on the first surface 10A and a lower electrode 22 provided on the second surface 10B. The lower electrode 22 contacts the lower surface of the fourth semiconductor portion 14 and is electrically connected to the fourth semiconductor portion 14. The upper electrode 21 contacts the third semiconductor portion 13 and is electrically connected to the third semiconductor portion 13. In addition, the upper electrode 21 contacts the fifth semiconductor portion 15, and the second semiconductor portion 12 is electrically connected to the upper electrode 21 via the fifth semiconductor portion 15.

[0014] The semiconductor device 1 of the first embodiment is a bipolar element, and has, for example, an IGBT (Insulated Gate Bipolar Transistor) structure. The lower electrode 22 is a collector electrode, the fourth semiconductor portion 14 is a collector layer, the first semiconductor portion 11 is a drift layer, the second semiconductor portion 12 is a base layer, the third semiconductor portion 13 is an emitter layer, the upper electrode 21 is an emitter electrode, and the fifth semiconductor portion 15 is a base contact layer.

[0015] The first semiconductor portion 11 in the element region R1 contacts the bottom surface of the second semiconductor portion 12 in the first direction Z. The first semiconductor portion 11 in the element region R1 has a first portion 11a located on the first surface 10A side and adjacent to the side surface of the second semiconductor portion 12 in the second direction X. The first semiconductor portion 11 in the element region R1 also has a second portion 11b located on the first surface 10A side and adjacent to the side surface of the second semiconductor portion 12 in the second direction X.

[0016] The semiconductor device 1 further includes a gate electrode 30. In the example shown in FIG. 1, a planar gate structure is shown. The gate electrode 30 is provided on the first surface 10A of the element region R1 of the silicon carbide layer 10. The second semiconductor portion 12 has a portion 12a located between the second portion 11b and the third semiconductor portion 13 in the second direction X. The gate electrode 30 faces at least the portion 12a of the second semiconductor portion 12. The gate electrode 30 is also located on the second portion 11b. The semiconductor device 1 is not limited to the planar gate structure, and may have a trench gate structure.

[0017] The semiconductor device 1 further includes a first insulating film 41 provided between the gate electrode 30 and the silicon carbide layer 10. The first insulating film 41 is provided between the portion 12a of the second semiconductor portion 12 and the gate electrode 30, and between the second portion 11b and the gate electrode 30. As the first insulating film 41, for example, a silicon oxide film can be used.

[0018] The semiconductor device 1 includes a second insulating film 42 provided on the first portion 11a of the first semiconductor portion 11 in the element region R1. The thickness of the second insulating film 42 in the first direction Z is greater than the thickness of the first insulating film 41 in the first direction Z. Part of the second insulating film 42 is also provided on the second semiconductor portion 12 adjacent to the first portion 11a and on the third semiconductor portion 13. As the second insulating film 42, for example, a silicon oxide film can be used.

[0019] The semiconductor device 1 further includes an interlayer insulating film 43 provided between the gate electrode 30 and the upper electrode 21. As the interlayer insulating film 43, for example, a silicon oxide film can be used.

[0020] When the semiconductor device 1 is in an on-operation state, a potential equal to or higher than the threshold value is applied to the gate electrode 30, and an inversion layer (n-type channel) is formed in a portion 12a of the second semiconductor portion 12 facing the gate electrode 30. A potential lower than that of the lower electrode 22 is applied to the upper electrode 21, and a potential higher than that of the upper electrode 21 is applied to the lower electrode 22. In this state, a current flows between the lower electrode 22 and the upper electrode 21 in the element region R1 through the fourth semiconductor portion 14, the second portion 11b of the first semiconductor portion 11, the n-type channel, and the third semiconductor portion 13.

[0021] According to this embodiment, by providing the first portion 11a in the first semiconductor portion 11 in the element region R1, carbon can be diffused into the first semiconductor portion 11 in the element region R1 through the first portion 11a as described below, thereby reducing carbon vacancies. This makes it possible to reduce recombination of holes and electrons in carbon vacancies when the semiconductor device 1 is in an on-state and performing bipolar operation, thereby suppressing deterioration in the operating characteristics of the semiconductor device 1.

[0022] Carbon diffuses from the first portion 11a downward of the first portion 11a, and further diffuses within the first semiconductor portion 11 in the second direction X and the third direction Y. Therefore, the carbon density within the first semiconductor portion 11 below the first portion 11a is higher than the carbon density within the first semiconductor portion 11 below the gate electrode 30 (below the second portion 11b). Also, the carbon density within the first semiconductor portion 11 on the first surface 10A side is higher than the carbon density within the first semiconductor portion 11 on the second surface 10B side.

[0023] When the potential of the gate electrode 30 becomes lower than the threshold potential, the n-type channel is cut off and the semiconductor device 1 is in an off state. In this off state, a depletion layer spreads in the first semiconductor part 11 from the pn junction between the n-type first semiconductor part 11 and the p-type second semiconductor part 12, and the breakdown voltage of the semiconductor device 1 is maintained. Since the second insulating film 42 is provided between the first part 11a and the upper electrode 21, it is possible to suppress the leakage current through the first part 11a and maintain the breakdown voltage. The thickness of the first insulating film 41 functioning as a gate insulating film is preferably several tens of nm, and the thickness of the second insulating film 42 for maintaining the breakdown voltage is preferably 100 nm or more.

[0024] A plurality of first portions 11a may be provided in the element region R1. The planar pattern of the first portions 11a may be, for example, a concentric circle pattern, a stripe pattern, a lattice pattern, a dot pattern, or the like.

[0025] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to Fig. 3(a) to Fig. 5(b). The cross sections shown in Fig. 3(a) to Fig. 5(b) correspond to the cross section of the portion in Fig. 1 where the first portion 11a of the first semiconductor portion 11 is provided.

[0026] As shown in FIG. 3(a), a first region r1 into which impurities are implanted and a second region r2 into which impurities are not implanted are formed on the upper portion of the silicon carbide layer 10. The first region r1 is a region into which impurities are implanted by ion implantation. The first region r1 includes a p-type second semiconductor portion 12 and an n-type third semiconductor portion 13. After a p-type impurity is implanted from the first surface 10A into the upper portion of the n-type first semiconductor portion 11, an n-type impurity is implanted. For example, Al (aluminum), B (boron), and Ga (gallium) can be used as the p-type impurity, and N (nitrogen) and P (phosphorus) can be used as the n-type impurity. The second region r2 is not implanted with impurities. The second region r2 is a part of the first semiconductor portion 11. The second region r2 is adjacent to the first region r1 in the second direction X. The first surface 10A of the silicon carbide layer 10 includes an upper surface of the first region r1 and an upper surface of the second region r2.

[0027] After the ion implantation, a first heat treatment step is performed. The first region r1 into which the impurities are implanted is activated by this first heat treatment step. The temperature of the first heat treatment step is, for example, 1600° C. or higher. The high-temperature heat treatment in this first heat treatment step may cause carbon (C) to be desorbed from the silicon carbide layer 10, resulting in vacancies. According to this embodiment, a second heat treatment step is performed after the first heat treatment step in order to fill the vacancies generated in the first heat treatment step with carbon.

[0028] After the first heat treatment step and before the second heat treatment step, it is preferable to cover the upper surface of the first region r1 with a protective film. As shown in FIG. 3(b), the protective film 40 is formed so as to cover the entire first surface 10A of the silicon carbide layer 10 including the upper surface of the first region r1 and the upper surface of the second region r2, and then an opening 40a is formed in the protective film 40 as shown in FIG. 4(a). In the opening 40a, the upper surface of the second region r2 is exposed from the protective film 40. The upper surface of the first region r1 is covered with the protective film 40. For example, a silicon nitride film can be used as the protective film 40.

[0029] In the second heat treatment step, the second region r2 is thermally oxidized at a temperature lower than that in the first heat treatment step. In the second heat treatment step, heat treatment is performed in an oxygen-containing atmosphere at a temperature of, for example, about 1300°C. As a result, a thermal oxidation reaction proceeds from the upper surface of the second region r2 exposed in the opening 40a, and a part (upper part) of the second region r2 is converted into a thermally oxidized portion 50 shown in FIG. 4(b). The upper surface of the first region r1 is not thermally oxidized because it is covered with the protective film 40. Note that although the upper surface of the region adjacent to the second region r2 in the second semiconductor portion 12 is covered with the protective film 40, thermal oxidation proceeds from the lateral direction (second direction X), and the thermally oxidized portion 50 may also be formed in the region adjacent to the second region r2 in the second semiconductor portion 12.

[0030] In the second heat treatment step, carbon in the silicon carbide layer 10 that has bonded with oxygen is desorbed as CO or CO2 gas, and carbon that has not bonded with oxygen thermally diffuses from the second region r2 downward in the silicon carbide layer 10 in the second direction X and the third direction Y, as shown typically by black circles in Fig. 4(b). This allows the vacancies generated in the first heat treatment step to be filled with carbon.

[0031] The second region r2 is a region into which no impurities are ion-implanted, and thus does not have any defects due to ion implantation. Therefore, carbon can diffuse from the second region r2 into the silicon carbide layer 10 without being inhibited by the defects due to ion implantation.

[0032] As a comparative example, a method of filling vacancies by ion-implanting carbon from the first surface 10A of the silicon carbide layer 10 after the first heat treatment step can be considered. However, in this case, defects caused by the carbon ion-implantation may occur at the pn junction interface between the second semiconductor portion 12 and the first semiconductor portion 11, which may cause leakage current.

[0033] According to this embodiment, carbon is diffused by thermal oxidation treatment, so that defects caused by carbon ion implantation are not generated.

[0034] After the second heat treatment step, the thermally oxidized portion 50 is removed. For example, the thermally oxidized portion 50 can be removed using hydrofluoric acid, dilute hydrofluoric acid, buffered hydrofluoric acid, or the like. As a result, a recess 10C is formed above the second region r2, as shown in FIG. 5(a). The second region r2 below the recess 10C becomes the first portion 11a of the first semiconductor portion 11 described above. Thereafter, the protective film 40 is removed. For example, the protective film 40 can be removed using hot phosphoric acid. As a result, the upper surface of the first region r1, the upper surface of the second region r2, and the recess 10C are exposed, as shown in FIG. 5(b).

[0035] After removing the protective film 40, the second insulating film 42 shown in FIG. 1 is formed in the recess 10C. For example, the second insulating film 42 can be formed by a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. The second insulating film 42 is provided at least on the first portion 11a of the first semiconductor portion 11.

[0036] In the step of removing the protective film 40, if the protective film 40 is removed under conditions that do not remove the thermally oxidized portion 50, the thermally oxidized portion 50 may not be removed and may remain as the second insulating film .

[0037] [Second embodiment] FIG. 6 is a schematic cross-sectional view of a semiconductor device 2 according to the second embodiment.

[0038] The semiconductor device 2 of the second embodiment includes a silicon carbide layer 110. The silicon carbide layer 110 has a first surface 110A and a second surface 110B located on the opposite side to the first surface 110A in the first direction Z. As in the first embodiment, the silicon carbide layer 110 of the second embodiment also has an element region and a termination region. Figure 6 is a cross-sectional view of the element region R1.

[0039] The silicon carbide layer 110 has an n-type first semiconductor portion 111 and a p-type second semiconductor portion 112 provided on the first semiconductor portion 111 in the first direction Z. The silicon carbide layer 110 further has an n-type third semiconductor portion 114. At least the first semiconductor portion 111 and the third semiconductor portion 114 are provided continuously in the element region and the termination region.

[0040] The third semiconductor portion 114 is a SiC substrate, and the first semiconductor portion 111 is epitaxially grown on the SiC substrate. The third semiconductor portion 114 has a higher n-type impurity concentration than the first semiconductor portion 111.

[0041] The semiconductor device 2 further includes an upper electrode 121 provided on the first surface 110A and a lower electrode 122 provided on the second surface 110B. The lower electrode 122 contacts the lower surface of the third semiconductor portion 114 and is electrically connected to the third semiconductor portion 114. The upper electrode 121 contacts the second semiconductor portion 112 and is electrically connected to the second semiconductor portion 112.

[0042] The semiconductor device 2 of the second embodiment is also a bipolar element, and has, for example, a PIN diode structure. The upper electrode 121 is an anode electrode, the second semiconductor portion 112 is an anode layer, the first semiconductor portion 111 is a drift layer, the third semiconductor portion 114 is a cathode layer, and the lower electrode 122 is a cathode electrode.

[0043] The first semiconductor portion 111 of the element region R1 contacts the bottom surface of the second semiconductor portion 112 in the first direction Z. In addition, the first semiconductor portion 111 of the element region R1 has a first portion 111a located on the first surface 110A side and adjacent to the side surface of the second semiconductor portion 112 in the second direction X.

[0044] The semiconductor device 2 includes an insulating film 142 provided on the first portion 111a of the first semiconductor portion 111 in the element region R1. A part of the insulating film 142 is also provided on a part of the second semiconductor portion 112 adjacent to the first portion 111a. The insulating film 142 may be, for example, a silicon oxide film.

[0045] When the semiconductor device 2 is in an on-operation state, a higher potential is applied to the upper electrode 121 than to the lower electrode 122, and a lower potential is applied to the lower electrode 122 than to the upper electrode 121. In this state, a current flows between the upper electrode 121 and the lower electrode 122 in the element region R1 through the second semiconductor portion 112, the first semiconductor portion 111, and the third semiconductor portion 114.

[0046] The manufacturing method of the semiconductor device 2 of the second embodiment, similar to the first embodiment described above, includes a step of forming a first region (a region where the second semiconductor portion 112 is provided) into which impurities are implanted and a second region (a region where the first portion 111a is provided) into which impurities are not implanted, in the upper part of the silicon carbide layer 110, a first heat treatment step of activating the first region, and, after the first heat treatment step, a second heat treatment step of thermally oxidizing the second region at a temperature lower than that of the first heat treatment step.

[0047] Then, in the second heat treatment step, similarly to the first embodiment, carbon is diffused into the first semiconductor portion 111 of the element region R1 through the first portion 111a, thereby reducing carbon vacancies. This reduces recombination of holes and electrons in carbon vacancies when the semiconductor device 2 is in an on-state and performing bipolar operation, thereby suppressing degradation of the operating characteristics of the semiconductor device 2.

[0048] Carbon diffuses from the first portion 111a downward of the first portion 111a, and further diffuses within the first semiconductor portion 111 in the second direction X and the third direction Y. Therefore, the carbon density within the first semiconductor portion 111 below the first portion 111a is higher than the carbon density within the first semiconductor portion 111 below the connection portion between the second semiconductor portion 112 and the upper electrode 121. Also, the carbon density within the first semiconductor portion 111 on the first surface 110A side is higher than the carbon density within the first semiconductor portion 111 on the second surface 110B side.

[0049] When a reverse voltage is applied to the pn junction between the second semiconductor portion 112 and the first semiconductor portion 111, a depletion layer spreads from the pn junction into the first semiconductor portion 111, thereby maintaining the breakdown voltage of the semiconductor device 2. Since the insulating film 142 is provided between the first portion 111a of the first semiconductor portion 111 and the upper electrode 121, it is possible to suppress leakage current through the first portion 111a, and it is possible to maintain the breakdown voltage. In order to maintain the breakdown voltage, the thickness of the insulating film 142 is preferably 100 nm or more.

[0050] A plurality of first portions 111a may be provided in the element region R1. The planar pattern of the first portions 111a may be, for example, a concentric circle pattern, a stripe pattern, a lattice pattern, a dot pattern, or the like.

[0051] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0052] 1,2...semiconductor device, 10,110...silicon carbide layer, 10A,110A...first surface, 10B,110B...second surface, 11,111...first semiconductor portion, 11a,111a...first portion, 11b...second portion, 12,112...second semiconductor portion, 13,114...third semiconductor portion, 14...fourth semiconductor portion, 15...fifth semiconductor portion, 21,121...upper electrode, 22,122...lower electrode, 30...gate electrode, 40...protective film, 41...first insulating film, 42...second insulating film, 43...interlayer insulating film, 50...thermal oxidation portion, 142...insulating film, R1...element region, R2...termination region, r1...first region, r2...second region

Claims

1. A silicon carbide layer having an element region and a termination region surrounding the element region, a first semiconductor portion of a first conductivity type having a first portion in the element region; a second semiconductor portion provided on the first semiconductor portion in a first direction and adjacent to the first portion in a second direction perpendicular to the first direction; a silicon carbide layer having a gate electrode facing the second semiconductor portion of the element region; a first insulating film provided between the gate electrode and the silicon carbide layer; a second insulating film provided on the first portion of the first semiconductor portion and thicker than the first insulating film; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein a carbon density in the first semiconductor portion below the first portion is higher than a carbon density in the first semiconductor portion below the gate electrode.

3. 3. The semiconductor device according to claim 1, wherein the second insulating film has a thickness of 100 nm or more.

4. A silicon carbide layer having an element region and a termination region surrounding the element region, a first semiconductor portion of a first conductivity type having a first portion in the element region; a second semiconductor portion provided on the first semiconductor portion in a first direction and adjacent to the first portion in a second direction perpendicular to the first direction; a silicon carbide layer having an upper electrode provided on the second semiconductor portion of the element region and electrically connected to the second semiconductor portion; an insulating film provided on the first portion of the first semiconductor portion; A semiconductor device comprising:

5. The semiconductor device according to claim 4 , wherein a carbon density in the first semiconductor portion below the first portion is higher than a carbon density in the first semiconductor portion below a connection portion between the second semiconductor portion and the upper electrode.

6. 6. The semiconductor device according to claim 4, wherein the insulating film has a thickness of 100 nm or more.

7. forming a first region doped with impurities and a second region not doped with impurities in an upper portion of the silicon carbide layer; a first heat treatment step for activating the first region; a second heat treatment step of thermally oxidizing the second region at a temperature lower than that of the first heat treatment step, after the first heat treatment step; A method for manufacturing a semiconductor device comprising the steps of:

8. The method for manufacturing a semiconductor device according to claim 7 , further comprising the step of covering an upper surface of the first region with a protective film before the second heat treatment step.

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