Semiconductor package

Abstract

To provide a semiconductor package with a novel structure.SOLUTION: A semiconductor package includes: a drift layer, disposed on a first principal surface of a Si substrate, which is made of a gallium-based semiconductor layer; a buffer layer interposed between the Si substrate and the drift layer; an anode electrode making contact with a first surface which is a surface, of the drift layer, opposite to the buffer layer; a trench which is formed by digging downward from a second principal surface of the Si substrate to a second surface, of the drift layer, opposite to the first surface, and which penetrates the Si substrate and the buffer layer so as to reach the second surface of the drift layer; a semiconductor element, formed on an inner surface of the trench, which includes a cathode electrode to make contact with the second surface of the drift layer; an anode terminal on which a semiconductor device is flip-chip mounted, and which is electrically connected to the anode electrode; and a cathode terminal which is electrically connected to the cathode electrode of the semiconductor device via a bonding wire.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to semiconductor packages. [Background technology]

[0002] Patent Document 1 discloses a Schottky barrier diode using gallium oxide (Ga2O3). The Schottky barrier diode described in Patent Document 1 includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide formed on the semiconductor substrate, an anode electrode in Schottky contact with the drift layer, and a cathode electrode in ohmic contact with the semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-179815 A

[0004] [overview] an anode electrode in contact with a first surface of the drift layer, the first surface being a surface of the drift layer opposite to the buffer layer; a trench formed by digging from the second main surface of the Si substrate toward a second surface of the drift layer opposite to the first surface of the drift layer, the trench penetrating the Si substrate and the buffer layer to reach the second surface of the drift layer; and a cathode electrode formed on an inner surface of the trench and in contact with the second surface of the drift layer; [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic plan view for explaining the configuration of a first semiconductor device mounted in a semiconductor package according to the present embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Diagram 3] FIG. 3 is a schematic plan view of a semiconductor package in which the first semiconductor device is mounted. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Diagram 5] FIG. 5 is a schematic plan view showing another example of a semiconductor package in which the first semiconductor device is mounted. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic plan view for explaining the configuration of a second semiconductor device mounted in the semiconductor package according to the present embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic plan view of a semiconductor package in which the second semiconductor device is mounted. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX in FIG. [Figure 11] FIG. 11 is a schematic plan view showing another example of a semiconductor package in which a second semiconductor device is mounted. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a schematic plan view for explaining the configuration of a third semiconductor device mounted in the semiconductor package according to the present embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view taken along line XIII-XIII in FIG. [Figure 15] FIG. 15 is a schematic plan view of a semiconductor package in which the third semiconductor device is mounted. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a schematic plan view showing another example of a semiconductor package in which a third semiconductor device is mounted. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a schematic plan view for explaining the configuration of a fourth semiconductor device mounted in a semiconductor package according to the present embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view taken along line XX-XX in FIG. [Figure 21] FIG. 21 is a schematic plan view of a semiconductor package in which the fourth semiconductor device is mounted. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Diagram 23] FIG. 23 is a schematic plan view showing another example of a semiconductor package in which a fourth semiconductor device is mounted. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG.

[0006] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0007] Fig. 1 is a schematic plan view for explaining the configuration of a first semiconductor device mounted in a semiconductor package according to the present embodiment, Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1.

[0008] The first semiconductor device 1 is a Schottky barrier diode. The first semiconductor device 1 is formed in the shape of a chip having a rectangular shape in a plan view, for example, as shown in FIG. 1. The length of each of the four sides of the first semiconductor device 1 in a plan view is, for example, about several mm. In this embodiment, the length of each of the four sides of the first semiconductor device 1 in a plan view is about 1 mm (1000 μm).

[0009] The first semiconductor device 1 includes a Si (silicon) substrate 2 having a first main surface (front surface) 2a and a second main surface (back surface) 2b. The Si substrate 2 has a quadrangular shape in a plan view. The first semiconductor device 1 also includes a buffer layer 3 formed on the first main surface 2a of the Si substrate 2. The buffer layer 3 has a first main surface (front surface) 3a and a second main surface (back surface) 3b. The buffer layer 3 has a quadrangular shape that matches the Si substrate 2 in a plan view.

[0010] Furthermore, the first semiconductor device 1 includes a drift layer 4 formed on the first main surface 3a of the buffer layer 3 and made of a gallium-based semiconductor layer. The drift layer 4 has a first main surface (front surface) 4a and a second main surface (back surface) 4b. The drift layer 4 has a quadrangular shape matching the buffer layer 3 in a plan view. The first main surface 4a of the drift layer 4 is an example of a "first surface of the drift layer" in the present disclosure, and the second main surface 4b of the drift layer 4 is an example of a "second surface of the drift layer" in the present disclosure.

[0011] The Si substrate 2 is doped with an n-type impurity. Phosphorus (P) or the like is used as the n-type impurity. The n-type impurity concentration in the Si substrate 2 is, for example, 1×10 16 cm -3 ~1×10 20 cm -3 The first main surface 2a and the second main surface 2b of the Si substrate 2 are (111) surfaces. The thickness of the Si substrate 2 is, for example, about 50 μm to 1000 μm. In this embodiment, the thickness of the Si substrate 2 is about 100 μm.

[0012] In this embodiment, the buffer layer 3 is made of aluminum nitride (AlN) having a crystal structure with in-plane 6-fold symmetry. The first main surface 3a and the second main surface 3b of the buffer layer 3 made of aluminum nitride are (0001) planes. That is, in this embodiment, a hexagonal material having a (0001) plane as the main surface is used as the buffer layer 3. The thickness of the buffer layer 3 is, for example, about 100 nm to 200 nm. In this embodiment, the thickness of the buffer layer 3 is about 160 nm.

[0013] The reason for providing the buffer layer 3 is as follows: If the drift layer 4 made of a gallium-based semiconductor layer is formed directly on the Si substrate 2, a high-quality drift layer 4 cannot be obtained due to a eutectic reaction between the silicon of the Si substrate 2 and the gallium of the drift layer 4. Therefore, in order to suppress the reaction (generation of mixed crystal) between the silicon of the Si substrate 2 and the gallium oxide of the drift layer 4, the buffer layer 3 is provided between the Si substrate 2 and the drift layer 4.

[0014] The drift layer 4 is made of a gallium-based semiconductor layer. The gallium-based semiconductor layer includes a Ga2O3-based semiconductor layer and a GaN-based semiconductor layer. The Ga2O3-based semiconductor layer is made of (In x1 Ga (1-x1) )2O3 layer, (Al x2 Ga (1-x2) )2O3 layer, etc. The GaN-based semiconductor layer is Sc x3 Ga (1-x3) N layer, Tl x4 Ga (1-x4) N layer, Al x5 Ga 1-x5 Includes N layer etc.

[0015] In this embodiment, the drift layer 4 is made of a lower first drift layer 21 formed on the first main surface 3a of the buffer layer 3, and an upper second drift layer 22 stacked on the first drift layer 21.

[0016] In this embodiment, the first drift layer 21 is made of a Ga2O3-based semiconductor layer doped with n-type impurities. The Ga2O3-based semiconductor layer may be, for example, (In x1 Ga 1-x )2O3(0≦x1<1) layer or (Al x2 Ga 1-x2 )2O3(0≦x2<1) layer is used.

[0017] In this embodiment, the first drift layer 21 is made of a gallium oxide (Ga2O3) layer doped with n-type impurities. In this embodiment, the n-type impurities are silicon (Si). The concentration of the n-type impurities is 1×10 18 cm -3~1×10 20 cm -3 In this embodiment, the concentration of n-type impurities is about 1×10 19 cm -3 The film thickness of the first drift layer 21 is about 200 nm. The n-type impurity may be tin (Sn).

[0018] The second drift layer 22 is made of a non-doped Ga2O3-based semiconductor layer. In this specification, a non-doped Ga2O3-based semiconductor layer is a layer having an impurity concentration of 1×10 16 / cm 3 The gallium oxide semiconductor layer is, for example, a Ga2O3-based semiconductor layer having a thickness of less than 100 nm. x1 Ga 1-x )2O3(0≦x1<1) layer or (Al x2 Ga 1-x2 )2O3 (0≦x2<1) is used. In this embodiment, the second drift layer 22 is made of a non-doped gallium oxide (Ga2O3) layer. The film thickness of the second drift layer 22 is about 6 μm.

[0019] The drift layer 4 may be composed of one gallium oxide (Ga2O3) layer doped with n-type impurities.

[0020] A single trench 5 is formed in the stack of the Si substrate 2 and the buffer layer 3 by digging from the center of the second main surface 2b of the Si substrate 2 toward the second main surface 4b of the drift layer 4. The trench 5 penetrates the Si substrate 2 and the buffer layer 3 to reach the second main surface 4b of the drift layer 4. The trench 5 is formed in order to reduce the resistivity from the first main surface 2a of the Si substrate 2 to the second main surface 2b of the Si substrate 2.

[0021] In this embodiment, the bottom surface of trench 5 is formed by the second main surface 4b of drift layer 4. In this embodiment, trench 5 has a circular cross-sectional shape. In this embodiment, trench 5 has a diameter of about 380 μm.

[0022] An ohmic metal 7 that is in ohmic contact with the second main surface 4b of the drift layer 4 is formed over the entire inner surface (bottom and side surfaces) of the trench 5 and the entire second main surface 2b of the Si substrate 2. The ohmic metal 7 is made of a metal (e.g., titanium (Ti), indium (In), etc.) that is in ohmic contact with an n-type Ga2O3-based semiconductor. In this embodiment, the ohmic metal 7 is made of titanium (Ti). The thickness of the ohmic metal 7 is, for example, about 0.3 nm to 300 nm.

[0023] In addition, an electrode metal 8 is formed on the surface of the ohmic metal 7. The electrode metal 8 is made of copper (Cu), gold (Au), or the like. In this embodiment, the electrode metal 8 is made of copper (Cu). The electrode metal 8 includes a first portion 8A covering the surface of the ohmic metal 7 inside the trench 5 and a second portion 8B covering the surface of the ohmic metal 7 outside the trench 5. The second portion 8B covers the entire second main surface 2b of the Si substrate 2.

[0024] The electrode metal 8 may be completely embedded in the trench 5. In that case, the back surface of the electrode metal 8 may be flat all over.

[0025] The cathode electrode 6 is composed of the ohmic metal 7 and the electrode metal 8. That is, in this embodiment, the cathode electrode 6 has a multilayer structure (a two-layer structure in this embodiment) of the ohmic metal 7 bonded to the Si substrate 2 and the electrode metal 8 laminated on the ohmic metal 7. In this embodiment, the electrode metal 8 is a portion of the cathode electrode 6 that is exposed on the outermost surface of the first semiconductor device 1 and to which a bonding wire or the like is bonded.

[0026] A region of the second main surface 4b of the drift layer 4 corresponding to the bottom surface of the trench 5 is covered with the ohmic metal 7 of the cathode electrode 6. In other words, a region of the second main surface 4b of the drift layer 4 corresponding to the bottom surface of the trench 5 is in contact with the ohmic metal 7 (cathode electrode 6). The other region of the second main surface 4b of the drift layer 4 (a region where the trench 5 is not formed in a plan view) is in contact with the first main surface 3a of the buffer layer 3.

[0027] A field insulating film 11 made of silicon nitride (SiN) is laminated on the first main surface 4a of the drift layer 4. The thickness of the field insulating film 11 is, for example, 100 nm or more, preferably about 700 nm to 4000 nm. The field insulating film 11 may be made of other insulators such as silicon oxide (SiO2).

[0028] An opening 12 that exposes the center of the drift layer 4 is formed in the field insulating film 11. In this embodiment, the opening 12 has a circular shape in a plan view. In this embodiment, the diameter of the opening 12 is about 400 μm. An anode electrode 14 is formed on the field insulating film 11.

[0029] The anode electrode 14 fills the opening 12 in the field insulating film 11 and projects outward in a flange shape from the opening 12 so as to cover the peripheral portion 13 of the opening 12 in the field insulating film 11 from above. That is, the peripheral portion of the opening 12 in the field insulating film 11 is sandwiched from above and below by the drift layer 4 and the anode electrode 14. In this embodiment, the anode electrode 14 has a quadrangular shape that matches the drift layer 4 in a plan view. In this embodiment, the anode electrode 14 functions as a terminal when the first semiconductor device 1 is flip-chip mounted, and therefore may be referred to as an external terminal.

[0030] In this embodiment, the anode electrode 14 has a multilayer structure (a two-layer structure in this embodiment) of a Schottky metal 15 joined to the drift layer 4 within the opening 12 of the field insulating film 11 and an electrode metal 16 laminated on this Schottky metal 15.

[0031] The Schottky metal 15 is made of a metal that forms a Schottky junction with a Ga2O3-based semiconductor. In this embodiment, the Schottky metal 15 is made of nickel (Ni). The Schottky metal 15 that is joined to the drift layer 4 forms a Schottky barrier (potential barrier) between itself and the Ga2O3-based semiconductor layer that constitutes the drift layer 4. In this embodiment, the thickness of the Schottky metal 15 is, for example, about 0.02 μm to 0.20 μm.

[0032] The electrode metal 16 is made of copper (Cu), gold (Au), or the like. In this embodiment, the electrode metal 16 is made of copper (Cu). In this embodiment, the thickness of the electrode metal 16 is larger than that of the Schottky metal 15, and is, for example, about 0.5 μm to 5.0 μm.

[0033] Fig. 3 is a schematic plan view of a semiconductor package in which the first semiconductor device 1 is mounted. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3.

[0034] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 3 and 4 may be used below. The +X direction is a predetermined direction along the main surfaces 2a and 2b of the Si substrate 2, and the +Y direction is a predetermined direction along the main surfaces 2a and 2b of the Si substrate 2 and is a direction perpendicular to the +X direction.

[0035] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0036] 3 and 4, the first semiconductor device 1 shown in FIGS. 1 and 2 is disposed upside down.

[0037] The semiconductor package 101 includes a rectangular parallelepiped resin package 102 , and an anode terminal 103 and a cathode terminal 104 sealed in the resin package 102 .

[0038] The two terminals 103 and 104 are made of metal plates formed into a predetermined shape. The anode terminal 103 includes an island 105 and a terminal portion .

[0039] In plan view, the island 105 has a quadrangular shape having two sides 103a and 103b parallel to the X direction and two sides 103c and 103d parallel to the Y direction. The terminal portion 106 extends in the -X direction from the center of the length of one side 103c of the island 105, and has a rectangular shape that is elongated in the X direction in plan view.

[0040] The cathode terminal 104 is disposed on the opposite side of the island 105 from the terminal portion 106. The cathode terminal 104 includes a wire connection portion 107 and a terminal portion 108.

[0041] The wire connection portion 107 is disposed at a distance in the +X direction from the side 103d of the island 105, and has a rectangular shape that is elongated in the Y direction in a plan view. The terminal portion 108 extends in the +X direction from the longitudinal center of the wire connection portion 107, and has a rectangular shape that is elongated in the X direction in a plan view.

[0042] The first semiconductor device 1 is flip-chip mounted on the center of the island 105 of the anode terminal 103. Specifically, the anode electrode 14 of the first semiconductor device 1 is bonded to the upper surface of the island 105 with the first semiconductor device 1 turned upside down.

[0043] The cathode electrode 6 of the first semiconductor device 1 is connected to the wire connection portion 107 of the cathode terminal 104 via a bonding wire 109 .

[0044] The first semiconductor device 1, the island 105, the base end of the terminal portion 106, the wire connection portion 107, the base end of the terminal portion 108, and the bonding wire 109 are sealed in the resin package 102. The tip end of the terminal portion 106 protrudes in the -X direction from the end face on the -X side of the resin package 102. The tip end of the terminal portion 108 protrudes in the +X direction from the end face on the +X side of the resin package 102.

[0045] In the first semiconductor device 1, heat is likely to be generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4. In this semiconductor package 101, the anode electrode 14 is joined to the island 105 of the anode terminal 103, so that the heat generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4 can be easily dissipated.

[0046] Fig. 5 is a schematic plan view showing another example of another semiconductor package in which the first semiconductor device 1 is mounted. Fig. 6 is a cross-sectional view taken along the line VI-VI in Fig. 5.

[0047] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 5 and 6 may be used below. The +X direction is a predetermined direction along the main surfaces 2a and 2b of the substrate 2, and the +Y direction is a predetermined direction along the main surfaces 2a and 2b of the substrate 2 and is a direction perpendicular to the +X direction.

[0048] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0049] 5 and 6, the first semiconductor device 1 shown in FIGS. 1 and 2 is disposed upside down.

[0050] The semiconductor package 201 includes a resin package 202 that is rectangular in plan view, and an anode terminal 203 and a cathode terminal 204 sealed in the resin package 202 .

[0051] The two terminals 203, 204 are made of metal plates formed into a predetermined shape. The anode terminal 203 includes an island 205 and a terminal portion 206. In a plan view, the island 205 is rectangular in shape having two sides 203a, 203b parallel to the X direction and two sides 203c, 203d parallel to the Y direction. The terminal portion 206 extends linearly in the -X direction from a position near the -Y end of one side 203c of the island 205, and has a rectangular shape that is elongated in the X direction in a plan view.

[0052] The cathode terminal 204 has a shape similar to that of the terminal portion 206 of the anode terminal 203 in a plan view, and is disposed at a distance in the +Y direction from the terminal portion 206 of the anode terminal 203. The +X side end of the cathode terminal 204 is disposed at a distance in the -X direction from the side 203c of the island 205.

[0053] The first semiconductor device 1 is flip-chip mounted on the center of the island 205 of the anode terminal 203. Specifically, the anode electrode 14 of the first semiconductor device 1 is bonded to the upper surface of the island 205 with the first semiconductor device 1 turned upside down.

[0054] The cathode electrode 6 of the first semiconductor device 1 is connected to the +X side portion of the cathode terminal 204 in the longitudinal direction via a bonding wire 209 .

[0055] The resin package 202 includes a rectangular parallelepiped main part 202a and a thin part 202b that is disposed on the +X side of the main part 202a and is thinner than the main part 202a. The bottom surface of the main part 202a and the bottom surface of the thin part 202b are flush with each other. A step 202c is formed between the top surface of the thin part 202b and the top surface of the main part 202a.

[0056] The main portion 202a encapsulates the first semiconductor device 1, a portion of the island 205 excluding its end in the +X direction, the base end of the terminal portion 206, the +X side portion in the longitudinal direction of the cathode terminal 204, and the bonding wire 209. The thin portion 102b encapsulates the end of the island 205 in the +X direction.

[0057] The tip of the terminal portion 206 protrudes in the -X direction from the -X side end face of the main portion 202a. The -X side portion of the cathode terminal 204 in the longitudinal direction protrudes in the -X direction from the -X side end face of the main portion 202a.

[0058] A through hole 210 is formed in the +X side end of the thin portion 102b and the island 205 near the center of the thin portion 102b in plan view, penetrating them in the up-down direction.

[0059] In the first semiconductor device 1, heat is likely to be generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4. In this semiconductor package 201, the anode electrode 14 is joined to the island 205 of the anode terminal 203, so that the heat generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4 can be easily dissipated.

[0060] Fig. 7 is a schematic plan view for explaining the configuration of a second semiconductor device 1A mounted in a semiconductor package according to this embodiment. Fig. 8 is a schematic cross-sectional view taken along line VIII-VIII in Fig. 7. In Figs. 7 and 8, parts corresponding to those in Figs. 1 and 2 are denoted by the same reference numerals as in Figs. 1 and 2.

[0061] For ease of explanation, the ratio of the diameter of the trench to the width of the second semiconductor device 1A is drawn larger than the actual ratio in Fig. 8. Therefore, the number of trenches is drawn smaller than the actual number in Fig. 8.

[0062] In the second semiconductor device 1A, the shape of the trench 5 is different from that of the first semiconductor device 1 shown in FIGS.

[0063] Specifically, a plurality of trenches 5 are formed. The plurality of trenches 5 are formed in a stack of the Si substrate 2 and the buffer layer 3 by being dug from the second main surface 2b of the Si substrate 2 toward the second main surface 4b of the drift layer 4. The plurality of trenches 5 penetrate the Si substrate 2 and the buffer layer 3 to reach the second main surface 4b of the drift layer 4. In this embodiment, the bottom surface of each trench 5 is formed by the second main surface 4b of the drift layer 4.

[0064] The multiple trenches 5 are arranged in a lattice pattern in plan view. In this embodiment, the multiple trenches 5 are arranged in a matrix pattern in plan view. The interval between two adjacent trenches 5 in the row or column direction is about 10 μm. The multiple trenches 5 may be arranged in a staggered pattern in plan view.

[0065] The cross-sectional shape of the trench 5 is arbitrary, and may be an ellipse or a polygon. The size of the cross-section of the trench 5 (the area of ​​the cross-section) and the interval between two adjacent trenches 5 can be set arbitrarily.

[0066] As with the first semiconductor device 1 of Figures 1 and 2, an ohmic metal 7 that is in ohmic contact with the second main surface 4b of the drift layer 4 is formed over the entire inner surface (bottom and side surfaces) of the trench 5 and the entire second main surface 2b of the Si substrate 2.

[0067] 1 and 2, an electrode metal 8 is formed on the surface of the ohmic metal 7 in the trench 5. The electrode metal 8 includes a first portion 8A covering the surface of the ohmic metal 7 in the trench 5, and a second portion 8B covering the surface of the ohmic metal 7 outside the trench 5. The second portion 8B covers the entire second main surface 2b of the Si substrate 2. In this way, a cathode electrode 6 made of the ohmic metal 7 and the electrode metal 8 is formed.

[0068] The electrode metal 8 may be completely embedded in the trench 5. In that case, the back surface of the electrode metal 8 may be flat all over.

[0069] A region of the second main surface 4b of the drift layer 4 corresponding to the bottom surface of the trench 5 is covered with the ohmic metal 7 of the cathode electrode 6. In other words, a region of the second main surface 4b of the drift layer 4 corresponding to the bottom surface of the trench 5 is in contact with the ohmic metal 7. The other region of the second main surface 4b of the drift layer 4 (a region outside the periphery of the trench 5 in a plan view) is in contact with the first main surface 3a of the buffer layer 3.

[0070] Fig. 9 is a schematic plan view of a semiconductor package in which the second semiconductor device 1A is mounted. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. In Figs. 9 and 10, parts corresponding to those in Figs. 3 and 4 described above are denoted by the same reference numerals as in Figs. 3 and 4.

[0071] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 9 and 10 may be used below. The +X direction is a predetermined direction along the main surfaces 2a and 2b of the substrate 2, and the +Y direction is a predetermined direction along the main surfaces 2a and 2b of the substrate 2 and is a direction perpendicular to the +X direction.

[0072] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0073] 9 and 10, the second semiconductor device 1A shown in FIGS. 7 and 8 is disposed upside down.

[0074] The semiconductor package 101A includes a resin package 102 in the shape of a flat rectangular parallelepiped, and an anode terminal 103 and a cathode terminal 104 sealed in the resin package 102.

[0075] The two terminals 103 and 104 are made of metal plates formed into a predetermined shape. The anode terminal 103 includes an island 105 and a terminal portion .

[0076] In plan view, the island 105 has a quadrangular shape having two sides 103a and 103b parallel to the X direction and two sides 103c and 103d parallel to the Y direction. The terminal portion 106 extends in the -X direction from the center of the length of one side 103c of the island 105, and has a rectangular shape that is elongated in the X direction in plan view.

[0077] The cathode terminal 104 is disposed on the opposite side of the island 105 from the terminal portion 106. The cathode terminal 104 includes a wire connection portion 107 and a terminal portion 108.

[0078] The wire connection portion 107 is disposed at a distance in the +X direction from the side 103d of the island 105, and has a rectangular shape that is elongated in the Y direction in a plan view. The terminal portion 108 extends in the +X direction from the longitudinal center of the wire connection portion 107, and has a rectangular shape that is elongated in the X direction in a plan view.

[0079] The second semiconductor device 1A is flip-chip mounted on the center of the island 105 of the anode terminal 103. Specifically, the anode electrode 14 of the second semiconductor device 1A is bonded to the upper surface of the island 105 with the second semiconductor device 1A turned upside down.

[0080] The cathode electrode 6 of the second semiconductor device 1 A is connected to the wire connection portion 107 of the cathode terminal 104 via a bonding wire 109 .

[0081] Second semiconductor device 1A, island 105, base end portion of terminal portion 106, wire connection portion 107, base end portion of terminal portion 108, and bonding wire 109 are sealed in resin package 102. A tip portion of terminal portion 106 protrudes in the -X direction from an end face on the -X side of resin package 102. A tip portion of terminal portion 108 protrudes in the +X direction from an end face on the +X side of resin package 102.

[0082] In the second semiconductor device 1A, heat is likely to be generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4. In this semiconductor package 101A, the anode electrode 14 is joined to the island 105 of the anode terminal 103, so that the heat generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4 can be easily dissipated.

[0083] Fig. 11 is a schematic plan view showing another example of a semiconductor package in which the second semiconductor device 1A is mounted. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 11. In Figs. 11 and 12, parts corresponding to those in Figs. 5 and 6 described above are denoted by the same reference numerals as in Figs. 5 and 6.

[0084] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 11 and 12 may be used below. The +X direction is a predetermined direction along the main surfaces 2a and 2b of the substrate 2, and the +Y direction is a predetermined direction along the main surfaces 2a and 2b of the substrate 2 and is a direction perpendicular to the +X direction.

[0085] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0086] 11 and 12, the second semiconductor device 1A shown in FIGS. 7 and 8 is disposed upside down.

[0087] The semiconductor package 201A includes a resin package 202 that is rectangular in plan view, and an anode terminal 203 and a cathode terminal 204 sealed in the resin package 202.

[0088] The two terminals 203, 204 are made of metal plates formed into a predetermined shape. The anode terminal 203 includes an island 205 and a terminal portion 206. In a plan view, the island 205 is rectangular in shape having two sides 203a, 203b parallel to the X direction and two sides 203c, 203d parallel to the Y direction. The terminal portion 206 extends linearly in the -X direction from a position near the -Y end of one side 203c of the island 205, and has a rectangular shape that is elongated in the X direction in a plan view.

[0089] The cathode terminal 204 has a shape similar to that of the terminal portion 206 of the anode terminal 203 in a plan view, and is disposed at a distance in the +Y direction from the terminal portion 206 of the anode terminal 203. The +X side end of the cathode terminal 204 is disposed at a distance in the -X direction from the side 203c of the island 205.

[0090] The second semiconductor device 1A is flip-chip mounted on the center of the island 205 of the anode terminal 203. Specifically, the anode electrode 14 of the second semiconductor device 1A is bonded to the upper surface of the island 205 with the second semiconductor device 1A turned upside down.

[0091] The cathode electrode 6 of the second semiconductor device 1A is connected to the +X side portion of the cathode terminal 204 in the longitudinal direction via a bonding wire 209.

[0092] Resin package 202A includes rectangular parallelepiped main part 202a and thin part 202b that is disposed on the +X side of main part 202a and is thinner than main part 202a. The bottom surface of main part 202a and the bottom surface of thin part 202b are flush with each other. A step 202c is formed between the top surface of thin part 202b and the top surface of main part 202a.

[0093] The main portion 202a encapsulates the second semiconductor device 1A, a portion of the island 205 except for its end in the +X direction, the base end of the terminal portion 206, the +X side portion in the longitudinal direction of the cathode terminal 204, and the bonding wire 209. The thin portion 102b encapsulates the end of the island 205 in the +X direction.

[0094] The tip of the terminal portion 206 protrudes in the -X direction from the -X side end face of the main portion 202a. The -X side portion of the cathode terminal 204 in the longitudinal direction protrudes in the -X direction from the -X side end face of the main portion 202a.

[0095] A through hole 210 is formed in the +X side end of the thin portion 102b and the island 205 near the center of the thin portion 102b in plan view, penetrating them in the up-down direction.

[0096] In the second semiconductor device 1A, heat is likely to be generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4. In this semiconductor package 201A, the anode electrode 14 is joined to the island 205 of the anode terminal 203, so that the heat generated at the boundary between the anode electrode 14 and the first main surface 4a of the drift layer 4 can be easily dissipated.

[0097] Fig. 13 is a schematic plan view for explaining the configuration of a third semiconductor device mounted in the semiconductor package according to the present embodiment, and Fig. 14 is a schematic cross-sectional view taken along line XIV-XIV in Fig. 13.

[0098] The third semiconductor device 1B is a PIN diode. The third semiconductor device 1B is formed in the shape of a chip having a rectangular shape in a plan view, for example, as shown in FIG. 13. The length of each of the four sides of the third semiconductor device 1B in a plan view is, for example, about several mm. In this embodiment, the length of each of the four sides of the third semiconductor device 1B in a plan view is about 1 mm (1000 μm).

[0099] The third semiconductor device 1B includes a Si (silicon) substrate 32 having a first main surface (front surface) 32a and a second main surface (back surface) 32b. The Si substrate 32 has a quadrangular shape in a plan view. The third semiconductor device 1B also includes a buffer layer 33 formed on the first main surface 32a of the Si substrate 32. The buffer layer 33 has a first main surface (front surface) 33a and a second main surface (back surface) 33b. The buffer layer 33 has a quadrangular shape that matches the Si substrate 32 in a plan view.

[0100] Furthermore, the third semiconductor device 1B includes a drift layer 34 formed on a first main surface 33a of the buffer layer 33 and made of a gallium-based semiconductor layer. The drift layer 34 has a first main surface (front surface) 34a and a second main surface (back surface) 34b. The drift layer 34 has a quadrangular shape that matches the buffer layer 33 in a plan view. The first main surface 34a of the drift layer 34 is an example of a "first surface of the drift layer" in the present disclosure, and the second main surface 34b of the drift layer 34 is an example of a "second surface of the drift layer" in the present disclosure.

[0101] The Si substrate 32 is doped with an n-type impurity. Phosphorus (P) or the like is used as the n-type impurity. The n-type impurity concentration in the Si substrate 32 is, for example, 1×10 16 cm -3 ~1×10 20 cm -3 The first main surface 32a and the second main surface 32b of the Si substrate 32 are (111) surfaces. The thickness of the Si substrate 32 is, for example, about 50 μm to 1000 μm. In this embodiment, the thickness of the Si substrate 32 is about 100 μm.

[0102] In this embodiment, the buffer layer 33 is made of aluminum nitride (AlN) having a crystal structure with in-plane 6-fold symmetry. The first main surface 33a and the second main surface 33b of the buffer layer 33 made of aluminum nitride are (0001) planes. That is, in this embodiment, a hexagonal material having a (0001) plane as the main surface is used as the buffer layer 33. The thickness of the buffer layer 33 is, for example, about 100 nm to 200 nm. In this embodiment, the thickness of the buffer layer 33 is about 160 nm.

[0103] The reason for providing the buffer layer 33 is as follows: If the drift layer 34 made of a gallium-based semiconductor layer is formed directly on the Si substrate 32, a high-quality drift layer 34 cannot be obtained due to a eutectic reaction between the silicon of the Si substrate 32 and the gallium of the drift layer 34. Therefore, in order to suppress the reaction (generation of mixed crystals) between the silicon of the Si substrate 32 and the gallium oxide of the drift layer 34, the buffer layer 33 is provided between the Si substrate 32 and the drift layer 34.

[0104] The drift layer 34 is made of a gallium-based semiconductor layer. The gallium-based semiconductor layer includes a Ga2O3-based semiconductor layer and a GaN-based semiconductor layer. The Ga2O3-based semiconductor layer is made of (In x1 Ga (1-x1) )2O3 layer, (Al x2 Ga (1-x2) )2O3 layer, etc. The GaN-based semiconductor layer is Sc x3 Ga (1-x3) N layer, Tl x4 Ga (1-x4) N layer, Al x5 Ga (1-x5) Includes N layer etc.

[0105] In this embodiment, the drift layer 34 comprises a lower first drift layer 51 formed on the first main surface 33a of the buffer layer 33, a middle second drift layer 52 stacked on the first drift layer 51, and an upper third drift layer 53 stacked on the second drift layer 52.

[0106] In this embodiment, the first drift layer 51 is made of a GaN-based semiconductor layer doped with n-type impurities. x3 Ga (1-x3) N(0≦x3<1) layer, Tl x4 Ga (1-x4) N(0≦x4<1) layer or Al x5 Ga (1-x5) N (0≦x5<1) layers are used.

[0107] In this embodiment, the first drift layer 51 is made of a GaN layer doped with n-type impurities. The first drift layer 51 may be an AlGaN layer doped with n-type impurities. In this embodiment, the n-type impurities are silicon (Si). The concentration of the n-type impurities is 1×10 17 cm -3 ~1×10 20 cm -3 The film thickness of first drift layer 51 is about 200 nm. The n-type impurity may be tin (Sn).

[0108] The second drift layer 42 is made of an undoped GaN-based semiconductor layer. In this specification, an undoped GaN-based semiconductor layer is defined as a layer having an impurity concentration of 1×10 16 / cm 3 The GaN-based semiconductor layer is, for example, a Sc x3 Ga (1-x3) N(0≦x3<1) layer, Tl x4 Ga (1-x4) N(0≦x4<1) or Al x5 Ga (1-x5) N (0≦x5<1) is used. In this embodiment, the second drift layer 52 is made of an undoped GaN layer. The second drift layer 52 may be an undoped AlGaN layer. The film thickness of the second drift layer 52 is about 6 μm.

[0109] In this embodiment, the third drift layer 53 is made of a GaN-based semiconductor layer doped with a p-type impurity. x3 Ga (1-x3) N(0≦x3<1) layer, Tl x4 Ga (1-x4) N(0≦x4<1) or Al x5 Ga (1-x5) N(0≦x5<1) is used.

[0110] In this embodiment, the third drift layer 53 is made of a GaN layer doped with a p-type impurity. The third drift layer 53 may be an AlGaN layer doped with a p-type impurity. In this embodiment, the p-type impurity is manganese (Mg). The concentration of the p-type impurity is 1×10 17 cm -3 ~1×10 20 cm -3 The film thickness of third drift layer 53 is about 200 nm.

[0111] A single trench 35 is formed in the stack of the Si substrate 32 and the buffer layer 33 by digging from the center of the second main surface 32b of the Si substrate 32 toward the second main surface 34b of the drift layer 34. The trench 35 penetrates the Si substrate 32 and the buffer layer 33 to reach the second main surface 34b of the drift layer 34. The trench 35 is formed to reduce the resistivity from the first main surface 32a of the Si substrate 32 to the second main surface 32b of the Si substrate 32.

[0112] In this embodiment, the bottom surface of the trench 35 is formed by the second main surface 34b of the drift layer 34. In this embodiment, the cross-sectional shape of the trench 35 is circular. In this embodiment, the diameter of the trench 35 is about 380 μm.

[0113] An inner metal 37 in contact with the second main surface 34b of the drift layer 34 is formed on the entire inner surface (bottom surface and side surface) of the trench 35 and the entire second main surface 32b of the Si substrate 32. In this embodiment, the inner metal 37 is made of nickel (Ni). The thickness of the inner metal 37 is, for example, about 0.3 nm to 300 nm.

[0114] Further, an outer metal 38 is formed on the surface of the inner metal 37. The outer metal 38 is made of copper (Cu), gold (Au), or the like. In this embodiment, the outer metal 38 is made of copper (Cu). The outer metal 38 includes a first portion 38A that covers the surface of the inner metal 37 inside the trench 35, and a second portion 38B that covers the surface of the inner metal 37 outside the trench 35. The second portion 38B covers the entire second main surface 32b of the Si substrate 32.

[0115] The outer metal 38 may be completely embedded in the trench 35. In that case, the rear surface (lower surface) of the outer metal 38 may be flat all over.

[0116] The inner metal 37 and the outer metal 38 form the cathode electrode 36. That is, in this embodiment, the cathode electrode 36 has a multilayer structure (a two-layer structure in this embodiment) of the inner metal 37 bonded to the Si substrate 32 and the outer metal 38 laminated on the inner metal 37. In this embodiment, the outer metal 38 is a portion of the cathode electrode 36 that is exposed on the outermost surface of the third semiconductor device 1B and to which a bonding wire or the like is bonded.

[0117] A region of the second main surface 34b of the drift layer 34 corresponding to the bottom surface of the trench 35 is covered with the inner metal 37 of the cathode electrode 36. In other words, a region of the second main surface 34b of the drift layer 34 corresponding to the bottom surface of the trench 35 is in contact with the inner metal 37 (cathode electrode 36). The other region of the second main surface 34b of the drift layer 34 (a region where the trench 35 is not formed in a plan view) is in contact with the first main surface 33a of the buffer layer 33.

[0118] An anode electrode 39 is formed on the first main surface 34a of the drift layer 34.

[0119] In this embodiment, the anode electrode 39 has a quadrangular shape in a plan view that matches the drift layer 34. In this embodiment, the anode electrode 39 functions as a terminal when the third semiconductor device 1B is flip-chip mounted, and therefore may be referred to as an external terminal.

[0120] In this embodiment, the anode electrode 39 has a multi-layer structure (two-layer structure in this embodiment) of an inner metal 40 joined to the drift layer 34 and an outer metal 41 laminated on the inner metal 40.

[0121] In this embodiment, the inner metal 40 is made of titanium (Ti). In this embodiment, the thickness of the inner metal 40 is, for example, about 0.02 μm to 0.20 μm.

[0122] The outer metal 41 is made of copper (Cu), gold (Au), or the like. In this embodiment, the outer metal 41 is made of copper (Cu). In this embodiment, the thickness of the outer metal 41 is greater than that of the inner metal 40, and is, for example, about 0.5 μm to 5.0 μm.

[0123] Fig. 15 is a schematic plan view of a semiconductor package in which a third semiconductor device 1B is mounted. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 15. In Figs. 15 and 16, parts corresponding to those in Figs. 3 and 4 described above are denoted by the same reference numerals as in Figs. 3 and 4.

[0124] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 15 and 16 may be used below. The +X direction is a predetermined direction along the main surfaces 32a and 32b of the Si substrate 32, and the +Y direction is a predetermined direction along the main surfaces 32a and 32b of the Si substrate 32 and is a direction perpendicular to the +X direction.

[0125] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0126] 15 and 16, the third semiconductor device 1B shown in FIGS. 13 and 14 is arranged upside down.

[0127] The semiconductor package 101B includes a rectangular parallelepiped resin package 102, and an anode terminal 103 and a cathode terminal 104 sealed in the resin package 102.

[0128] The two terminals 103 and 104 are made of metal plates formed into a predetermined shape. The anode terminal 103 includes an island 105 and a terminal portion .

[0129] In plan view, the island 105 has a quadrangular shape having two sides 103a and 103b parallel to the X direction and two sides 103c and 103d parallel to the Y direction. The terminal portion 106 extends in the -X direction from the center of the length of one side 103c of the island 105, and has a rectangular shape that is elongated in the X direction in plan view.

[0130] The cathode terminal 104 is disposed on the opposite side of the island 105 from the terminal portion 106. The cathode terminal 104 includes a wire connection portion 107 and a terminal portion 108.

[0131] The wire connection portion 107 is disposed at a distance in the +X direction from the side 103d of the island 105, and has a rectangular shape that is elongated in the Y direction in a plan view. The terminal portion 108 extends in the +X direction from the longitudinal center of the wire connection portion 107, and has a rectangular shape that is elongated in the X direction in a plan view.

[0132] The third semiconductor device 1B is flip-chip mounted on the center of the island 105 of the anode terminal 103. Specifically, the anode electrode 39 of the third semiconductor device 1B is bonded to the upper surface of the island 105 with the third semiconductor device 1B turned upside down.

[0133] The cathode electrode 36 of the third semiconductor device 1 B is connected to the wire connection portion 107 of the cathode terminal 104 via a bonding wire 109 .

[0134] The third semiconductor device 1B, the island 105, the base end of the terminal portion 106, the wire connection portion 107, the base end of the terminal portion 108, and the bonding wire 109 are sealed in the resin package 102. The tip end of the terminal portion 106 protrudes in the -X direction from the end face on the -X side of the resin package 102. The tip end of the terminal portion 108 protrudes in the +X direction from the end face on the +X side of the resin package 102.

[0135] In the third semiconductor device 1B, heat is likely to be generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34. In this semiconductor package 101B, the anode electrode 39 is joined to the island 105 of the anode terminal 103, so that heat generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34 can be easily dissipated.

[0136] Fig. 17 is a schematic plan view showing another example of another semiconductor package in which the third semiconductor device 1B is mounted. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig. 17. In Figs. 17 and 18, parts corresponding to those in Figs. 5 and 6 described above are denoted by the same reference numerals as in Figs. 5 and 6.

[0137] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 17 and 18 may be used below. The +X direction is a predetermined direction along the main surfaces 32a and 32b of the substrate 32, and the +Y direction is a predetermined direction along the main surfaces 32a and 32b of the substrate 32 and is a direction perpendicular to the +X direction.

[0138] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0139] 17 and 18, the third semiconductor device 1B shown in FIGS. 13 and 14 is arranged upside down.

[0140] The semiconductor package 201B includes a resin package 202 that is rectangular in plan view, and an anode terminal 203 and a cathode terminal 204 sealed in the resin package 202.

[0141] The two terminals 203, 204 are made of metal plates formed into a predetermined shape. The anode terminal 203 includes an island 205 and a terminal portion 206. In a plan view, the island 205 is rectangular in shape having two sides 203a, 203b parallel to the X direction and two sides 203c, 203d parallel to the Y direction. The terminal portion 206 extends linearly in the -X direction from a position near the -Y end of one side 203c of the island 205, and has a rectangular shape that is elongated in the X direction in a plan view.

[0142] The cathode terminal 204 has a shape similar to that of the terminal portion 206 of the anode terminal 203 in a plan view, and is disposed at a distance in the +Y direction from the terminal portion 206 of the anode terminal 203. The +X side end of the cathode terminal 204 is disposed at a distance in the -X direction from the side 203c of the island 205.

[0143] The third semiconductor device 1B is flip-chip mounted on the center of the island 205 of the anode terminal 203. Specifically, the anode electrode 39 of the third semiconductor device 1B is bonded to the upper surface of the island 205 with the third semiconductor device 1B turned upside down.

[0144] The cathode electrode 36 of the third semiconductor device 1B is connected via a bonding wire 209 to the +X side portion in the longitudinal direction of the cathode terminal 204 .

[0145] The resin package 202 includes a rectangular parallelepiped main part 202a and a thin part 202b that is disposed on the +X side of the main part 202a and is thinner than the main part 202a. The bottom surface of the main part 202a and the bottom surface of the thin part 202b are flush with each other. A step 202c is formed between the top surface of the thin part 202b and the top surface of the main part 202a.

[0146] The main portion 202a encapsulates the third semiconductor device 1B, a portion of the island 205 excluding its end in the +X direction, the base end of the terminal portion 206, the +X side portion in the longitudinal direction of the cathode terminal 204, and the bonding wire 209. The thin portion 102b encapsulates the end of the island 205 in the +X direction.

[0147] The tip of the terminal portion 206 protrudes in the -X direction from the -X side end face of the main portion 202a. The -X side portion of the cathode terminal 204 in the longitudinal direction protrudes in the -X direction from the -X side end face of the main portion 202a.

[0148] A through hole 210 is formed in the +X side end of the thin portion 102b and the island 205 near the center of the thin portion 102b in plan view, penetrating them in the up-down direction.

[0149] In the third semiconductor device 1B, heat is likely to be generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34. In this semiconductor package 201B, the anode electrode 39 is joined to the island 205 of the anode terminal 203, so that heat generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34 can be easily dissipated.

[0150] Fig. 19 is a schematic plan view for explaining the configuration of a fourth semiconductor device mounted in a semiconductor package according to this embodiment. Fig. 20 is a schematic cross-sectional view taken along line XX-XX in Fig. 19. In Fig. 19 and Fig. 20, parts corresponding to those in Fig. 13 and Fig. 14 are denoted by the same reference numerals as in Fig. 13 and Fig. 14.

[0151] 20, for convenience of explanation, the ratio of the trench diameter to the width of the fourth semiconductor device 1C is drawn larger than the actual ratio, and therefore the number of trenches is drawn smaller than the actual number in FIG.

[0152] In the fourth semiconductor device 1C, the shape of the trench 35 is different from that of the third semiconductor device 1B shown in FIGS.

[0153] Specifically, a plurality of trenches 35 are formed. The plurality of trenches 35 are formed in a stack of the Si substrate 32 and the buffer layer 33 by being dug from the second main surface 32b of the Si substrate 32 toward the second main surface 34b of the drift layer 34. The plurality of trenches 35 penetrate the Si substrate 32 and the buffer layer 33 to reach the second main surface 34b of the drift layer 34. In this modification, the bottom surface of each trench 35 is formed by the second main surface 34b of the drift layer 34.

[0154] The multiple trenches 35 are arranged in a lattice pattern in plan view. In this modification, the multiple trenches 35 are arranged in a matrix pattern in plan view. The interval between two adjacent trenches 35 in the row or column direction is about 10 μm. The multiple trenches 35 may be arranged in a staggered pattern in plan view.

[0155] The cross-sectional shape of the trench 35 is arbitrary, and may be an ellipse or a polygon. The size of the cross-section of the trench 35 (the area of ​​the cross-section) and the interval between two adjacent trenches 35 can be set arbitrarily.

[0156] As with the third semiconductor device 1B of Figures 13 and 14, an inner metal 37 in contact with the second main surface 34b of the drift layer 34 is formed over the entire inner surface (bottom and side surfaces) of the trench 35 and the entire second main surface 32b of the Si substrate 32.

[0157] 13 and 14, an outer metal 38 is formed on the surface of the inner metal 37 in the trench 35. The outer metal 38 includes a first portion 38A covering the surface of the inner metal 37 in the trench 35 and a second portion 38B covering the surface of the inner metal 37 outside the trench 35. The second portion 38B covers the entire second main surface 32b of the Si substrate 32. In this way, a cathode electrode 36 made of the inner metal 37 and the outer metal 38 is formed.

[0158] The outer metal 38 may be completely embedded in the trench 35. In that case, the back surface of the outer metal 38 may be flat all over.

[0159] A region of the second main surface 34b of the drift layer 34 corresponding to the bottom surface of the trench 35 is covered with the inner metal 37 of the cathode electrode 36. In other words, a region of the second main surface 34b of the drift layer 34 corresponding to the bottom surface of the trench 35 is in contact with the inner metal 37. The other region of the second main surface 34b of the drift layer 34 (a region outside the periphery of the trench 35 in a plan view) is in contact with the first main surface 33a of the buffer layer 33.

[0160] Fig. 21 is a schematic plan view of a semiconductor package in which a fourth semiconductor device 1C is mounted. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 21. In Figs. 21 and 22, parts corresponding to those in Figs. 3 and 4 described above are denoted by the same reference numerals as in Figs. 3 and 4.

[0161] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 21 and 22 may be used below. The +X direction is a predetermined direction along the main surfaces 32a and 32b of the substrate 32, and the +Y direction is a predetermined direction along the main surfaces 32a and 32b of the substrate 32 and is a direction perpendicular to the +X direction.

[0162] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0163] 21 and 22, the fourth semiconductor device 1C shown in FIGS. 19 and 20 is arranged upside down.

[0164] The semiconductor package 101C includes a resin package 102 in the shape of a flat rectangular parallelepiped, and an anode terminal 103 and a cathode terminal 104 sealed in the resin package 102.

[0165] The two terminals 103 and 104 are made of metal plates formed into a predetermined shape. The anode terminal 103 includes an island 105 and a terminal portion .

[0166] In plan view, the island 105 has a quadrangular shape having two sides 103a and 103b parallel to the X direction and two sides 103c and 103d parallel to the Y direction. The terminal portion 106 extends in the -X direction from the center of the length of one side 103c of the island 105, and has a rectangular shape that is elongated in the X direction in plan view.

[0167] The cathode terminal 104 is disposed on the opposite side of the island 105 from the terminal portion 106. The cathode terminal 104 includes a wire connection portion 107 and a terminal portion 108.

[0168] The wire connection portion 107 is disposed at a distance in the +X direction from the side 103d of the island 105, and has a rectangular shape that is elongated in the Y direction in a plan view. The terminal portion 108 extends in the +X direction from the longitudinal center of the wire connection portion 107, and has a rectangular shape that is elongated in the X direction in a plan view.

[0169] The fourth semiconductor device 1C is flip-chip mounted on the center of the island 105 of the anode terminal 103. Specifically, the anode electrode 39 of the fourth semiconductor device 1C is bonded to the upper surface of the island 105 with the fourth semiconductor device 1C turned upside down.

[0170] The cathode electrode 36 of the fourth semiconductor device 1 C is connected to the wire connection portion 107 of the cathode terminal 104 via a bonding wire 109 .

[0171] The fourth semiconductor device 1C, the island 105, the base end of the terminal portion 106, the wire connection portion 107, the base end of the terminal portion 108, and the bonding wire 109 are sealed in the resin package 102. The tip end of the terminal portion 106 protrudes in the -X direction from the end face on the -X side of the resin package 102. The tip end of the terminal portion 108 protrudes in the +X direction from the end face on the +X side of the resin package 102.

[0172] In the fourth semiconductor device 1C, heat is likely to be generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34. In this semiconductor package 101C, the anode electrode 39 is joined to the island 105 of the anode terminal 103, so that heat generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34 can be easily dissipated.

[0173] Fig. 23 is a schematic plan view showing another example of a semiconductor package in which a fourth semiconductor device 1C is mounted. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 23. In Figs. 23 and 24, parts corresponding to those in Figs. 5 and 6 described above are denoted by the same reference numerals as in Figs. 5 and 6.

[0174] For ease of explanation, the +X direction, -X direction, +Y direction, and -Y direction shown in Figures 23 and 24 may be used below. The +X direction is a predetermined direction along the main surfaces 32a and 32b of the substrate 32, and the +Y direction is a predetermined direction along the main surfaces 32a and 32b of the substrate 32 and is a direction perpendicular to the +X direction.

[0175] The -X direction is the direction opposite to the +X direction. The -Y direction is the direction opposite to the +Y direction. The +X direction and the -X direction are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are collectively referred to simply as the "Y direction."

[0176] 23 and 24, the fourth semiconductor device 1C shown in FIGS. 19 and 20 is arranged upside down.

[0177] The semiconductor package 201C includes a resin package 202 that is rectangular in plan view, and an anode terminal 203 and a cathode terminal 204 sealed in the resin package 202.

[0178] The two terminals 203, 204 are made of metal plates formed into a predetermined shape. The anode terminal 203 includes an island 205 and a terminal portion 206. In a plan view, the island 205 is rectangular in shape having two sides 203a, 203b parallel to the X direction and two sides 203c, 203d parallel to the Y direction. The terminal portion 206 extends linearly in the -X direction from a position near the -Y end of one side 203c of the island 205, and has a rectangular shape that is elongated in the X direction in a plan view.

[0179] The cathode terminal 204 has a shape similar to that of the terminal portion 206 of the anode terminal 203 in a plan view, and is disposed at a distance in the +Y direction from the terminal portion 206 of the anode terminal 203. The +X side end of the cathode terminal 204 is disposed at a distance in the -X direction from the side 203c of the island 205.

[0180] The fourth semiconductor device 1C is flip-chip mounted on the center of the island 205 of the anode terminal 203. Specifically, the anode electrode 39 of the fourth semiconductor device 1C is bonded to the upper surface of the island 205 with the fourth semiconductor device 1C turned upside down.

[0181] The cathode electrode 36 of the fourth semiconductor device 1C is connected via a bonding wire 209 to the +X side portion in the longitudinal direction of the cathode terminal 204.

[0182] The resin package 202 includes a rectangular parallelepiped main part 202a and a thin part 202b that is disposed on the +X side of the main part 202a and is thinner than the main part 202a. The bottom surface of the main part 202a and the bottom surface of the thin part 202b are flush with each other. A step 202c is formed between the top surface of the thin part 202b and the top surface of the main part 202a.

[0183] The main portion 202a encapsulates the fourth semiconductor device 1C, a portion of the island 205 excluding its end in the +X direction, the base end of the terminal portion 206, the +X side portion in the longitudinal direction of the cathode terminal 204, and the bonding wire 209. The thin portion 102b encapsulates the end of the island 205 in the +X direction.

[0184] The tip of the terminal portion 206 protrudes in the -X direction from the -X side end face of the main portion 202a. The -X side portion of the cathode terminal 204 in the longitudinal direction protrudes in the -X direction from the -X side end face of the main portion 202a.

[0185] A through hole 210 is formed in the thin portion 202b and the +X side end of the island 205 near the center of the thin portion 202b in plan view, penetrating them in the up-down direction.

[0186] In the fourth semiconductor device 1C, heat is likely to be generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34. In this semiconductor package 201B, the anode electrode 39 is joined to the island 205 of the anode terminal 203, so that heat generated at the boundary between the anode electrode 39 and the first main surface 34a of the drift layer 34 can be easily dissipated.

[0187] Although the embodiment of the present disclosure has been described above, the present disclosure can be embodied in other forms. For example, in the first semiconductor device 1 and the third semiconductor device 1B described above, the trenches 5 and 35 are formed in a circular shape in a plan view, but they may be formed in a shape other than a circle, such as an ellipse or a polygon. The size of the trenches 5 and 35 can also be set to any size.

[0188] In the second semiconductor device 1A and the fourth semiconductor device 1C described above, the trenches 5, 35 are arranged in a lattice pattern such as a matrix or a staggered pattern in a plan view, but they do not have to be arranged in a lattice pattern. The cross-sectional shape and size of the trenches 5, 35 can be set arbitrarily.

[0189] In the second semiconductor device 1A and the fourth semiconductor device 1C described above, the trenches 5, 35 are formed in almost the entire area of ​​the second semiconductor device 1A and the fourth semiconductor device 1C in a plan view, but they can be set arbitrarily in the area in which the trenches 5, 35 are formed. For example, the trenches 5, 35 may be formed only in the central area or only in the peripheral area of ​​the semiconductor device 1A, 1C in a plan view.

[0190] Also, for example, in the first to fourth semiconductor devices 1 to 1C described above, the anode electrodes 14, 39 have a two-layer structure, but may have a one-layer structure or a three-layer structure or more. The Schottky metal 15 (inner metal 40) and the electrode metal 16 (outer metal 41) may be made of an appropriate material. The thicknesses of the Schottky metal 15 (inner metal 40) and the electrode metal 16 (outer metal 41) are merely examples, and may be appropriately selected to use appropriate values. The planar shape of the anode electrodes 14, 39 is a rectangle, but may be a shape other than a rectangle, such as a circle, an ellipse, or a polygon.

[0191] In the first to fourth semiconductor devices 1 to 1C described above, the cathode electrodes 6, 36 have a two-layer structure, but may have a one-layer structure or a three-layer or more structure. The ohmic metal 7 (inner metal 37) and the electrode metal 8 (outer metal 38) may be made of an appropriate material. The thicknesses of the ohmic metal 7 (inner metal 37) and the electrode metal 8 (outer metal 38) are merely examples, and may be appropriately selected to use appropriate values.

[0192] Furthermore, in the above-described first to fourth semiconductor devices 1 to 1C, the buffer layers 3, 33 are AlN layers, but the buffer layers 3, 33 may be AlAs layers, cubic AlN layers, C (diamond) layers, or the like.

[0193] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiment, but are not intended to limit the scope of each clause to the embodiment.

[0194] [A1] A Si substrate (2, 32) having a first main surface (2a, 32a) and a second main surface (2b, 32b); a drift layer (4, 34) formed of a gallium-based semiconductor layer and disposed on a first main surface (2a, 32a) of the Si substrate (2, 32); a buffer layer (3, 34) interposed between the Si substrate (2, 32) and the drift layer (4, 34); an anode electrode (14, 39) in contact with a first surface (4a, 34a) of the drift layer (4, 34), the first surface being a surface opposite to the buffer layer (3, 33); a trench (5, 35) formed by digging down from the second main surface (2b, 32b) of the Si substrate (2, 32) toward a second surface (4b, 34b) that is the surface opposite to the first surface (4a, 34a) of the drift layer (4, 34), penetrating the Si substrate (2, 32) and the buffer layer (4, 34) to reach the second surface (4b, 34b) of the drift layer (4, 34); a semiconductor element (1-1C) including a cathode electrode (6, 36) formed on an inner surface of the trench (5, 35) and in contact with the second surface (4b, 34) of the drift layer (4, 34); anode terminals (103), (203) on which the semiconductor device (1 to 1C) is flip-chip mounted and electrically connected to the anode electrodes (14, 39); cathode terminals (104), (204) electrically connected to the cathode electrodes (6, 36) of the semiconductor devices (1 to 1C) via bonding wires (109), (209); a semiconductor package comprising the semiconductor device (1 to 1C), and sealing resin (102), (202) for sealing the anode terminal (103), (203) and the cathode electrode (104), (204).

[0195] [A2] The semiconductor package according to [A1], wherein the first main surface (2a, 32a) is a (111) surface of the Si substrate (2, 32).

[0196] [A3] The semiconductor package according to [A1] or [A2], wherein the gallium-based semiconductor includes GaN or Ga2O3.

[0197] [A4] Gallium-based semiconductors (In x1 Ga 1-x )2O3(0≦x1<1) layer, (Al x2 Ga 1-x2 )2O3(0≦x2<1) layer, Sc x3 Ga 1-x3 N(0≦x3<1) layer, Tl x4 Ga 1-x4 N(0≦x4<1) layer or Al x5 Ga 1-x5 The semiconductor package according to [A3], comprising N (0≦x5<1) layers.

[0198] [A5] The semiconductor package according to any one of [A1] to [A4], wherein the buffer layer (3, 33) is made of an AlN layer.

[0199] [A6] The semiconductor package according to any one of [A1] to [A5], wherein only one trench (5, 35) is formed.

[0200] [A7] The semiconductor package according to any one of [A1] to [A5], wherein the trenches (5, 35) are formed in plurality.

[0201] [A8] The semiconductor package according to any one of [A1] to [A7], wherein the anode electrode (14) includes a Schottky metal (15) in Schottky contact with the first surface (4a) of the drift layer (4).

[0202] [A9] The semiconductor package described in any one of [A1] to [A8], wherein the cathode electrode (6) includes an ohmic metal (7) formed on an inner surface of the trench (5) and in ohmic contact with the second surface (4b) of the drift layer (4).

[0203] [A10] The semiconductor package according to any one of [A1] to [A9], wherein the semiconductor device (1, 1A) is a Schottky barrier diode.

[0204] [A11] The drift layer (4) comprises a first drift layer (21) formed on the first main surface (2a) and made of a gallium-based semiconductor doped with n-type impurities; The semiconductor package according to [A10], further comprising: a second drift layer (22) formed on a surface of the first drift layer (21) opposite the Si substrate (2) and made of a non-doped gallium-based semiconductor.

[0205] [A12] The semiconductor package according to [A11], wherein the n-type impurity is silicon or tin.

[0206] [A13] The semiconductor package according to any one of [A1] to [A7], wherein the semiconductor device is a PIN diode.

[0207] [A14] The drift layer (34) comprises a first drift layer (51) formed on the first main surface (32a) and made of a gallium-based semiconductor doped with an n-type impurity; a second drift layer (52) formed on a surface of the first drift layer (51) opposite to the Si substrate (32), the second drift layer (52) being made of a non-doped gallium-based semiconductor; The semiconductor package described in [A13] includes a third drift layer (53) formed on a surface of the second drift layer (52) opposite the Si substrate (32), and made of a gallium-based semiconductor doped with p-type impurities.

[0208] [A15] The n-type impurity is silicon or tin, The semiconductor package according to [A14], wherein the p-type impurity is manganese.

[0209] Although the embodiments of the present disclosure have been described in detail, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims. [Explanation of symbols]

[0210] 1, 1A, 1B, 1C Semiconductor device 2,32 Si substrate 2a,32a 1st main surface 2b,32b 2nd principal surface 3,33 Buffer layer 3a,33a 1st main surface 3b,33b 2nd principal surface 4,34 Drift layer 4a,34a 1st main surface 4b,34b 2nd principal surface 5,35 Trench 6,36 Cathode electrode 7 Ohmic Metal 8 Electrode Metal 37 Inner metal 38 Outer Metal 8A,38A 1st part 8B,38B 2nd part 11 Field insulating film 12 aperture 14,39 Anode electrode 15 Schottky Metal 16 Electrode metal 40 Inner metal 41 Outer metal 21,51 First drift layer 22,52 Second drift layer 53 3rd Drift Layer 101, 101A, 101B, 201, 201A, 201B Semiconductor packages 102,202 Resin Package 202a Main part 202b Thin wall part 202c Stepped section 103,203 Anode terminal 103a~103d, 203a~203d area 104,204 Cathode terminal 105,205 Island 106,206 Terminal part 107 Wire connection 108 Terminal part 109,209 Bonding Wire 210 Through hole

Claims

1. a Si substrate having a first main surface and a second main surface; a drift layer formed on a first main surface of the Si substrate and made of a gallium-based semiconductor layer; a buffer layer interposed between the Si substrate and the drift layer; an anode electrode in contact with a first surface of the drift layer, the first surface being a surface opposite to the buffer layer; a trench formed by digging from the second main surface of the Si substrate toward a second surface, which is a surface of the drift layer opposite to the first surface, penetrating the Si substrate and the buffer layer to reach the second surface of the drift layer; a semiconductor device including a cathode electrode formed on an inner surface of the trench and in contact with the second surface of the drift layer; an anode terminal on which the semiconductor device is flip-chip mounted and which is electrically connected to the anode electrode; a cathode terminal electrically connected to the cathode electrode of the semiconductor device via a bonding wire; A semiconductor package comprising the semiconductor device, and a sealing resin for sealing the anode terminal and the cathode electrode.

2. The semiconductor package according to claim 1 , wherein the first main surface is a (111) surface of the Si substrate.

3. The gallium-based semiconductor is GaN or Ga ２ O ３ The semiconductor package of claim 1 , comprising:

4. Gallium-based semiconductors (In ｘ１ G １－ｘ ) ２ O ３ (0≦x1<1) layer, (Al ｘ２ G １－ｘ２ ) ２ O ３ (0≦x2<1) layer, Sc ｘ３ G １－ｘ３ N (0≦x3<1) layer, Tl ｘ４ G １－ｘ４ N (0≦x4<1) layer or Al ｘ５ G １－ｘ５ The semiconductor package of claim 3 comprising N layers, where 0≦x5<1.

5. The semiconductor package according to claim 1 , wherein the buffer layer is an AlN layer.

6. The semiconductor package of claim 1 , wherein only one trench is formed.

7. The semiconductor package according to claim 1 , wherein the trench is formed in a plurality of portions.

8. The semiconductor package of claim 1 , wherein the anode electrode comprises a Schottky metal in Schottky contact with the first surface of the drift layer.

9. The semiconductor package of claim 1 , wherein the cathode electrode comprises an ohmic metal formed on an inner surface of the trench and in ohmic contact with the second surface of the drift layer.

10. 10. The semiconductor package according to claim 1, wherein the semiconductor device is a Schottky barrier diode.

11. the drift layer includes a first drift layer formed on the first principal surface and made of a gallium-based semiconductor doped with an n-type impurity; The semiconductor package according to claim 10 , further comprising: a second drift layer formed on a surface of the first drift layer opposite to the Si substrate, the second drift layer being made of a non-doped gallium-based semiconductor.

12. 12. The semiconductor package of claim 11, wherein the n-type impurity is silicon or tin.

13. 8. The semiconductor package according to claim 1, wherein the semiconductor device is a PIN diode.

14. the drift layer includes a first drift layer formed on the first principal surface and made of a gallium-based semiconductor doped with an n-type impurity; a second drift layer formed on a surface of the first drift layer opposite to the Si substrate and made of a non-doped gallium-based semiconductor; 14. The semiconductor package according to claim 13, further comprising: a third drift layer formed on a surface of the second drift layer opposite to the Si substrate, the third drift layer being made of a gallium-based semiconductor doped with a p-type impurity.

15. the n-type impurity is silicon or tin; 15. The semiconductor package of claim 14, wherein the p-type impurity is manganese.

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