Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a mounting area of circuit elements containing a plurality of resistors.SOLUTION: A semiconductor device includes: a voltage dividing circuit which includes a plurality of resistors connected in series, and a plurality of first switching elements each connected to each resistor in parallel, and which divides a voltage applied to the plurality of resistors; a control circuit which controls on and off of the first switching elements; and a second switching element which is connected to the plurality of resistors in series, is in a conductive state regardless of the on or off state of the first switching elements, and functions as a current source for supplying a specific current to the plurality of resistors. The voltage dividing circuit outputs a voltage, as a divided voltage, generated when a current is fed to a resistor connected to the first switching element in parallel being turned off by the control circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a high-voltage drop circuit that drops a high voltage and outputs the dropped voltage (see FIG. 9 of Patent Document 1). The high-voltage drop circuit disclosed in Patent Document 1 includes a plurality of resistors connected in series and a plurality of switch elements each connected in parallel to the plurality of resistors, and functions as a voltage divider circuit that divides the voltage applied to the plurality of resistors and outputs a divided voltage (Vdiv). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-289023 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology of Patent Document 1, when the current is reduced and the resistance value is increased in order to reduce power consumption, the size of the resistor for generating the divided voltage may become large. Therefore, it may not be possible to meet the need to reduce the mounting area of ​​the circuit element in a semiconductor device including a high voltage drop circuit. Thus, the conventional technology has room for improvement in terms of miniaturizing a semiconductor device including multiple resistors.

[0005] In consideration of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of reducing the mounting area of ​​a circuit element including a plurality of resistors. [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor device according to the present disclosure includes a plurality of resistors connected in series and a plurality of first switch elements each connected in parallel to a plurality of the resistors, the plurality of first switch elements being connected in parallel to the plurality of resistors, a voltage divider circuit that divides a voltage applied to the plurality of resistors, a control circuit that controls on / off of the first switch elements, a second switch element that is connected in series to the plurality of resistors, is in a conductive state regardless of an on / off state of the first switch elements, and functions as a current source that supplies a specific current to the plurality of resistors, and the voltage divider circuit outputs, as a divided voltage, a voltage generated when the current flows through the resistor that is connected in parallel to the first switch element that is turned off by the control circuit. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a semiconductor device that can reduce the mounting area of ​​a circuit element including a plurality of resistors. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing the voltage (gate-source Vgs) vs. current (drain-source current Ids) characteristics of the second switch element shown in FIG. [Diagram 3] FIG. 3 is a diagram showing a configuration of a semiconductor device according to a comparative example. [Figure 4] FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing a configuration of a semiconductor device according to a third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0010] [First embodiment] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device 100-1 may include a voltage divider circuit 10, a control circuit 20, a second switch element SW2, a detection circuit 40, and a reference voltage switching circuit 50.

[0011] The voltage-dividing circuit 10 may include a plurality of resistors R1 to Rn connected in series, and a plurality of first switch elements SW1 each connected in parallel to the plurality of resistors R1 to Rn. n may be interpreted as a natural number equal to or greater than 1. The voltage-dividing circuit 10 may be interpreted as a circuit that divides a voltage Vh applied to the plurality of resistors R1 to Rn. The voltage Vh may be interpreted as a voltage output from a DC voltage source.

[0012] The voltage divider circuit 10 may output, as the divided voltage Vdiv, a voltage generated by a current flowing through the resistors R1 to Rn connected in parallel to the first switch element SW1 that the control circuit 20 has turned off.

[0013] The second switch element SW2 is connected in series to multiple resistors R1 to Rn, is in a conductive state regardless of the on / off state of the first switch element SW1, and may be interpreted as a switch element that functions as a current source that supplies a specific current to the multiple resistors R1 to Rn.

[0014] The control circuit 20 may be interpreted as a circuit that controls the on / off of the first switch element SW1. Specifically, the control circuit 20 controls the on / off of the first switch element SW1 that is connected in parallel to each of the multiple resistors R1 to Rn included in the voltage dividing circuit 10. For example, when a current is passed through the first resistor R1 from the side to which the voltage Vh is applied among the multiple resistors R1 to Rn shown in FIG. 1 and a current is not passed through the remaining resistors R2 to Rn, the control circuit 20 may turn the first switch element SW1-1 that is connected in parallel to the first resistor R1 into an off state and turn all the remaining first switch elements SW1-2 to SW1-n into an on state. By turning the first switch element SW1-1 into an off state, a current flows through the resistor R1. By turning all the remaining first switch elements SW1-2 to SW1-n into an on state, a current is diverted to these switch elements, so that no current flows through the resistors that are connected in parallel to these switch elements.

[0015] The second switch element SW2 may be interpreted as a switch element that is connected in series to the multiple resistors R1 to Rn, is in a conductive state regardless of the on / off state of the first switch element SW1, and functions as a current source that supplies a specific current to the multiple resistors R1 to Rn. The second switch element SW2 may be interpreted as a depletion-type NMOS. The drain node of the NMOS is connected to the resistor Rn and the source node of the NMOS that constitutes the detection circuit 40. The bulk node, source node, and gate node of the NMOS are connected to GND.

[0016] The detection circuit 40 may be interpreted as a differential amplifier circuit. Specifically, the detection circuit 40 may be interpreted as a circuit that compares the divided voltage Vdiv with a specific reference voltage Vref and outputs a detection signal indicating that a divided voltage Vdiv higher than the specific reference voltage Vref or a divided voltage Vdiv lower than the specific reference voltage Vref has been detected.

[0017] More specifically, when the specific reference voltage Vref>the divided voltage Vdiv, the detection circuit 40 outputs an H-level detection signal to activate the operation of the charge pump circuit and boost the voltage Vh. When the specific reference voltage Vref<the divided voltage Vdiv, the detection circuit 40 outputs an L-level detection signal to, for example, stop the operation of the charge pump circuit.

[0018] The reference voltage switching circuit 50 may be interpreted as a circuit that holds a plurality of reference voltages having different values, switches between these reference voltages, and outputs the selected reference voltage to the detection circuit 40. The reference voltage switching circuit 50 may select one of the plurality of reference voltages input from outside the reference voltage switching circuit 50, and output the selected reference voltage as a specific reference voltage Vref for the detection circuit 40.

[0019] (Operation of Semiconductor Device) Next, the operation of the semiconductor device 100-1 will be described with reference to Fig. 2. Fig. 2 is a diagram showing the voltage (gate-source Vgs) vs. current (drain-source current Ids) characteristics of the second switch element SW2 shown in Fig. 1.

[0020] The second switch element SW2 is a depletion-type NMOS, and therefore has the Vgs-Ids characteristics as shown in Fig. 2. That is, when the Vgs of the second switch element SW2 is 0 [V], the second switch element SW2 operates as a current source that passes a current Id1.

[0021] Assuming that the second switch element SW2 operates as a current source in this manner, when the control circuit 20 shown in FIG. 1 sets the first first switch element SW1 to the off state and sets all the remaining first switch elements SW1 to the on state, the divided voltage Vdiv can be expressed by equation (1) according to Ohm's law. Vdiv = Vh - R1 × Id1 (1)

[0022] When the two input voltages are equal, the detection circuit 40 inverts the detection signal that is its output. Therefore, the condition shown in equation (2) is the output inversion condition of the detection circuit 40. Vdiv = Vref (2)

[0023] From the above equations (1) and (2), the reference voltage Vref can be expressed by equation (3). Vref = Vh - R1 × Id1 (3)

[0024] By modifying the above equation (3), the voltage Vh can be expressed by equation (4). Vh = R1 × Id1 + Vref (4)

[0025] The voltage Vh shown in the above formula (4) is used as the threshold voltage value of the detection circuit 40. When a voltage higher than this is input to the voltage Vh, the detection circuit 40 outputs an H-level detection signal. When a voltage lower than this is input to Vh, the detection circuit 40 outputs an L-level detection signal.

[0026] As shown in the above formula (4), since the voltage Vh varies in proportion to R1, the control circuit 20 controls the on / off of the first switches SW1-1, SW1-2, ..., SW1-n to vary the resistance values ​​used in the voltage-dividing circuit 10. This makes it possible to adjust the threshold voltage value.

[0027] (Comparative Example) Fig. 3 is a diagram showing the configuration of a semiconductor device according to a comparative example. The semiconductor device 100A according to the comparative example differs from the semiconductor device 100-1 shown in Fig. 1 in that a voltage-dividing circuit 10A includes a resistor Rn1 connected in series to the resistors R1 to Rn in addition to the resistors R1 to Rn.

[0028] The voltage divider circuit 10A can input the divided voltage Vdiv divided by the resistors R1 to Rn1 to the detection circuit 40. However, in the semiconductor device 100A according to the comparative example, when the current is reduced and the resistance value is increased in order to reduce power consumption, the dimensions of the resistors for generating the divided voltage, that is, the resistor Rn1, etc., may become large. Therefore, there is a possibility that the need to reduce the mounting area of ​​the circuit elements in the semiconductor device 100A including the voltage divider circuit 10A cannot be met. Furthermore, the increase in the mounting area of ​​the circuit elements may relatively increase the manufacturing cost of the semiconductor device 100A.

[0029] (Action and effect) As described above, the semiconductor device 100-1 of the present disclosure includes the second switch element SW2 that is connected in series to the multiple resistors R1 to Rn, is in a conductive state regardless of the on / off state of the first switch element SW1, and functions as a current source that supplies a specific current to the multiple resistors R1 to Rn, and the voltage divider circuit 10 outputs, as a divided voltage, a voltage generated when a current flows through a resistor connected in parallel to the first switch element SW1 that is turned off by the control circuit 20.

[0030] In this way, by combining the second switch element SW2 functioning as a current source, specifically a depletion-type NMOS, with the voltage divider circuit 10, it becomes possible to finely adjust the threshold voltage value of the detection circuit 40 as in the conventional circuit, while reducing the resistance and making it possible to reduce the mounting area of ​​the circuit elements.

[0031] Second embodiment Fig. 4 is a diagram showing the configuration of a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device 100-2 according to the second embodiment differs from the semiconductor device 100-1 shown in Fig. 1 in that the semiconductor device 100-2 according to the second embodiment includes a non-inverting amplifier 60 instead of the detection circuit 40.

[0032] The non-inverting amplifier 60 may be interpreted as a circuit having a non-inverting input terminal Vin1 for inputting a voltage (input signal Vin) from a power supply, an inverting input terminal Vin2 connected to a first end T1 of a series body including a plurality of resistors R1 to Rn and for inputting a divided voltage, and an output terminal Vout at a second end T2 opposite the first end T1 of the series body, for outputting a voltage that is a non-inverted amplified version of the voltage from the power supply.

[0033] Since the output signal of the non-inverting amplifier 60 is not inverted with respect to the input signal Vin, the phase of the input signal Vin and the output signal of the non-inverting amplifier 60 are in phase. The amplification factor of the non-inverting amplifier 60 is defined as 1+R2 / R1, where R2 is set to the resistance value of resistors R1 to Rn, and R1 is set to the resistance value of Rn1.

[0034] (Action and effect) As described above, the semiconductor device 100-2 of the present disclosure includes a non-inverting input terminal Vin1, an inverting input terminal Vin2 connected to a first end T1 of a series body including a plurality of resistors R1 to Rn for inputting a divided voltage, and an output terminal Vout for outputting a voltage obtained by non-inverting and amplifying a voltage from a power supply. In addition to the effect of the first embodiment, this configuration makes it possible to change the values ​​of the plurality of resistors R1 to Rn to obtain Vout, which is a signal obtained by shifting Vin upward by a potential of R×Ids, that is, a potential shift (potential offset) of a DC signal. The operation of the potential offset by the semiconductor device 100-2 will be described below.

[0035] When the feedback loop is stable, the + input (Vin1) and - input (Vin2) of the operational amplifier (non-inverting amplifier 60) are equal, so the divided voltage Vdiv and the input signal Vin can be expressed by equation (5). Vdiv = Vin (5)

[0036] If the total resistance of R1 to Rn shown in FIG. 4 is R, and the current flowing through SW2 is Ids, then Vout can be expressed by equation (6). Vout=Vdiv+R×Ids = Vin + R × Ids (6)

[0037] From equations (5) and (6), Vout is a signal obtained by shifting Vin upward by the potential of R×Ids.

[0038] Third embodiment Fig. 5 is a diagram showing a configuration of a semiconductor device according to a third embodiment of the present disclosure. The semiconductor device 100-3 according to the third embodiment differs from the semiconductor device 100-1 shown in Fig. 1 in that the semiconductor device 100-3 includes a current mirror circuit 70.

[0039] The current mirror circuit 70 includes a second switch element SW2 and a third switch element SW3. The third switch element SW3 may be interpreted as a transistor whose gate and drain are connected to the gate of the second switch element SW2 and whose drain is supplied with a current from a current source 71.

[0040] The second switch element SW2 is not limited to a depletion type NMOS, but may be an enhancement type NMOS. Similarly, the third switch element SW3 may be either a depletion type NMOS or an enhancement type NMOS.

[0041] (Action and effect) As described above, the semiconductor device 100-3 of the present disclosure includes a current mirror circuit 70 including the second switch element SW2. This configuration is generally used in many cases. Since a current can be flowed into the resistor of the voltage divider circuit 10 by using an enhancement type NMOS, the yield of the semiconductor device 100-3 can be improved in addition to the effect of the first embodiment. Furthermore, since the input resistance value of the current mirror circuit 70 is relatively small, the input current can be kept constant regardless of the driving conditions of the semiconductor device 100-3, and a specific divided voltage Vdiv can be easily set.

[0042] In addition, the following supplementary notes are provided in relation to the above description.

[0043] (Appendix 1) a voltage dividing circuit including a plurality of resistors connected in series and a plurality of first switch elements each connected in parallel to the plurality of resistors, the voltage dividing circuit dividing a voltage applied to the plurality of resistors; A control circuit that controls the on / off of the first switch element; a second switch element that is connected in series to the plurality of resistors, is in a conductive state regardless of an on / off state of the first switch element, and functions as a current source that supplies a specific current to the plurality of resistors; The voltage divider circuit includes: The semiconductor device outputs, as a divided voltage, a voltage generated when the current flows through the resistor connected in parallel to the first switch element in which the control circuit is turned off. (Appendix 2) The semiconductor device according to claim 1, further comprising a detection circuit that compares the divided voltage with a specific reference voltage and outputs a detection signal indicating that the divided voltage is higher than the specific reference voltage or that the divided voltage is lower than the specific reference voltage. (Appendix 3) The semiconductor device described in Appendix 1 has a non-inverting input terminal for inputting a voltage from a power supply, and an inverting input terminal connected to a first end of a series body including a plurality of the resistors and for inputting the divided voltage, and further comprises a non-inverting amplifier at a second end opposite to the first end of the series body for outputting a voltage obtained by non-inverting and amplifying the voltage from the power supply. (Appendix 4) 4. The semiconductor device according to claim 2, wherein the second switch element is a depletion-type N-channel transistor having a grounded gate. (Appendix 5) 2. The semiconductor device according to claim 1, further comprising: a current mirror circuit including the second switch element and a third switch element whose gate and drain are connected to the gate of the second switch element and whose drain is supplied with current from a current source. [Explanation of symbols]

[0044] 10, 10A voltage divider circuit 40 Detection circuit 60 Non-inverting amplifier 70 Current Mirror Circuit 71 Current source 100, 100A Semiconductor Device SW1 First switch element SW2 Second switch element SW3 Third switch element

Claims

1. a voltage divider circuit including a plurality of resistors connected in series and a plurality of first switch elements each connected in parallel to the plurality of resistors, the voltage divider circuit dividing a voltage applied to the plurality of resistors; A control circuit for controlling the on / off of the first switch element; a second switch element that is connected in series to the plurality of resistors, is in a conductive state regardless of an on / off state of the first switch element, and functions as a current source that supplies a specific current to the plurality of resistors; The voltage divider circuit includes: The semiconductor device outputs, as a divided voltage, a voltage generated when the current flows through the resistor connected in parallel to the first switch element in which the control circuit is turned off.

2. 2. The semiconductor device according to claim 1, further comprising a detection circuit that compares the divided voltage with a specific reference voltage and outputs a detection signal indicating that the divided voltage is higher than the specific reference voltage or that the divided voltage is lower than the specific reference voltage.

3. 2. The semiconductor device according to claim 1, further comprising a non-inverting input terminal for inputting a voltage from a power supply, and an inverting input terminal connected to a first end of a series body including a plurality of the resistors and for inputting the divided voltage, and a non-inverting amplifier at a second end of the series body opposite to the first end for outputting a voltage obtained by non-inverting and amplifying the voltage from the power supply.

4. 4. The semiconductor device according to claim 2, wherein the second switch element is a depletion-type N-channel transistor having a gate grounded.

5. 2. The semiconductor device according to claim 1, further comprising a current mirror circuit including the second switch element and a third switch element having a gate and a drain connected to the gate of the second switch element and having a current supplied to the drain from a current source.

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