Integrated circuit device

Abstract

To provide an integrated circuit device that performs, only once when power supply is connected first, a memory load operation that is performed at switching from a low-power mode to a high-power mode and thereby reduces the current amount used for memory loading.SOLUTION: An integrated circuit device according to the present invention is characterized by including: a memory for storing trim data; a sleep register for inputting trim data to a sleep function block; a normal register for inputting trim data to a normal function block; a memory controller for loading the trim data stored in the memory into the sleep register or the normal register; and a wake controller for loading the trim data stored in the normal register into the sleep register via the memory controller at a first self-wakeup time after power supply is connected, so as to ensure that the memory is loaded only once after power supply is connected.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to integrated circuit devices. [Background technology]

[0002] Generally, an integrated circuit for diagnosing and managing the state of a battery receives power from the battery and operates.

[0003] If the integrated circuit battery draws a large current, it can affect the battery's life and performance.

[0004] To minimize such effects, integrated circuits use a low-power mode (sleep mode) and switch to a high-power mode (normal mode) only when necessary.

[0005] However, the integrated circuit performs a memory load operation each time it switches from a low power mode to a high power mode.

[0006] As a result, the current consumption of the battery increases, which may shorten the battery life, and the time required for mode switching increases, which may result in the mode switching failing.

[0007] The background art of the present invention is disclosed in Patent Document 1, "Battery diagnostic device and method." [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Korean Patent Publication No. 10-2018-0057230 Summary of the Invention [Problem to be solved by the invention]

[0009] The present invention has been made to improve the above-mentioned problems, and an object of one aspect of the present invention is to provide an integrated circuit device in which the memory load operation that is performed when switching from low power mode to high power mode is performed only once, at the beginning when the power supply is connected, thereby reducing the amount of current used for memory load. [Means for solving the problem]

[0010] An integrated circuit device according to one aspect of the present invention includes a memory for storing trim data, a sleep register for inputting the trim data to a sleep functional block, a normal register for inputting the trim data to a normal functional block, a memory controller for loading the trim data stored in the memory into the sleep register or the normal register, and a wake controller for loading the trim data stored in the normal register into the sleep register via the memory controller at the time of the first self-wakeup after power is connected, so that the memory is loaded only the first time after power is connected.

[0011] The wake controller of the present invention is characterized in that when a power supply is connected and a stabilization completion signal is received from the sleep function block, it turns on the power supplies to the memory, the memory controller, the normal register, and the normal function block.

[0012] The memory controller of the present invention is characterized in that it loads the trim data into the sleep register and the normal register, and loads the trim data stored in the normal register into the sleep register before entering a low power mode.

[0013] The memory of the present invention is characterized in that it retains the trim data even when the power is turned off.

[0014] The memory controller of the present invention is characterized in that, at the time of external wakeup after self-wakeup, the trim data stored in the sleep register is loaded into the normal register.

[0015] The sleep register of the present invention is characterized in that it holds the trim data while power is constantly being supplied.

[0016] The normal register of the present invention is characterized in that it holds the trim data while the constant power supply and the normal power supply are supplied. [Effects of the Invention]

[0017] An integrated circuit device according to one aspect of the present invention performs a memory load operation when switching from low power mode to high power mode only once, when the power supply is connected, thereby reducing the amount of current used for memory load in low power mode.

[0018] An integrated circuit device according to another aspect of the present invention reduces the time it takes to switch into a high power mode, allowing for a quick response to fault conditions.

[0019] An integrated circuit device according to yet another aspect of the present invention pre-applies trim data to functional blocks to increase wake-up robustness. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a diagram illustrating a system configuration to which an integrated circuit device according to an embodiment of the present invention can be applied; [Figure 2] 1 is a block diagram of an integrated circuit device according to an embodiment of the present invention; [Figure 3] FIG. 10 is a diagram showing a self-wake-up sequence of an integrated circuit device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a diagram showing an external wake-up sequence of an integrated circuit device according to an embodiment of the present invention. [Figure 5]FIG. 4 illustrates a memory load sequence according to one embodiment of the present invention. [Figure 6] FIG. 10 is a diagram illustrating an example of a reduction in high power mode switching time according to an embodiment of the present invention. [Figure 7] FIG. 10 illustrates an example of pre-application of trim data according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] An integrated circuit device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, the thickness of lines and the size of components shown in the drawings may be exaggerated for clarity and convenience. Furthermore, the terms used below are defined in consideration of the functions of the present invention, and may vary depending on the intentions or practices of users and operators. Therefore, definitions of such terms should be based on the overall content of this specification.

[0022] FIG. 1 is a diagram showing the configuration of a system to which an integrated circuit device according to an embodiment of the present invention can be applied.

[0023] Referring to FIG. 1, a plurality of ICs 10 are coupled to a battery 20 to diagnose the state of the battery 20.

[0024] Each of the multiple ICs 10 constantly consumes current from the battery 20 .

[0025] To reduce battery drain, IC10 switches from low-power mode to high-power mode only when necessary.

[0026] The IC 10 performs a memory load operation every time it switches from the low power mode to the high power mode, and such a memory load operation consumes a large amount of current.

[0027] Therefore, it is necessary to limit memory load operations to reduce current consumption.

[0028] An integrated circuit device according to one embodiment of the present invention performs a memory load operation, which is normally performed when switching from a low power mode to a high power mode, only once at the beginning when the power supply is first connected.

[0029] FIG. 2 is a block diagram of an integrated circuit device according to an embodiment of the present invention; FIG. 3 is a diagram showing a self-wake-up sequence of an integrated circuit device according to an embodiment of the present invention; FIG. 4 is a diagram showing an external wake-up sequence of an integrated circuit device according to an embodiment of the present invention; FIG. 5 is a diagram showing a memory load sequence according to an embodiment of the present invention; FIG. 6 is a diagram showing an example of shortening high power mode switching time according to an embodiment of the present invention; and FIG. 7 is a diagram showing an example of pre-application of trim data according to an embodiment of the present invention.

[0030] Referring to FIG. 2, an integrated circuit device according to one embodiment of the present invention includes a sleep function block 110, a sleep register 120, a wake controller 130, a normal function block 210, a memory 220, a memory controller 230, and a normal register 240.

[0031] The sleep functional block 110, sleep register 120, and wake controller 130 operate in a sleep domain 100 that remains always on.

[0032] The wake controller 130, normal function block 210, memory 220, memory controller 230, and normal register 240 operate in a normal domain 200 in which on and off are repeated.

[0033] The sleep function block 110 may be an analog function block that operates in a sleep mode.

[0034] The sleep function block 110 can operate by applying trim data stored in a sleep register 120 .

[0035] The trim data may be information about clock frequency and current for a functional block to obtain maximum performance within the power range specified by the functional block.

[0036] The sleep function block 110 is capable of recognizing a wake-up signal.

[0037] The sleep function block 110 can transmit a stabilization completion signal (Power OK) to the wake controller 130 during the first self-wake-up sequence after the power supply is connected.

[0038] Normal function block 210 may be an analog function block operating in a normal mode.

[0039] The normal function block 210 can operate by applying the trim data stored in the normal register 240 .

[0040] The sleep register 120 can receive constant power and retain trim data.

[0041] The sleep register 120 inputs trim data to the sleep function block 110, allowing the sleep function block 110 to apply the trim data of the sleep register 120.

[0042] The sleep register 120 can receive and store trim data from the normal register 240 in response to a control command from the memory controller 230 before entering the low power mode during self-wakeup.

[0043] Upon external wake-up, the sleep register 120 can load trim data into the normal register 240 in response to a control command from the memory controller 230 .

[0044] The wake controller 130 can receive a stabilization complete signal from the sleep function block 110 when power is applied.

[0045] Upon receiving the stabilization completion signal, the wake controller 130 can turn on the normal power supply of the normal domain 200. That is, the wake controller 130 can turn on the power supplies of the memory 220, the memory controller 230, the normal registers 240, and the normal function block 210.

[0046] The wake controller 130 performs a memory load operation only once when the power supply is connected.

[0047] That is, at the first self-wakeup after power is connected, the wake controller 130 loads the trim data stored in the normal register 240 into the sleep register 120 via the memory controller 230 before entering the low power mode.

[0048] Furthermore, at the time of external wakeup after self-wakeup, the wake controller 130 loads the trim data stored in the sleep register 120 into the normal register 240 via the memory controller 230 .

[0049] That is, as shown in FIG. 5, the memory load operation is not performed each time the low power mode is switched to the high power mode by an external wake-up signal, but is performed only once at the beginning of self-wake-up after the power is turned on, thereby significantly reducing current consumption.

[0050] The memory 220 can store trim data.

[0051] The memory 220 can transmit the trim data to the normal register 240 in response to a control command from the memory controller 230 .

[0052] The memory 220 retains the trim data even when the power is turned off.

[0053] Normal register 240 can store trim data.

[0054] The normal register 240 can hold trim data while both constant power and normal power are supplied.

[0055] The normal register 240 inputs trim data to the normal function block, allowing the normal function block to apply the trim data of the normal register 240.

[0056] The normal register 240 can load trim data into the sleep register 120 in response to a control command from the memory controller 230 during self-wakeup and before entering the low power mode.

[0057] Upon external wake-up, the normal register 240 can receive and store trim data from the normal register 240 in response to a control command from the memory controller 230 .

[0058] At the time of self-wakeup, the normal register 240 can load the trim data stored in the memory 220 into the sleep register 120 and the normal register 240 .

[0059] Once the trim data is loaded into the sleep register 120, the trim data stored in the sleep register 120 is applied to the sleep function block 110 from this point on.

[0060] When the trim data is loaded into the normal register 240, the trim data stored in the normal register 240 is applied to the normal function block 210 from this point on.

[0061] Thereafter, before entering the low power mode, the memory controller 230 stores the trim data stored in the normal register 240 in the sleep register 120. As a result, the sleep register 120 holds the trim data, so even when entering the low power mode from the high power mode, the sleep functional block 110 maintains a state in which the trim data stored in the sleep register 120 is applied. In contrast, the normal functional block 210 maintains a state in which the trim data is not applied because no power is applied.

[0062] This will be explained in detail with reference to FIGS.

[0063] Referring to FIG. 3, after power is connected, the sleep function block 110 transmits a stabilization completion signal to the wake controller 130 during self-wakeup.

[0064] Upon receiving the stabilization completion signal from the sleep functional block 110, the wake controller 130 turns on the power supply to the normal domain 200. This causes the normal power supplies of the normal functional block 210, the normal register 240, the memory controller 230, and the memory 220 to be turned on.

[0065] When the normal power supply is turned on, the wake controller 130 causes the memory controller 230 to run.

[0066] The memory controller 230 loads the trim data stored in the memory 220 into the sleep register 120 and the normal register 240 .

[0067] Once the trim data is loaded into the sleep register 120, the trim data stored in the sleep register 120 is applied to the sleep function block 110 from this point on.

[0068] When the trim data is loaded into the normal register 240, the trim data stored in the normal register 240 is applied to the normal function block 210 from this point on.

[0069] Thereafter, before entering the low power mode, the memory controller 230 loads the trim data stored in the normal register 240 into the sleep register 120. In this case, since the sleep register 120 holds the trim data, even when the high power mode is switched to the low power mode, the sleep functional block 110 maintains a state in which the trim data stored in the sleep register 120 is applied. In contrast, since the normal functional block 210 is not powered, the trim data is maintained in a state in which it is not applied.

[0070] Referring to FIG. 4, when an external wakeup occurs after a self-wakeup, the sleep function block 110 is in a state in which the trim data of the sleep register 120 has already been applied due to the self-wakeup.

[0071] When the sleep function block 110 receives the wake-up signal, it notifies the wake controller 130 that the wake-up signal has been transmitted.

[0072] The wake controller 130 turns on the power supply to the normal domain 200. As a result, the normal power supplies to the normal function block 210, the normal register 240, the memory controller 230, and the memory 220 are turned on.

[0073] When the normal power supply is turned on, the memory controller 230 loads the trim data stored in the sleep register 120 into the normal register 240. As a result, the normal function block 210 applies the trim data stored in the normal register 240.

[0074] That is, as shown in FIG. 5, when the memory controller 230 self-wakes up, it loads the trim data stored in the normal register 240 into the sleep register 120 before entering the low power mode, and thereafter, when it externally wakes up, it uploads the trim data in the sleep register 120 to the normal register 240, so that memory loading is performed only once after the power supply is connected, thereby reducing the amount of current used for memory loading in the low power mode.

[0075] Also, as shown in FIG. 6, the memory load time of each IC 10 connected to the battery 20 can be reduced, so that the memory load time can be reduced by the number of ICs 10, thereby shortening the fault reaction time.

[0076] For example, if the time required to load 2 kbits of memory is approximately 1 ms and 20 ICs 10 are installed, the memory load time can be reduced by a total of 20 ms.

[0077] Moreover, as shown in FIG. 7, wake-up robustness can be improved by applying trim data in advance.

[0078] For example, if the frequency of a 100 kHz oscillator that recognizes the frequency of the wake-up pulse is out of sync, the oscillator may not be woken up. However, this embodiment can solve this problem by loading trim data into the sleep register 120 in advance. [Explanation of symbols]

[0079] 10 ICs, 20 batteries, 100 sleep domains, 110 sleep function blocks, 120 sleep registers, 130 wake controllers, 200 normal domains, 210 normal function blocks, 220 memories, 230 memory controllers, 240 normal registers.

Claims

1. A memory for storing trim data; a sleep register for inputting said trim data to a sleep function block; a normal register for inputting the trim data to a normal function block; a memory controller for loading the trim data stored in the memory into the sleep register or the normal register; and a wake controller that loads the trim data stored in the normal register into the sleep register via the memory controller at the first self-wakeup time after the power supply is connected, so that the memory is loaded only the first time after the power supply is connected.

2. The wake controller includes:

2. The integrated circuit device according to claim 1, wherein when a power supply is connected and a stabilization completion signal is received from the sleep functional block, the integrated circuit device turns on the power supplies of the memory, the memory controller, the normal register, and the normal functional block.

3. The memory controller includes:

2. The integrated circuit device of claim 1, further comprising: loading said trim data into said sleep register and said normal register; and loading said trim data stored in said normal register into said sleep register prior to entering a low power mode.

4. The memory includes:

2. The integrated circuit device according to claim 1, wherein the trim data is maintained even when the power is turned off.

5. The memory controller includes:

2. The integrated circuit device according to claim 1, wherein the trim data stored in the sleep register is loaded into the normal register upon external wake-up after self-wake-up.

6. The sleep register includes:

2. The integrated circuit device according to claim 1, wherein the trim data is held while power is constantly being supplied.

7. The normal register is 2. The integrated circuit device according to claim 1, wherein the trim data is held while a constant power supply and a normal power supply are supplied.

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