Power converter controller
Patent Information
- Application Number
- JP2024137632
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-08-23
- Filing Date
- 2024-08-19
- Publication Date
- 2025-03-07
Smart Images
Figure 2025031621000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to a power converter controller, and more particularly, to a controller for constant on-time (COT) power converters with improved transient response. [Background technology]
[0002] Constant on-time (COT) buck converters are widely deployed in DC-DC converter applications that require fast transient response and ease of use. COT control relies on high equivalent series resistance (ESR) of the output capacitor for stable operation.
[0003] The wide range of ceramic capacitors used for decoupling the output of point-of-load (PoL) buck converters have the lowest ESR, which makes the default COT control unstable. To avoid stability issues, an artificial ramp is added to one end of the COT comparator. This ramp emulates the effect of a high ESR while maintaining the benefits of a low ESR output capacitor for dynamic performance.
[0004] The minimum ramp size to ensure theoretically stable operation of a COT converter is smaller than the ramp size typically used for practical reasons. Small ramp amplitudes lead to large switching frequency jitter that is often considered undesirable. This is discussed in “Advantages of Constant-On-Time Control in DC / DC converters” by Dave Baker, November 2019, https: / / www.monolithicpower.com / en / advantages-of-constant-on-time-control-in-dc-dc-converters, and “Adaptive Constant On-Time (D-CAP®) Control Study in Notebook Applications” by Chuan Ni and Tateishi Tetsuo et al., SLVA281B, July 2007, revised December 2007, https: / / www.ti.com / lit / an / slva281b / slva281b.pdf.
[0005] The transient response of the converter is degraded by the addition of a compensation ramp. If the ramp is made larger than the minimum size to ensure stable operation, the transient response of the converter is further reduced. Therefore, for large transient load conditions the converter may become unstable or noise limited at the switching frequency. Summary of the Invention
[0006] It is an object of the present disclosure to address one or more of the above-mentioned shortcomings.
[0007] According to a first aspect of the present disclosure, a controller is provided, the controller including: a ramp generator for generating a ramp signal; and a ramp regulator adapted to compare a feedback signal of the converter and a threshold signal to obtain a comparison signal, and to adjust an amplitude of the ramp signal based on the comparison signal.
[0008] For example, the ramp signal may be a periodic signal, such as a triangular signal that varies between positive and negative amplitudes. The amplitude of the ramp signal may be half the peak-to-peak amplitude of the ramp signal.
[0009] Optionally, the comparison signal is a logic signal, for example, the logic signal may be a 1-bit signal or a multi-bit signal.
[0010] Optionally, during the steady state, the ramp signal has a steady state amplitude, and the ramp regulator is configured to cause the logic signal to change state such that when the feedback signal decreases to reach a value equal to or lower than the threshold signal, the amplitude of the ramp signal decreases below the steady state amplitude.
[0011] For example, the feedback signal may decrease if the load increases suddenly.
[0012] Optionally, the controller includes a comparator adapted to compare the ramp signal with a first reference voltage to generate the driver control signal. For example, the first reference voltage may be a target output voltage.
[0013] Optionally, the controller comprises a voltage supply adapted to generate a second reference voltage, where the threshold signal is equal to the second reference voltage and the second reference voltage is less than the first reference signal.
[0014] Optionally, the ramp generator includes a capacitor coupled to a resistor circuit including a plurality of resistors, where the comparison signal is configured to activate or deactivate one or more of the resistors.
[0015] Optionally, the ramp generator comprises a capacitor coupled to a transconductance amplifier, where the comparison signal is configured to adjust a transconductance value of the transconductance amplifier.
[0016] Optionally, the capacitor is coupled to ground through a variable resistor.
[0017] According to a second aspect of the present disclosure, there is provided a power converter including: a controller according to the first aspect coupled to a power stage, the power stage including a high-side power switch coupled to a low-side power switch at a switching node; an inductor; and a driver configured to drive the high-side power switch and the low-side power switch.
[0018] Optionally, the power converter is a constant on-time converter.
[0019] According to a third aspect of the present disclosure, there is provided a method of controlling a converter, the method comprising: generating a ramp signal; comparing the transducer feedback signal with a threshold signal to obtain a comparison signal; adjusting the amplitude of the ramp signal based on the comparison signal; Includes.
[0020] Optionally, the comparison signal is a logic signal.
[0021] Optionally, during the steady state, the ramp signal has a steady state amplitude, where when the feedback signal decreases to reach a value equal to or lower than the threshold signal, the logic signal changes state such that the amplitude of the ramp signal decreases below the steady state amplitude.
[0022] Optionally, the logic signal is a one-bit signal having a first state during steady state and a second state during transient state.
[0023] Optionally, the logic signal is a multi-bit signal. [Brief description of the drawings]
[0024] The present disclosure will now be described in further detail, by way of example only, with reference to the accompanying drawings, in which: [Figure 1]FIG. 1 illustrates a conventional constant on-time (COT) buck converter. [Diagram 2] 2 is a plot of lamp voltage as a function of time illustrating the operation of the converter of FIG. 1. [Diagram 3] 1 is a flowchart illustrating a method for controlling a COT converter according to the present disclosure. [Figure 4] FIG. 1 illustrates a COT converter according to the present disclosure. [Diagram 5] FIG. 5 illustrates an exemplary embodiment of the converter of FIG. 4. [Figure 6] FIG. 5 illustrates another exemplary embodiment of the converter of FIG. 4. [Figure 7] 5 illustrates yet another exemplary embodiment of the converter of FIG. 4. [Figure 8] 2 is a simulation illustrating the operation of the COT converter of FIG. 1. [Figure 9] 5 is a simulation illustrating the operation of the COT converter of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] 1 shows a conventional constant on-time (COT) buck converter. The converter 100 includes a high-side power switch S1, a low-side power switch S2, an inductor L, a driver 110, and an output regulation loop for regulating the output voltage of the converter. The output regulation loop is regulated by a feedback ramp signal V RAMP , and a pulse width modulation (PWM) comparator 130. The PWM comparator 130 is connected to a reference signal V ref a first input for receiving a feedback ramp voltage V RAMP and one output coupled to the driver 110.
[0026] FIG. 2 is a plot diagram illustrating the operation of the converter of FIG. 1. The upper waveform shows the feedback reference voltage, and the lower waveform shows the state (on or off) of switch S1. During operation, the feedback lamp voltage V RAMP (=Vout + lamp) is V ref When the duty cycle is reached, comparator 130 sends a logic high to driver 110. Driver 110 then turns on high-side switch S1 for a fixed period of time D*T, where D represents the duty cycle and T represents the switching period, hence the name "constant on-time switching converter." After this fixed period has elapsed, driver 110 turns off switch S1 and turns on switch S2. The output voltage becomes equal to D*V. in where V in represents the supply voltage. S1 is turned on for a pre-determined period of time, at which point S1 is turned off. To accommodate larger output loads, it is common practice to have multiple power stages paralleled.
[0027] 3 is a flow chart illustrating a method for controlling a COT converter according to the present disclosure. In step 310, a ramp signal is generated. In step 320, a feedback signal of the converter is compared with a threshold signal to obtain a comparison signal. For example, the feedback signal may be the output voltage of the converter. In step 330, an amplitude of the ramp signal is adjusted based on the comparison signal.
[0028] During steady state, the comparison signal has a steady state amplitude. During a load transient, the feedback signal decreases, and when the feedback signal reaches a value equal to or less than the threshold signal, the comparison signal increases above the steady state value and the amplitude of the ramp signal decreases.
[0029] Low switching frequency noise is desirable under most conditions. However, COT controlled converters exhibit large instantaneous changes in switching frequency under large load transients. Therefore, the ramp size requirement that ensures low switching frequency noise under large transients can be ignored and the ramp amplitude can be reduced momentarily. The ramp amplitude can then be increased momentarily or gradually returned to the normal range.
[0030] The comparison signal may be a logic signal, such as a 1-bit signal having only two levels: a low state 0 and a high state 1. Alternatively, the logic signal may be a multi-bit signal having three or more levels. For example, a 2-bit signal has four levels, with two high states (11, 10) and two low states (00, 01) associated with each of the two bits.
[0031] This approach improves the load transient response of the converter without increasing noise at the switching frequency and while maintaining converter stability.
[0032] 4 is a diagram illustrating a COT converter according to the present disclosure. The power converter 400 includes a power stage 410 coupled to a controller formed of a comparator 420, a ramp generator 430, and a ramp regulator 440.
[0033] The power stage 410 includes a high-side power switch coupled to a low-side power switch at a switching node, an inductor, and a driver configured to drive the high-side power switch and the low-side power switch. The inductor has a first terminal coupled to the switching node and a second terminal coupled to an output port of the converter, the first terminal being connected to an output voltage V out and a second terminal for supplying
[0034] The comparator 420 is a first reference voltage V ref1 a first input for receiving a ramp voltage V from a ramp generator 430; ramp and a second input for receiving
[0035] The ramp generator 430 is coupled in parallel with the inductor L. The ramp regulator 440 provides an output voltage V out a first input, for example an inverting input, for receiving a second reference voltage V ref2 The second reference voltage V is formed of a comparator having a second input, e.g. a non-inverting input, for receiving the second reference voltage V and an output for providing the adjustment signal S_adjust. ref2 is the threshold voltage Vth The threshold voltage is also called V th =V ref2 <V ref1 is selected so that
[0036] Optionally, the second input can be connected to a positive offset voltage V offset In this case, a voltage supply is provided for supplying a threshold voltage V th V th =V ref1 -V offset The offset voltage may be selected depending on the application.
[0037] A ramp generator 430 is coupled in parallel with the inductor L. The ramp generator has an input for receiving the output of the regulation circuit 440 and an output coupled to the comparator 420.
[0038] 5 is a diagram illustrating an exemplary embodiment of the converter of FIG. 4. In this embodiment, the ramp generator 530 includes a capacitor C1 coupled to a resistive circuit formed of two resistors R1 and R2 coupled in parallel. The resistors R1 and R2 are coupled via a switch controlled by an adjust signal S_adjust. When the adjust signal is high (logic 1), the switch is closed and the amplitude of the ramp signal is reduced. The resistive circuit may be modified to include an additional resistor coupled in parallel via an additional switch.
[0039] 6 is a diagram showing another exemplary embodiment of the converter of FIG. 4. For clarity of illustration, only a portion of the COT circuit is shown. In this embodiment, a ramp generator 630 includes a resistor R1 in series with a capacitor C1. The capacitor C1 is coupled in parallel to a transconductance amplifier 632. The transconductance amplifier 632 has a first input coupled to a first (positive) terminal of the capacitor C1, a second input coupled to a second (negative) terminal of the capacitor C1, and a ramp signal V ramp Optionally, the output of the transconductance amplifier 632 is coupled to a variable resistor R sThe ramp signal V ramp The amplitude of is determined by the transconductance gm and the resistance R s The ramp signal is proportional to the product of g and the ramp amplitude. The transconductance amplifier 632 is configured to receive an adjustment signal S_adjust for adjusting the value of the transconductance g. When the adjustment signal is high (logic 1), the transconductance g decreases, decreasing the amplitude of the ramp signal.
[0040] 7 is a diagram showing another exemplary embodiment of the converter of FIG. 4. For clarity of illustration, only a portion of the COT circuit is shown. In this embodiment, a ramp generator 730 includes a transconductance amplifier 732 having a first input coupled to the switching node Lx, a second input coupled to the output of the converter, and an output for providing a ramp signal. The output of the transconductance amplifier 732 is coupled to a sensing capacitor C s may be coupled to ground through a sense resistor Rs in parallel with R s and C s is used to convert the current square wave igm into a triangular voltage, i.e. a ramp that mimics the inductor current. The amplitude of the ramp signal is determined by the transconductance gm and the resistance R s and capacitor C s It is proportional to the product of .
[0041] Figure 8 is a simulation illustrating the operation of the prior art COT converter of Figure 1. Figure 8 shows the waveforms of the output voltage 810, the inductor current 830, the ramp signal 840, and the reference signal 850.
[0042] Figure 9 is a simulation illustrating the operation of the COT converter of Figure 4. Figure 9 shows waveforms of the output voltage 910, the adjustment signal S_adjust 920 (output of 440), the inductor current 930, the ramp signal 940, and the reference signal 950.
[0043] The amplitude of the ramp signal decreases during the high state of signal 920. Compared to the circuit of Figure 1, the circuit of Figure 4 significantly reduces the undershoot of the output voltage transient, thus improving efficiency.
[0044] The proposed approach may also be applied to multi-phase COT converters, which would require multiple lamp regulators, one for each lamp.
[0045] Those skilled in the art will appreciate that variations of the disclosed arrangements are possible without departing from the present disclosure. Thus, the above description of specific embodiments is for purposes of illustration and not limitation. It will be apparent to those skilled in the art that minor modifications can be made without significantly altering the operation described above.
Claims
1. A controller, a ramp generator for generating a ramp signal; a ramp regulator adapted to compare a converter feedback signal with a threshold signal to obtain a comparison signal and to adjust an amplitude of the ramp signal based on the comparison signal; Including, the controller.
2. The controller of claim 1 , wherein the comparison signal is a logic signal.
3. 3. The controller of claim 2, wherein during a steady state, the ramp signal has a steady state amplitude, and the ramp regulator is configured to cause the logic signal to change state such that the amplitude of the ramp signal decreases below the steady state amplitude when the feedback signal decreases to a value equal to or lower than the threshold signal.
4. The controller of claim 1 comprising a comparator adapted to compare the ramp signal with a first reference voltage to generate a driver control signal.
5. 5. The controller of claim 4, further comprising a voltage supply adapted to generate a second reference voltage, the threshold signal being equal to the second reference voltage, the second reference voltage being less than the first reference signal.
6. 2. The controller of claim 1, wherein the ramp generator includes a capacitor coupled to a resistive circuit including a plurality of resistors, and the comparison signal is configured to activate or deactivate one or more resistors.
7. The controller of claim 1 , wherein the ramp generator includes a capacitor coupled to a transconductance amplifier, and the comparison signal is configured to adjust a transconductance value of the transconductance amplifier.
8. The controller of claim 7 , wherein the capacitor is coupled to ground through a variable resistor.
9. 1. A power converter comprising:
13. The controller of claim 1 coupled to a power stage, the power stage including a high side power switch coupled to a low side power switch at a switching node; An inductor; a driver configured to drive the high-side power switch and the low-side power switch; 2. A power converter comprising:
10. 10. The power converter of claim 9 which is a constant on-time converter.
11. 1. A method of controlling a converter, comprising: generating a ramp signal; comparing the transducer feedback signal to a threshold signal to obtain a comparison signal; adjusting an amplitude of the ramp signal based on the comparison signal; A method comprising:
12. The method of claim 11 , wherein the comparison signal is a logic signal.
13. 13. The method of claim 12, wherein during a steady state, the ramp signal has a steady state amplitude, and when the feedback signal decreases to a value equal to or less than the threshold signal, the logic signal changes state such that the amplitude of the ramp signal decreases below the steady state amplitude.
14. 13. The method of claim 12, wherein the logic signal is a one-bit signal having a first state during a steady state and a second state during a transient state.
15. The method of claim 12 , wherein the logic signal is a multi-bit signal.