Imaging apparatus

Abstract

To provide a camera system capable of wide dynamic range shooting with a simpler constitution.SOLUTION: A disclosed camera system includes: a first photoelectric conversion unit; a first charge storage area; a first transistor; a second charge storage area; a second photoelectric conversion unit; and a third charge storage area. The camera system is configured to generate, within one frame period, a first signal corresponding to a potential in the first charge storage area when the first signal charge is accumulated in the first charge storage area when the first transistor is off, a second signal corresponding to the potential in the first charge storage area and the second charge storage area when the first signal charges are accumulated in the first charge storage area and the second charge storage area when the first transistor is on, and a third signal corresponding to the potential in the third charge storage area when the second signal charge is stored in the third charge storage area.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] In recent years, proposals have been made to realize a wide dynamic range in imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary MOS) image sensors. For example, the following Patent Document 1 discloses a solid-state imaging device using high-sensitivity cells and low-sensitivity cells of different sizes. The following Patent Document 2 discloses a method of obtaining two signals with different sensitivities from each pixel by performing two electronic shutter operations with different exposure periods. In the technology described in Patent Document 2, an image with an expanded dynamic range is formed by selecting one of two signals for each pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-125209 A [Patent Document 2] JP 2011-040926 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology described in Patent Document 1 requires the formation of two types of imaging cells in the imaging region. On the other hand, according to the technology described in Patent Document 2, although the structure of each imaging cell can be made common, it is necessary to provide a separate exposure period for acquiring a high-sensitivity signal and an exposure period for acquiring a low-sensitivity signal. Therefore, the timing of the exposure start and the length of the exposure period cannot be matched between the two signals of high sensitivity and low sensitivity, and therefore there is a risk of image quality degradation. Furthermore, two reset operations are required corresponding to the two signals. [Means for solving the problem]

[0005] According to certain non-limiting exemplary embodiments of the present disclosure, the following is provided:

[0006] an imaging device comprising: a first imaging cell including a first photoelectric conversion unit; and a first signal detection circuit that detects an electrical signal generated in the first photoelectric conversion unit, the first signal detection circuit including: a first transistor, one of a source and a drain electrically connected to the first photoelectric conversion unit, a first capacitive element, one end of which is electrically connected to the other of the source and the drain of the first transistor and the other end of which is applied with a reference potential, and a second transistor, the gate of which is electrically connected to the first photoelectric conversion unit, the first imaging cell sequentially outputting, within one frame period, a first image signal that is a signal when the first transistor is in an off state, and a second image signal that is a signal when the first transistor is in an on state.

[0007] The generic or specific aspects may be realized as an element, a device, a module, a system, an integrated circuit, a method, or a computer program. Also, the generic or specific aspects may be realized by any combination of an element, a device, a module, a system, an integrated circuit, a method, and a computer program.

[0008] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and / or advantages may be achieved by various embodiments or features disclosed in the specification and drawings. These are provided individually and you do not need all of them to obtain one or more of them. Effect of the Invention

[0009] According to an embodiment of the present disclosure, an imaging device capable of capturing images in a wide dynamic range is provided, despite having a simpler configuration. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic circuit diagram showing an exemplary circuit configuration of the imaging cell 10a. [Diagram 3] FIG. 3 is a timing chart for explaining a typical example of a signal read operation in the first embodiment. [Figure 4] FIG. 4 is a diagram showing a circuit configuration of a modified example of the imaging device according to the first embodiment. [Diagram 5] FIG. 5 is a block diagram showing an exemplary configuration of an imaging device according to the second embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic circuit diagram showing an exemplary circuit configuration of the imaging cell 10c shown in FIG. [Figure 7] FIG. 7 is a diagram showing a typical example of the circuit configuration of the sensitivity switching register 90. As shown in FIG. [Figure 8] FIG. 8 is a diagram for explaining the switching of sensitivity in the imaging cell 10c in response to a change in voltage of the charge storage node FD due to exposure to light. [Figure 9] FIG. 9 is a diagram for explaining the switching of sensitivity in the imaging cell 10c in response to a change in voltage of the charge storage node FD due to exposure. [Figure 10]FIG. 10 is a timing chart for explaining a typical example of a signal read operation in the second embodiment. [Figure 11] FIG. 11 is a timing chart showing an example of a change in voltage BS00 applied to the gate of the sensitivity switching transistor 36 of the imaging cell 10c in the 0th row, 0th column, and a change in voltage BS01 applied to the gate of the sensitivity switching transistor 36 of the imaging cell 10c in the 0th row, 1st column. [Figure 12] FIG. 12 is a schematic circuit diagram showing a modified example of the imaging device according to the second embodiment. [Figure 13] FIG. 13 is a schematic circuit diagram showing a modified example of the imaging cell. [Figure 14] FIG. 14 is a schematic circuit diagram showing another modified example of the imaging cell. [Figure 15] FIG. 15 is a schematic circuit diagram showing still another modified example of the imaging cell. [Figure 16] FIG. 16 is a block diagram showing an example configuration of a camera system including an imaging device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] An outline of one aspect of the present disclosure is as follows.

[0012] [Item 1] a first imaging cell including a first photoelectric conversion unit and a first signal detection circuit that detects an electrical signal generated by the first photoelectric conversion unit; the first signal detection circuit includes a first transistor, one of a source and a drain of which is electrically connected to the first photoelectric conversion unit, a first capacitance element, one end of which is electrically connected to the other of the source and the drain of the first transistor and the other end of which is applied with a reference potential, and a second transistor, a gate of which is electrically connected to the first photoelectric conversion unit; An imaging device, wherein a first imaging cell sequentially outputs, within one frame period, a first image signal which is a signal when the first transistor is in an off state, and a second image signal which is a signal when the first transistor is in an on state.

[0013] According to the configuration of item 1, while exposing each imaging cell once in one frame period, it is possible to obtain a first image signal and a second image signal individually from each imaging cell. Since the exposure period for obtaining the first image signal and the exposure period for obtaining the second image signal in each imaging cell are common, it is possible to form a wide dynamic range image with suppressed degradation of image quality.

[0014] [Item 2] a plurality of first imaging cells each including a first photoelectric conversion unit and a first signal detection circuit that detects an electrical signal generated in the first photoelectric conversion unit; the first signal detection circuit includes a first transistor, one of a source and a drain electrically connected to the first photoelectric conversion unit, a first capacitance element, one end of which is electrically connected to the other of the source and drain of the first transistor and the other end of which is applied with a reference potential, and a second transistor, a gate of which is connected to the first photoelectric conversion unit; An imaging device, wherein, during one frame period, some of a plurality of first imaging cells output a first image signal which is a signal when a first transistor is in an off state, and one or more of the first imaging cells other than the some of the first imaging cells output a second image signal which is a signal when the first transistor is in an on state when the some of the first imaging cells output the first image signal.

[0015] According to the configuration of item 2, since either the first image signal or the second image signal is selectively read out from each imaging cell in one frame period, faster operation is possible. Also, the length of the exposure period for acquiring the first image signal can be made the same as that of the exposure period for acquiring the second image signal.

[0016] [Item 3] a second imaging cell including a second photoelectric conversion unit and a second signal detection circuit that detects an electrical signal generated in the second photoelectric conversion unit; The imaging device described in item 1, wherein the second signal detection circuit includes a third capacitive element having one end electrically connected to the second photoelectric conversion unit and the other end to which a reference potential is applied, and a third transistor having a gate electrically connected to the second photoelectric conversion unit.

[0017] [Item 4] the first signal detection circuit includes a second capacitance element having one end electrically connected to the first photoelectric conversion unit and the other end electrically connected to the other of the source and drain of the first transistor; 4. The imaging device according to any one of items 1 to 3, wherein the capacitance value of the second capacitance element is smaller than the capacitance value of the first capacitance element.

[0018] According to the configuration of item 4, more effective noise cancellation can be performed.

[0019] [Item 5] 5. The imaging device according to any one of items 1 to 4, further comprising a first feedback circuit that forms a feedback path for negatively feeding back the electrical signal generated in the first photoelectric conversion unit.

[0020] According to the configuration of item 5, it is possible to reduce kTC noise.

[0021] [Item 6] one of a source and a drain of the first transistor is connected to the first photoelectric conversion unit; 6. The imaging device according to item 5, wherein the first feedback circuit negatively feeds back the electrical signal generated in the first photoelectric conversion unit to the other of the source and drain of the first transistor.

[0022] According to the configuration of item 6, similarly to the configuration of item 4, the effect of reducing kTC noise can be obtained.

[0023] [Item 7] a second imaging cell including a second photoelectric conversion unit and a second signal detection circuit that detects an electrical signal generated by the second photoelectric conversion unit; a second feedback circuit that forms a feedback path for negatively feeding back the electrical signal generated by the second photoelectric conversion unit; Further equipped with The imaging device described in item 5 or 6, wherein the second signal detection circuit includes a third capacitive element having one end electrically connected to the second photoelectric conversion unit and the other end to which a reference potential is applied, and a third transistor having a gate connected to the second photoelectric conversion unit.

[0024] According to the configuration of item 7, it is possible to provide an imaging device that can handle a wider dynamic range.

[0025] [Item 8] 8. The imaging device according to item 7, wherein the second signal detection circuit does not include a transistor connected between the second photoelectric conversion unit and one end of the third capacitive element.

[0026] [Item 9] a first imaging cell including a first photoelectric conversion unit and a first signal detection circuit that detects an electrical signal generated by the first photoelectric conversion unit; the first signal detection circuit includes a first transistor, one of a source and a drain electrically connected to the first photoelectric conversion unit, a first capacitance element, one end of which is electrically connected to the other of the source and drain of the first transistor and the other end of which is applied with a reference potential, and a second transistor, a gate of which is connected to the first photoelectric conversion unit; an imaging device in which, within one frame period, a first imaging cell selectively outputs either a first image signal, which is a signal when the first transistor is in an off state, or a second image signal, which is a signal when the first transistor is in an off state, based on the magnitude of the electrical signal generated in the first photoelectric conversion unit.

[0027] [Item 10] a sensitivity switching circuit electrically connected to the first signal detection circuit, the first signal detection circuit further includes a third transistor having a gate connected to the sensitivity switching circuit and connected in series to the first transistor; 10. The imaging device according to item 9, wherein the sensitivity switching circuit turns the third transistor on or off based on the magnitude of the signal detected when the first transistor is off.

[0028] [Item 11] Item 11. The imaging device according to item 10, wherein the sensitivity switching circuit includes a comparator that compares the magnitude of the signal detected when the first transistor is in an off state with the magnitude of a reference signal.

[0029] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of components, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as there is no contradiction. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. In the following description, components having substantially the same functions are indicated by common reference symbols, and descriptions may be omitted.

[0030] (First embodiment) Fig. 1 shows an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. The imaging device 100A shown in Fig. 1 has a pixel array PA including a plurality of imaging cells 10a, and a peripheral circuit. The imaging cells 10a are arranged two-dimensionally on a semiconductor substrate, for example, to form an imaging region. In this example, the imaging cells 10a are arranged in a matrix of m rows and n columns.

[0031] In the illustrated example, the center of each imaging cell 10a is located on a lattice point of a square lattice. Of course, the arrangement of the imaging cells 10a is not limited to the illustrated example, and for example, the imaging cells 10a may be arranged so that each center is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. The imaging cells 10a may be arranged one-dimensionally. That is, the imaging cells 10a may be arranged in m rows and 1 column or 1 row and n columns. In this case, the imaging device 100A can be used as a line sensor.

[0032] 1, the peripheral circuits include a row scanning circuit 80, a column circuit 82, a signal processing circuit 84, an output circuit 86, and a control circuit 88. The peripheral circuits may be arranged on a semiconductor substrate on which the pixel array PA is formed, or a part of the peripheral circuits may be arranged on another substrate.

[0033] The row scanning circuit 80 is connected to the reset control line R i and the feedback control line F i The reset control line R i and the feedback control line F i is provided corresponding to each row of the pixel array PA. That is, among the multiple imaging cells 10a, one or more imaging cells 10a belonging to the i-th row are connected to the reset control line R i and the feedback control line F i Here, i=0 to m-1, and m is an integer of 1 or more.

[0034] The row scanning circuit 80 has connections to address control lines not shown in FIG. i and the feedback control line F i Similarly, a row scanning circuit 80 is provided corresponding to each row of the pixel array PA and is connected to one or more imaging cells 10a belonging to the i-th row. The row scanning circuit 80 applies a predetermined voltage to the address control line to select the imaging cells 10a row by row, reads out the signal voltage, and performs a reset operation, which will be described later. The row scanning circuit 80 is also called a vertical scanning circuit.

[0035] The column circuit 82 has output signal lines S j Connect with Here, j=0 to n-1, and n is an integer equal to or greater than 1. Of the multiple imaging cells 10a, one or more imaging cells 10a belonging to the j-th column have an output signal line S j Connected to The output signals from the imaging cells 10a selected row by row by the row scanning circuit 80 are transmitted to the output signal line S jThe column circuit 82 reads out the image from the imaging cell 10a. The extracted output signal is subjected to noise suppression signal processing, typically correlated double sampling, analog-to-digital conversion (AD conversion), and other processes.

[0036] The signal processing circuit 84 performs various processes on the image signal obtained from the imaging cell 10a. In this specification, the "image signal" is the signal output from the output signal line S j Among the signals read out through the This refers to an output signal used to form an image. As will be described in detail later, in the first embodiment, readout of an image signal from an imaging cell 10a in a high sensitivity state (hereinafter, sometimes referred to as a "high sensitivity signal") and readout of an image signal from an imaging cell 10a in a low sensitivity state (hereinafter, sometimes referred to as a "low sensitivity signal") are executed. The signal processing circuit 84 forms a wide dynamic range image based on these high sensitivity signal and low sensitivity signal. The output of the signal processing circuit 84 is read out to the outside of the imaging device 100A via the output circuit 86.

[0037] The control circuit 88 receives command data, a clock, and the like provided from, for example, an external source of the imaging device 100A, and controls the entire imaging device 100A. The control circuit 88 typically has a timing generator, and supplies drive signals to the row scanning circuit 80, the column circuit 82, and the like.

[0038] Fig. 2 shows an exemplary circuit configuration of the imaging cell 10a. Fig. 2 shows the imaging cell 10a in the j-th column belonging to the i-th row of the pixel array PA. As shown in Fig. 2, the imaging cell 10a has a photoelectric conversion unit 11 and a signal detection circuit SC that detects an electrical signal generated by the photoelectric conversion unit 11.

[0039] The signal detection circuit SC has a first capacitive element 21, a reset transistor 24, and a signal detection transistor 26. In this example, the signal detection circuit SC includes an address transistor 28. Typically, the reset transistor 24, the signal detection transistor 26, and the address transistor 28 are field effect transistors (FETs) formed on a semiconductor substrate. In the following, unless otherwise specified, an example in which an N-channel MOS is used as the transistor will be described. Note that the semiconductor substrate is not limited to a substrate whose entirety is a semiconductor, and may be an insulating substrate having a semiconductor layer provided on the surface on the side where the imaging region is formed.

[0040] The photoelectric conversion unit 11 receives the incidence of light and generates a signal according to the illuminance. Here, as the photoelectric conversion unit 11, a structure in which a photoelectric conversion layer 11y is sandwiched between a pixel electrode 11x and a counter electrode 11z is exemplified. In this case, typically, an interlayer insulating layer is provided on a semiconductor substrate on which the above-mentioned reset transistor 24 and the like are formed, and the photoelectric conversion unit 11 is disposed on this interlayer insulating layer. That is, the imaging device 100A may be a so-called stacked type imaging device having a photoelectric conversion layer on the upper part of a semiconductor substrate. In the following, an example in which the imaging device 100A is a stacked type imaging device will be described. Of course, the photoelectric conversion unit 11 may be a photodiode or the like formed on a semiconductor substrate. In that case, a transfer transistor may be provided between the photoelectric conversion unit 11 and a charge accumulation node FD described later. After the charge generated in the photoelectric conversion unit 11 is transferred to the charge accumulation node FD via the transfer transistor, the operation described in each of the following embodiments can be applied.

[0041] In the photoelectric conversion unit 11, the pixel electrode 11x is disposed on an interlayer insulating layer that covers the above-mentioned reset transistor 24 and the like. The pixel electrode 11x is provided for each imaging cell 10a. Typically, the pixel electrode 11x of each imaging cell 10a is spatially separated from the pixel electrode 11x of the other adjacent imaging cells 10a, and is thereby electrically isolated from the pixel electrodes 11x of the other imaging cells 10a. The pixel electrodes 11x are formed of metals such as aluminum and copper, metal nitrides, polysilicon doped with impurities to provide electrical conductivity, or the like.

[0042] The photoelectric conversion layer 11y is formed of an organic material or an inorganic material such as amorphous silicon, and generates positive and negative charges (hole-electron pairs) by photoelectric conversion. Typically, the photoelectric conversion layer 11y is formed across the multiple imaging cells 10a. The photoelectric conversion layer 11y may include a layer made of an organic material and a layer made of an inorganic material.

[0043] The counter electrode 11z, which faces the pixel electrode 11x via the photoelectric conversion layer 11y, is an electrode made of a transparent conductive material such as ITO, and is disposed on the light-incident side of the two main surfaces of the photoelectric conversion layer 11y. Typically, the counter electrode 11z is formed across the multiple imaging cells 10a, similar to the photoelectric conversion layer 11y.

[0044] When the imaging device 100A is in operation, a predetermined voltage Vp is applied to the counter electrode 11z. By forming the counter electrode 11z across the multiple imaging cells 10a, the voltage Vp can be applied to the multiple imaging cells 10a at once. A different voltage may be supplied to each pixel block consisting of a. By supplying a different voltage to each pixel block, the sensitivity of each pixel block can be made different. The voltage Vp may be supplied from the row scanning circuit 80 (see FIG. 1) or from another power supply circuit.

[0045] By applying a voltage Vp to the counter electrode 11z, one of holes and electrons generated in the photoelectric conversion layer 11y can be collected by the pixel electrode 11x. When holes are used as signal charges, the potential of the counter electrode 11z may be set higher than that of the pixel electrode 11x. When holes are used as signal charges, for example, a voltage Vp of about 10V is applied to the counter electrode 11z. In the following, holes are exemplified as signal charges. Electrons may also be used as signal charges.

[0046] The photoelectric conversion unit 11 and the signal detection circuit SC are electrically connected by a wiring layer provided in an interlayer insulating layer. As shown in FIG. 2, the pixel electrode 11x and the gate of the signal detection transistor 26 are connected here. The signal charge collected by the pixel electrode 11x is accumulated in a charge accumulation node (also called a "floating diffusion node") FD, which is a node between the pixel electrode 11x and the gate of the signal detection transistor 26. Therefore, a voltage according to the amount of signal charge accumulated in the charge accumulation node FD is applied to the gate of the signal detection transistor 26.

[0047] The source of the signal detection transistor 26 is connected to the output signal line S via an address transistor 28. j The output signal line S j is a constant current source CC j The drain of the signal detection transistor 26 is connected to the power supply The signal detection transistor 26 and the output signal line S j A constant current source CC connected to j A source follower circuit is formed by these. When the imaging device 100A is in operation, the signal detection transistor 26 amplifies the voltage applied to the gate by receiving a power supply voltage VDD (e.g., about 3.3 V) at its drain. In other words, the signal detection transistor 26 amplifies the signal generated by the photoelectric conversion unit 11.

[0048] The voltage amplified by the signal detection transistor 26 is selectively read out as a signal voltage via an address transistor 28. As shown in the figure, the gate of the address transistor 28 is connected to an address control line A i Connected to Dress control line A i are typically connected to a row scanning circuit 80 (see FIG. 1) The scanning circuit 80 detects the address control line A i The address transition is controlled by controlling the voltage AD applied to The star 28 can be controlled to be on and off.

[0049] As described above, the signal detection circuit SC has the first capacitive element 21 and the reset transistor 24. One of the source and drain (typically the drain) of the reset transistor 24 is connected to the charge storage node FD, and the other of the source and drain is connected to one electrode of the first capacitive element 21. Hereinafter, for convenience of explanation, the node between the reset transistor 24 and the first capacitive element 21 may be referred to as a "reset drain node RD."

[0050] During operation of the imaging device 100A, a reference potential VR (e.g., 0 V) ​​is applied to the other electrode of the first capacitive element 21. The reference potential VR may be applied by the row scanning circuit 80 (see FIG. 1) or by another power supply circuit.

[0051] The first capacitance element 21 has a relatively large capacitance value C1. The first capacitance element 21 may have a MIS (metal-insulator-semiconductor) structure or a MIM (metal-insulator By adopting the MIM structure, it is easy to obtain a larger capacitance value. In this specification, a "capacitor" means a capacitor having an insulating layer between electrodes. The term "electrode" refers to a structure in which a dielectric such as an insulating film is sandwiched between the electrodes. In this specification, the term "electrode" is not limited to an electrode made of metal, but is interpreted broadly to include a polysilicon layer and the like. In this specification, the term "electrode" may be a part of a semiconductor substrate.

[0052] 2, the signal detection circuit SC further includes a second capacitive element 22 connected in parallel to the reset transistor 24. From the viewpoint of individually acquiring a low sensitivity signal and a high sensitivity signal while limiting the number of exposures to one, the second capacitive element 22 is not essential. However, by connecting the second capacitive element 22 in parallel to the reset transistor 24, the effect of noise cancellation, which will be described later, can be improved, so from the viewpoint of noise reduction, it is advantageous for the signal detection circuit SC to include the second capacitive element 22.

[0053] The capacitance value C2 of the second capacitive element 22 is smaller than the capacitance value C1 of the first capacitive element 21. The capacitance value C2 is typically sufficiently smaller than the capacitance value C1. The ratio (C2 / C1) of the capacitance value C2 of the second capacitive element 22 to the capacitance value C1 of the first capacitive element 21 may be, for example, about 1 / 10. The structure of the second capacitive element 22 may be either an MIS structure or an MIM structure. The structure of the first capacitive element 21 and the structure of the second capacitive element 22 do not need to be the same.

[0054] The gate of the reset transistor 24 is connected to a reset control line R i Therefore, the row scanning circuit 80 is connected to the reset control line R i By controlling the voltage RST applied to the reset control line R i The reset signal of the imaging cell 10a having a connection to the The reset transistor 24 can be switched on and off. By turning off the reset transistor 24, a capacitance circuit in which the first capacitance element 21 and the second capacitance element 22 are connected in series can be formed between the charge storage node FD and the reference potential VR in the imaging cell 10a. As described later, in the first embodiment, during one frame period, a signal is read out with the reset transistor 24 in an off state, and a signal is read out with the reset transistor 24 in an on state. This makes it possible to obtain a high sensitivity signal and a low sensitivity signal in sequence. In this specification, "sequentially" means not simultaneously.

[0055] In this example, the imaging device 100A includes a feedback circuit FC. The feedback circuit FC is connected to an output signal line S j In response to the above, an inversion amplifier is provided for each example of the pixel array PA. breadboard 32 j Includes an inverting amplifier 32 j may be part of the peripheral circuitry described above.

[0056] As shown, an inverting amplifier 32 j The inverting input terminal of Output signal line S having connection to module 10a j On the other hand, the non-inverting input terminal is connected to the During operation of the device 100A, a predetermined voltage (for example, 1 V or a positive voltage close to 1 V) Vref is supplied. This voltage Vref is used as a reference voltage for resetting. j The output terminal of the feedback line L j is connected to.

[0057] In the illustrated example, the imaging cell 10a has a feedback transistor 34, one of the source and drain of which is connected to a reset drain node RD. j is connected to the other of the source and drain of the feedback transistor 34. As shown, the gate of the feedback transistor 34 is connected to a feedback control line F connected to the row scanning circuit 80. i Thus, the row scanning circuit 80 has a connection to the Feedback control line F i By controlling the voltage FB applied to the feedback transistor 34 can be switched on and off. i Marked The applied voltage FB is not limited to high and low level voltages, but may be a ramp voltage. A "ramp voltage" can include a ramp voltage that generally increases or generally decreases over time. The term "ramp voltage" is not limited to a voltage that increases or decreases linearly, but may be a voltage that has a step-like waveform, a voltage that increases or decreases with oscillation, or the like.

[0058] By turning on the feedback transistor 34 and the address transistor 28, a feedback path can be formed that negatively feeds back the electrical signal generated in the photoelectric conversion unit 11. In other words, the feedback circuit FC is a circuit that negatively feeds back the electrical signal generated in the photoelectric conversion unit 11 to the source or drain of the reset transistor 24 that is not connected to the charge storage node FD. The feedback transistor 34 and the inverting amplifier 32 j forms part of the feedback path in the feedback circuit FC. breadboard 32 j may be called a feedback amplifier.

[0059] By forming a feedback path, it is possible to perform noise cancellation, which will be described later. In this example, a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC includes a band control circuit 40 having a feedback transistor 34, a first capacitive element 21, and a second capacitive element 22 as a part thereof. In noise cancellation, the first capacitive element 21 and the feedback transistor 34 function as an RC filter circuit. The feedback path is formed by a feedback circuit FC that negatively feeds back the output of the signal detection circuit SC. j The imaging cells 10a are sequentially connected to each other. In other words, noise cancellation is performed on a row-by-row basis.

[0060] (Signal Readout Operation in the First Embodiment) 3 is a timing chart for explaining a typical example of a signal read operation in the first embodiment. In FIG. 3, RSTps indicates a voltage pulse that specifies the timing of starting resetting in each row of the pixel array PA. AD i ,RST i and F.B. i are respectively , the address control line A of the i-th row i , reset control line R i and the feedback control line F i Marked The figure shows the change in the voltage applied to the sensor. The operation described below is an example of applying a so-called rolling shutter, which performs exposure and signal readout on a row-by-row basis. In FIG. 3, the shaded rectangles HR, LR, and RR indicate the periods for reading out the high-sensitivity signal, low-sensitivity signal, and reset signal, respectively. The double-headed arrow NRC indicates the period for resetting and noise cancellation after acquiring the signal. Details of resetting and noise cancellation will be described later.

[0061] Here, we focus on row 0. Prior to exposure and signal readout, the charge in the charge storage node FD is reset by a reset operation, which will be described later. At this time, the kTC noise generated during the reset is reduced by executing noise cancellation, which will be described later. After the reset and noise cancellation, exposure begins. During the exposure period of row 0, AD0, RST0, and FB0 are all at low level. That is, The address transistor 28, the reset transistor 24, and the feedback transistor 34 of the imaging cell 10a are all in an off state. Note that, to avoid complicating the drawing, FIG. 3 does not show the reset and noise cancellation before exposure, and the subsequent exposure period.

[0062] By the exposure, a signal charge (here, holes) according to the illuminance is accumulated in a signal charge accumulation region (hereinafter, sometimes referred to as a "charge accumulation region") including the charge accumulation node FD. After the exposure period ends, the row scanning circuit 80 changes AD0 to a high level, thereby When the address transistor 28 is turned on, a signal corresponding to the amount of accumulated charge is output to the output signal line S via the signal detection transistor 26. j Read out to can be.

[0063] In this example, first, a signal is read out with the reset transistor 24 in an off state. When the reset transistor 24 is off, a capacitance circuit in which the first capacitance element 21 and the second capacitance element 22 are connected in series is formed between the photoelectric conversion unit 11 and the reference potential. If the capacitance value of the parasitic capacitance of the charge storage node FD is Cfd, the capacitance value of the entire charge storage region when the reset transistor 24 is off is expressed as (Cfd+(C1C2) / (C1+C2)). As described above, the capacitance value C2 of the second capacitance element 22 is typically sufficiently smaller than the capacitance value C1 of the first capacitance element 21. Therefore, the capacitance value of the entire signal charge storage region when the reset transistor 24 is off is approximately (Cfd+C2).

[0064] In the first embodiment, the image signal acquired through the signal detection transistor 26 when the reset transistor 24 is in an off state corresponds to the high sensitivity signal described above. The readout period of the image signal may include a period for AD conversion by the column circuit 82 (see FIG. 1). Image data (first image data) corresponding to the high sensitivity signal is temporarily stored in a buffer memory. The buffer memory is disposed, for example, in the column circuit 82 or the signal processing circuit 84 described above.

[0065] In the first embodiment, after reading out the image signal with the reset transistor 24 in the off state, the image signal is further read out with the reset transistor 24 in the on state. After reading out the image signal with the reset transistor 24 in the off state, the row scanning circuit 80 changes RST0 to a high level to turn on the reset transistor 24. When the reset transistor 24 is turned on, the first capacitive element 21 is connected to the photoelectric conversion unit 11 via the reset transistor 24. When the first capacitive element 21 is connected to the photoelectric conversion unit 11 via the reset transistor 24, the capacitance value of the entire charge accumulation region increases from (Cfd+C2) to (Cfd+C1).

[0066] After the reset transistor 24 is turned on, the image signal is read out. At this time, the image signal acquired through the signal detection transistor 26 corresponds to the above-mentioned low sensitivity signal. As can be seen from FIG. 2, the above-mentioned high sensitivity signal is read out non-destructively without taking out the signal charge itself from the charge storage node FD. Note that, although the signal charge is accumulated even during the readout of the high sensitivity signal, the time required for reading out the image signal is sufficiently short compared to the entire exposure period. Therefore, it can be said that the length of the exposure period is the same between the high sensitivity signal and the low sensitivity signal. Therefore, there is almost no change in the amount of charge accumulated in the entire charge storage region between the readout of the high sensitivity signal and the readout of the low sensitivity signal.

[0067] Here, the capacitance value of the entire charge storage region when the low sensitivity signal is read out is larger than that when the high sensitivity signal is read out. Therefore, the gate voltage of the signal detection transistor 26 is lowered, and the output signal level is lowered even though the charge storage amount is the same. In other words, a state similar to that of photographing with the sensitivity of the imaging cell 10a lowered is realized. For example, if (Cfd+C2):(Cfd+C1)=1:10, a sensitivity ratio of 10:1 can be realized between the state in which the reset transistor 24 is off (corresponding to a high sensitivity state) and the state in which the reset transistor 24 is on (corresponding to a low sensitivity state).

[0068] After the low-sensitivity signal is read out with the reset transistor 24 on, reset and noise cancellation are performed again. In this example, the reset transistor 24 and the feedback transistor 34 are turned on by changing RST0 and FB0 to high level, and then the reset transistor 24 is turned off, thereby performing reset. In the first embodiment, the reset transistor 24 has a function of switching whether the high-sensitivity signal or the low-sensitivity signal is to be output from the imaging cell 10a, and a function of starting the reset of the charge storage node FD.

[0069] In this example, following the turning off of the reset transistor 24, the voltage FB0 is set to a high level. After reset and noise cancellation, the output signal line S j By reading out the voltage of A reset signal is obtained. The readout period of the reset signal may include a period for AD conversion. The reset signal is used for correlated double sampling by the column circuit 82 (see FIG. 1). The correlated double sampling may be performed by the signal processing circuit 84.

[0070] As shown in Fig. 3, the above-mentioned series of operations is executed row by row. One frame period ends when the readout of the reset signal in the last row is completed. In this specification, "one frame period" is defined as the period from the readout of the high sensitivity signal or low sensitivity signal in the first row (here, row 0) to the end of the readout of the reset signal in the last row (here, row (m-1)).

[0071] In the example shown in FIG. 3, after the low-sensitivity signal is read out, the reset transistor 24 is turned off once and then turned on again. That is, in this example, control is executed such that the reset transistor 24 in each of the imaging cells 10a is turned on twice (or off twice) in one frame period. In this manner, control may be executed such that the reset transistor 24 in each of the imaging cells 10a is turned on or off at least twice in one frame period. Alternatively, after the low-sensitivity signal is read out, resetting may be started by turning on the feedback transistor 34 without turning off the reset transistor 24. The reset transistor 24 and the feedback transistor 34 are turned on and off based on the control of, for example, the above-mentioned control circuit 88 (see FIG. 1).

[0072] By synthesizing image data (first image data) corresponding to a high sensitivity signal and image data (second image data) corresponding to a low sensitivity signal, it is possible to form an image (wide dynamic range image) in which whiteout and blackout are suppressed. The formation of such an image is called "high dynamic range synthesis". As a specific method of high dynamic range synthesis, a known method can be applied. The synthesis of the first image data and the second image data is performed, for example, by the signal processing circuit 84. The synthesis of the first image data and the second image data may be performed on a row-by-row basis or on a frame-by-frame basis. By performing synthesis on a row-by-row basis, the time difference between the readout of the high sensitivity signal and the readout of the low sensitivity signal can be suppressed to the length of a 1H period (the time required for scanning one row).

[0073] Thus, in the first embodiment, each of the imaging cells 10a sequentially outputs a high sensitivity signal and a low sensitivity signal in one frame period. As is clear from the above description, according to the first embodiment, while each imaging cell 10a is exposed once in one frame period, a high sensitivity signal and a low sensitivity signal can be obtained individually from each imaging cell 10a. In other words, there is no need to set a total of two exposure periods for obtaining a high sensitivity signal and a low sensitivity signal, respectively. Therefore, the occurrence of deterioration in image quality in a wide dynamic range image is suppressed. In addition, the operation can be made faster. There is no need to perform a reset operation every time a high sensitivity signal and a low sensitivity signal are obtained.

[0074] Furthermore, for each of the imaging cells 10a in the same row, the timing of the start of the exposure period for acquiring the high-sensitivity signal and the timing of the start of the exposure period for acquiring the low-sensitivity signal are the same, and the lengths of these exposure periods are substantially the same. Therefore, according to the first embodiment, it is possible to ensure synchronicity between the image data corresponding to the high-sensitivity signal and the image data corresponding to the low-sensitivity signal.

[0075] (Reset and Noise Cancellation) Here, the details of the reset and noise cancellation operations will be described with reference to Figures 2 and 3. As described above, the reset is started by turning on the reset transistor 24 and the feedback transistor 34. As can be seen from Figure 2, by turning on the reset transistor 24 and the feedback transistor 34, the charge storage node FD and the feedback line L j The reset transistor 24 and The output signal line S is connected to the output signal line S via a feedback transistor 34 to form a feedback path for feeding back (here, negative feedback) the signal of the photoelectric conversion unit 11. The feedback transistor 34 has a function of switching whether or not the feedback path is formed. The formation of the feedback path is controlled by the output signal line S j Among the imaging cells 10a connected to the address control line A iVoltage A-D i High level The image pickup device 10 performs the image pickup process on the imaging cells 10a in the selected row by selecting the row as the "selected row".

[0076] Charge storage node FD and feedback line L j The output is electrically connected to Signal line S j The voltage of the inverting amplifier 32 j The voltage Vref converges to the voltage Vref applied to the non-inverting input terminal of the inverter 1. The voltage Vref may be any voltage between the power supply voltage (for example, 3.3 V) and the ground (0 V).

[0077] Next, the reset transistor 24 is turned off. By turning off the reset transistor 24, kTC noise is generated. Therefore, the kTC noise is added to the voltage of the charge storage node FD after reset.

[0078] 2, while the feedback transistor 34 is on, a feedback path including the charge storage node FD, the signal detection transistor 26, the feedback transistor 34, and the second capacitance element 22 is continuously formed. When the feedback path is formed (which may be said to be when the feedback transistor 34 is not off), the signal output by the feedback transistor 34 is attenuated by an attenuation circuit formed by the second capacitance element 22 and the parasitic capacitance of the charge storage node FD. The attenuation rate B at this time is expressed as B=C2 / (C2+Cfd). Therefore, if the gain of the feedback circuit FC is A, the kTC noise generated by turning off the reset transistor 24 is suppressed to 1 / (1+A×B) times.

[0079] In this example, the output signal line S j The voltage of is input to the inverting amplifier 32 j The voltage Vref applied to the non-inverting input terminal of the output signal line S j By keeping the voltage close to the target voltage Vref after noise cancellation, the kTC noise can be canceled in a relatively short time.

[0080] Here, the feedback control line F immediately after the reset transistor 24 is turned off i The voltage level of is high. Therefore, the reset transistor 24 is turned off. The operating band of the feedback transistor 34 immediately after the switching is turned on is relatively wide. If the operating band of the feedback transistor 34 is wide, it is possible to suppress noise at high speed.

[0081] Further, after the reset transistor 24 is turned off, the feedback control line F i The voltage level of the feedback is gradually decreased from high to low. The feedback control line F is connected across the threshold voltage of the transistor 34. i The potential of When the feedback control line F is gradually decreased from a high level to a low level, the feedback transistor 34 is gradually changed from an on state to an off state. i Apply to Voltage FB i As the resistance of feedback transistor 34 decreases, When the resistance of the feedback transistor 34 increases, The operating band of the feedback transistor 34 is narrowed, and the frequency range of the signal being fed back is narrowed. By making the operating band of the feedback transistor 34 sufficiently lower than the operating band of the signal detection transistor 26, the noise suppression effect can be improved.

[0082] Feedback control line F i The voltage applied to FB iWhen the feedback transistor 34 is turned off, the feedback path is eliminated. If the operating band of the feedback transistor 34 is sufficiently lower than the operating band of the signal detection transistor 26, the thermal noise generated in the feedback transistor 34 is reduced by the feedback circuit FC to 1 / (1+A×B) 1 / 2 The feedback loop is suppressed by 2 times. By turning off the feedback transistor 34 in a state in which the operating band of the feedback transistor 34 is lower than the operating band of the signal detection transistor 26, it is possible to reduce the kTC noise remaining in the charge storage node FD.

[0083] In this way, by providing the feedback circuit FC, the kTC noise can be reduced. Therefore, a wide dynamic range image in which the influence of noise is suppressed can be obtained. In addition, the first capacitive element 21 can be effectively used not only for obtaining two signals (high sensitivity signal and low sensitivity signal) corresponding to different sensitivity states, but also for noise cancellation. As will be easily understood by those skilled in the art, even with a circuit configuration in which the second capacitive element 22 is omitted, the switching between the high sensitivity signal and the low sensitivity signal is possible. However, by using the second capacitive element 22 having a sufficiently small capacitance value, a larger value can be obtained as the attenuation rate B, so that the noise can be cancelled more effectively.

[0084] (Modification of the first embodiment) FIG. 4 shows a modified example of the imaging device according to the first embodiment. The imaging device 100B shown in FIG. 4 differs from the imaging device 100A described with reference to FIGS. 1 to 3 in that the imaging device 100B has, in addition to the imaging cell 10a, a second imaging cell 10b having a lower sensitivity than the imaging cell 10a. As described below, by using the imaging cells 10a and 10b, it becomes easier to capture a scene with a wider dynamic range. Hereinafter, the imaging cell 10b will be referred to as the low-sensitivity cell 10b.

[0085] In the configuration illustrated in FIG. 4, the imaging cell 10a and the low-sensitivity cell 10b are adjacent to each other along the row direction. In this specification, the row direction means the direction in which the rows extend, and the column direction means the direction in which the columns extend. That is, for example, in FIG. 1, the vertical direction on the paper surface is the column direction, and the horizontal direction on the paper surface is the row direction. In this example, the imaging cell 10a and the low-sensitivity cell 10b adjacent to each other in the same row form a cell pair 10P. A plurality of cell pairs 10P are arranged in a matrix on a semiconductor substrate, for example, to form an imaging region in the imaging device 100B. FIG. 4 shows a typical example of a circuit configuration in a cell pair 10P in the j-th column, which is one of the cell pairs 10P belonging to the i-th row of the pixel array PA of the imaging device 100B. The cell pair 10P may be formed by arranging the imaging cell 10a and the low-sensitivity cell 10b adjacent to each other along the column direction.

[0086] The low-sensitivity cell 10b has a configuration similar to that of the imaging cell 10a described above. As shown in Fig. 4, the low-sensitivity cell 10b has a photoelectric conversion unit 12b and a signal detection circuit SCb that detects an electrical signal generated by the photoelectric conversion unit 12b.

[0087] The signal detection circuit SCb has a third capacitance element 23b connected between the photoelectric conversion unit 12b and a reference potential VR, and a signal detection transistor 26b. In the example shown in FIG. 4, the signal detection circuit SCb further includes an address transistor 28b. The address transistor 28b is connected to one of the source or drain (the source here) of the signal detection transistor 26b and an output signal line Sb connected to the column circuit 82 (see FIG. 1). j is connected between

[0088] The photoelectric conversion unit 12b may have a similar configuration to the photoelectric conversion unit 11 in the imaging cell 10a. Here, as the photoelectric conversion unit 12b, a structure in which a photoelectric conversion layer 12y is sandwiched between a pixel electrode 12x and a counter electrode 12z, similar to the photoelectric conversion unit 11, is illustrated.

[0089] The pixel electrode 12x is typically disposed on an interlayer insulating layer that covers the signal detection transistor 26b, the address transistor 28b, and the like. The pixel electrode 12x is spatially separated, and is therefore electrically separated from the other adjacent pixel electrodes 11x and pixel electrodes 12x. On the other hand, typically, the photoelectric conversion layer 12y in the low-sensitivity cell 10b and the photoelectric conversion layer 11y in the imaging cell 10a are each part of a continuous single photoelectric conversion layer. Also, typically, the counter electrode 12z in the low-sensitivity cell 10b and the counter electrode 11z in the imaging cell 10a are each part of a continuous single electrode.

[0090] During operation of the imaging device 100B, a predetermined voltage Vp is applied to the counter electrode 12z of the low-sensitivity cell 10b, similar to the counter electrode 11z of the imaging cell 10a. By applying a predetermined voltage Vp to the counter electrode 12z, one of the positive and negative charges generated in the photoelectric conversion layer 12y can be collected by the pixel electrode 12x. A different voltage may be supplied as the voltage Vp to each pixel block consisting of several cell pairs 10P.

[0091] As shown in Fig. 4, the pixel electrode 12x is connected to the gate of the signal detection transistor 26b. A charge storage node FDb, which is a node between the pixel electrode 12x and the gate of the signal detection transistor 26b, constitutes at least a part of a charge storage region in which signal charges are stored. Therefore, a voltage according to the amount of signal charges stored in the charge storage node FDb is applied to the gate of the signal detection transistor 26b.

[0092] 4, the low-sensitivity cell 10b has a third capacitive element 23b having one electrode connected to a charge storage node FDb. The third capacitive element 23b has a relatively large capacitance value C3, similar to the first capacitive element 21 in the imaging cell 10a. Typically, the capacitance value C3 of the third capacitive element 23b is equal to or greater than the capacitance value C1 of the first capacitive element 21. In this example, no transistor is connected between the photoelectric conversion unit 12b and the third capacitive element 23b.

[0093] A specific value of the capacitance value C3 is set so that the low-sensitivity cell 10b has a lower sensitivity than the imaging cell 10a in a state where the reset transistor 24 is turned on, in other words, in a low-sensitivity state. As described later, in the imaging device 100B, the imaging cell 10a in a state where the reset transistor 24 is turned off, the imaging cell 10a in a state where the reset transistor 24 is turned on, and the low-sensitivity cell 10b are used as the most sensitive cell, the medium sensitivity cell, and the least sensitive cell, respectively. The luminance value of a pixel in the wide dynamic range image is determined based on one selected from three image signals having different sensitivities obtained from these cells.

[0094] The source or drain of the signal detection transistor 26b, which is not connected to the address transistor 28b (here, the drain), is connected to a power supply line (source follower power supply) and receives the power supply voltage VDD during operation of the imaging device 100B. j Constant current source CCb connected to j In other words, the signal detection transistor 26b amplifies the signal generated by the photoelectric conversion unit 12b.

[0095] By turning on the address transistor 28b, the signal amplified by the signal detection transistor 26b is supplied to the constant current source CCb j Output signal line Sb having a connection with j Read out to As shown in the figure, the gate of the address transistor 28b is connected to the address control line Ab i Address control line Ab i is typically connected to the row scanning circuit 80 (see FIG. 1). i By controlling the voltage ADb applied to The low-sensitivity cells 10b can be selected row by row to read out signals. iThe address control transistor 28 of the imaging cell 10a is connected to the gate of the address control transistor 28. Line A i and may be a common signal line.

[0096] 4, the imaging device 100B includes a feedback circuit FCb that forms a feedback path for negatively feeding back an electrical signal generated by the photoelectric conversion unit 12b. As shown in the figure, the feedback circuit FCb has an inverting input terminal connected to the output signal line Sb j Connected to the output Terminal is feedback line Lb i Inverting amplifier 32b connected to j Includes feedback line Lb i A feedback transistor 34b is connected between the charge storage node FDb and the can be.

[0097] The gate of the feedback transistor 34b is connected to the feedback control line Fb i Connected to Feedback control line Fb i The feedback is done by controlling the voltage FBb applied to By turning on transistor 34b, feedback transistor 34b and inverting amplifier 32b j A feedback path can be formed that includes the feed Back control line Fb i is connected to the gate of the feedback transistor 34 of the imaging cell 10a. Connected feedback control line F i and may be a common signal line.

[0098] Feedback control line Fb in resetting and noise cancellation of low-sensitivity cell 10b i The control of the potential of the imaging cell 10a is performed in accordance with the reset and noise suppression described with reference to FIG. Feedback control line F in cancellation i The control of the potential can be almost the same as that of the low sensitivity. The reset in the cell 10b is initiated by turning on the feedback transistor 34b. For example, the feedback control line Fb i By controlling the potential of the feedback transistor 34b It is possible to reduce the kTC noise that occurs when the imaging cell 10a is turned off. Since the sensitivity of the low-sensitivity cell 10b is lower than that of the imaging cell 10a in the low-sensitivity state, the effect of the kTC noise in the low-sensitivity cell 10b is smaller than that of the imaging cell 10a. Therefore, the low-sensitivity cell 10b does not need to have a stronger noise cancellation than the imaging cell 10a. In one embodiment, the feedback circuit FCb may be omitted.

[0099] The timing of signal readout from the low-sensitivity cells 10b may be substantially the same as the timing of signal readout from the imaging cells 10a described with reference to Fig. 3. However, the image signal is read out from each low-sensitivity cell 10b once during one frame period. Since the sensitivity of the low-sensitivity cells 10b is set lower than that of the imaging cells 10a in the low-sensitivity state, for ease of explanation, the image signal obtained from the low-sensitivity cells 10b will be referred to as an ultra-low-sensitivity signal below.

[0100] In the imaging device 100B, three signals, a high sensitivity signal, a low sensitivity signal, and an ultra-low sensitivity signal, can be obtained by one exposure to each of the imaging cell 10a and the low sensitivity cell 10b. That is, although there are only two types of imaging cells, the same effect as when three cells with high sensitivity, low sensitivity, and lower sensitivity are arranged can be obtained. By performing high dynamic range synthesis using the high sensitivity signal, the low sensitivity signal, and the ultra-low sensitivity signal, an image with suppressed white blowout and black crush can be formed even when a scene with a wider dynamic range is photographed.

[0101] For example, the capacitance value of the parasitic capacitance of the charge storage node FDb in the low-sensitivity cell 10b is It is assumed that C3=C1=Cs is equal to the parasitic capacitance Cfd of the charge storage node FD in the cell 10a. In this case, the capacitance value (Cfd+Cs) of the entire charge storage region in the low-sensitivity cell 10b is equal to the capacitance value (Cfd+Cs) of the entire charge storage region of the imaging cell 10a when the reset transistor 24 is on. If the ratio between the area of ​​the pixel electrode 12x of the photoelectric conversion unit 12b of the low-sensitivity cell 10b and the area of ​​the pixel electrode 11x of the photoelectric conversion unit 11 of the imaging cell 10a is 1:10, the sensitivity ratio between the low-sensitivity cell 10b and the imaging cell 10a when the reset transistor 24 is on is approximately 1:10. Here, if the ratio of the capacitance value (Cfd+Cs) of the entire charge storage region when the reset transistor 24 is on to the capacitance value (Cfd+C2) of the entire charge storage region when the reset transistor 24 is off in the imaging cell 10a is 10:1, the sensitivity ratio between the imaging cell 10a when the reset transistor 24 is on and the imaging cell 10a when it is off is approximately 1:10. As a result, a sensitivity ratio of 1:10:100 is obtained between the low-sensitivity cell 10b, the imaging cell 10a when the reset transistor 24 is on, and the imaging cell 10a when the reset transistor 24 is off. Therefore, a wider dynamic range can be realized than when the low-sensitivity cell 10b is not used. Note that, during operation of the imaging device 100B, a sensitivity difference may be provided between the low-sensitivity cell 10b and the imaging cell 10a by supplying different voltages between the counter electrode 12z of the low-sensitivity cell 10b and the counter electrode 11z of the imaging cell 10a.

[0102] 4, the imaging device 100B has a feedback circuit FCb, which can reduce the effect of kTC noise on the ultra-low sensitivity signal. Furthermore, in the imaging device 100B, ultra-low sensitivity image data is acquired by the low sensitivity cell 10b, and high sensitivity image data and low sensitivity image data are acquired by the imaging cell 10a that can perform stronger noise cancellation, so that a low-noise wide dynamic range image can be effectively formed.

[0103] Second embodiment Fig. 5 shows an exemplary configuration of an imaging device according to a second embodiment of the present disclosure. The main difference between an imaging device 100C shown in Fig. 5 and the imaging device 100A shown in Fig. 1 is that a pixel array PA in the imaging device 100C includes a plurality of imaging cells 10c connected to a sensitivity switching register 90. In this example, the sensitivity switching register 90 is disposed in a column circuit 82B.

[0104] Among the multiple imaging cells 10c, one or more imaging cells 10c belonging to the i-th row are connected to a reset control line R i and the feedback control line F i Among the multiple imaging cells 10c, one or more imaging cells 10c belonging to the j-th column are connected to output signal lines S j Here, the jth The one or more imaging cells 10c belonging to the column are further connected to a sensitivity switching line B j As shown in the figure, the sensitivity switching line B j is connected to column circuit 82B.

[0105] As will be described in detail later, in the second embodiment, the sensitivity switching line B j The voltage level of By changing the sensitivity switching line B, it is possible to switch between a high sensitivity signal and a low sensitivity signal to be read out from the corresponding imaging cell 10c. j The voltage level of the output signal line S jThe sensitivity is determined by comparing the voltage read out via the reference voltage with the reference voltage. In other words, the sensitivity when reading out the image signal from each imaging cell 10c is dynamically changed according to the amount of signal charge accumulated by exposure. The image signal read out from each imaging cell 10c in one frame period is either a high sensitivity signal or a low sensitivity signal, and therefore, the length of the exposure period can be made uniform between the high sensitivity signal and the low sensitivity signal in imaging cells 10c belonging to the same row. Also, since either the high sensitivity signal or the low sensitivity signal is selectively read out from each imaging cell 10c in one frame period, the high sensitivity image signal for one frame can be read out. Basically, no synthesis process is required between the image data and one frame of low-sensitivity image data.

[0106] Fig. 6 shows an exemplary circuit configuration of the imaging cell 10c. Schematically, the imaging cell 10c has a configuration similar to that of the imaging cell 10a described with reference to Fig. 2. That is, the imaging cell 10c has a photoelectric conversion unit 11 and a signal detection circuit SCc that detects an electrical signal generated by the photoelectric conversion unit 11. However, the signal detection circuit SCc in the imaging cell 10c includes a sensitivity switching transistor 36 at a reset drain node RD.

[0107] The sensitivity switching transistor 36 is connected between the source and drain of the reset transistor 24 that is not connected to the photoelectric conversion unit 11 and the electrode of the first capacitance element 21 that is not applied with a reference potential during operation of the imaging device 100C. j For example, the first If the sensitivity switching transistor 36 is in the imaging cell 10c that belongs to column 0, the sensitivity switching line B0 is connected to the gate of the sensitivity switching transistor 36.

[0108] As already described, in the first embodiment, the image signal to be read from the imaging cell 10a is switched between a high-sensitivity signal and a low-sensitivity signal by switching the voltage level applied to the gate of the reset transistor 24. In the first embodiment, the high-sensitivity signal and the low-sensitivity signal are read out sequentially. In contrast, in the second embodiment, the sensitivity switching line B j The voltage level applied to the gate of the sensitivity switching transistor 36 is controlled via the In this way, either the high sensitivity signal or the low sensitivity signal is selected, and the image signal is read out in one frame period.

[0109] 7 shows a typical example of the circuit configuration of the sensitivity switching register 90. As shown in FIG. 7, the sensitivity switching register 90 includes comparators Cmp j , register Rg j and OR gate Gt j The set includes a plurality of sets consisting of: 7, four sets corresponding to the 0th, 1st, 2nd and (m-1)th columns are shown as representatives of the m sets. For ease of explanation, FIG. 7 also shows the imaging cells 10c belonging to a certain row among the multiple imaging cells 10c included in the pixel array PA.

[0110] As shown in the figure, each comparator Cmp j is the reference voltage line 50 The reference voltage line 50 is connected to a voltage source (not shown), and a predetermined reference voltage REF is applied to the reference voltage line 50 during operation of the imaging device 100C. As the reference voltage REF, for example, an operating limit voltage that is a criterion for determining whether or not an overflow of charge occurs at the charge storage node FD can be used.

[0111] Comparator Cmp of the jth column j corresponds to the output signal line S j The comparator Cmp j is the output signal line S jThe voltage of the register Rg is compared with the reference voltage REF. j The result is returned to the comparator Cmp j For example, the output signal line S j When the voltage of the input terminal is higher than the reference voltage REF, the input terminal outputs a high-level signal.

[0112] Register Rg j is the output signal line S j The comparison result between the voltage of the output signal line S and the reference voltage REF is temporarily held. j A "1" is asserted when the voltage on The output signal line S j "0" is set when the voltage on the In the configuration shown in FIG. j is the register reset signal By supplying a predetermined signal to the register reset signal line 52, each register Rg j You can reset the register to its initial state. By setting the voltage RGrst applied to the bit signal line 52 to a low level, each register Rg j Resets the comparison result held in to "0".

[0113] OR gate Gt j is the register Rg j and the voltage level of a reset signal line 54 that supplies a voltage pulse that specifies the timing of starting resetting each row of the pixel array PA. j For example, in Figure 7, Since the reset signal line Rg0 holds a "0", the voltage level of the reset signal line 54 becomes low. When the signal is turned on, the voltage level of the corresponding sensitivity switching line B0 becomes low. Since the voltage level of B0 is low, one or more imaging cells 10c belonging to the 0th column When the sensitivity switching transistor 36 is turned off, the photoelectric conversion unit 11 and the first capacitance element 21 are connected via the second capacitance element 22 (see FIG. 6), and the imaging cell 10c is in a high sensitivity state. j When the voltage level of the corresponding A high-sensitivity signal is read out from the imaging cell 10c.

[0114] On the other hand, since the register Rg1 holds "1", the voltage level of the corresponding sensitivity switching line B1 is at a high level. Therefore, the sensitivity switching transistor 36 in one or more imaging cells 10c belonging to the first column is turned on. When the reset transistor 24 is on, the photoelectric conversion unit 11 and the first capacitance element 21 are connected via the reset transistor 24 and the sensitivity switching transistor 36 (see FIG. 6), and the capacitance value of the entire charge accumulation region increases. Therefore, the image signal read out from the one or more imaging cells 10c belonging to the first column becomes a low sensitivity signal. In this way, the sensitivity switching line B j The voltage level of At this time, a low sensitivity signal is read out from the corresponding imaging cell 10c.

[0115] 8 and 9 are diagrams for explaining the switching of sensitivity in the imaging cell 10c according to the change in the voltage of the charge storage node FD due to exposure. FIG. 8 and FIG. 9 are schematic diagrams showing the relationship between the exposure time (time for signal charge storage) and the voltage of the charge storage node FD (which may be called the amount of stored signal charge or the gate voltage of the signal detection transistor 26) in the 0th and 1st columns shown in FIG. 7, respectively. The horizontal and vertical axes of the graphs shown in FIG. 8 and FIG. 9 respectively indicate the exposure time Ta and the voltage Vfd of the charge storage node FD. Ts and Te on the horizontal axis respectively indicate the timing of the start and end of exposure, and Vth on the vertical axis indicates the above-mentioned operating limit voltage. The double-headed arrow Exp in the graph indicates the exposure period.

[0116] As shown in FIG. 8, in the imaging cell 10c in the 0th column, the voltage Vfd of the charge storage node FD is lower than the operating limit voltage Vth throughout the entire exposure period Exp. Therefore, the voltage level of the corresponding sensitivity switching line B0 is at a low level. An image signal corresponding to the voltage Vfd is outputted to the output signal line S0 as it is. A high-sensitivity signal is read out from the imaging cell 10c in the first column. On the other hand, in the imaging cell 10c in the first column, as shown in FIG. 9, after a certain point in the exposure period, the voltage Vfd of the charge storage node FD exceeds the operating limit voltage Vth. Therefore, the voltage level of the corresponding sensitivity switching line B1 becomes high. This causes the sensitivity switching transistor 36 to turn on.

[0117] When the reset transistor 24 is on, the sensitivity switching transistor 36 is turned on, and the photoelectric conversion unit 11 and the first capacitance element 21 are connected via the sensitivity switching transistor 36. If either the reset transistor 24 or the sensitivity switching transistor 36 is off, the capacitance value of the entire charge storage region is (Cfd+C2), and if both the reset transistor 24 and the sensitivity switching transistor 36 are on, the capacitance value of the entire charge storage region is (Cfd+C1). Therefore, when the reset transistor 24 is on, the sensitivity switching transistor 36 goes from off to on, and the capacitance value of the entire charge storage region increases from (Cfd+C2) to (Cfd+C1). For example, if (Cfd+C2):(Cfd+C1)=1:10, then when the sensitivity switching transistor 36 By turning it on, as shown by the downward arrow, the voltage Vfd drops to about 1 / 10. That is, a low sensitivity signal is read out from the imaging cell 10c.

[0118] 10 is a timing chart for explaining a typical example of a signal read operation in the second embodiment. In FIG. 10, RGrst indicates a change in voltage applied to the register reset signal line 52. BS iis the sensitivity switching transistor of the imaging cell 10c belonging to the i-th row. Sensitivity switching line B on gate of Sta. 36 j The change in voltage applied through the AD i ,RST i and F.B. i 3, respectively, the address control line A i , Reset Control line R i and the feedback control line F i 10 shows a change in the voltage applied to the sensor 1. In Fig. 10, the shaded rectangle RR indicates the period for reading out the reset signal, as in Fig. 3, and the double-headed arrow NRC indicates the period for resetting and noise cancellation after the signal is acquired.

[0119] Let us look at the 0th row. Before exposure and signal readout, the above-mentioned reset and noise cancellation are performed. After the reset and noise cancellation, exposure begins. In the operation example described here, before exposure, the register Rg j To Assume that it is set to "0".

[0120] During the exposure period of the 0th row, AD0, RST0 and FB0 are all at low level. That is, the address transistor 28, the reset transistor 24, and the feedback transistor 34 of the imaging cell 10a in the 0th row are all in the off state. j Since "0" is set to each column's sensitivity switching line B j The voltage level of is low, and the sensitivity switching transistor 36 is also in the off state.

[0121] After the signal charge is accumulated in the charge accumulation region by exposure, the address transistor 28 in the 0th row is turned on. As a result, a signal corresponding to the amount of accumulated charge is output to the output signal line S of each column. j The comparator Cmp in the sensitivity switching register 90 is jis the output signal of the corresponding column. Line S j The voltage of the register Rg is compared with the reference voltage REF. j The result is returned to the register Rg0 in the 0th column (see FIG. 7). The register Rg1 in the first column is set to "1". The shaded periods are the periods when each output signal line S j The time required for comparing the voltage of the It represents the space between the two.

[0122] Output signal line S j The voltage of each column of the pixel array PA is compared with the reference voltage REF. Sensitivity switching line B j The voltage applied to the corresponding resistor Rg j In this example, the register Rg0 in the 0th column is set to "0". Therefore, the voltage applied to the sensitivity switching line B0 in the 0th row and 0th column is The voltage in the first column remains at the same level (the lower dashed line in the graph of voltage BS0 in FIG. 10). Since register Rg1 is set to "1", the sensitivity switching at row 0, column 1 is The voltage applied to line B1 switches to a high level (upper dashed line in the graph of voltage BS0 in FIG. 10).

[0123] Output signal line S j After comparing the voltage of the image signal from the imaging cell 10c with the reference voltage REF, 10, a shaded rectangle SR indicates a period during which an image signal is read from the imaging cell 10c. The image signal is read out when RST0 is changed to a high level. state, i.e. with reset transistor 24 turned on.

[0124] FIG. 11 shows the voltage BS applied to the gate of the sensitivity switching transistor 36 of the imaging cell 10c in the 0th row and 0th column. 00 and the voltage BS applied to the gate of the sensitivity switching transistor 36 of the imaging cell 10c in the 0th row and the 1st column. 01 An example of the change in Fig. 11 is shown below. , voltage BS 00 and voltage BS 01 The graphs in show typical examples of changes in voltage applied to the sensitivity switching line B0 of the 0th column and changes in voltage applied to the sensitivity switching line B1 of the 1st column when the 0th row is selected.

[0125] Here, when reading out the image signal, the voltage BS applied to the sensitivity switching line B0 00 but , is at a low level. Therefore, for the imaging cell 10c in the 0th row and 0th column, the sensitivity switching transistor 36 is in an off state, that is, a signal is read out in a high sensitivity state. In other words, a high sensitivity signal is read out from the imaging cell 10c in the 0th row and 0th column. On the other hand, in this case, when an image signal is read out, the sensitivity switching line B 01 A high-level voltage is applied to the imaging cell 10c in the 0th row and 1st column. Therefore, for the imaging cell 10c in the 0th row and 0th column, a signal is read out in a low-sensitivity state with the sensitivity switching transistor 36 turned on. That is, a low-sensitivity signal is read out. In other words, when a high-sensitivity signal is read out from the imaging cell 10c in the 0th row and 0th column, the imaging cell 10c in the 0th row and 1st column outputs a low-sensitivity signal. In this way, in the second embodiment, whether a high-sensitivity signal or a low-sensitivity signal is read out may differ depending on the column, even between imaging cells 10c belonging to the same row.

[0126] After the image signal is read out, the above-mentioned reset and noise cancellation are performed at the rising (or falling) timing of the voltage pulse RSTps. As can be seen from FIG. 7, the OR gate Gt j The reset supply voltage pulse RSTps The register signal line 54 is one of the inputs. Therefore, when the voltage pulse RSTps goes high, the register Rg j Regardless of the comparison result stored in The sensitivity switching transistor 36 in 10c can be turned on. That is, at the start of reset, the sensitivity switching transistor 36 is turned on, and the output of the feedback transistor 34 can be supplied to the charge storage node FD via the reset transistor 24 and the sensitivity switching transistor 36. After noise cancellation, a reset signal is acquired (period RR shown in FIG. 10).

[0127] The above-mentioned series of operations is executed row by row. For example, as shown in FIG. 11, in this example, the voltage RGrst applied to the register reset signal line 52 is switched to a high level between the readout of the image signal and the reset operation. Therefore, after the readout of the image signal from the imaging cell 10c, the voltage RGrst applied to each register Rg j You can reset the That is, the sensitivity of the imaging cell 10c in a certain column in a certain row when an image signal is read out may differ from the sensitivity of the imaging cell 10c in the next row in the same column when an image signal is read out. For example, a high-sensitivity signal may be read out from the imaging cell 10c in the 0th row and 0th column, and a low-sensitivity signal may be read out from the imaging cell 10c in the 1st row and 0th column.

[0128] A final image is formed by the image signals obtained from each imaging cell 10c. In the second embodiment, the obtained image contains a mixture of pixels corresponding to a high sensitivity signal and pixels corresponding to a low sensitivity signal. For example, if there is a particularly high brightness part in the subject, the sensitivity at the time of reading out the image signal in the imaging cell 10c corresponding to that part is automatically reduced. That is, a wide dynamic range image can be formed without synthesizing one frame of high sensitivity image data and one frame of low sensitivity image data. Therefore, according to the second embodiment, it is possible to capture a wide dynamic range scene without requiring a buffer memory such as a frame memory or a line memory. If necessary, the brightness level may be corrected between the pixels corresponding to the high sensitivity signal and the pixels corresponding to the low sensitivity signal. In the imaging device 100C, information indicating whether the read-out image signal is a high sensitivity signal or a low sensitivity signal is stored in each register Rg. j Since it is stored in It is also relatively easy to correct the brightness at the position.

[0129] In this way, in the second embodiment, the sensitivity of the imaging cell 10c when reading out the image signal is j It is dynamically adjusted column by column according to the data stored in In one frame period, either a high-sensitivity signal or a low-sensitivity signal is selectively read out from each of the imaging cells 10c in accordance with the illuminance. j of Although it is necessary to compare the voltage with the reference voltage REF, since the image signal accompanied by A / D conversion is read out from each imaging cell 10c once per frame period, faster operation is possible compared to the case where the image signal is read out twice per frame period. Furthermore, as is clear from the operation example described with reference to Figures 8 to 11, according to the second embodiment, the length of the exposure period for acquiring the high sensitivity signal and the length of the exposure period for acquiring the low sensitivity signal can be made the same in the same row of the pixel array PA.

[0130] Note that the on and off of each transistor including the sensitivity switching transistor 36 may be controlled, for example, by the above-mentioned control circuit 88 (see FIG. 1). For example, in one frame period, control may be performed such that the sensitivity switching transistors 36 in some of the imaging cells 10c in the pixel array PA are turned on and the sensitivity switching transistors 36 in the remaining imaging cells 10c are turned off.

[0131] (Modification of the second embodiment) Fig. 12 shows a modified example of the imaging device according to the second embodiment. The imaging device 100D shown in Fig. 12 has a second imaging cell 10b (low-sensitivity cell 10b) having a lower sensitivity than the imaging cell 10c, similar to the imaging device 100B described with reference to Fig. 4. In the configuration shown in Fig. 12, the imaging cell 10c and the low-sensitivity cell 10b adjacent to each other in the row direction form a cell pair 10Pc. A plurality of cell pairs 10Pc are arranged in a matrix on a semiconductor substrate, for example, to form an imaging region in the imaging device 100D.

[0132] In the imaging device 100D, the imaging cell 10c with the sensitivity switching transistor 36 turned off, the imaging cell 10c with the sensitivity switching transistor 36 and the reset transistor 24 turned on, and the low-sensitivity cell 10b are used as the most sensitive cell, the medium sensitivity cell, and the least sensitive cell, respectively. During one frame period, either a high-sensitivity signal or a low-sensitivity signal is read out from each imaging cell 10c according to the illuminance at the time of exposure. On the other hand, an extremely low-sensitivity signal is read out from each low-sensitivity cell 10b.

[0133] A wide dynamic range image is synthesized based on either the high-sensitivity signal or the low-sensitivity signal acquired from the imaging cell 10c and the very low-sensitivity signal acquired from the low-sensitivity cell 10b. According to the configuration illustrated in Fig. 12, the image signal read from each imaging cell 10c during one frame period is either the high-sensitivity signal or the low-sensitivity signal, so that image data of a scene with a wider dynamic range can be acquired at a higher speed.

[0134] (Other variations) 13 and 14 show modified examples of the imaging cell. The imaging cell 10d shown in Fig. 13 has a signal detection circuit SCd including a capacitive element 39 connected to a charge storage node FD via a sensitivity switching transistor 37. As shown in the figure, the capacitive element 39 is connected between one of the source and drain of the sensitivity switching transistor 37 and a reference potential VR. The gate voltage GC of the sensitivity switching transistor 37 i By controlling When the sensitivity switching transistor 37 is turned on, a low sensitivity signal can be read out from the imaging cell 10d.

[0135] As shown in FIG. 14, the signal detection circuit SCe of the imaging cell 10e has a charge storage node FD and a capacitance A second sensitivity switching transistor 38 may be further disposed between the capacitance element 39. For example, the gate voltage GL i and a sensitivity switching transistor Gate voltage GC of 37 i By controlling the row and column units, the image signal This allows more flexible switching of the sensitivity from the imaging cell 10d during readout. From the viewpoint of miniaturization of pixels, it is more advantageous to use the capacitance element 39 as both a capacitance element for noise cancellation and a capacitance element for sensitivity modulation, rather than providing a separate capacitance element 39 in addition to the first capacitance element 21 and the second capacitance element 22.

[0136] The present disclosure includes all the above-mentioned embodiments and includes the case where a photodiode formed on a semiconductor substrate is used. The imaging cell 10f shown in FIG. 15 is an example of the case where a photodiode is used as the photoelectric conversion unit 11 in FIG. 2 of the first embodiment. The imaging cell 10f shown in FIG. 15 is different from the imaging cell 10a shown in FIG. 2 in that a transfer transistor 60 is provided between the photodiode 11 and the charge storage node FD, and that a feedback circuit FC and a second capacitance element C2 are not provided. In the imaging cell 10f shown in FIG. 15, a predetermined reset voltage is applied to the source and drain of the transistor 61 that is not connected to the first capacitance element 21.

[0137] In the imaging cell 10f, when a voltage pulse is supplied to the gate of the transfer transistor 60, the charge accumulated in the photodiode 11 is transferred to the charge accumulation node FD via the transfer transistor 60. The operation after the transfer is basically the same as that described in the first embodiment, except for the operation related to feedback.

[0138] Fig. 16 shows a configuration example of a camera system including an imaging device according to an embodiment of the present disclosure. The camera system 200 shown in Fig. 16 includes a lens optical system 201, an imaging device 100, a camera signal processing unit 202, and a system controller 203. Any of the imaging devices 100A to 100D described above can be used as the imaging device 100.

[0139] The lens optical system 201 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens optical system 201 focuses light on the imaging surface of the imaging device 100. The camera signal processing unit 202 functions as a signal processing circuit that processes an output signal from the imaging device 100. The camera signal processing unit 202 executes processes such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance, and outputs image data (or signals). The camera signal processing unit 202 may be realized by, for example, a DSP (Digital Signal Processor). The system controller 203 controls the entire camera system 200. The system controller 203 may be realized by, for example, a microcomputer. By applying the above-mentioned embodiment to the imaging device 100, it is possible to obtain image signals with different sensitivities while setting the exposure period for each imaging cell to one, and it is possible to more easily capture a scene having a wide dynamic range.

[0140] Each of the reset transistor 24, the signal detection transistors 26, 26b, the address transistors 28, 28b, the feedback transistors 34, 34b, and the sensitivity switching transistors 36 to 38 may be an N-channel MOS or a P-channel MOS. It is not necessary that all of these are unified to either an N-channel MOS or a P-channel MOS. As the transistors, in addition to FETs, bipolar transistors may also be used. [Industrial Applicability]

[0141] The imaging device of the present disclosure is useful, for example, as an image sensor, a digital camera, etc. The imaging device of the present disclosure can be used as a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc. [Explanation of symbols]

[0142] Cell pair 10P, 10Pc Imaging cells 10a~10e Photoelectric conversion unit 11, 12b 21 First Capacitor 22 Second Capacitor 23b third capacitance element 24 Reset transistor 26, 26b Signal detection transistor 28, 28b Address transistor 32 j , 32b j Inverting Amplifier 34, 34b Feedback transistor 36~38 Sensitivity switching transistor 80 Row Scanning Circuit 82, 82B column circuit 84 Signal Processing Circuit 90 Sensitivity Switching Register 100, 100A to 100D Imaging device 200 Camera System A i , Ab i Address control line for row i B j Sensitivity switching line of column j Cmp j jth column comparator FC, FCb Feedback circuit FD, FDb Charge storage nodes F i , Fb i Feedback control line of the ith row Rg j Register in column j R i Reset control line for row i SC, SCb~SCe signal detection circuit S j , Sb j Output signal line

Claims

1. A first photoelectric conversion unit; a first floating diffusion electrically connected to the first photoelectric conversion unit; A first transistor; a second floating diffusion connected to the first floating diffusion via the first transistor; A second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit in a plan view; Equipped with reading out, within one frame period, a first signal corresponding to the charge generated by the first photoelectric conversion unit and stored in the first floating diffusion when the first transistor is in an off state, a second signal corresponding to the charge generated by the first photoelectric conversion unit and stored in the first floating diffusion and the second floating diffusion when the first transistor is in an on state, and a third signal corresponding to the charge generated by the second photoelectric conversion unit; Imaging device.

2. A first photoelectric conversion unit; a first floating diffusion electrically connected to the first photoelectric conversion unit; A first transistor; a second floating diffusion connected to the first floating diffusion via the first transistor; A second photoelectric conversion unit having an area smaller than that of the first photoelectric conversion unit in a plan view; Equipped with generating, within one frame period, a first signal corresponding to the charge generated by the first photoelectric conversion unit and stored in the first floating diffusion when the first transistor is in an off state, a second signal corresponding to the charge generated by the first photoelectric conversion unit and stored in the first floating diffusion and the second floating diffusion when the first transistor is in an on state, and a third signal corresponding to the charge generated by the second photoelectric conversion unit; Imaging device.

3. Further comprising a second transistor connected between the first photoelectric conversion unit and the first floating diffusion.

3. The imaging device according to claim 1.

4. the first signal, the second signal, and the third signal have different sensitivities to each other; The imaging device according to claim 1 .

5. a capacitance element having one end electrically connected to the second photoelectric conversion unit and the other end to which a reference potential is applied; The imaging device according to claim 1 .

6. The first photoelectric conversion unit includes a photodiode. The imaging device according to claim 1 .

7. The second photoelectric conversion unit includes a photodiode. The imaging device according to claim 1 .

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