Shielded connector assemblies with temperature and alignment control

Abstract

To provide connector assemblies which control temperatures and / or alignment while reducing EMI.SOLUTION: The invention provides high-speed connectors and connector assemblies 1 that are able to utilize a variety of connector side plate designs and can include temperature or alignment control. Side plates include apertures, and receive and hold portions of one or more wafers to align tail edges of terminals of each wafer tail portion within the same geometrical plane.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 010061, filed April 15, 2020, and U.S. Provisional Patent Application No. 63 / 116648, filed November 20, 2020, both of which are incorporated by reference in their entireties herein.

[0002] FIELD OF THEINVENTION The present disclosure relates to the field of connector assemblies, and more specifically to connector assemblies and components thereof suitable for use in high data rate applications (eg, at least 100 Gigabits per second (Gbps)). [Background technology]

[0003] This section introduces aspects that may be helpful in promoting a better understanding of the invention. Accordingly, the statements in this section are to be read in this light and not understood as admissions about what is or is not prior art.

[0004] To date, high speed data connector assemblies have had difficulty controlling the temperature caused by, for example, electronic circuitry within a plug module connected to the assembly, while at the same time maintaining alignment of the conductors within the assembly and, among other things, reducing the effects of potentially harmful electromagnetic interference (EMI). In particular, it is difficult to control the temperature attained within the receptacle cage of the assembly.

[0005] It is therefore desirable to provide solutions to these problems. Summary of the Invention

[0006] We describe various configurations of exemplary miniature, high speed, multi-level, multi-port connector assemblies and their components. The assemblies and components of the present invention are configured to, among other things, reduce EMI while controlling temperature and / or alignment.

[0007] In one embodiment, the high speed multi-level multi-port connector assembly of the present invention may include a shielded cage and a connector within the cage, the connector including an inner housing made of plastic configured to enclose one or more wafers, a first supporting side plate on one side of the housing, and a second supporting side plate on an opposite side of the housing, each side plate configured to receive and retain a tail portion of one or more wafers to align the tail edges of each tail portion in the same geometric plane. In an embodiment, the plastic may include high temperature liquid crystal polymer (LCP), and the one or more wafers may be equal to, for example, 1 to 8 wafers.

[0008] Several different internal housings are provided. In one embodiment, the internal housing of the present invention surrounds a portion of the top port and a portion of the bottom port, while in another embodiment, the internal housing surrounds a portion of the top port and does not surround the bottom port. If the housing does not surround the bottom port, such a housing may still include one or more notches on both sides for contacting the bottom port, for example, to support the top port and the housing. Alternatively, an alternative housing may include an upper port support structure fixably configured between the top port and the bottom port, which may include one or more apertures, each configured to receive a respective upper port protrusion to fixably position the upper port support structure.

[0009] The housing may be secured in a number of different ways: In one embodiment, the housing may include one or more boardlocks for securing the housing to the PCB, and the one or more boardlocks may be constructed from a deformable metal or plastic.

[0010] It should be understood that one or more of the wafers of the connector assembly of the present invention may include a wafer of a top port wafer assembly, while others may include, for example, a wafer of a bottom port assembly.

[0011] Each of the wafers of the connector assembly of the present invention may include one or more wafer protrusions, and the first and second support side plates may be configured to receive the one or more wafer protrusions, and the side plates may be made of a metal, such as stainless steel, or a plastic, such as LCP. More specifically, the first and second support side plates may be configured to have one or more apertures for receiving the one or more wafer protrusions, and each corresponding wafer protrusion and aperture may be configured such that each protrusion is structurally biased to a corner of the respective aperture to control the tail portion of each wafer such that the tail portion of the wafer is in the same geometric plane as, for example, a PCB that is also connected to the assembly.

[0012] The connector assembly of the present invention may further include an upper port tail alignment and support structure (e.g., made from a non-conductive material) including one or more protrusions, and the first support side plate and the second support side plate may be configured to receive the one or more protrusions of the upper port tail alignment and support structure. Such an upper port tail alignment and support structure of the present invention may further include one or more mounting structures for mounting the structure to a printed circuit board (PCB), for example, (i) some of the one or more mounting structures may comprise a non-conductive plastic covered with adhesive and some of the mounting structures may comprise a solderable plated non-conductive plastic, or metal, or (ii) one or more of the mounting structures may comprise a non-conductive plastic covered with adhesive, or (iii) one or more of the mounting structures may comprise a solderable plated non-conductive plastic, or metal.

[0013] Additionally, the assembly of the present invention may further include a bottom port wafer assembly that may be configured to be connected to a PCB, for example, by surface mount technology, ball grid array, solder charge, press fit, or by fiber optic technology. Furthermore, in an embodiment, the assembly of the present invention may additionally include a conductive bottom port tail alignment and support structure configured to align the tail edges of one or more terminals of each tail portion of the bottom port wafer of the bottom port assembly, or may further be configured as a ground reference plane structure that surrounds the differential high speed terminals of the bottom port wafer and electrically mirrors an electrical ground plane structure formed on a surface of the PCB mated to the connector assembly. It should be understood that such a conductive bottom port tail alignment and support structure need not be connected to the PCB, but may be configured to be separated from the surface of the PCB by a distance of, for example, 0.25 to 0.50 millimeters, as one non-limiting distance. In one embodiment, the conductive bottom port tail alignment and support structure may include plated plastic or stainless steel, and may be configured as an integral part of the bottom port wafer assembly, for example.

[0014] In one embodiment, a conductive grounded plastic shielding element may be configured to cover the wafers of the bottom port wafer assembly, and such conductive grounded plastic shielding element may include plated plastic, plated ceramic, or a hybrid laminate having dielectric and conductive elements, or another conductive material with a dielectric coating.

[0015] Moreover, such a conductive grounded plastic shield element may include multiple separate elements.

[0016] In embodiments, a connector assembly of the present invention may include, for example, a quad-small form-factor pluggable input / output (I / O) connector or a quad-double density small form-factor pluggable I / O connector.

[0017] Each of the terminals of the connector assembly of the present invention may include a terminal overmolded with a plastic or plated plastic construction, including a differential high speed terminal, a low speed terminal, a power terminal, and a ground terminal, and each differential high speed signal terminal may be configured, for example, to have another differential high speed signal terminal on one side and a ground terminal on the other side.

[0018] In an embodiment, each differential high speed signal terminal may, for example, transfer signals up to at least 100 gigabits per second (Gbps). Additionally, the portions of each wafer corresponding to the low speed and power terminals may electrically isolate a set of differential high speed terminals adjacent the low speed and power terminals from another set of adjacent differential high speed terminals in the same wafer to prevent destructive electrical interference with each other.

[0019] The inventive connector assembly provided by the inventors may also include a housing including one or more latches on either side configured to secure or lock the top of each wafer in place, each latch may be configured as part of the housing and operable to deflect to secure one or more wafers.

[0020] In addition to the alignment features described above, the connector assemblies of the present invention may include one or more conductive ground shield elements that may be configured to cover some or all of the terminals of one or more wafers. Thus, in some embodiments in which one or more wafers each support one or more differential high speed terminals, one or more low speed terminals, one or more power terminals, and one or more ground terminals, a conductive ground shield of the present invention may be positioned between some of the one or more wafers.

[0021] For example, the one or more conductive ground shields may include two or more separate shields with a gap between each shield configured to cover the differential high speed transmit terminals and two or more separate shields with a gap between each shield configured to cover the high speed receive terminals (i.e., air flows through the gap and over the uncovered low speed and power terminals) to enable temperature control. In another embodiment, a first conductive ground shield element of the one or more conductive ground shield elements may be configured to cover one or more differential high speed terminals of one of the wafers and a second conductive ground shield element of the one or more conductive ground shield elements may be configured to cover additional differential high speed terminals of the same wafer. Furthermore, the first and second conductive ground shields may be configured to have a gap therebetween, the dimension of the gap corresponding to an area of ​​the total number of low speed and power terminals in the row of terminals plus one terminal multiplied by the required pitch of the terminals. In one embodiment, the gap may include, for example, 4.0 millimeters.

[0022] In an embodiment, one or more conductive ground shield elements may be configured along a vertical axis (with or without a gap between them), or along an axis other than the vertical axis (with or without a gap between them). Regardless of the orientation of the shield or shields, in an embodiment, the ground shield elements may be configured to cover, for example, one or more differential high speed terminals, one or more low speed terminals, one or more power terminals, and one or more ground terminals of a respective wafer.

[0023] As described above and elsewhere herein, one or more of the differential high speed terminals may be covered by a conductive ground shield element. If one set of differential high speed terminals are transmitting elements and another set are receiving elements, for example, one conductive ground shield element (the "first" conductive ground shield element) may cover the transmitting terminals and another conductive ground shield element (the "second" conductive ground shield element) may cover the receiving terminals.

[0024] Furthermore, if the one or more wafers each support one or more differential high speed terminals, the connector assembly may be further configured to position a conductive ground shield at a first distance proximate to one or more of the respective differential high speed terminals of the one or more wafers to create field affinity between the respective ground shield and the respective differential high speed terminal.

[0025] The inventive connector assemblies provided by the inventors may include additional temperature control in addition to the aforementioned gaps in the shield, for example, low speed and power terminals in the same row of a wafer may be configured to be offset from low speed and power terminals in another row of another wafer.

[0026] For example, the housings described above and elsewhere herein may include one or more gaps to allow airflow therethrough to remove heat generated by at least the low speed and power terminals of one or more wafers.

[0027] The inventors also provide a connector assembly including the inventive combination of a ground conductor and a plastic ground shield. For example, in one embodiment, one or more insert molded metal ground conductors (e.g., made of copper, copper alloy, gold, or platinum) may each be stitchably mated with a ground conductive portion that is part of a plastic ground shield element, e.g., the ground conductive portion or portions may include conductive plastic, conductive metal, conductive or plated plastic, or a hybrid laminate having a dielectric element and a conductive element.

[0028] Each of the stitched, one or more insert molded metal ground conductors may, for example, comprise a continuous conductive structure.

[0029] To reduce undesirable voltage gradients in the connector assembly, the inventors provide one or more wafers (of the top and / or bottom wafer assemblies) each of which may include a dual ground path, where a first path may be formed by an individual ground conductor and a second ground path may be formed by a conductive finger and a conductive plated plastic shield. The inventors believe that the dual ground paths of the present invention substantially reduce the shared complex impedance along the length of each path, where the shared complex impedance may be less than the impedance of either of the individual paths.

[0030] With respect to the fingers of the present invention described above, each of the conductive fingers may be electrically and galvanically connected to a contact portion of one of the respective ground conductors and may comprise, for example, a finger of a conductive ground plate, or may comprise, for example, an insert molded finger of a plastic ground shield structure.

[0031] In addition to the inventive connector assembly, we also provide an associated inventive method therefor in tandem with the inventive connector assembly.

[0032] In one embodiment, the connector assembly of the present invention may include an inner housing having a first side and a second side opposite the first side, and first and second support side plates connected respectively to the first and second sides of the inner housing, each side plate configured to fix the position of the tail portions of the wafer within the inner housing relative to each other and to align the tail edges of the terminals of each tail portion in the same geometric plane.

[0033] In one embodiment, both of the side plates may include metal side plates and the inner housing may include a plastic, such as a liquid crystal polymer (LCP). Further, each of the side plates may be configured, for example, to receive a wafer protrusion within one or more apertures in each side plate to retain the tail portions of the terminals and align the tail edges of each tail portion in the same geometric plane.

[0034] It should be understood that the connector assembly of the present invention may also include multiple wafers (both top port wafers and bottom port wafers) within the internal housing, each of which may include terminals overmolded with plastic or plated plastic.

[0035] An exemplary inventive connector assembly may further include a top port tail alignment and support structure including one or more tail alignment and support structure protrusions, and a bottom port tail alignment and support structure including one or more tail alignment and support structure protrusions.

[0036] In one embodiment, the top port tail alignment and support structure may be made of a non-conductive material, while the bottom port tail alignment and support structure may be made of a conductive material, for example.

[0037] Furthermore, the exemplary upper port tail alignment and support structure may include one or more mounting structures for mounting the upper port tail alignment and support structure to a printed circuit board (PCB), which may include (i) a non-conductive plastic covered with an adhesive, or (ii) a solderable plated non-conductive plastic or metal that may be soldered to the PCB, or (iii) a combination of a non-conductive plastic covered with an adhesive and a solderable plated non-conductive plastic or metal soldered to the PCB.

[0038] In alternative embodiments, each of the side panels may include one or more inwardly or outwardly bent or configured hook-like tabs that are connected to the PCB and may also include, for example, one or more integral solder nails for securing each side panel to the PCB.

[0039] Another embodiment of the present invention relates to components of the connector assembly, particularly the side plates. In one embodiment, the side plates of the present invention may be connected to the sides of the inner housing, and the side plates may be configured to receive the protrusions of the tail alignment and support structure and the wafer protrusions to, among other things, hold the tail portions of each of the multiple wafers and align the tail edges of the terminals of each tail portion in the same geometric plane. Such side plates may also further include one or more inwardly or outwardly bent or configured hook-like tabs connected to the PCB or integral and / or one or more solder nails for fastening each side plate to the PCB.

[0040] In addition to the connector assemblies and components of the present invention, the inventors provide methods of the present invention that are related in parallel to the connector assemblies and components of the present invention. For example, a method for fixing the position of a wafer in a connector assembly may include fixing the position of a wafer relative to one another in an internal housing of the connector assembly using first and second support side plates connected to first and second sides of the internal housing, and receiving a protrusion of a non-conductive top port tail alignment and support structure, a protrusion of a conductive bottom port tail alignment and support structure, and a wafer protrusion into apertures of the first and second side plates to hold each tail portion of the wafer and align the tail edges of the terminals of each tail portion in the same geometric plane. [Brief description of the drawings]

[0041] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numbers indicate similar elements and in which:

[0042] [Figure 1A] 1 is a diagram of an exemplary inventive connector assembly, according to one embodiment of the present invention. [Figure 1B] 1 is a diagram of an exemplary inventive connector assembly, according to one embodiment of the present invention. [Diagram 2] FIG. 2 is an exploded view of an exemplary inventive connector assembly, in accordance with one embodiment of the present invention. [Figure 3A] 2A-2C are different views of an exemplary inventive connector, in accordance with an embodiment of the present invention. [Figure 3B] 2A-2C are different views of an exemplary inventive connector, in accordance with an embodiment of the present invention. [Figure 3C] FIG. 2 illustrates an exemplary inventive wafer, in accordance with an embodiment of the present invention. [Figure 3D] FIG. 2 illustrates an exemplary inventive alignment control mechanism, in accordance with an embodiment of the present invention. [Figure 3E] FIG. 2 illustrates an exemplary inventive alignment control mechanism, in accordance with an embodiment of the present invention. [Figure 3F] 1 illustrates an exemplary inventive conductive ground shield in accordance with an embodiment of the present invention. [Figure 3G] FIG. 2 is a close-up view of an exemplary inventive temperature control mechanism, in accordance with one embodiment of the present invention. [Figure 3H] FIG. 2 illustrates an exemplary inventive wafer, in accordance with an embodiment of the present invention. [Figure 3I] 11 is a diagram illustrating an additional exemplary inventive temperature control mechanism, according to an embodiment of the present invention. [Figure 3J] 1 illustrates an exemplary inventive conductive ground shield in accordance with an embodiment of the present invention. [Figure 3K] 1 illustrates an exemplary inventive conductive ground shield in accordance with an embodiment of the present invention. [Figure 3L] 1A-1C illustrate an exemplary inventive stitching of a ground terminal to a conductive ground shield in accordance with an embodiment of the present invention. [Figure 3M] 1A-1C illustrate an exemplary inventive stitching of a ground terminal to a conductive ground shield in accordance with an embodiment of the present invention. [Figure 3N] 1A-1C illustrate an exemplary inventive stitching of a ground terminal to a conductive ground shield in accordance with an embodiment of the present invention. [Figure 3P] 1A-1C illustrate exemplary inventive ground path configurations in accordance with embodiments of the present invention. [Figure 3Q]1A-1C illustrate exemplary inventive ground path configurations in accordance with embodiments of the present invention. [Figure 3R] 1A-1C illustrate exemplary inventive ground path configurations in accordance with embodiments of the present invention. [Figure 3S] 1A-1C show exemplary inventive tail alignment and support structures, in accordance with embodiments of the present invention. [Figure 3T] 1A-1C show exemplary inventive tail alignment and support structures, in accordance with embodiments of the present invention. [Figure 3U] 2A-2C are different views of an exemplary inventive connector, in accordance with an embodiment of the present invention. [Figure 3V] FIG. 2 illustrates an exemplary inventive alignment control mechanism, in accordance with an embodiment of the present invention. [Figure 3W] FIG. 2 illustrates an exemplary inventive alignment control mechanism, in accordance with an embodiment of the present invention. [Figure 3X] 1A-1C show an exemplary inventive alignment control mechanism and an exemplary inventive tail alignment and support structure, in accordance with an embodiment of the present invention. [Figure 4A] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4B] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4C] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4D] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4E] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4F] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4G] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4H] 1A-1C illustrate exemplary inventive features of a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 4I] 1A-1C illustrate exemplary tail alignment and support structures for at least a bottom port wafer assembly in accordance with an embodiment of the present invention. [Figure 5A] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5B] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5C] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5D] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5E] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5F] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5G] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5H] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5I] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 5J] 11A-11C are diagrams of exemplary features of an alternative exemplary connector, in accordance with an embodiment of the present invention. [Figure 6A] FIG. 13 illustrates an alternative top port wafer assembly configuration in accordance with one embodiment of the present invention. [Figure 6B] FIG. 13 illustrates an alternative top port wafer assembly configuration in accordance with one embodiment of the present invention.

[0043] Certain embodiments of the present invention are disclosed below with reference to various drawings and schematics. Both the description and the illustrations have been drafted with the intention of enhancing understanding. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements, and well-known elements that are beneficial or even necessary for commercially successful implementation may not be depicted so as to make the embodiments less ambiguous and more clear.

[0044] Simplicity and clarity in both illustration and description are required to effectively enable a person skilled in the art to make, use, and best practice the present invention in view of what is already known in the art. Those skilled in the art will understand that various modifications and changes can be made to the specific embodiments described below without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as descriptive and illustrative, rather than restrictive or comprehensive, and all such modifications to the specific embodiments described below are intended to be included within the scope of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] The following detailed description describes exemplary embodiments and is not intended to be limited to the combinations expressly disclosed. Thus, unless otherwise stated, features disclosed herein may be combined together to form additional combinations not otherwise shown for purposes of brevity.

[0046] The disclosure provided herein describes features in terms of its preferred and exemplary embodiments, and many other embodiments, modifications, and variations within the scope and spirit of the appended claims will occur to those skilled in the art from a consideration of the present disclosure.

[0047] As used in this specification and the appended claims, the terms "comprises," "comprising," or any other variation thereof, as well as "includes" or "including" and any other variations thereof, are intended to refer to a non-exclusive inclusion, such that a process, method, manufacture, or apparatus that includes a list of elements does not include only those elements on the list, but may also include other elements that are not expressly listed or that are not inherent to such process, method, manufacture, or apparatus.

[0048] As used herein, the terms "a" or "an" mean one or more than one. As used herein, the term "plurality" means two or more than two. As used herein, the term "another" means at least one more.

[0049] Unless otherwise indicated herein, if any, the use of relational terms such as "first" and "second," "top" and "bottom," "left" or "right" is only used to distinguish one element, component, entity or operation from another element, component, entity or operation, and in so doing does not necessarily require or imply an actual relationship, order or importance between such elements, components, entities or operations.

[0050] As used herein, the terms "including" and / or "having" are defined as comprising (i.e., open language). As used herein, the term "coupled" is defined as connected, although not necessarily directly and not necessarily mechanically. The use of "or" or "and / or" herein is defined as inclusive (A, B, or C means any one or any two or all three letters) and not exclusive (unless expressly stated to be exclusive). Thus, the use of "and / or" in some cases should not be construed to imply that the use of "or" elsewhere means that the use of "or" is exclusive. Terms derived from the term "indicating" (e.g., "indicates" and "indication") are intended to encompass all the various technologies available for conveying or referring to the object / information being shown. Some, but not all, examples of technologies that may be used to convey or refer to the shown object / information include conveying the shown object / information, conveying an identifier for the shown object / information, conveying information used to generate the shown object / information, conveying a part or portion of the shown object / information, conveying any derivative of the shown object / information, and conveying any symbol that represents the shown object / information.

[0051] As used herein, the terms "high speed," "high speed signal," "high speed data," "high speed data signal," and the like are meant to be synonymous unless otherwise indicated by the context or the knowledge of one of ordinary skill in the art. An example of a high speed data signal would be a signal of at least 100 Gbps.

[0052] Similarly, the phrases "low speed," "low speed signal," "low speed data," "low speed data signal," and the like are meant to be synonymous unless otherwise understood by the context or the knowledge of one of ordinary skill in the art. In general, low speed signals may be considered signals associated with control and system maintenance, as opposed to signals associated with information transfer. Furthermore, non-limiting low speed signals may be associated with data transmission rates less than 1 Gbps, and typically do not require specialized signal carrying structures such as earth-supported waveguides. For simplicity, references to "low speed terminals" may include power terminals, depending on the context.

[0053] As used herein, the phrases "configured to" or "operable to" mean "to function" unless otherwise understood by the context or the knowledge of one of ordinary skill in the art.

[0054] As used herein, the phrase "a-n" refers to a first element "a" and a last element "n", e.g., one or more apertures, where "a" is the first aperture and "n" is the last aperture. Furthermore, the letters "n" or "nn" refer to one exemplary element of several similar elements, e.g., aperture 11n.

[0055] As used herein, the terms "exemplary" and "embodiment" refer to one or more non-limiting examples of a connector assembly of the invention, a component or element of the invention, a process of the invention, or a portion of a process of the invention.

[0056] As used herein, the terms "terminal" and "conductor" may be used interchangeably unless otherwise understood by the context or the knowledge of one of ordinary skill in the art.

[0057] As used herein, the terms "hold" and "fix" may be used interchangeably unless otherwise understood by the context or the knowledge of one of ordinary skill in the art.

[0058] Referring now to FIG. 1A, a diagram of an exemplary inventive shielded, high speed, multi-level, multi-port connector assembly 1 is shown. As shown, the assembly 1 may include an electromagnetic shielding cage 2 that may be configured to protect several different connectors, each of which may have a top port and a bottom port (both hidden from view) and may be connected to a main electronic printed circuit board 3 (PCB) in accordance with one embodiment of the present invention. Also shown are pluggable module assemblies 4a, 4b, which may include PCB subassemblies, with one pluggable module assembly 4a being connected to a top port via a card slot (not shown) in the top port and the other assembly 4b being connected to a bottom port via a card slot in the bottom port. FIG. 1B shows the two assemblies 4a, 4b prior to connection with the top and bottom ports 8a, 8b.

[0059] More specifically, the cage 2 is positioned over a portion of the connector's top and bottom ports 8a, 8b to provide shielding for at least the connector and other components within the cage 2 from the effects of electromagnetic interference (EMI).

[0060] 2, an "exploded" view of exemplary components that may be used to construct an exemplary connector assembly 1 is shown. As shown, the cage 2 may include a three-sided conductive cover 2a (e.g., top and two side surfaces) along with a cage base 2b, a shielded backplate 2c, and a front-end shield 2d. Each of these components 2a, 2b, 2c, and 2d may be operable to shield the components that they each cover, such as the connector 1a, from EMI. When so positioned, the cage 2 may be operable to shield the connector 1a from a range of EMI (e.g., nominally covering 10 MHz to 50 GHz).

[0061] In one embodiment, components 2a, 2b, 2c and 2d may be comprised of, for example, a sufficiently conductive metal or a sufficiently conductive plated plastic, which are just two of the types of conductive materials that may be used. Additionally, these shielded component structures may be comprised of one or more differently configured perforated and / or non-perforated apertures to allow airflow and help control the temperature of the components that make up assembly 1. Such apertures may also be configured to reduce the effects of EMI.

[0062] More specifically, the front-end shield 2d may include one or more associated openings, apertures, or vents 5a (collectively, "apertures") operable to allow air to flow into and / or out of the interior of the cage 2 to reduce the temperature of components enclosed by the cage 2, such as the connector 1a. Additionally, the front-end shield 2d may further include a plurality of electrically conductive deformable structures or elements 6 that may be formed around a portion, or substantially all, of the circumference of the shield 2d. In one embodiment, another device (e.g., a paddle card, see element 7b) having a corresponding opposing deformable structure or element (not shown) may be pressed onto and positioned above the element 6, such that the other device may be "plugged in," so to speak, into port 8b of the connector 1a via a card slot in port 8b. The opposing forces of the two opposing sets of deformable elements, together with one or more latches (e.g., one latch typically located on each side of the cage 2 near the front, as described elsewhere herein), secure the other device to port 8b of the connector 1a. Furthermore, in one embodiment, such a "plug-in" configuration forms a continuous EMI shielding seal. Furthermore, because element 6 is conductive, an electrical ground path can be established.

[0063] Subsequently, the assembly 1 may further include an upper heat sink 2g and a second fastening clip 2h, as well as an internal integral (e.g., one-piece) central housing 2j surrounding the bottom and top ports 8a, 8b, with the paddle card 7b illustrated as being inserted into the bottom port 8b.

[0064] Optionally, the assembly 1 may further include a cage center portion that includes an internal heat sink 2e and fastening clips 2f.

[0065] In one embodiment, the upper heat sink 2g may extend substantially the entire length of the cage 2, while the inner central housing 2j is within the cage 2.

[0066] 2 illustrates assembly 1 as including all of the components previously described, it should be understood that other connector assembly embodiments are envisioned that include only a subset of such components. Still further, additional embodiments may include, for example, (i) additional components not shown in FIG. 2, (2) fewer components (i.e., a subset of the components shown in FIG. 2), and / or (iii) a subset of the components shown in FIG. 2 and additional components not shown in FIG. 2.

[0067] The first fastening clip 2f may then include one or more deformable elements 2ff operable to apply a spring-like force to the internal heat sink 2e within either side of the cage 2. As a result of such force, the heat sink 2e may come into contact with components within the cage 2, such as the top port. With reference to the second fastening clip 2h, in one embodiment, the clip 2h may be operable to apply a force to the top heat sink 2g such that the heat sink 2g comes into contact with components surrounded by and within the cage 2, such as, for example, optical / electrical (O / E) and / or electrical / optical (E / O) conversion circuitry, active devices, and / or retiming circuitry (not shown).

[0068] In embodiments of the present invention, the assembly 1 of the present invention may include additional components other than the front end shield 2d that are operable to reduce the temperature of the components of the assembly 1. For example, the cage 2 and the shielded backplate 2c may also include one or more correspondingly associated apertures 5b, 5c, respectively, configured to allow air to flow into the interior of the cage 2 to reduce the temperature of the components enclosed by the cage 2 (see FIGS. 1A and 2). In one embodiment, when connected to the assembly 1a, the plug-in paddle card 7b and the PCB 3 form a fully functional connection that allows for transfers of, for example, up to at least 100 Gbps.

[0069] Depending on the embodiment, one or more of each of the above-mentioned apertures may be shaped as a hexagon. Alternatively, one or more of each of the above-mentioned apertures may be shaped as a circle, to name just two of the many different types of aperture shapes that may be utilized, and still allow the apertures to function as temperature controls to reduce the temperature of the components of the assembly of the present invention. Furthermore, a given set of related apertures may include, for example, a subset of hexagonally shaped apertures and a subset of circularly shaped apertures. In an embodiment, the surface area and / or structure of the components of the assembly of the present invention (e.g., components 2a, 2c, and 2d) may allow for the inclusion of more hexagonally shaped apertures than circularly shaped apertures (i.e., more hexagonally shaped apertures than circularly shaped apertures may be formed in the components) due to the dimensions of the components and apertures.

[0070] Additionally, each aperture may be configured to have a width to reduce the effects of EMI on components within the interior of the assembly 1 depending on the frequency or frequencies desired to be attenuated, and an extrusion depth to reduce the effects of EMI on the internal components depending on the amount of attenuation desired (e.g., dB). For example, the smaller the aperture width, the higher the upper cutoff frequency that can be attenuated, while the deeper the extrusion depth, the more the aperture can attenuate a given signal at a given frequency (i.e., reduce the decibel level of the signal). In one embodiment, apertures used as part of the assembly of the present invention may have a width and extrusion depth (i.e., may be sized) corresponding to the amount of attenuation desired.

[0071] Further, in embodiments, apertures of a given size within a group of apertures may be repeated non-periodically to avoid aperture amplification or "gain" at a given frequency or frequency band. Still further, the exemplary apertures may each have the same width and therefore attenuate signals in substantially the same frequency range. However, by varying the extrusion depth of a given aperture, such an aperture will attenuate a given signal more at a given frequency than an aperture with a smaller (shorter) extrusion depth (i.e., an aperture with a larger extrusion depth may reduce the decibel level of a signal more than an aperture with a shorter extrusion depth).

[0072] In one embodiment, the thickness and composition of the cover 2a of the cage 2 can be set to achieve a desired EMI, attenuation level. For example, a thinner thickness of a given material may attenuate unwanted frequencies less than a thicker thickness of the same given material. Furthermore, the cover 2a of the cage 2 may be made of multiple layers of the same or different, attenuating materials (e.g., layers may be made of a metallic material while others may be made of other conductive materials such as plated plastic).

[0073] 3A and 3U, a diagram of connector 1a is shown. In one embodiment, the connector includes a central inner housing 2j that resides substantially within a shielded cage 2 and may be made of a plastic such as high temperature liquid crystal polymer (LCP), which may be configured to enclose portions of both the top and bottom ports 8a, 8b as well as one or more respective wafers (not shown) within connector 1a.

[0074] Also shown in Figures 3A and 3U is a first support side plate 9a on one side of the inner housing 2j that may be configured to have features that connect to and secure the wafers relative to each other in the inner housing 2j. For example, side plate 9a (and a second, opposite side plate 9b of the housing 2j, hidden from view in Figure 3A) may be configured to receive and hold the "tail" portion of the terminal of each wafer, for example, by receiving one or more posts or protrusions 14a-14n (collectively "protrusions") of the upper port tail alignment and support structure 14 as well as wafer protrusions or posts 10a-10n (collectively "protrusions"), to align the tail edges of each tail portion (see description of Figure 3C, e.g., 1-8 wafers) in the same geometric plane (i.e., the geometric plane in which the tail edges terminate is in the same plane as the PCB 3). In an embodiment, side plates 9a, 9b may be made of metal (e.g., stainless steel). Since the side plates 9a, 9b are connected to the housing 2j, it can be said that the housing 2j is configured to control the center-to-center positioning between each wafer.

[0075] As shown, in one embodiment, connector 1a may be configured as a shielded, high speed, multi-level, multi-port connector with temperature and alignment control. In one embodiment, connector 1a may include an input / output (I / O) connector, such as may be used for small form factor pluggable applications or double density small form factor pluggable applications (e.g., QSFP, SFP, QSFP-DD, SFP-DD, OSFP, CDFP applications). As configured, assembly 1 including connector 1a may be referred to as a shielded, high speed, multi-port, multi-level connector assembly 1 with temperature and alignment control, among other features.

[0076] More specifically, referring now to FIG. 3C, connector 1a may include multiple wafers 15a-15n (e.g., 4-8 wafers, although only four are shown) within inner housing 2j that are aligned at their tips or tops with card slots of ports, such as ports 8a, 8b. In one embodiment, each wafer 15a-15n may support a set of terminals, including terminals overmolded with plastic or plated plastic structures described in more detail elsewhere herein (e.g., differential high speed terminals, low speed terminals, power terminals, and ground terminals, not shown for clarity). More specifically, unless otherwise indicated, the terminals of each wafer may include a high speed portion, the high speed portion including differential high speed signal terminals and ground terminals extending side-by-side across the wafer, each respective differential high speed signal terminal configured to have another differential high speed signal terminal on one side of the respective differential high speed signal terminal and a ground terminal on the other side (see, e.g., FIG. 3K).

[0077] Further, each terminal may have three portions: a tip, top or contact portion (collectively, "contact portion") that contacts a pluggable card, such as cards 7a, 7b, an opposing tail portion, and a central body portion between the contact portion and the tail portion. As shown in FIG. 3C, each tail portion of the terminals of wafers 15a-15n may include several tail edges 30a'-30n' (ground conductor tail edges), 31a'-31n' (low speed or power terminal tail edges), and 32a'-32n' (high speed tail edges) that are aligned in the same geometric plane.

[0078] As can be seen throughout the figures herein, the terminals of each wafer may be arranged in one or more rows for contacting a pluggable card (see, for example, Figures 3Q and 3R).

[0079] In an embodiment, the contact portions of one or more terminals of the wafer may be arranged to form, for example, a top row of terminals in contact with the card slot, and a bottom row of terminals in contact with the card slot (see, for example, Figures 3Q and 3R).

[0080] The conductive terminals that are part of wafers 15a-15n may be configured to conduct electrical signals. Additionally, in alternative embodiments, the terminals may also be configured to, for example, provide electrical signals to E / O conversion circuitry or receive electrical signals from O / E conversion circuitry. In the latter case, such O / E or E / O conversion circuitry may be included in a mated plug-in module or card (e.g., component 7b) and then connected to the respective conductive wafers of connector 1a.

[0081] In many cases, signals conducted through the wafer's terminals or through additional O / E and E / O conversion circuitry can generate significant amounts of heat during operation. Thus, as described herein, the inventors provide an inventive solution for controlling such temperatures.

[0082] Referring to FIG. 3B, an illustrated view of the connector 1a and, separately, its components is shown, which may include the connector 1a removed from the housing 2j for ease of illustration, with the understanding that the components shown in FIG. 3B are typically connected to or within the housing 2j. Such components include the first support side plate 9a, the second support side plate 9b, the tail alignment and support structure 14, and the top port wafer assembly 10 (the bottom port wafer assembly is not shown, but is actually within the connector 1a). In one embodiment, the composition of the inner housing 2j, the top side plates 9a, 9b, and the alignment and support structure 14 may be made of plastic (e.g., LCP material). In an embodiment, the structure 14 may be a non-conductive material that may be fully or partially plated.

[0083] In an embodiment of the invention, the side plates 9a, 9b may be configured with one or more apertures 11a-11n, one or more of which may be configured to receive one or more of the aforementioned wafer protrusions of each wafer 15a-15n of the top port wafer assembly 10 (see elements 10a-10n in FIG. 3C which are configured at the tail portions of the terminals of the wafers 15a-15n). As configured, the protrusions serve to control the alignment and positioning of the respective wafers 15a-15n to ensure that the tail portions of the terminals of each wafer 15a-15n are retained and that corresponding tail edges are aligned in the same plane (i.e., the tail edges of each terminal are coplanar with the plane of the PCB 3). 3B and 3C show only protrusions (e.g., 10a-10n) on one side of each wafer 15a-15n (i.e., into side plate 9a), it should be understood that both sides of each wafer can be configured with protrusions that extend into apertures 11a-11n in each side plate 9a, 9b. In one embodiment, the protrusions can be insert molded protrusions.

[0084] Additionally, the housing 2j may include one or more latches 12a-12n on both sides of the housing 2j (see FIGS. 3A and 3B). In one embodiment, each set of latches 12a-12n (e.g., at least one on each side) may be configured to substantially secure or lock the top of each wafer 15a-15n in place to prevent the top port wafer assembly 10 from exiting the housing 2j (i.e., moving away from the front of the port 8a). Although only one latch on one side of the housing 2j is shown, it should be understood that both sides of the housing 2j may include such latches. In one embodiment, each latch 12a-12n may be configured as an integral or separately connected part of the housing 2j that may be operable to deflect outwardly as (for example) a top port wafer assembly 10 including one or more wafers is inserted into the housing 2j. As the wafer assembly 10 contacts the latches 12a-12n, the latches 12a-12n may be biased inwardly when (for example) a wafer 15a-15n passes the latches 12a-12n and reaches a determined position within the housing 2j that secures one or more wafers 15a-15n. Alternatively, a housing post that fits into an additional aperture in the enclosure 2j may be used in place of the latches 12a-12n.

[0085] 3D, for example, shows an enlarged view of wafer protrusions 10a-10n inserted into apertures 11a-11n of side plate 9a (also applies to side plate 9b). Also shown are tail edges 30a'-30n' (ground conductor tail edges), 31a'-31n' (low speed or power terminal tail edges), and 32a'-32n' (high speed tail edges) aligned in the same geometric plane.

[0086] FIG. 3E shows the side S A ~S D 1 shows an enlarged view of an exemplary inserted single protrusion 10n having sides s1-s4, along with an aperture 11n in side plate 9a. In one embodiment, each protrusion 10a-10n and aperture 11a-11n has a side S A ~s1 and S BThe distance between ~s2 and the side S of the lower right corner c2 c ~s3 and S D s4 to s5, respectively.

[0087] More specifically, sides s2 and S B are line-to-line (i.e., non-overlapping) and have sides s1 and S A Also line-to-line. On the other hand, sides s3 and S C overlap each other, and sides s4 and S D In one embodiment, the overlapping sides create an interference / compression fit force acting on the protrusion 10n that orients the protrusion 10n toward the upper left corner c1. Thus, the surfaces close to c1 (e.g., s2 and S B and s1 and S A ) is pushed closer to corner c1, and the surfaces (e.g., s3 and S C and s4 and S D ) is pushed further away from corner c2. In an exemplary embodiment, surfaces s3 and S C and s4 and S D For example, surfaces s2 and S B and s1 and S A may be 0.03 mm further away from corner c2 than it is from corner c1.

[0088] Thus, protrusions 10a-10n can be said to be "biased" toward the upper left corner c1, for example. However, it should be understood that the bias toward the upper left corner is merely exemplary. In alternative embodiments, protrusion 10n can be biased toward any one of the four corners, provided that the overlapping sides are correctly configured and the same or similar distance difference is achieved.

[0089] Such exemplary biased protrusions are one of the alignment control mechanisms of the present invention discovered by the inventors, for example, because such biased protrusions control the planarity and position of the tail portions of the wafers 15a-15n when the wafers are connected to the main PCB 3 using surface mount technology (SMT). More specifically, such biased protrusions serve to control the tail portions of the terminals of each wafer 15a-15n such that the tail edges of each tail portion of the terminals are aligned in the same plane (i.e., in the same geometric plane as the PCB 3). Without such biasing, the height of the tails of one or more of the terminals of the wafers 15a-15n may vary, and thus the tail edges may not be coplanar (i.e., may be misaligned).

[0090] Further, Figures 3B and 3D show additional alignment control mechanisms. In Figure 3B, a non-conductive tail alignment and support structure 14 of the present invention is shown which may include one or more tail alignment protrusions 14a-14n. In Figure 3D, in one embodiment, one or more of the apertures 11a-11n in each of the side plates 9a, 9b may be configured to receive one or more of the protrusions 14a-14n to further secure the tail portion of each wafer 15a-15n to a common datum (i.e., a fixed reference structure) and to allow the side plates 9a, 9b to be connected. Although only four wafers are shown connected to the side plates 9a, 9b in Figure 3D, it should be understood that more than four wafers may be connected to the side plates. For example, eight wafers may be connected to the side plates (see Figure 3X).

[0091] In short, each exemplary side plate 9a, 9b can be configured to receive the protrusions 14a-14n and wafer protrusions 10a-10n of the tail alignment and support structure 14 to hold each of the multiple wafers 15a-15n, so as to align the tail edges 30a'-30n', 31a'-31n' and / or 32a'-32n' of each tail portion within the same geometric plane as a PCB, such as PCB 3.

[0092] Figures 3V, 3W, and 3X show alternative side panels 9aa, 9ab, and 9ac, respectively. Although only one side and panel may be shown, it should be understood that each side of the housing may include similar side panels 9aa, 9ab, and 9ac.

[0093] As shown in Figures 3V and 3W, side plates 9aa, 9ab may include one or more inwardly or outwardly bent or configured hook-like tabs 19a-19n. In one embodiment, tabs 19a-19n may be connected to a PCB, such as PCB 3, by soldering. In these embodiments, side plate 9ab in Figure 3W is shown connected to housing 2j, and side plate 9aa in Figure 3V is shown connected to bottom port 88b (see Figures 5A-5E for bottom port 88b), but these are merely exemplary configurations.

[0094] In the series of views making up FIG. 3X, the side plate 9ac is shown connected to the housing 2j using protrusions and apertures as described elsewhere herein. In this embodiment, the side plate 9ac may be configured to have one or more integral solder nails 29a-29n. As shown, each solder nail 29a-29n may be received within an aperture in the PCB 3, for example, to secure the side plate 9ac and the housing 2j to the PCB 3. Additionally, the solder nails 29a-29n may be configured to make frictional contact with the tail alignment and support structures 14, 46, for example, at location 3a, to further hold the structures 14, 46 in a fixed position.

[0095] As before, each side plate 9aa, 9ab and 9ac can be configured to receive a protrusion of the tail alignment and support structure and a wafer protrusion to help hold or secure each of the multiple wafers and align the tail edges of each tail portion of the terminals of each wafer in the same geometric plane as PCB 3.

[0096] For ease of understanding, we now describe a discussion of the inventive features of a top port wafer assembly (e.g., assembly 10) that may be incorporated into a connector assembly of the present invention, such as assembly 1. Further herein, we describe a discussion of a bottom port wafer assembly. Thus, it should be understood that one or more features of the inventive top port wafer assembly may be utilized within a bottom port wafer assembly of the present invention, and vice versa.

[0097] In one embodiment, the top port wafer assembly 10 may include one or more separate power, high-speed, and low-speed communication signal conductors, and separate ground, power, and ground conductors (sometimes referred to as "terminals") that form part of the communication signal paths. In an embodiment, each high-speed conductor / terminal may be configured to transfer signals up to at least 100 Gigabits per second (Gbps), and in alternative embodiments, greater than 100 Gbps may be transferred by the high-speed signal terminals of the assembly 10 (as well as the bottom port assembly). In alternative embodiments, communication signals up to 160 Gbps may be transferred by the high-speed terminals of the assembly.

[0098] In one embodiment, the top port wafer assembly 10 may each include differential high speed terminals, centrally located low speed / power terminals, and ground terminals. Stated another way, the differential high speed terminals may be located on the left and right sides of each wafer of the top port connector assembly 10, while the low speed or power terminals may be, for example, centrally located (i.e., "on center") between the high speed terminals. In one embodiment, this "on center" portion of each wafer in the assembly 10 corresponding to the positioning of the low speed and power terminals may electrically isolate the differential high speed terminals on either side of the low speed and power terminals from harmful electrical interference. More specifically, this portion may function to isolate or "block" one set of high speed terminals configured to conduct communication (data) signals on one side of the low speed and power terminals from harmful electrical interference caused by communication (data) signals being conducted by a second set of high speed terminals on the opposite side of the same low speed and power terminals. This "block" or isolation portion may reduce detrimental electrical crosstalk between opposing differential high speed terminals, as well as improve the signal-to-noise performance of the respective high speed data signals being transferred by the high speed terminals.

[0099] Referring now to FIG. 3F, one or more separate conductive ground shield elements 16a-16n are shown. In one embodiment, one or more elements, in this case element 16a (the "first element"), may be configured to cover one or more differential high speed terminals of a wafer of the top port wafer assembly 10 (terminals not shown are covered), while another element 16n (the "second element") may be configured to cover a different differential high speed terminal of the same wafer. In one embodiment, elements 16a-16n together may comprise a multi-piece conductive ground shield. It should be understood that each wafer of the wafer assembly 10 may have its own conductive ground shield element (see, for example, elements 16aa-16an in FIG. 3H).

[0100] Additionally, as shown, there is no conductive ground shield covering the low speed and power terminals 31a-31n within gap "g1." Stated differently, in one embodiment, the first and second conductive ground shields 16a, 16n may be configured to have a gap g1 therebetween, with the dimension of gap g1 corresponding to the area (length x width) of the total number of low speed and power terminals 31a-31n plus one terminal multiplied by the required pitch of the terminals (e.g., if the area of ​​four terminals is "X", then the dimension of gap g1 is equal to (area of ​​X + area of ​​1 / 4X) x terminal pitch. For the benefit of the reader, if an exemplary terminal pitch is 0.8 millimeters and there are five exemplary low speed and power terminals, gap g1 may be, for example, 4.0 millimeters.

[0101] Because the exemplary conductive multi-piece ground shield does not cover all terminals of the wafer, heat generated and dissipated by at least the uncovered low speed and power terminals 31a-31n during operation of at least the low speed and power terminals 31a-31n may be cooled, for example, by air flowing past the terminals. Stated another way, air flowing past the terminals may remove heat generated by such terminals, for example. Additionally, in embodiments where one of the conductive ground shields 16a is configured to cover a high speed transmit / transmitter terminal and the other 16n is configured to cover a high speed receive / receiver terminal, the separation of the ground shields may function to electrically separate the transmit terminals from the receive terminals, for example, to reduce the effects of harmful electrical interference and / or noise. The separate conductive ground shields 16a-16n are only one of the temperature and electrical controls of the present invention discovered by the inventors. The use of multiple separate (e.g., two) elements 16a, 16n may be referred to herein as a "split conductive ground shield," or simply a "split shield."

[0102] While the shield in FIG. 3F is separated into two elements 16a, 16n with a gap g1 between them, it should be understood that alternative exemplary shields may include additional shields (e.g., two or more separate shields with a gap between each may be configured to cover the high speed transmit terminals, and two or more separate shields with a gap between each may be configured to cover the high speed receive terminals).

[0103] Furthermore, the two shields 16a, 16n may be combined into a single shield having an opening, vent, or aperture in the central portion to allow for air flow and temperature control. In other words, one (or more) conductive ground shield elements may be configured to cover some or all of the differential high speed terminals of the wafer.

[0104] 3F and 3G also illustrate another feature of the assembly of the present invention. More specifically, one or more of the low speed / power terminals 31a-31n in a row of wafers (i.e., in the same row) of the top port assembly 10 may be configured to be offset (i.e., shifted from the vertical axis "Y") from the low speed / power terminals in another row of another wafer, as indicated by the circled portions 18a-18n.

[0105] FIG. 3G shows a close-up view of offsets 18a-18n. As can be seen in gap g1, there may be multiple rows of terminals (e.g., terminals 31a-31n) nested one under the other within gap g1 (except for the top row). For ease of understanding, for example, in FIG. 3G, the rows of terminals are labeled 1-4 to represent the four wafers in the exemplary top port.

[0106] As shown, the low speed / power terminals in rows 3 and 4 may be offset to the left by ½ pitch, while the terminals in rows 1 and 2 may be offset to the right by ½ pitch. In an embodiment, the offset allows terminals 1-4 in each row to line up and allows air to pass through. In one embodiment, the distance that the terminals (e.g., 31a-31n) may be offset from the vertical axis Y″ may be, for example, ½ pitch.

[0107] Additionally, by configuring one set of terminals in a row that is offset from the vertical axis "Y", the terminals (eg, low speed and power terminals) may be more easily aligned.

[0108] 3H, another view of the exemplary wafers 15a-15n is shown (i.e., the labeled lines in FIG. 3H now refer to the tail edges and contact points of the wafers 15a-15n). It should be understood that in one embodiment of the invention, each of the one or more wafers 15a-15n may support one or more differential high speed terminals, one or more low speed terminals, one or more power terminals, and one or more ground terminals. Additionally, a conductive ground shield (e.g., a split shield or integral shield) as described elsewhere herein may be configured between some of the one or more wafers to, among other things, reduce detrimental crosstalk between the respective conductors that make up each wafer. However, in certain embodiments, no shield may be configured between certain wafers. For example, FIG. 3H shows wafers 15a-15n where, for example, conductive ground shields 16aa-16an may be configured between wafers 15a and 15b, between 15c and 15n, and over wafers 15a and 15d, but no shield may be configured between wafers 15b and 15c due to, for example, the field affinity created between shield 16ac and the terminals of wafer 15c.

[0109] More specifically, one or more wafers 15a-15n supporting one or more differential high speed terminals may each have a conductive ground shield positioned at a first distance proximate its respective differential high speed terminal to create field affinity between the respective ground shield and the differential high speed terminal. In one embodiment, the differential high speed terminals of each wafer 15a-15n may be configured to conduct communication data signals at a particular power level. Thus, each corresponding ground shield 16aa-16an may function as a conductive ground reference structure positioned in close proximity to the respective terminals of a given wafer 15a-15n to create field affinity. That is, the close positioning of each ground shield 16aa-16an to its respective wafer 15a-15n and included terminals serves to electrically couple signals (e.g., high speed data signals) being conducted within the terminals to the respective shield 16aa-16an (referred to as signal or field "affinity").

[0110] To create such field affinity in the connector assembly of the present invention, in one embodiment, each exemplary shield, e.g., shield 16ac of FIG. 3H, may be positioned a first distance h1 from a respective signal terminal of a wafer, e.g., wafer 15c, that is less than a second distance h2 from the same terminal of wafer 15c to the terminal of another wafer, e.g., wafer 15b. Stated differently, shield 16ac may be positioned a smaller distance closer to the terminal of wafer 15c compared to the positioning of the terminal of wafer 15b.

[0111] In an embodiment, this field affinity may be created between each wafer 15a-15n and its respective positioned shield 16aa-16an such that no shielding is required between wafers 15b and 15c.

[0112] Exemplary, non-limiting distances h1 and h2 may be 0.30 millimeters and 2.40 millimeters, respectively.

[0113] Still further, in one embodiment, the first distance h1 must be less than a third distance between any two differential signal terminals of a given wafer (e.g., in FIG. 3R, the third distance h3 represents the distance between adjacent high speed differential signal terminals of the same wafer, and thus h1 must be less than h3). Still further, in an embodiment including a ground terminal between a set of differential signal terminals (e.g., one of the terminals 30a-30n between the set of differential terminals 32a-32n in FIG. 3R), the distance h1 must be much less than the distance formed between one of the differential signal terminals 32a-32n of one set of terminals and the nearest adjacent differential signal terminal 32a-32n of the adjacent second set of differential signal terminals, as shown by h4 in FIG. 3R.

[0114] Referring to Figure 3I, an alternative embodiment is shown that includes an additional temperature control mechanism. This view shows the back side of the housing 2j. As shown, the housing 2j has one or more gaps or openings g. 2a-2n In one embodiment, the gap g 2a-2n The dimensions (i.e., area) of the central gap of the housing 2j may be at least equal to the dimensions of the gap g1 described elsewhere herein. In one embodiment, the housing 2j has an opening g 2a-2n 3B, 3F, and 3I, the conductive split ground shield is separated into multiple elements along a vertical axis "Y." Also shown in FIG. 3I are pegs 17a-17n for fastening the housing to a PCB, for example.

[0115] Now referring to FIG. 3J, in an alternative embodiment, an exemplary conductive split ground shield may include two or more separate elements 20a-20n separated, for example, along an axis other than the vertical or Y axis, e.g., the “X” or “Z” axis, for covering, for example, portions of the terminals of wafer 15nn.

[0116] While the above description describes a split shield, it should be understood that this is merely exemplary. Alternatively, the conductive ground shield of the present invention for a wafer (e.g., a top port wafer or a bottom port wafer) may include a single element (i.e., a single piece). Thus, in an alternative embodiment, the conductive ground shield element may be configured to cover one or more differential high speed terminals, one or more low speed terminals, one or more power terminals, and one or more ground terminals of each wafer (e.g., one shield per each wafer).

[0117] For example, referring now to Figure 3K, a single-element conductive ground shield 21 is shown that is configured to cover all of one or more terminals of one or more wafers (e.g., low speed and power terminals 31a-31n and high speed terminals 32a-32n and ground conductors or terminals 30a-30n). As shown, each differential high speed terminal 32a-32n can be configured with another differential high speed signal terminal 32a-32n positioned on one side and a ground terminal 30a-30n positioned on the other side.

[0118] In addition to the temperature and alignment control mechanisms, the inventors also provide a method and structure of the present invention that combines a metal ground conductor / terminal and a plastic conductive ground shield.

[0119] 3L-3N, stitched, insert molded ground conductors or terminals are shown. In one embodiment, by "stitching," it is meant that one or more insert molded metal ground conductors 22a-22n of, for example, FIGS. 3L and 3M, can be mated with respective ground conductive portions that are part of plastic ground shield elements 16a", 16n" by applying an interference mating force that (typically) forcibly holds the respective elements together (referred to as "stitchably mated").

[0120] In these embodiments, the ground conductive portions 23a-23n may include conductive plastic operable to function as ground path segments that may connect, for example, one conductive metal portion 22a to another metal portion 22n.

[0121] Although Figure 3L shows the illustrated metal conductive ground portions 22a-22n separately from the respective ground conductor portions 23a-23n of the respective plastic conductive ground shields, it should be understood that all of the components of Figure 3L may comprise a single stitchably interlocking structure when combined, for example, as shown in Figure 3M. In an embodiment, the illustrated metal portions 22a-22n may be made of copper, a copper alloy, or another conductive metal (e.g., gold, platinum).

[0122] Note that stitching the conductors / terminals of the wafer is one way of connecting the conductors, or the conductors / terminals may include support structures for connecting the terminals of the wafer to, for example, the nosepiece of the top port module.

[0123] The ground conductive portions 23a-23n of the ground shield elements 16a", 16n" may be made of metal, or conductive or plated plastic, or a hybrid laminate having dielectric and conductive elements, such as PCB portions. For example, in FIG. 3M, the ground conductive portions 23a-23n are made of plated plastic. Alternatively, in FIG. 3N, the ground conductive portions 24a-24n may be metal. Thus, the electrical ground paths P1-P N can be formed as a continuous metal conductor (eg, as in FIG. 3N) or some combination of metal and plastic conductive portions (eg, as in FIG. 3M).

[0124] It should be noted that portions 22a-22n may be continuous conductive structures rather than being separated into portions.

[0125] In addition to providing the inventive temperature and alignment control mechanisms, the inventive connection assemblies provided by the inventors may also include mechanisms for reducing the impedance of the respective ground paths, and for reducing harmful electrical crosstalk. For example, in an embodiment of the present invention, the inventors provide a connector assembly of the present invention that includes an electrical ground structure that functions to maintain substantially the same voltage gradient (i.e., voltage difference) substantially along the length of the ground structure. While a zero voltage gradient along the entire ground structure may not be practically achievable, in an embodiment of the present invention, the ground structure discovered and provided by the inventors minimizes such gradients substantially along the entire structure at operating temperatures. The ability to minimize such voltage gradients substantially along the entire ground structure provides a connector assembly of the present invention with a high quality ground reference structure, which in turn may reduce conducted crosstalk and even reduced coupled crosstalk between terminals, providing reduced shared voltages and providing an effective ground drain for any induced or coupled voltages due to electrical noise.

[0126] For example, the present inventors provide a connector that includes a structure configured to form a dual ground path. Referring now to Figure 3P, a dual ground path configuration is shown in accordance with one embodiment of the present invention. For ease of illustration, low speed and power terminals are not included in Figure 3P.

[0127] As shown, the diagram of the upper port ground path assembly 10" may include dual ground paths, one formed by individual ground conductors 30a-30n and the other ground path formed by conductive deflectable spring "fingers" or tabs 28a-28n (collectively "fingers") of insert molded conductive ground plate 28 and conductive plated plastic shield 21a. More specifically, each of fingers 28a-28n may be inserted into a channel 36a-36n formed in shield 21a.

[0128] In one embodiment, each of the ground conductors 30a-30n may function as a first ground path including a structure connected at one end to a terminal of an input / output module (e.g., card 7b), positioned parallel and in-line with the respective differential signal conductors, and connected at the opposite end to a surface of a PCB (e.g., PCB 3).

[0129] When assembled, each of the fingers 28a-28n may be electrically and galvanically connected to (i.e., in contact with) a respective contact portion of the ground conductors 30a-30n (i.e., the tip of the conductors 30a-30n), thereby functioning to provide a portion of a second ground path that may run from such contact point through the respective finger 28a-28n and conductive plate 28 and then through the conductive plated plastic 21a.

[0130] While the figures and description herein describe a second ground path formed to the differential high speed terminals 32a-32n, it should be understood that similar additional ground paths may be formed to the low speed terminals 31a-31n. In either case (high speed and low speed applications), the inventors have discovered that the formation of dual or multiple ground paths results in an overall improvement in the integrity of the ground path structure of the assembly. This ensures that the electrical impedance and steady state resistance of the ground structure along the length of the ground path is controlled. The ability to control the impedance and resistance further allows for control of the temperature of the power terminals / conductors associated with the ground, for example, when such power conductors conduct higher currents, the dual ground paths share the current (i.e., the lower the resistance, the less power can be lost or dissipated).

[0131] As described herein, the shield 21a may be a plated plastic. Alternatively, the shield 21a may be made of, for example, a plated ceramic (i.e., a ceramic with conductive flashing), a plated metal, or another conductive material with a dielectric coating, such as a nickel, tin, gold, or copper coating. Although the conductive deflectable fingers are shown as part of the overall plate, it should be understood that this is merely exemplary. Alternatively, each of the fingers may be insert molded into a respective plastic ground shield structure, for example.

[0132] It should be noted that in embodiments including separate finger-type structures, terminals that can be supported by redundant isolated ground paths can take advantage of an overall lower longitudinal resistance along the path to the board termination, and therefore share the benefits of reduced path resistance and can have lower heat generation in the power delivery function.

[0133] Other dual ground path structures / configurations may also be included in the assemblies of the present invention. For example, Figures 3Q and 3R show a configuration including conductive deflectable spring fingers or tabs 35a-35n (collectively "fingers") that may be insert molded as part of the conductive plated plastic shield 21b, but not as part of the conductive plate. In this embodiment, a first ground path may be formed by each of the ground conductors 30a-30n, while a second ground path may be formed by each of the fingers 35a-35n contacting a respective contact portion of the ground conductors 30a-30n (i.e., the tip or top of the conductors 30a-30n), thereby functioning to provide a second ground path from such contact point through the respective fingers 35a-35n and the conductive plastic shield 21b. Figure 3Q also shows an optional gap g in the mid-shield (hidden from view) of the top port wafer assembly 10 for temperature control. 3a-3n This shows that.

[0134] In each of the dual ground paths described herein, each path has an associated voltage difference that can be measured between opposing ends of the path (e.g., from the tip of each finger 28a-28n to the PCB 3 or from the tip of each conductor 30a-30n to the PCB 3) due to the impedance of each path. In an embodiment, the presence of dual ground paths substantially reduces the shared complex impedance along the length of each path. For example, if a first path has an impedance of Z1 and a second path has an impedance of Z2, then the shared complex impedance Z3 is less than Z1 or Z2 and may be given by the relationship Z3=1 / [(1 / Z1)+(1 / Z2)].

[0135] 3S and 3T, diagrams of exemplary tail alignment and support structures 14, 46 are shown, according to embodiments of the present invention. In one embodiment, for example, structure 14 is configured as a non-conductive top port tail alignment and support structure that may be connected to tail edges 30a'-30n' of ground terminals 30a-30n, tail edges 32a'-32n' of differential high speed terminals 32a-32n, and tail edges 31a'-31n' of low speed and power terminals 31a-31n at the bottom of the connector assembly, while structure 46 is configured as a conductive bottom port tail alignment and support structure that may be connected to tail edges 30a'-30n' of ground terminals 43a-43n, differential high speed terminals 42a-42n, and low speed and power terminals 49a-49n at the bottom of the connector assembly.

[0136] The structure 14 may include tail alignment protrusions 14a-14n, each of which may be inserted into an aperture in the side plates 9a, 9b or affixed to the side plates (see FIG. 3A or FIG. 3D). In addition, such an exemplary structure 14 may include one or more mounting structures 26a-26n and 27a-27n. In one embodiment, the structures 26a-26n may comprise, for example, a non-conductive plastic that may be covered with adhesive for mounting the structure 14 to a PCB, such as PCB 3 of FIG. 1A, and may be combined with one or more structures 27a-27n made of solderable plated non-conductive plastic or metal that may be soldered to further mount the structure 14 to the PCB. Alternatively, all of the structures 26a-26n and 27a-27n may comprise, for example, a non-conductive plastic that may be covered with adhesive, or all may comprise, for example, a solderable plated non-conductive plastic or metal.

[0137] We now turn to the bottom port wafer assembly. Recall that assembly 1 in Figure 1B shows both a top port 8a and a bottom port 8b. Each port has a corresponding wafer assembly that may contain multiple wafers and thus multiple terminals.

[0138] Figure 4A shows a close-up of the bottom port 8b, while Figure 4B shows a close-up of an exemplary bottom port wafer assembly 40 within the port 8b. It should be understood that some of the features of the top port wafer assembly may be incorporated into the bottom port wafer assembly. For example, the bottom port wafer assembly may include side plates for holding the tail portions of the wafer terminals to align the tail edges of the wafer terminals, although such plates are not shown in Figures 4A and 4B.

[0139] In one embodiment, the bottom port wafer assembly 40 may be configured to be connected to the PCB 3 using, for example, SMT. In alternative embodiments, the bottom port wafer assembly 40 may be connected to the PCB 3 using, for example, ball grid array, solder charge, press fit, SMT, fiber optic technology, or a combination of such technologies.

[0140] Similar to the top port wafer assembly, each wafer of the bottom port wafer assembly 40 may include one or more separate power and low speed communication signal conductors / terminals, one or more differential high speed conductors / terminals, and one or more ground conductors. In an embodiment, at least exemplary high speed communication signals up to and exceeding 100 Gigabits Gbps may be transported by the high speed signal conductors of the assembly 40. In an alternative embodiment, communication signals up to 160 Gbps may be transported by the high speed conductors.

[0141] In one embodiment, the low speed / power terminals may be located, for example, in the center of the wafer, and each differential high speed terminal may be configured such that another differential high speed signal terminal is located on one side and a ground terminal is located on the other side.

[0142] In FIG. 4B, the bottom port wafer assembly 40 may include a conductive grounded plastic shield element 41 configured to cover the lead frames and their respective wafers. As with the top port wafer assembly described above, the shield 41 may include plated plastic. Alternatively, the shield 41 may be made of, for example, plated ceramic (i.e., ceramic with conductive flashing), plated metal, a hybrid laminate having dielectric and conductive elements such as a PCB section, or another conductive material with a dielectric coating such as a nickel, tin, gold or copper coating. Although shown as a single integral piece, it should be understood that the shield 41 may include multiple separate elements (e.g., two elements) where dual or redundant paths may be created to take advantage of the overall lower longitudinal resistance and thus share the benefits of reduced path resistance and have lower heat generation in the power delivery function.

[0143] The bottom port wafer assembly may also include a dual ground path configuration similar to that described above. For example, one ground path may be formed by individual ground conductors 43a-43n, and the other ground path may be formed by conductive deflectable "fingers" 45a-45n. More specifically, each of the ground conductors 43a-43n may function as a ground path to a PCB, such as PCB 3. In one embodiment, when assembled, each of the fingers 45a-45n may be electrically and galvanically connected to a respective contact portion (i.e., tip or top portion) of the ground conductor 43a-43n, thereby functioning to provide a second ground path from such contact point through the respective finger 45a-45n, then through the conductive plated plastic 41, and to the PCB. High speed terminals 42a-42n and low speed and power terminals 49a-49n are also shown.

[0144] Other dual ground path configurations may also be utilized. For example, rather than providing fingers 45a-45n insert molded into shield 41, the fingers may be part of the plate, similar to plate 28 described above. In each of the dual ground path embodiments, the dual ground path configuration may provide features as previously described herein.

[0145] 4C, there is shown a close-up view of an exemplary wafer 40a of assembly 40. As shown, wafer 40a illustrates a dual ground path formed by individual ground conductors 43a-43n and by conductive deflectable "fingers" 45a-45n and shield 41.

[0146] 4D shows an exploded view of an exemplary wafer 40a. In one embodiment, the deflectable metal "fingers" 45a-45n may be welded or otherwise conductively affixed to a dielectric leadframe support structure 44a-44n that also supports, for example, the primary ground conductors 42a-42n (e.g., high speed conductors / terminals).

[0147] 4E shows an exploded view of bottom port wafer assembly 40. As shown, assembly 40 may include a plurality of dielectric leadframe support structures 47a-47n, each for supporting and electrically isolating one or more wafers having one or more conductors (e.g., high speed terminals, low speed terminals, power terminals, and ground conductors). Also shown is a conductive bottom port tail alignment structure 46 for holding the tail portions of the terminals of each wafer and for helping to align the tail edges of each terminal of the bottom port wafer. In one embodiment, structure 46 may include plated plastic or stainless steel (e.g., stainless steel SUS301, copper C70250, etc.).

[0148] A close-up view of the exemplary wafer 40a is shown in Figures 4F and 4G, and a bottom view of the bottom port wafer 40a is shown in Figure 4H. Green cones are shown in Figures 4F and 4G to illustrate one exemplary method of connecting the conductive fingers 45a-45n to the lead frame 47a, it being understood that such cones are merely exemplary of connection points and are not physical structures. In one embodiment, at each connection point indicated by the green cone, the exemplary conductive fingers 45a-45n can be welded to connect with the lead frame 47a, for example.

[0149] 4I, a close-up view of an exemplary conductive bottom port tail alignment and support structure 46 according to an embodiment of the present invention is shown, as viewed from below the port 8b. In one embodiment, unlike the tail alignment and support structure 14 of the top port wafer assembly, as previously described, the structure 46 may be made of a conductive material (e.g., metal, plated plastic). To provide alignment control, the tail edges 42a'-42n' of one or more high speed terminals 42a-42n, the tail edges 49a'-49n' of one or more low speed and power terminals 49a-49n, and the tail edges 43a'-43n' of one or more ground conductors 43a-43n of the wafer may be connected to the structure 46. Additionally, the bottom port tail alignment and support structure may include a number of protrusions that may be inserted into the side plates (e.g., apertures similar to 11a-11n and protrusions similar to 14a-14n).

[0150] In addition to alignment control, structure 46 may provide control of undesired electrical interference (e.g., noise). For example, structure 46 may be configured as a ground reference plane structure that surrounds, for example, differential high speed terminals 42a-42n and their tail edges 42a'-42n'. Such a ground reference plane structure may be configured to electrically "mirror" (i.e., be configured similarly to) an electrical ground plane structure formed on the surface of a mated PCB (e.g., PCB3). It should be understood that in embodiments, the "mirrored" conductive ground structure (e.g., structure 46 and the surface of PCB3) and the conductive surface need not be in direct galvanic contact with each other to electrically isolate, for example, differential signals conducted within high speed terminals 32a-32n from differential signals conducted by terminals / conductors on the surface of the PCB. In one embodiment, to provide such electrical isolation, structure 46 may be separated from the surface of the PCB by 0.25-0.50 mm, to name just one non-limiting distance. Although not in direct galvanic contact, two opposing mirrored structures / surfaces can function as an electrical capacitor, i.e., the two conductive structures / surfaces are separated by a dielectric (in this case, typically air).

[0151] In one embodiment, the structure 46 may be an integral part of the bottom port wafer assembly.

[0152] In the previous discussion, the assembly 1 included a central housing 2j that surrounded portions of both the top and bottom ports 8a, 8b. In one embodiment, an alternative housing may surround a single port.

[0153] 5A, connector 1b is shown that may be part of an alternative high speed shielded multi-level multi-port connector assembly 100. As shown, connector 1b may include a center housing 102. Like housing 2j, center housing 102 may be within cage 2 and may be made of plastic (e.g., LCP). Unlike housing 2j, housing 102 may surround a portion of top port 88a, but may not surround bottom port 88b. Housing 102 may be configured to protect one or more conductive wafers (not shown) within housing 102.

[0154] In one embodiment, the housing 102, the ports 88a, 88b, the internal wafers and their respective terminals, and additional components within the housing 102 may form a high speed, shielded, multi-level, multi-port connector with temperature and alignment control, among other features. In one embodiment, the connector 1b may include an input / output (I / O) connector, such as those used in quad small form factor pluggable applications or quad double density small form factor pluggable applications (e.g., QSFP, OSFP, CDFP applications). Thus, the assembly 100, including the housing 102, may be referred to as a high speed, shielded, multi-port, multi-level connector assembly with temperature and alignment control, among other features.

[0155] Conductive terminals that are part of the wafers in connector 1b may be configured to conduct electrical signals. Additionally, in alternative embodiments, the terminals may also be configured to provide electrical signals to, or receive electrical signals from, e.g., E / O conversion circuitry. In the latter case, such O / E or E / O conversion circuitry may be included and connected to the respective conductive wafers, e.g., the cages may be mated to active electronic circuitry.

[0156] In many cases, signals being conducted through the conductive wafer, O / E, E / O conversion circuitry, active devices, and retiming circuitry can generate significant amounts of heat during operation. Thus, as described herein, the inventors provide an inventive solution for controlling such temperatures.

[0157] The housing 102 may be configured to have one or more notches 101a-101n on both sides to contact the bottom port 88b. Alternatively, pillars or trusses may also be used to support the housing above the bottom port 88b (see, for example, FIG. 5D). Compared to the housing 2j, the housing 102 provides an additional degree of freedom in the assembly process because it does not surround a portion of the bottom port 88b, unlike the housing 2j, which surrounds a portion of the bottom port 88b (i.e., the upper port 88a and the lower port 88b are independent of each other and can be freely manipulated without affecting each other).

[0158] 5B shows an exploded view of the connector 1b. As shown, the housing 102 may include a central structure 102a, a first supporting side plate 102b, and a second supporting side plate 102c (e.g., a metal side plate) opposite the first supporting side plate 102b. In an embodiment of the present invention, each side plate 102b, 102c may be configured to connect to and secure relative to each other (i.e., wafer-to-wafer) the position of the wafers within the inner housing 102. More specifically, the side plates 102b, 102c may be configured to have one or more apertures 104a-104n, each configured to receive a respective first protrusion 105a-105n of the top port wafer assembly to control the positioning of the terminals of the wafer within the top port, such that the wafers may be held and the tail edges of the respective terminal tail portions may be aligned in the same plane. Further, to secure the central structure 102a and each side plate 102b, 102c to an underlying PCB (e.g., PCB 3 in FIG. 1A), the central structure 102a and each side plate 102b, 102c may be configured with one or more integral deformable board locks 103a-103n, which may be made of, for example, a deformable metal or plastic.

[0159] 5B also shows a number of dielectric leadframe support structures or hangers 117a-117n ("hangers" for short), which may be made of a plastic such as LCP. In one embodiment, each hanger 117a-117n may be configured to provide physical support and alignment for a respective upper leadframe. Each hanger 117a-117n may be further configured with a heat stake post 118a-118n (see FIG. 5C), each post may be configured to be received by an alignment opening in a respective side plate 102b, 102c.

[0160] 5D and 5E, an alternative top port support structure 107 is shown that is fixably configured between the top port 88a and the bottom port 88b. In one embodiment, the structure 107 can include one or more apertures 108a-108n, each configured to receive a respective top port protrusion 109a-109n to fixably position the structure 107. As configured, the structure 107 can be operable to support the top port 88a and a wafer within the top port 88a. Although shown as an open rectangle, it should be understood that this is merely one exemplary shape and structure for the top port support structure 107. Other shapes and structures can be used, such as, for example, an open or filled square structure.

[0161] In further embodiments, the top port 88a may be separately connected to the PCB 3 using, for example, SMT techniques. Such an exemplary top port assembly is shown in FIG. 5F. In addition to SMT type connections, as mentioned above, the assembly may be connected to the PCB 3 using, for example, one or more board locks 103a-103n that may be inserted into corresponding apertures in the PCB 3 (e.g., pin-in-paste holes or compliant pin (press-fit) holes) to provide alignment control of the wafers that make up the top port assembly substrate and their respective terminals during a reflow operation.

[0162] 5G-5J show diagrams of a connector 1b that includes temperature control.

[0163] In FIG. 5G, the back cover 102d of the internal top port housing 102 may include one or more openings 110a-110n that allow air to flow over the terminals (e.g., low speed signal and power terminals) within the wafer of the connector 1b.

[0164] 5H and 5I, a diagram of a top port leadframe ground shield 111 is shown. The shield 111 may include a temperature control mechanism for controlling the temperature of the conductors / terminals. For example, one or more openings 112a-112n may be configured within the leadframe ground shield 111 to, for example, allow air to flow over the low speed signal and power terminals 116a-116n. Also shown are high speed signal terminals 114a-114n (e.g., differential signal pairs) that may be nested between the ground conductors 113a-113n. As configured, this configuration provides enhanced shielding. It should be noted that the top port wafer assembly configuration shown in FIGS. 5G and 5H may also be incorporated by the top port wafer assembly 10 previously described herein.

[0165] 5H and 5I also illustrate, for example, exemplary dielectric leadframe support structures 115a-115n of the upper port assembly. The leadframe support structures 115a-115n can be configured to align and support, for example, a plurality of ground conductors 113a-113n, a plurality of high speed conductors or terminals 114a-114n, and a plurality of low speed and power conductors or terminals 116a-116n.

[0166] Although the ground, high speed, low speed and power conductor terminals are shown as facing downward, it should be understood that the assembly may also include leadframe structures including upward facing terminals that may be supported by a similar leadframe and covered by a similar ground shield, i.e., the top port assembly may include multiple leadframe structures.

[0167] In embodiments of the present invention, the signal and field affinity between the terminals of each leadframe structure 115a-115n of the assembly and its respective ground shield may be sufficient to limit, for example, deleterious inter-leadframe coupling and crosstalk, as previously described herein.

[0168] 5J shows a view of connector 1b with top port 88a before bottom port 88b is connected. Also shown are board locks 103a-103n that secure the top port assembly to a PCB (e.g., PCB 3) during, for example, a reflow operation.

[0169] 6A and 6b, a diagram of the top port wafer assembly 13 is shown. As shown, the assembly may include opposing metal side plates (only one shown) of an inner housing 102. In one embodiment, the assembly may be aligned and connected to a PCB, such as PCB 3, using, for example, SMT and board locks 103a-103n. The assembly 13 may include one or more gaps g that provide airflow over the terminals. 4a-4n on each of the intermediate conductive shields (e.g., plated plastic shields).

[0170] As described herein, the inventors have discovered an inventive connector assembly and associated methods that include multiple alignment controls for both the mated device (e.g., high speed active plug module) and the inner conductor and ground wafer alignment. Additionally, the temperature controls included in the inventive connector assembly enable such connectors to control the temperature (e.g., up to 20 watts or more) generated by the electronic circuitry within the connected plug-in module, allowing for the effective transfer of communication (data) signals up to at least 100 Gbps.

[0171] Although certain inventive features and functions have been described with respect to one embodiment of the present invention or with respect to exemplary drawings, it should be understood that this is by way of example only, i.e., some features and functions may be applicable and may be incorporated in many embodiments other than those specifically described or illustrated.

[0172] The claims contained below are incorporated herein by reference in an expanded format, i.e., hierarchically from broadest to narrowest, with each possible combination being represented by reference to multiple dependent claims that are presented as a unique and independent embodiment.

[0173] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments of the present invention. However, the benefits, advantages, solutions to problems, and any elements that may cause or result in such benefits, advantages, or solutions, or that may make such benefits, advantages, or solutions more apparent, should not be construed as critical, necessary, or essential features or elements of any or all of the claims.

Claims

1. 1. A connector assembly comprising: Housing and a side plate on one side of the housing, the side plate including an aperture; a wafer assembly including an array of conductors and a protrusion at one end of the array of conductors; The protrusions are inserted into apertures in the side plates to align the rows of conductors.

2. The connector assembly of claim 1 , wherein the side plate includes an array of apertures that aligns an array of a plurality of conductors.

3. a second side panel on the other side of the housing, the second side panel including an aperture; the wafer assembly further includes a second protrusion at the other end of the row of conductors; 2. The connector assembly of claim 1, wherein the second projection is inserted into an aperture in the second side plate to align the rows of conductors.

4. the side panel extends along a first bottom edge of the housing on one side of the housing; The connector assembly of claim 3 , wherein the second side plate extends along a second bottom edge of the housing on the other side of the housing.

5. 2. The connector assembly of claim 1, wherein the housing includes a latch that contacts a wafer positioned within a port of the housing and locks a top of the wafer assembly within the housing.

6. further comprising a tail alignment structure including a tail alignment protrusion; the wafer assembly including a tail portion; a tail portion of the wafer assembly extending through an opening in the tail alignment structure; the side panel includes a second aperture; The connector assembly of claim 1 , wherein the tail alignment protrusions are inserted into second apertures in the side plates to further align the rows of conductors.

7. The connector assembly of claim 6 , wherein the tail alignment structure includes a mounting structure for mounting the connector assembly to a printed circuit board.

8. The connector assembly of claim 7 , wherein the mounting structure includes a plurality of non-conductive structures and a plurality of solderable structures.

9. The connector assembly of claim 8 , wherein the non-conductive structure comprises an adhesive.

10. The connector assembly of claim 1 , wherein the side plate includes tabs for connecting the connector assembly to a printed circuit board.

11. the wafer assembly including a row of second conductors and a second protrusion at one end of the row of second conductors; the side panel includes a second aperture; 2. The connector assembly of claim 1, wherein the second projection is inserted into a second aperture in the side plate to align the second row of conductors.

12. the housing includes a top port and a bottom port; the wafer assembly includes a top port wafer assembly having contacts in a top port of the housing; The connector assembly of claim 1 , further comprising a bottom port wafer assembly having contacts in a bottom port of the housing.

13. the bottom port wafer assembly including a bottom port row of conductors and a bottom port wafer protrusion at one end of the bottom port row of conductors; the side panel includes a second aperture; 13. The connector assembly of claim 12, wherein the bottom port wafer protrusion is inserted into a second aperture in the side plate to align the bottom port row of conductors.

14. the top port wafer assembly includes a plurality of top rows of conductors; the bottom port wafer assembly includes a plurality of bottom rows of conductors; 13. The connector assembly of claim 12, wherein the side plate includes a first row of apertures that align a top row of conductors and a second row of apertures that align a bottom row of conductors.

15. A printed circuit board; a cage over the printed circuit board; a connector within the cage; and A connector assembly comprising: The connector is Housing and a side plate on one side of the housing, the side plate including an aperture; a wafer assembly including a row of conductors and a protrusion at one end of the row of conductors; a connector assembly, the projections being inserted into apertures in the side plate to align tail portions of the rows of conductors with a surface of the printed circuit board;

16. a second side panel on the other side of the housing, the second side panel including an aperture; the wafer assembly further includes a second protrusion at the other end of the row of conductors; 16. The connector assembly of claim 15, wherein the second projection is inserted into an aperture in the second side plate to align tail portions of the rows of conductors with a surface of the printed circuit board.

17. the side panel is on one side of the housing and extends along a first bottom edge of the housing above the printed circuit board; 17. The connector assembly of claim 16, wherein the second side plate is on the other side of the housing and extends along a second bottom edge of the housing above the printed circuit board.

18. further comprising a tail alignment structure including a tail alignment protrusion; the wafer assembly including a tail portion; a tail portion of the wafer assembly extending through an opening in the tail alignment structure; the side panel includes a second aperture; The connector assembly of claim 15 , wherein the tail alignment protrusions are inserted into second apertures in the side plates to further align the rows of conductors.

19. the wafer assembly including a row of second conductors and a second protrusion at one end of the row of second conductors; the side panel includes a second aperture; The connector assembly of claim 15 , wherein the second projection is inserted into a second aperture in the side plate to align the second row of conductors.

20. the housing includes a top port and a bottom port; the wafer assembly includes a top port wafer assembly having contacts located within a top port of the housing; the connector further includes a bottom port wafer assembly having contacts located in a bottom port of the housing; the bottom port wafer assembly including a bottom port row of conductors and a bottom port wafer protrusion at one end of the bottom port row of conductors; the side panel includes a second aperture; 16. The connector assembly of claim 15, wherein the bottom port wafer protrusion is inserted into the second aperture in the side plate to align the bottom port array of conductors with a surface of the printed circuit board.

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