Semiconductor device, high frequency device and method for manufacturing the same

Abstract

To provide a semiconductor device with adjustable characteristics.SOLUTION: A semiconductor device 100 comprises a conductive base 11, first and second chips mounted on the base, a first bonding wire 32 that electrically connects the first chip to the second chip and transmits high-frequency signals, and the base has a first aperture 15 that penetrates in the direction of thickness and overlaps at least a portion of the first bonding wire without intervening conductive layers as viewed from the thickness direction of the base.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a high-frequency device, and a manufacturing method thereof. [Background technology]

[0002] It is known to mount a plurality of chips, including a semiconductor chip, on a conductive base and electrically connect the plurality of chips to each other using bonding wires (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-113284 A [Patent Document 2] JP 2003-318329 A [Patent Document 3] JP 2012-104792 A Summary of the Invention [Problem to be solved by the invention]

[0004] The characteristics may differ due to differences in height and length of the bonding wires that electrically connect the chips together, making it difficult to adjust the characteristics.

[0005] The present disclosure has been made in consideration of the above problems, and has an object to enable adjustment of characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising a conductive base, a first chip and a second chip mounted on the base, and a first bonding wire electrically connecting the first chip and the second chip and transmitting a high-frequency signal, wherein the base has a first opening that penetrates in a thickness direction and overlaps at least a portion of the first bonding wire when viewed from the thickness direction of the base without a conductive layer in between. Effect of the Invention

[0007] According to the present disclosure, it is possible to adjust the characteristics. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of FIG. [Diagram 3] FIG. 3 is a circuit diagram of one set in the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a plan view of the high-frequency device according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view taken along line AA of FIG. [Figure 6] FIG. 6 is a cross-sectional view of the high-frequency device according to the first comparative example. [Figure 7] FIG. 7 is a cross-sectional view illustrating a first example of the high-frequency device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view illustrating a second example of the high-frequency device in accordance with the first embodiment. [Figure 9] FIG. 9 is a flowchart illustrating a method for manufacturing the high-frequency device according to the first embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 11] FIG. 11 is a circuit diagram of one set in the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a plan view of a semiconductor device in accordance with a third embodiment. [Figure 13]FIG. 13 is a cross-sectional view of a high-frequency device according to a third embodiment. [Figure 14] FIG. 14 is a circuit diagram of one set in the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including a conductive base, a first chip and a second chip mounted on the base, and a first bonding wire that electrically connects the first chip and the second chip and transmits a high-frequency signal, the base having a first opening that penetrates the base in a thickness direction and overlaps at least a portion of the first bonding wire without sandwiching a conductive layer when viewed from the thickness direction of the base, thereby making it possible to adjust the characteristics of the first bonding wire and to adjust the characteristics of the semiconductor device. (2) In the above (1), a first terminal provided outside the base, a second terminal provided outside the base, a second bonding wire electrically connecting the first terminal and the first chip, and a third bonding wire electrically connecting the second terminal and the second chip may be provided, whereby the characteristics of the first bonding wire provided between the first terminal and the second terminal can be adjusted. (3) In the above (2), the first chip may be a semiconductor chip having a transistor that amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal, thereby making it possible to adjust the characteristics of an inductor connected to the transistor. (4) In the above (3), the second chip may include a dielectric substrate and an electrode provided on the dielectric substrate, a capacitor is formed between the electrode and the base, and the first bonding wire and the third bonding wire are connected to the electrode. This makes it possible to adjust the characteristics of an inductor connected to the semiconductor chip in the T-shaped circuit of the LCL. (5) In the above (4), the second chip, the first bonding wire, and the third bonding wire may form a matching circuit that matches an impedance seen from the second terminal to the third bonding wire with an impedance seen from the first bonding wire to the semiconductor chip, thereby adjusting the characteristics of the matching circuit of a transistor. (6) In the above (1), the semiconductor device includes a third chip mounted on the base, and the semiconductor device includes a first terminal provided outside the base, a second terminal provided outside the base, a second bonding wire electrically connecting the first terminal and the first chip, a third bonding wire electrically connecting the second chip and the third chip, and a fourth bonding wire electrically connecting the second terminal and the third chip, and the base may have a second opening penetrating in a thickness direction and overlapping at least a part of the third bonding wire without sandwiching a conductive layer when viewed from the thickness direction of the base. This allows the characteristics of both the first and third bonding wires to be adjusted independently. (7) In the above (6), the first chip may be a semiconductor chip having a transistor that amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal, the second chip may include a first dielectric substrate and a first electrode provided on the first dielectric substrate, a first capacitor is formed between the first electrode and the base, the first bonding wire and the third bonding wire are connected to the first electrode, and the third chip may include a second dielectric substrate and a second electrode provided on the second dielectric substrate, a second capacitor is formed between the second electrode and the base, and the third bonding wire and the fourth bonding wire are connected to the second electrode. This allows the characteristics of both the first and third bonding wires to be adjusted independently. (8) In any one of (1) to (7) above, a resin layer may be provided on the base to seal the first chip, the second chip, and the first bonding wires, thereby making it possible to adjust the shape characteristics of the first bonding wires, the shape of which cannot be finely adjusted. (9) One embodiment of the present disclosure is a high-frequency device including a semiconductor device according to any one of (1) to (8), an insulating substrate, and a mounting board including a first conductor layer provided on the insulating substrate, the first conductor layer mounting the semiconductor device, and having a third opening at least partially overlapping the first opening without sandwiching a conductor layer when viewed in a thickness direction of the insulating substrate, whereby the characteristics of the first bonding wire can be adjusted. (10) In the above (9), a second conductive layer may be provided on a surface of the insulating substrate opposite to the first conductive layer and overlapping the third opening without sandwiching a conductive layer when viewed in a thickness direction of the insulating substrate, thereby making it possible to adjust the characteristics of the first bonding wire. (11) In the above (9), a third conductor layer may be provided inside the insulating substrate and overlapping the third opening without sandwiching a conductor layer when viewed in a thickness direction of the insulating substrate, thereby making it possible to adjust the characteristics of the first bonding wire. (12) One embodiment of the present disclosure is a method for manufacturing a high-frequency device, including the steps of: preparing a semiconductor device according to any one of (1) to (8), preparing a plurality of mounting substrates having different heights of reference potential surfaces that overlap at least a portion of the first opening when viewed from a thickness direction of the mounting substrate when the semiconductor device is mounted on an upper surface of the mounting substrate, acquiring information on high-frequency characteristics of the semiconductor device, selecting one mounting substrate from the plurality of mounting substrates based on the acquired information, and mounting the semiconductor device on the selected one mounting substrate, thereby making it possible to adjust the characteristics of the high-frequency device.

[0010] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices, high frequency devices, and methods of manufacturing the same according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] Fig. 1 is a plan view of a semiconductor device according to Example 1. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. The thickness direction of base 11 is the Z direction, the extension direction of a straight line connecting terminals 13 and 12 is the X direction, and the direction perpendicular to the X direction and the Z direction is the Y direction.

[0012] As shown in Figures 1 and 2, the semiconductor device 100 of the first embodiment has a structure in which a semiconductor chip 20 and a passive element chip 25 mounted on a base 11 of a conductive lead frame 10 are sealed with a resin layer 14. The lead frame 10 has a base 11 and terminals 12 and 13. The base 11 and the terminals 12 and 13 are not in contact with each other. The base 11 is a die pad, and the terminals 12 and 13 are leads. A connection bar that connects the base 11, the terminals 12 and the terminals 13 before cutting is omitted from the illustration. The lower surfaces of the base 11 and the terminals 12 and 13 are exposed from the lower surface of the resin layer 14.

[0013] The base 11 includes portions 11a to 11c and has an H-shaped planar shape. The portion 11a is closer to the terminal 12 than the portion 11b, and the portion 11b is closer to the terminal 13 than the portion 11a. The terminal 12, the semiconductor chip 20, the passive element chip 25, and the terminal 13 are arranged in order in the negative direction of the X direction. Two sets 16 of the terminal 12, the semiconductor chip 20, the passive element chip 25, and the terminal 13 are provided, and the two sets 16 are arranged in the Y direction. The number of sets 16 may be one, or three or more.

[0014] A semiconductor chip 20 is mounted on the portion 11a, and a passive element chip 25 is mounted on the portion 11b. The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. The substrate 21 is, for example, a semiconductor substrate. The electrodes 22 and 23 are provided on the upper surface of the substrate 21. The electrode 24 is provided on the lower surface of the substrate 21.

[0015] The passive element chip 25 includes a substrate 26 and electrodes 27 and 28. The substrate 26 is, for example, a dielectric substrate. The electrode 27 is provided on the upper surface of the substrate 26, and the electrode 28 is provided on the lower surface of the substrate 26. A conductive bonding layer 35 bonds the base 11 to the electrodes 24 and 28. The electrodes 24 and 28 are electrically connected to the base 11 and short-circuited. The bonding wire 31 electrically connects the terminal 12 to the electrode 23. The bonding wire 32 electrically connects the electrode 22 to the electrode 27. The bonding wire 33 electrically connects the electrode 27 to the terminal 13.

[0016] Between the portions 11a and 11b of the base 11 is an opening 15 of the base 11, where the base 11 is not provided and a resin layer 14 is provided. When viewed from the Z direction, a part of the bonding wire 32 overlaps the opening 15. No conductive layer is sandwiched between the bonding wire 32 and the opening 15.

[0017] FIG. 3 is a circuit diagram of one set in the semiconductor device according to the first embodiment. As shown in FIG. 3, the set 16 includes terminals 12 and 13, a transistor Q, inductors L1 to L3, and a capacitor C1. The transistor Q is, for example, a FET (Field Effect Transistor), and has a source S, a gate G, and a drain D. The inductors L3 and L2 are connected in series between the terminal 13 and the gate G. The capacitor C1 is shunt-connected to a node between the inductors L3 and L2. The source S is grounded. The inductor L1 is connected between the drain D and the terminal 12. The inductors L3, L2, and the capacitor C1 form a matching circuit 18, which is an LCL T-type circuit. The matching circuit 18 matches the impedance seen from the terminal 13 to the impedance seen from the matching circuit 18 to the impedance seen from the matching circuit 18 to the transistor Q.

[0018] The transistor Q is provided on a semiconductor chip 20. The source S, gate G and drain D correspond to electrodes 24, 22 and 23, respectively. The electrode 22 is an input electrode to which a high frequency signal is input, and the electrode 23 is an output electrode to which a high frequency signal is output. The capacitor C1 is provided on a passive element chip 25, and corresponds to a substrate 26 and electrodes 27 and 28 that sandwich the substrate 26. The inductors L1, L2 and L3 correspond to bonding wires 31, 32 and 33, respectively.

[0019] The high frequency signal input to terminal 13 passes through matching circuit 18 and is input to gate G. The high frequency signal amplified by transistor Q passes through inductor L1 from drain D and is output to terminal 12. Inductor L1 may form a part of the matching circuit. When semiconductor device 100 is used in an amplifier circuit for a mobile communication base station, the frequency of the high frequency signal is, for example, 0.5 GHz to 10 GHz. The frequency of the high frequency signal may be 10 GHz or higher.

[0020] The transistor Q is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). When the transistor Q has a GaN HEMT, the substrate 21 is, for example, a silicon carbide substrate or a gallium nitride substrate. The electrodes 22 to 24 are, for example, metal layers such as gold layers.

[0021] When the passive element chip 25 has a capacitor C1, the substrate 26 is, for example, a dielectric substrate, such as an alumina (aluminum oxide) substrate, a high dielectric ceramic substrate having a higher dielectric constant than an alumina substrate, a silicon substrate, or a gallium arsenide substrate. The electrodes 27 and 28 are, for example, metal layers such as gold layers.

[0022] FIG. 4 is a plan view of the high-frequency device according to the first embodiment. FIG. 5 is a cross-sectional view taken along the line AA of FIG. 4. In the high-frequency device 105 of the first embodiment, the semiconductor device 100 is mounted on a mounting board 50a. The mounting board 50a includes an insulating board 46, conductive layers 40 and 48, and a via 47. The conductive layer 40 is provided on the upper surface of the insulating board 46, and the conductive layer 48 is provided on the lower surface of the insulating board 46. The conductive layer 40 includes a ground layer 41, and signal lines 42 and 43. The ground layer 41 includes ground layers 41a and 41b, and the conductive layer 40 is not provided between the ground layers 41a and 41b, but an opening 45. The conductive layer 48 and the ground layers 41a and 41b are electrically connected to each other by the via 47 and short-circuited.

[0023] The base 11 of the semiconductor device 100 is electrically connected to the ground layer 41 by using the bonding layer 36 and is short-circuited. When viewed from the Z direction, at least a part of the opening 15 of the base 11 and at least a part of the opening 45 of the ground layer 41 overlap with each other. The terminals 12 and 13 of the semiconductor device 100 are electrically connected to the signal lines 42 and 43 by using the bonding layer 36 and are short-circuited. A reference potential such as a ground potential supplied to the conductive layer 48 is supplied to the base 11 through the via 47, the ground layer 41, and the bonding layer 36. This makes the conductive layer 48 and the base 11 have the same potential. A high-frequency signal is input from the signal line 43 to the terminal 13 through the bonding layer 36. A high-frequency signal is output from the terminal 12 to the signal line 42 through the bonding layer 36. The insulating substrate 46 is an organic insulating substrate such as a glass epoxy resin substrate. The conductive layers 40, 48 and the via 47 are metal layers such as a copper layer.

[0024] [Comparative Example 1] 6 is a cross-sectional view of a high-frequency device according to Comparative Example 1. In a high-frequency device 112 of Comparative Example 1, an opening 15 is not provided in a base 11 of a semiconductor device 110. An opening 45 is not provided in a ground layer 41 of a mounting board 50b. When a height H1 of a bonding wire 32 from a base 11 and a length of the bonding wire 32 change, a high-frequency characteristic (e.g., impedance) of the bonding wire 32 changes. This changes a high-frequency characteristic of a matching circuit 18, and a high-frequency characteristic of the semiconductor device 110 changes.

[0025] When the high frequency characteristics of the bonding wires 31 and 33 change, it is possible to adjust the high frequency characteristics of the high frequency device 112 on the mounting board 50b outside the semiconductor device 110. However, when the high frequency characteristics of the bonding wire 32 change, it is difficult to adjust the high frequency characteristics on the mounting board 50b.

[0026] [Explanation of Example 1] Fig. 7 is a cross-sectional view showing Example 1 of the high-frequency device according to the embodiment 1. As shown in Fig. 7, in the high-frequency device 106 of the embodiment 1, a mounting board 50b is used, and an opening 15 is not provided in the ground layer 41. The other configurations are the same as those in Fig. 5, and therefore description thereof will be omitted.

[0027] Fig. 8 is a cross-sectional view showing a second example of the high-frequency device in accordance with the first embodiment. As shown in Fig. 8, in the high-frequency device 107 of the first embodiment, a mounting board 50c is used, and an opening 15 is provided in a ground layer 41. A conductor layer 49 inside the mounting board 50c is provided below the opening 45. The conductor layer 49 is electrically connected to the conductor layer 48 by a via 47, and is short-circuited.

[0028] 5, in the high-frequency device 105, the conductive layer 48 below the bonding wire 32 serves as the reference potential plane 39. The distance between the bonding wire 32 and the reference potential plane 39 is H2.

[0029] 7, in the high-frequency device 106, the ground layer 41 below the bonding wire 32 serves as the reference potential plane 39. The distance between the bonding wire 32 and the reference potential plane 39 is H2a.

[0030] 8, in the high-frequency device 107, the conductive layer 49 below the bonding wire 32 serves as the reference potential plane 39. The distance between the bonding wire 32 and the reference potential plane 39 is H2b.

[0031] The height H1 is, for example, 100 μm to 300 μm, the thickness of the base 11 is, for example, 100 μm to 300 μm, and the thickness of the mounting substrates 50a to 50c is, for example, 200 μm to 1000 μm. Therefore, the distances H2, H2a, and H2b can be changed within a range of, for example, about 200 μm to 2000 μm.

[0032] Fig. 9 is a flowchart showing a method for manufacturing a high-frequency device according to Example 1. As shown in Fig. 9, a plurality of mounting substrates 50a to 50c having different heights from the upper surfaces of the mounting substrates 50a to 50c to the reference potential surface 39 are prepared (step S10). Next, the semiconductor device 100 of Example 1 is prepared (step S12).

[0033] Next, information on the high frequency characteristics of the semiconductor device 100 is obtained (step S14). The information on the high frequency characteristics can be obtained, for example, by measuring the high frequency characteristics of the semiconductor device 100. The high frequency characteristics can be measured, for example, by measuring small signal characteristics such as the S parameter between the terminals 13 and 12, and large signal characteristics such as the output power relative to the input power when a large signal with a large amplitude is input to the semiconductor device 100. The information on the high frequency characteristics may be, for example, information on the shape of the bonding wire 32.

[0034] Next, based on the measurement result of step S14, one mounting board is selected from the multiple mounting boards 50a to 50c (step S16). For example, the mounting board 50a, 50b, or 50c is selected so that the high-frequency characteristics when the semiconductor device 100 is mounted on the mounting boards 50a to 50c are desired characteristics. Next, the semiconductor device 100 is mounted on the selected mounting board 50a, 50b, or 50c (step S18). Through the above steps, the high-frequency device 105, 106, or 107 is manufactured.

[0035] In this way, in the first embodiment, the distances H2, H2a, and H2b between the bonding wire 32 and the reference potential surface 39 can be changed by changing the mounting boards 50a to 50c. When the distances H2, H2a, and H2b change, the capacitance between the bonding wire 32 and the reference potential surface 39 changes. This changes the high frequency characteristics of the bonding wire 32. Even if the characteristics of the semiconductor device 100 differ from the desired values ​​because the height H1 or length of the bonding wire 32 differs from the desired value and the high frequency characteristics of the bonding wire 32 differ from the desired value, the high frequency characteristics of the bonding wire 32 can be brought closer to the desired value. Therefore, the high frequency characteristics of the high frequency device can be brought closer to the desired value.

[0036] [Example 2] Fig. 10 is a plan view of a semiconductor device according to a second embodiment. As shown in Fig. 10, in a semiconductor device 101 of the second embodiment, electrodes 27a and 27b are provided on the upper surface of a passive element chip 25. An inductor L4 is connected between the electrodes 27a and 27b. The inductor L4 is, for example, a spiral inductor, and is illustrated in Fig. 10 using an inductor symbol. A bonding wire 32 electrically connects the electrodes 22 and 27a. A bonding wire 33 electrically connects the electrode 27b and a terminal 13. The other configurations are the same as those in Fig. 2, and therefore description thereof will be omitted.

[0037] FIG. 11 is a circuit diagram of one set in the semiconductor device according to the second embodiment. As shown in FIG. 11, an inductor L4 is connected in series between inductors L2 and L3. A capacitor C1 is shunt-connected between inductors L2 and L4. A capacitor C2 is shunt-connected between inductors L4 and L3. Inductors L2 to L4 and capacitors C1 and C2 form a matching circuit 18. Inductor L4, capacitors C1 and C2 are provided on a passive element chip 25. Inductor L4 is a spiral inductor formed on a substrate 26. Capacitor C1 corresponds to the substrate 26 and electrodes 27a and 28 that sandwich the substrate 26. Capacitor C2 corresponds to the substrate 26 and electrodes 27b and 28 that sandwich the substrate 26. The other configurations are the same as those in FIG. 3, and will not be described.

[0038] [simulation] The resonance frequency of the matching circuit 18 was simulated for a circuit A in which the openings 15 and 45 were not provided, and a circuit B in which the opening 15 was provided and no conductive layer overlapping the opening 15 was provided on the mounting board 50a. The simulation conditions are as follows. L1:0.5nH, L2:0.5nH, L3:1nH, L4:0.5nH C1: 2pF, C2: 4pF Q: GaN-HEMT, saturated power is 15W H1: 400μm H2: 1400μm

[0039] Two resonant frequencies are formed for the reflection characteristic S11 from the terminal 13 to the matching circuit 18. The two resonant frequencies are as follows. Circuit A: 3.64GHz, 7.82GHz Circuit B: 3.36GHz, 7.38GHz As described above, the high-frequency characteristics of matching circuit 18 can be changed by changing the distance between bonding wire 32 and reference potential surface 39. Therefore, it can be seen that the high-frequency characteristics of matching circuit 18 can be adjusted by selecting mounting boards 50a to 50c.

[0040] [Example 3] FIG. 12 is a plan view of a semiconductor device according to a third embodiment. FIG. 13 is a cross-sectional view of a high-frequency device according to a third embodiment. As shown in FIG. 12 and FIG. 13, in the semiconductor device 102 and the high-frequency device 108, the base 11 has portions 11d and 11e in addition to portions 11a to 11c. The portion 11d is closer to the terminal 13 than the portion 11b. The portion 11e connects the portion 11b and the portion 11d. An opening 15a is provided between the portions 11b and 11d. A passive element chip 25a is mounted on the portion 11d. The passive element chip 25a includes a substrate 26a, and electrodes 27a and 28a. A bonding wire 34 electrically connects the electrode 27 and the electrode 27a. A bonding wire 33 electrically connects the electrode 27a and the terminal 13.

[0041] In the mounting board 50c, the conductor layer 40 may be provided so as to overlap the opening 15 when viewed from the Z direction, or the opening 45 may be provided. When the opening 45 is provided, the conductor layer 49 may or may not be provided. In addition, in the mounting board 50c, the conductor layer 40 may be provided so as to overlap the opening 15a when viewed from the Z direction, or the opening 45a may be provided. When the opening 45a is provided, the conductor layer 49a may or may not be provided.

[0042] Fig. 14 is a circuit diagram of one set in the semiconductor device according to the third embodiment. As shown in Fig. 14, the capacitor C1 is provided in the passive element chip 25, and the capacitor C2 is provided in the passive element chip 25a. The inductor L4 corresponds to the bonding wire 34. The other configurations are the same as those in Fig. 11, and the description will be omitted.

[0043] In the third embodiment, a plurality of mounting boards 50c are prepared, each of which has a different height of the reference potential surface overlapping the opening 15 and a different height of the reference potential surface overlapping the opening 15a when viewed from the Z direction. Based on information on the high-frequency characteristics of the semiconductor device 102, one mounting board 50c is selected from the plurality of mounting boards 50c. This allows the high-frequency characteristics of the bonding wires 32 and 34 to be adjusted independently. This allows the characteristics of the matching circuit 18 to be further adjusted.

[0044] According to the first to third embodiments, a semiconductor chip 20 (first chip) and a passive element chip 25 (second chip) are mounted on a conductive base 11. The bonding wire 32 (first bonding wire) in the first to third embodiments electrically connects the semiconductor chip 20 and the passive element chip 25 to transmit a high-frequency signal. The base 11 has an opening 15 (first opening) that penetrates in the thickness direction and overlaps with at least a part of the bonding wire 32 when viewed from the thickness direction of the base 11. No conductive layer is provided between the bonding wire 32 and the opening 15. That is, when viewed from the Z direction, the bonding wire 32 and the opening 15 overlap without sandwiching a conductive layer.

[0045] 9, information on the high frequency characteristics of the semiconductor device is acquired, and one mounting board on which the semiconductor device is to be mounted is selected in step S16. In step S18, the semiconductor device is mounted on the selected mounting board. This makes it possible to adjust the high frequency characteristics of the bonding wires 32 in the semiconductor device. Thus, the characteristics of the semiconductor device can be adjusted.

[0046] Both the first chip and the second chip may be passive element chips. An example in which the outline of the base 11 viewed from the Z direction is a notch has been described as the opening 15. The portion 11c may not be provided, and the opening 15 may be between the portions 11a and 11b. The opening 15 may be a closed space surrounded by the base 11. If the portions 11a and 11b of the base 11 are separated and the portion 11c is not provided, the parasitic inductance between the reference potential of the semiconductor chip 20 and the reference potential of the passive element chip 25 increases. Therefore, the portion 11c may connect the portions 11a and 11b.

[0047] Terminal 12 (first terminal) is provided outside base 11 and outputs a high frequency signal. Terminal 13 (second terminal) is provided outside base 11 and inputs a high frequency signal. Bonding wire 31 (second bonding wire) electrically connects terminal 12 to semiconductor chip 20. Bonding wire 33 (third bonding wire) electrically connects terminal 13 to passive element chip 25. This makes it possible to adjust the high frequency characteristics of bonding wire 32 provided between terminal 13 for inputting a signal and terminal 12 for outputting a signal.

[0048] The semiconductor chip 20 has a transistor Q that amplifies a high-frequency signal input to a terminal 13 and outputs the amplified high-frequency signal to a terminal 12. This makes it possible to adjust the high-frequency characteristics of an inductor connected to the amplifying transistor Q.

[0049] The passive element chip 25 includes a substrate 26, which is a dielectric, and an electrode 27 provided on the substrate 26, and a capacitor C1 is formed between the electrode 27 and the base 11. Bonding wires 32 and 33 are connected to the electrode 27. This makes it possible to adjust the high frequency characteristics of the inductor connected to the semiconductor chip 20 in the LCL T-shaped circuit formed by the passive element chip 25 and the bonding wires 32 and 33.

[0050] The passive element chip 25 and the bonding wires 32 and 33 form a matching circuit 18 that matches the impedance of the bonding wire 33 as seen from the terminal 13 with the impedance of the semiconductor chip 20 as seen from the bonding wire 32. This makes it possible to adjust the high frequency characteristics of the matching circuit 18 of the transistor Q.

[0051] Resin layer 14 is provided on base 11 and seals semiconductor chip 20, passive element chip 25, and bonding wires 31 to 33. In this case, since bonding wire 32 is inside resin layer 14, the shape of bonding wire 32 cannot be finely adjusted. However, by providing opening 15, the high frequency characteristics of bonding wire 32 can be adjusted.

[0052] In the mounting board 50b, the conductive layer 40 (first conductive layer) is provided on the insulating substrate 46, the semiconductor device 100 or 101 is mounted thereon, and the opening 15 overlaps with the conductive layer without sandwiching the conductive layer when viewed from the Z direction.

[0053] In mounting boards 50a and 50c, the conductor layer 40 (first conductor layer) has an opening 45 (third opening) that at least partially overlaps with the opening 15 without sandwiching the conductor layer when viewed from the Z direction.

[0054] In the mounting board 50a, the conductive layer 48 (second conductive layer) is provided on the surface of the insulating substrate 46 opposite the conductive layer 40, and overlaps the opening 45 when viewed from the Z direction without sandwiching a conductive layer therebetween.

[0055] In the mounting board 50c, the conductive layer 49 (third conductive layer) is provided inside the insulating substrate 46 and overlaps the opening 45 without sandwiching a conductive layer when viewed from the Z direction. A plurality of mounting boards 50c in which the height of the conductive layer 49 in the Z direction is different may be prepared.

[0056] In this manner, a mounting substrate for mounting the semiconductor devices 100 and 101 is selected from the mounting substrates 50a and 50c, whereby the high frequency characteristics of the bonding wires 32 can be adjusted.

[0057] In the above description, the opening 45 is a portion between the separated ground layers 41a and 41b. The opening 45 may be a cutout in the outline of the ground layer 41. The opening 45 may be a closed space surrounded by the ground layer 41.

[0058] In the third embodiment, the bonding wire 31 (second bonding wire) electrically connects the terminal 12 and the semiconductor chip 20. The bonding wire 32 (first bonding wire) electrically connects the semiconductor chip 20 and the passive element chip 25. The bonding wire 34 (third bonding wire) electrically connects the passive element chip 25 and the passive element chip 25a (third chip). The bonding wire 33 (fourth bonding wire) electrically connects the passive element chip 25a and the terminal 13. The base 11 has an opening 15 that overlaps at least a part of the bonding wire 32 without sandwiching a conductive layer when viewed from the Z direction, and an opening 15a (second opening) that overlaps at least a part of the bonding wire 34 without sandwiching a conductive layer. This allows the high frequency characteristics of both the bonding wires 32 and 34 to be adjusted independently.

[0059] The semiconductor chip 20 has a transistor Q that amplifies a high-frequency signal input to the terminal 13 and outputs the amplified high-frequency signal to the terminal 12. The passive element chip 25 includes a substrate 26 (first dielectric substrate) and an electrode 27 (first electrode) provided on the substrate 26, and a first capacitor C1 is formed between the electrode 27 and the base 11. The passive element chip 25a includes a substrate 26a (second dielectric substrate) and an electrode 27a (second electrode) provided on the substrate 26a, and a first capacitor C2 is formed between the electrode 27a and the base 11. This allows the high-frequency characteristics of both bonding wires 32 and 34, which correspond to inductors L2 and L4 in the matching circuit 18, to be adjusted independently.

[0060] Although an example of an input matching circuit has been described as the matching circuit 18, a passive element chip may be provided between the semiconductor chip 20 and the terminal 13, and the opening 15 of the base 11 may be provided so as to overlap a bonding wire that electrically connects the semiconductor chip 20 and the passive element chip. In this manner, the transistor Q may amplify a high-frequency signal input to the terminal 12 and output the amplified high-frequency signal to the terminal 13. Although an example in which the matching circuit 18 is provided as the bonding wire 32 has been described, the bonding wire 32 that electrically connects the first chip and the second chip may be any bonding wire that propagates a high-frequency signal.

[0061] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0062] 10 Lead frame 11. Base 11a, 11b, 11c, 11d, 11e parts 12, 13 Terminals 14 Resin layer 15, 15a, 45, 45a opening 16 sets 18 Matching circuit 20. Semiconductor Chips 21, 26, 26a Board 22, 23, 24, 27, 27a, 28, 28a electrode 25, 25a Passive element chip 31, 32, 33, 34 Bonding wire 35, 36 bonding layer 39 Reference potential surface 40, 48, 49, 49a Conductor layer 41, 41a, 41b Ground layer 42, 43 Signal line 50a, 50b, 50c Mounting board 100, 101, 102, 110 Semiconductor device 105, 106, 107, 108, 112 High frequency devices

Claims

1. A conductive base; a first chip and a second chip mounted on the base; a first bonding wire electrically connecting the first chip and the second chip and transmitting a high-frequency signal; Equipped with The base has a first opening penetrating in a thickness direction and overlapping at least a portion of the first bonding wire without a conductive layer therebetween when viewed from the thickness direction of the base.

2. A first terminal provided outside the base; A second terminal provided outside the base; a second bonding wire electrically connecting the first terminal and the first chip; a third bonding wire electrically connecting the second terminal and the second chip; The semiconductor device according to claim 1 .

3. 3. The semiconductor device according to claim 2, wherein the first chip is a semiconductor chip having a transistor that amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal.

4. The semiconductor device according to claim 3, wherein the second chip comprises a dielectric substrate and an electrode provided on the dielectric substrate, a capacitor is formed between the electrode and the base, and the first bonding wire and the third bonding wire are connected to the electrode.

5. 5. The semiconductor device according to claim 4, wherein the second chip, the first bonding wire and the third bonding wire form a matching circuit that matches an impedance seen from the second terminal to the third bonding wire with an impedance seen from the first bonding wire to the semiconductor chip.

6. a third chip mounted on the base; The semiconductor device includes: A first terminal provided outside the base; A second terminal provided outside the base; a second bonding wire electrically connecting the first terminal and the first chip; a third bonding wire electrically connecting the second chip and the third chip; a fourth bonding wire electrically connecting the second terminal and the third chip; Equipped with 2 . The semiconductor device according to claim 1 , wherein the base has a second opening penetrating in a thickness direction and overlapping at least a portion of the third bonding wire when viewed in the thickness direction of the base without a conductive layer therebetween.

7. the first chip is a semiconductor chip having a transistor that amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal, the second chip comprises a first dielectric substrate and a first electrode provided on the first dielectric substrate, a first capacitor is formed between the first electrode and the base, the first bonding wire and the third bonding wire are connected to the first electrode, The semiconductor device of claim 6, wherein the third chip comprises a second dielectric substrate and a second electrode provided on the second dielectric substrate, a second capacitor is formed between the second electrode and the base, and the third bonding wire and the fourth bonding wire are connected to the second electrode.

8. 8. The semiconductor device according to claim 1, further comprising a resin layer provided on the base, the resin layer sealing the first chip, the second chip, and the first bonding wires.

9. A semiconductor device according to any one of claims 1 to 7, a mounting board including an insulating substrate, and a first conductor layer provided on the insulating substrate, the first conductor layer having the semiconductor device mounted thereon and a third opening at least partially overlapping with the first opening when viewed in a thickness direction of the insulating substrate without a conductor layer therebetween; A high frequency device comprising:

10. 10. The high-frequency device according to claim 9, further comprising a second conductive layer provided on a surface of the insulating substrate opposite the first conductive layer and overlapping the third opening without a conductive layer sandwiched between the second conductive layer and the first conductive layer when viewed in the thickness direction of the insulating substrate.

11. The high frequency device according to claim 9 , further comprising a third conductive layer provided inside the insulating substrate and overlapping the third opening when viewed in a thickness direction of the insulating substrate without sandwiching a conductive layer therebetween.

12. A step of preparing a semiconductor device according to any one of claims 1 to 7; preparing a plurality of mounting substrates each having a different height of a reference potential surface that at least partially overlaps with at least a portion of the first opening when viewed in a thickness direction of the mounting substrate when the semiconductor device is mounted on an upper surface of the mounting substrate; acquiring information regarding high frequency characteristics of the semiconductor device; selecting one mounting board from the plurality of mounting boards based on the acquired information; mounting the semiconductor device on the selected one of the mounting boards; A method for manufacturing a high frequency device comprising the steps of:

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