Semiconductor device and electronic apparatus

Abstract

To provide a semiconductor device and an electronic apparatus with high reliability.SOLUTION: In an electronic apparatus 1, a semiconductor device 100 includes a semiconductor chip 110 having a first surface (lower surface) existing on a substrate 10 side, and a second surface (upper surface) on a side opposite to the first surface, in which the second surface is a circuit surface, a re-wiring layer 160 provided on the second surface side, a first bump 140A connecting the substrate and the first surface of the semiconductor chip, and a metal pillar 150 connecting the substrate and the first surface of the semiconductor chip.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and an electronic device. [Background technology]

[0002] Conventionally, there has been a mounting structure having a circuit board, a joint provided on the circuit board, and an electronic component connected to the circuit board via the joint, the joint having a solder base and a metal layer formed on a surface of the solder base and having a lower electrical resistivity than the solder base (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-116980 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a conventional mounting structure (semiconductor device), when the mounting density of the joints is increased, solder bridges that connect the joints having solder bases to each other may occur, which may reduce the reliability of the semiconductor device. This is also true for electronic devices that include semiconductor devices.

[0005] It is therefore an object of the present invention to provide a highly reliable semiconductor device and electronic device. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment of the present disclosure includes a semiconductor chip having a first surface located on the substrate side and a second surface opposite the first surface, the second surface being a circuit surface, a redistribution layer provided on the second surface side, a first bump connecting the first surface of the semiconductor chip to the substrate, and a metal pillar connecting the first surface of the semiconductor chip to the substrate. Effect of the Invention

[0007] It is possible to provide a highly reliable semiconductor device and electronic device. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram illustrating an example of a cross-sectional configuration of a semiconductor device 100 according to an embodiment. [Diagram 2] 13 is a diagram showing an example of the arrangement of regions A and B, solder balls 140A and 140B, and a metal pillar 150. FIG. [Diagram 3] 10 is a diagram showing an example of a simulation result using a simulation model of the electronic device 1. FIG. [Figure 4] FIG. 13 is a diagram showing an electronic device 1A according to a first modified example of the embodiment. [Diagram 5] FIG. 13 is a diagram illustrating a semiconductor device 100B and an electronic device 1 according to a second modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in which the semiconductor device and electronic device are applied. In the following, the same elements are denoted by the same reference numerals, and duplicated descriptions may be omitted.

[0010] In the following, the XYZ coordinate system is defined and explained. The direction parallel to the X axis (X direction), the direction parallel to the Y axis (Y direction), and the direction parallel to the Z axis (Z direction) are mutually perpendicular. The X direction is an example of a first axis direction, the Y direction is an example of a second axis direction, and the Z direction is an example of a third axis direction. In the following, for convenience of explanation, the -Z direction side may be referred to as the lower side or bottom, and the +Z direction side as the upper side or top, but this does not represent a universal relationship between the top and bottom. In addition, a planar view refers to a view on an XY plane.

[0011] In the following description, the length, width, thickness, etc. of each part may be exaggerated to make the configuration easier to understand. Furthermore, the terms parallel, right angle, orthogonal, horizontal, vertical, up and down, etc., are permitted to be deviated to the extent that the effect of the embodiment is not impaired.

[0012] In the following, the term "millimeter wave" or "millimeter wave band" includes the quasi-millimeter wave band of 24 GHz to 30 GHz in addition to the frequency band of 30 GHz to 300 GHz.

[0013] <Embodiment> Fig. 1 is a diagram showing an example of a cross-sectional configuration of a semiconductor device 100 according to an embodiment. As an example, the semiconductor device 100 has a rectangular shape in a plan view (XY plan view), and Fig. 1 shows a cross-sectional configuration parallel to the XZ plane. Fig. 1 shows an XZ cross section at a certain position in the Y direction.

[0014] The semiconductor device 100 includes, for example, a semiconductor chip 110, a mold resin 120, metal pillars 130A and 130B, solder balls 140A and 140B, a metal pillar 150, a rewiring layer 160, and an antenna 170. The solder ball 140A is an example of a first bump, and the solder ball 140B is an example of a first bump. The metal pillar 150 is an example of a metal pillar. Note that in FIG. 1, the number of solder balls 140A and 140B and the metal pillars 150 are reduced so that the cross-sectional configuration of the semiconductor device 100 can be easily understood.

[0015] As an example, the semiconductor device 100 is mounted on an RF (Radio Frequency) board 10 via solder balls 140A and 140B and a metal pillar 150. The semiconductor device 100 is mounted on the RF board 10 by a reflow process. The semiconductor device 100 is a semiconductor package including a semiconductor chip 110. The electronic device 1 of the embodiment includes the semiconductor device 100, the RF board 10, and a heat sink 20. The RF board 10 is an example of a substrate.

[0016] The semiconductor device 100 is, for example, a semiconductor package (Antenna in Package: AiP) that includes an antenna 170 as an RF antenna in the package. The semiconductor device 100 is, for example, a wireless communication device that can be mounted in a radio unit (Radio Unit: RU) at the front end of a base station, and the RF board 10 is, for example, a motherboard of the base station.

[0017] The AiP is structured to amplify signals in the built-in semiconductor chip 110 and radiate radio waves from an antenna 170. In other words, signal amplification and complex signal processing are performed within the semiconductor chip 110. The semiconductor chip 110 contains within a single package the functions of modulating and amplifying signals into high-frequency signals, and radiating radio waves into space via multiple antennas 170 that constitute an array antenna.

[0018] In recent mobile communication systems (for example, fifth generation mobile communication systems (5G)), millimeter wave band frequencies are being utilized or considered for utilization in order to support ultra-high speed communication, ultra-low latency, and multiple simultaneous connections. In order to realize high output in the AiP for base stations, it is necessary to arrange an RF chip including a heat generating part such as a power amplifier near the antenna 170 so that radio waves with low signal attenuation, low loss, and high output can be radiated from the antenna 170. For this reason, it is necessary to miniaturize the semiconductor device 100. In addition, since the semiconductor device 100 includes a plurality of antennas 170 realized by patch antennas, it is necessary to arrange the antennas 170 of a small size according to the short wavelength, and the pitch between the antennas 170 becomes short, so miniaturization is also required. In addition, since the semiconductor device 100 includes a high output power amplifier and the like, an extremely efficient heat dissipation mechanism is required.

[0019] <Areas A and B> The semiconductor device 100 has regions A and B in plan view. Here, description will be made using FIG. 2 in addition to FIG. 1. FIG. 2 is a diagram showing an example of an arrangement of regions A and B, solder balls 140A and 140B, and metal pillars 150. FIG. 2 shows the semiconductor device 100 from the -Z direction side (bottom side). FIG. 2 shows, as an example, solder balls 140A and 140B and metal pillars 150 arranged in an 18 x 18 array in the X-axis and Y-axis directions.

[0020] Region A is a rectangular region in which the semiconductor chip 110 is present in a plan view. Region A is located in the center of the semiconductor device 100 in a plan view. Region B is a rectangular annular region surrounding region A. More specifically, as an example, region A is a rectangular region overlapping with the semiconductor chip 110 in a plan view, region B is a rectangular annular region outside region A, and the outer edge of region B is equal to the outer edge of the rectangular region in which the semiconductor device 100 is present.

[0021] Of the components of the semiconductor device 100, the metal pillar 130A, the solder ball 140A, and the metal pillar 150 are located in an area A, and the metal pillar 130B and the solder ball 140B are located in an area B.

[0022] 2, in region A, solder balls 140A and metal pillars 150 are provided in a 14×14 array in the X-axis direction and the Y-axis direction. In region A, solder balls 140A and metal pillars 150 are mixed. In region B, solder balls 140B are arranged in a double rectangular ring shape so as to surround region A. The arrangement of the solder balls 140A and 140B and the metal pillars 150 will be described in detail later.

[0023] <RFボード10> The RF board 10 has pads 11A and 11B, a resist 12, and a metal part 15. The pads 11A and 11B are provided on the surface of the RF board 10 on the +Z direction side, and the resist 12 is provided on a portion of the surface of the RF board 10 on the +Z direction side where the pads 11A and 11B are not provided.

[0024] The pad 11A is provided in the region A, and the pad 11B is provided in the region B. The solder ball 140A and the metal pillar 150 of the semiconductor device 100 are connected to the upper surface of the pad 11A, and the lower surface of the pad 11A is connected to the metal part 15. The solder ball 140B of the semiconductor device 100 is connected to the pad 11B. As an example, the pad 11A is a pad (terminal) included in a path for dissipating heat of the semiconductor device 100 to the metal part 15 via the solder ball 140A and the metal pillar 150. The pad 11B is a pad (terminal) for transmitting a power supply and a clock signal of the semiconductor device 100.

[0025] As an example, the metal part 15 is provided in a through hole penetrating in the Z direction directly below the semiconductor chip 110 of the semiconductor device 100 of the RF board 10 for cooling the semiconductor chip 110. As an example, the metal part 15 is a mass of metal with high thermal conductivity such as aluminum or copper. The upper surface of the metal part 15 is connected to the lower surface of the pad 11A. The heat sink 20 is attached directly below the metal part 15. Note that a thermally conductive sheet or the like may be provided between the lower surface of the metal part 15 and the upper surface of the heat sink 20.

[0026] Heat emitted by the semiconductor chip 110 is conducted to the metal part 15 via the pads 111, the solder balls 140A, the metal pillars 150, and the pads 11A. The heat conducted to the metal part 15 is further conducted to the heat sink 20 and is discharged from the heat sink 20 into the air. In this manner, the semiconductor chip 110 is cooled. Note that the heat sink 20 is, for example, an air-cooled heat sink made of a metal with high thermal conductivity, such as aluminum or copper.

[0027] The pads 11A and 11B may be formed of, for example, a metal such as copper or aluminum. In particular, the pad 11A is preferably formed of a metal having high thermal conductivity such as copper or aluminum in order to contribute to heat dissipation of the semiconductor device 100.

[0028] The resist 12 is a protective film that protects the surface on the +Z direction side of the RF board 10. The upper surfaces of the pads 11A and 11B are exposed from the resist 12.

[0029] <Semiconductor chip 110> The semiconductor chip 110 is an RFIC manufactured by a semiconductor manufacturing process, and is manufactured, for example, based on a silicon substrate etc. The semiconductor chip 110 is covered with a molding resin 120 on all surfaces except the surface on the -Z direction side.

[0030] The surface of the semiconductor chip 110 on the +Z direction side is, for example, a circuit surface that inputs and outputs electrical signals when the semiconductor chip 110 operates as a circuit. For example, the semiconductor chip 110 uses the surface on the -Z direction side as a path for dissipating heat of the semiconductor chip 110.

[0031] Here, in order to further increase the circuit surface, the surface on the -Z direction side of the semiconductor chip 110 may be used as a path for dissipating heat from the semiconductor chip 110, and may also be used as a surface for inputting and outputting electrical signals when operating as a circuit. That is, the circuit surface of the semiconductor chip 110 may be the surface on the +Z direction side and a part of the surface on the -Z direction side. Note that, as an example, a form in which electrical signals are not inputted and outputted on the surface on the -Z direction side when operating as a circuit will be described here.

[0032] The semiconductor chip 110 has a pad 111 provided on the surface on the -Z direction side, and a pad 112 provided on the surface on the +Z direction side. A solder ball 140A and a metal pillar 150 are connected to the pad 111. A metal pillar 130A is connected to the pad 112. The pads 111 and 112 may be formed of a metal such as copper or aluminum, for example. In particular, the pad 111 is preferably formed of a metal with high thermal conductivity such as copper or aluminum, in order to contribute to heat dissipation of the semiconductor chip 110.

[0033] The semiconductor chip 110 also includes, for example, a wireless communication circuit such as a power amplifier for transmission and an LNA (Low Noise Amplifier) ​​for reception, and a control circuit for controlling a beam angle in beamforming, which will be described later. The wireless communication circuit and the control circuit are connected to a pad 112 via wiring or the like (not shown). The pad 112 is connected to an antenna 170 via a rewiring layer 160.

[0034] <Mold resin 120> The mold resin 120 is filled between the side and top surface of the semiconductor chip 110 and the metal pillars 130A and 130B. The mold resin 120 is formed of a thermosetting resin such as an epoxy resin, for example. As an example, the metal pillars 130A and 130B are formed with the rewiring layer 160 turned upside down, and the semiconductor chip 110 is connected to the metal pillar 130A. Then, the mold resin 120 is formed by filling the area around the semiconductor chip 110 with a thermosetting resin.

[0035] <Metal pillar 130A> A plurality of metal pillars 130A are provided in the region A. A plurality of metal pillars 130A are provided two-dimensionally in the region A. Each metal pillar 130A has a lower end connected to a pad 112 on the upper surface of the semiconductor chip 110 and an upper end extending to the upper surface of the molding resin 120. The upper end of the metal pillar 130A shown in FIG. 1 is connected to the wiring layer 161 on the lower surface of the rewiring layer 160. The metal pillar 130A shown in FIG. 1 transmits an electric signal between the pad 112 of the semiconductor chip 110 and the wiring layer 161 on the lower surface of the rewiring layer 160. In the present embodiment, as an example, the metal pillar 130A shown in FIG. 1 is connected to the wireless communication circuit of the semiconductor chip 110 via the pad 112 and transmits a wireless communication signal. In addition, the metal pillar 130A not shown in FIG. 1 is connected to the metal pillar 130B via the rewiring layer 160 and transmits a power supply and a clock signal.

[0036] The material composition or the method of forming the metal pillar 130A is not particularly limited. Examples of metals that can be used to form the metal pillar 130A include copper, nickel, silver, gold, aluminum, chromium, zinc, and alloys containing these metals. Examples of methods for forming the metal pillar 130A include electroplating, electroless plating, and wire bonding. The metal pillar 130A located on the upper side of the semiconductor chip 110 is less affected by heat than the metal pillar 150 described below, and may therefore be made of a metal with a lower thermal conductivity than the metal pillar 150.

[0037] <Metal pillar 130B and pad 131B> A plurality of metal pillars 130B are provided in region B. The plurality of metal pillars 130B are provided two-dimensionally in region B having a rectangular ring shape. Each metal pillar 130B has a lower end connected to a pad 131B and an upper end connected to the lower surface of the rewiring layer 160. The pad 131B is exposed to the lower surface of the molding resin 120 in region B. The upper end of the metal pillar 130B is connected to a metal pillar 130A (not shown in FIG. 1) via the rewiring layer 160.

[0038] The pad 131B is exposed on the lower surface of the molding resin 120 in the region B, and is connected to the solder ball 140B. Power and a clock signal are input from the RF board 10 to the metal pillar 130B via the solder ball 140B. The power and the clock signal input to the metal pillar 130B are input to the semiconductor chip 110 via the rewiring layer 160 and the metal pillar 130A not shown in FIG.

[0039] As an example, the material composition or formation method of the metal pillar 130B is not particularly limited, similar to the metal pillar 130A. The metals and formation methods capable of producing the metal pillar 130B are similar to the metals and formation methods capable of producing the metal pillar 130A.

[0040] <Solder ball 140A> The solder ball 140A is provided in the area A between the pad 11A on the upper surface of the RF board 10 and the pad 111 on the lower surface of the semiconductor chip 110. The solder ball 140A, together with the solder ball 140B, is a solder ball for a BGA (Ball Grid Array).

[0041] 2, the solder balls 140A are arranged alternately with the metal pillars 150 in the X and Y directions in a plan view within region A. The solder balls 140A are also arranged in a staggered manner in a plan view within region A. Therefore, the metal pillars 150 are also arranged in a staggered manner in a plan view within region A.

[0042] The solder balls 140A have a configuration in which every other solder ball in the X and Y directions is omitted from the BGA solder balls arranged in a matrix at equal intervals in the X and Y directions in the region A. The reason for this arrangement will be described later together with the configuration of the metal pillars 150.

[0043] The solder ball 140A may be made of, for example, tin-silver (SnAg) solder or tin-silver-copper (SnAgCu) solder, but may be made of other solders. Also, a metal layer of nickel, gold, or the like may be provided on the surface of the solder ball 140A.

[0044] <Solder ball 140B> The solder ball 140B is provided between the pad 11B on the upper surface of the RF board 10 and the metal pillar 130B in the region B. The solder ball 140B, together with the solder ball 140A, is a solder ball for a BGA (Ball Grid Array).

[0045] As the solder ball 140B, for example, tin-silver (SnAg) solder or tin-silver-copper (SnAgCu) can be used like the solder ball 140A, but a solder other than these solders may also be used. Also, a metal layer such as nickel or gold may be provided on the surface of the solder ball 140B.

[0046] <Metal pillar 150> 1, the metal pillar 150 is provided between the pad 11A on the upper surface of the RF board 10 and the pad 111 on the lower surface of the semiconductor chip 110. Moreover, a plurality of metal pillars 150 are provided as shown in FIG. 2. The plurality of metal pillars 150 are arranged alternately with the solder balls 140A in the X direction and the Y direction in a plan view within the region A. The plurality of metal pillars 150 are arranged in a staggered manner in a plan view within the region A.

[0047] The metal pillar 150 located under the semiconductor chip 110 is significantly affected by the heat of the semiconductor chip 110, and therefore may be made of a metal having a higher thermal conductivity than solder, and the material composition or the method of formation is not particularly limited. In other words, the metal pillar 150 may be made of a metal having a higher thermal conductivity than the solder ball 140A. Examples of metals that can be used to fabricate the metal pillar 150 include copper, nickel, silver, gold, aluminum, chromium, zinc, and alloys containing these metals. Among these, the metals that can be used to fabricate the metal pillar 150 are preferably copper or aluminum, which have particularly high thermal conductivity and an established manufacturing method. Examples of methods for forming the metal pillar 150 include electroplating, electroless plating, and wire bonding.

[0048] A thin solder layer may be used to connect the lower end of the metal pillar 150 to the pad 11A. The solder of the solder layer may be tin-silver (SnAg) solder or tin-silver-copper (SnAgCu) solder, but may be a solder other than these solders. A metal layer of nickel, gold, or the like may be provided on the surface of the solder layer.

[0049] Furthermore, a metal paste containing solder or metal fine powder may be present at the mounting interface between the metal pillar 150 and the RF board 10. Even if solder or metal paste is present, most of the heat conduction path is the metal pillar 150 with high thermal conductivity, so there is no effect on the reduction of thermal resistance and it is effective in terms of increasing the bonding strength. Examples of the metal paste include silver paste and copper paste.

[0050] Here, the reason for providing the metal pillars 150 will be explained using a comparative semiconductor device. The comparative semiconductor device is a semiconductor device 100 shown in FIG. 1 in which all of the metal pillars 150 are replaced with solder balls 140A.

[0051] As the frequency at which the semiconductor chip 110 operates increases, for example to 28 GHz, 39 GHz, and 47 GHz, the pitch between the antennas 170 narrows according to the frequency, and the comparative semiconductor device becomes smaller according to the pitch between the antennas 170. As the size is reduced, heat is concentrated in a small area near the semiconductor chip 110, and the heat density increases. In addition, as the heat density increases, it is required to reduce the thermal resistance of the solder balls 140A, but there is a limit to reducing the thermal resistance by reducing the pitch of the solder balls 140A and increasing the number of the solder balls 140A. This limit occurs because if the pitch of the solder balls 140A is small, the possibility of solder bridging increases.

[0052] When the solder balls 140A with the solder bridge formed are not connected to the pads 111 on the underside of the semiconductor chip 110, the number of solder balls 140A supporting the underside of the semiconductor chip 110 decreases. In this state, compared to a state in which all the solder balls 140A support the semiconductor chip 110, unnecessary stress is applied to the semiconductor chip 110, which may distort the semiconductor chip 110 and adversely affect the operation of the semiconductor chip 110. If the operation of the semiconductor chip 110 is adversely affected, the reliability of the comparative semiconductor device decreases.

[0053] Furthermore, when a solder bridge occurs in the solder balls 140A near the outer edge of the region A, warping occurs in the portion of the semiconductor chip 110 near the outer edge of the region A. When such warping occurs, distortion or the like occurs in the metal pillars 130B for clock signals and power supplies, which may adversely affect the operation of the semiconductor chip 110. When the operation of the semiconductor chip 110 is adversely affected, the reliability of the comparative semiconductor device decreases.

[0054] Furthermore, if there is a circuit surface on part of the underside of the semiconductor chip 110, a solder bridge will occur on the solder balls 140A connected to the circuit surface on the underside, causing problems in the circuit connections of the semiconductor chip 110 and reducing the reliability of the comparative semiconductor device.

[0055] The above-mentioned miniaturization and increase in heat density also occur in the semiconductor device 100 and electronic device 1 of the embodiment. The semiconductor device 100 and electronic device 1 of the embodiment have high reliability by replacing some of the solder balls 140A in the region A with metal pillars 150.

[0056] The metal pillars 150 are not limited to being arranged in a staggered manner in a plan view in the region A as shown in FIG. 2. For example, the metal pillars 150 may be arranged alternately with the solder balls 140A only in the X direction in a plan view in the region A. In this case, the 14 metal pillars 150 that are at the same position in the X direction in a plan view in the region A are arranged adjacent to each other continuously in the Y direction. The metal pillars 150 may be arranged alternately with the solder balls 140A only in the Y direction in a plan view in the region A. In this case, the 14 metal pillars 150 that are at the same position in the Y direction in a plan view in the region A are arranged adjacent to each other continuously in the X direction.

[0057] In the above, the region A is a rectangular region overlapping with the semiconductor chip 110 in a plan view, and the region B is a rectangular ring-shaped region outside the region A, and the outer edge of the region B is equal to the outer edge of the rectangular region in which the semiconductor device 100 is present. However, the region A may be larger or smaller than the rectangular region in which the semiconductor chip 110 is present in a plan view. The region A does not have to be rectangular, and may be circular or elliptical, for example. The shape and size of the region A may be determined according to the heat distribution due to the heat generated by the semiconductor chip 110.

[0058] Moreover, region B does not have to be rectangular and annular. For example, if region A is circular or elliptical, the inner edge of region B may be aligned with the shape of the outer edge of region A (circular or elliptical). The outer edge of region B may be larger or smaller than the region in which the semiconductor device 100 is present. The outer edge of region B is not limited to a rectangular shape, and may be circular or elliptical. The shape and size of the inner and outer edges of region B, together with region A, may be determined according to the heat distribution due to heat generation from the semiconductor chip 110.

[0059] Also, in the above description, a configuration has been described in which the region in which the semiconductor device 100 exists in plan view is divided into a rectangular region A overlapping the semiconductor chip 110 and a rectangular ring-shaped region B surrounding region A. However, region B may not exist, and the region in which the semiconductor device 100 exists in plan view may entirely be region A. In this case, a configuration may be used in which the multiple solder balls 140B in FIG. 1 are replaced with solder balls 140A and metal pillars 150. In other words, a configuration may be used in which either the solder balls 140A or the metal pillars 150 are connected to the lower end of each of the multiple metal pillars 130B.

[0060] <Rewiring layer 160> The rewiring layer 160 is a wiring layer produced in a manufacturing process for producing rewiring. The rewiring layer 160 shown in Fig. 1 has, as an example, three wiring layers 161, vias 162 connecting the three wiring layers 161 in the Z direction, and an insulating layer 163. In Fig. 1, the insulating layer 163 is shown as an integrated unit, but in reality, a plurality of insulating layers 163 are provided between the three wiring layers 161 and on the top wiring layer 161.

[0061] The rewiring layer 160 has a configuration in which a plurality of insulating layers 163 and a plurality of wiring layers 161 are alternately stacked, and the plurality of wiring layers 161 are connected with vias 162. In addition, an antenna 170 is provided on the upper surface of the top insulating layer 163. As an example, the antenna 170 can be manufactured in the manufacturing process for manufacturing the rewiring.

[0062] 1 shows only some of all the wiring layers 161 and vias 162 in order to show an XZ cross section at a certain position in the Y direction, but the bottom wiring layer 161 is connected to the antenna 170 via the via 162. Furthermore, the power supply terminal and the clock signal terminal of the semiconductor chip 110 are connected to the metal pillar 130B via a wiring layer and via (not shown) similar to the wiring layer 161 and the via 162.

[0063] The wiring layer 161 is made of copper (copper foil pattern) as an example. The vias 162 are made of copper as an example, and connect between the multiple wiring layers 161. The vias 162 are small-diameter through-hole vias.

[0064] The insulating layer 163 has a structure using, for example, a film material in which a filler such as alumina is mixed into epoxy resin (for example, ABF material manufactured by Ajinomoto Fine-Techno Co., Ltd.), or a resin film material such as a polyimide film.

[0065] The redistribution layer 160 may also be provided on the lower surface of the semiconductor chip 110. Since the redistribution layer 160 and the semiconductor chip 110 have different linear expansion coefficients, for example, in cases where distortion occurs on the lower surface side of the semiconductor chip 110, the redistribution layer 160 may be provided on the lower surface side of the semiconductor chip 110. In this case, the solder balls 140A and the metal pillars 150 may be connected to the metal portion 15 through the wiring layer 161 and the vias 162 of the redistribution layer 160 on the lower surface side of the semiconductor chip 110.

[0066] <Antenna 170> The antennas 170 are patch antennas provided in plurality on the upper surface of the rewiring layer 160. The antennas 170 can be fabricated, for example, as a copper foil pattern in the manufacturing process for fabricating the rewiring, similar to the wiring layer 161 and the vias 162. The semiconductor device 100 may include at least two or more antennas 170.

[0067] Radio waves radiated from the multiple antennas 170 form one beam by beamforming, and the angle of the beam can be changed by the wireless communication circuit in the semiconductor chip 110 controlling the phase of the radio waves radiated from the multiple antennas 170. The wireless communication circuit controls the phase of the wireless communication signal transmitted to the antenna 170, thereby controlling the beam angle in beamforming.

[0068] <Simulation results> 3 is a diagram showing an example of a simulation result using a simulation model of the electronic device 1. A simulation was performed to calculate thermal resistance using the simulation model of the electronic device 1.

[0069] Simulations were performed using simulation models 1 to 3. Simulation models 1 and 2 are simulation models of the electronic device 1 of the embodiment, and simulation model 3 is a simulation model of an electronic device for comparison.

[0070] Simulation model 1 is a simulation model that uses a copper metal pillar 150. Simulation model 2 is a simulation model that uses an aluminum metal pillar 150. Simulation model 3 is a simulation model in which the metal pillar 150 is replaced with a solder ball 140A. That is, in simulation model 3, the entire area A is filled with solder balls 140A.

[0071] Simulation models 1 to 3 include a semiconductor chip 110 with a length of 9 mm in the X and Y directions. In simulation models 1 and 2, the pitch of the solder balls 140A and the metal pillars 150 in the region A in the X and Y directions was set to 650 μm. A solder layer made of tin silver (SnAg) was provided on the lower ends of the solder balls 140A and the metal pillars 150. In simulation model 3, the pitch of the solder balls 140A in the region A in the X and Y directions was set to 650 μm. A solder layer made of tin silver (SnAg) was provided on the lower ends of the solder balls 140A.

[0072] In the simulation models 1 and 2, the solder balls 140A and the metal pillars 150 were arranged in a staggered pattern in the region A of 14×14 balls on the central side of the 18×18 balls in the X and Y directions, as shown in FIG. 2. There were 98 solder balls 140A and 98 metal pillars 150. In the simulation model 3, the solder balls 140A were arranged in a 14×14 balls in the X and Y directions in the region A. In the simulation models 1 to 3, the solder balls 140B were arranged in a double rectangular ring shape in the portion excluding the 14×14 balls on the central side of the 18×18 balls in the region B, as shown in FIG. 2.

[0073] Moreover, the thermal resistance of the heat sink 20 in the simulation models 1 to 3 was set to 3.5° C. / W, and the simulation was performed under the condition that a thermally conductive sheet was placed between the lower surface of the metal part 15 and the upper surface of the heat sink 20.

[0074] In the above-described simulation models 1 to 3, the semiconductor chip 110 was made to generate heat at 10 W, and the temperatures of the center of the underside of the metal part 15 of the RF board 10 and the semiconductor chip 110 were calculated, and the thermal resistance from the semiconductor chip 110 to the center of the underside of the metal part 15 was also calculated.

[0075] As shown in FIG. 3, the temperatures of the semiconductor chip 110 in the simulation models 1 to 3 were 65.4° C., 65.7° C., and 66.8° C., respectively. Compared to the simulation models 1 and 2, the temperature of the semiconductor chip 110 in the simulation model 3 was higher.

[0076] Moreover, the temperatures at the center of the lower surface of the metal part 15 of the simulation models 1 to 3 were approximately the same, 63.0° C., 63.0° C., and 62.9° C., respectively.

[0077] The thermal resistances of the semiconductor chip 110 in the simulation models 1 to 3 were 0.24° C. / W, 0.27° C. / W, and 0.39° C. / W, respectively.

[0078] From the above, simulation models 1 and 2, in which metal pillars 150 were mixed in region A, had lower thermal resistance and the temperature of the semiconductor chip 110 was approximately 1°C lower than simulation model 3, in which only solder balls 140A were provided in region A.

[0079] From the above, it was confirmed that by mixing metal pillars 150 with a higher thermal conductivity than solder balls 140A within region A, the temperature of semiconductor chip 110 in simulation models 1 and 2 can be made at least equal to or lower than the temperature of semiconductor chip 110 in simulation model 3.

[0080] <First Modification> 4 is a diagram showing an electronic device 1A according to a first modification of the embodiment, in which differences from the electronic device 1 according to the embodiment shown in FIGS.

[0081] The electronic device 1A includes a semiconductor device 100 and an RF board 10A. The electronic device 1A has a configuration in which the RF board 10 of the electronic device 1 shown in Fig. 1 is replaced with an RF board 10A, and the heat sink 20 (see Fig. 1) is omitted. The RF board 10A differs from the RF board 10 shown in Fig. 1 in that it does not include a metal part 15.

[0082] In this way, the electronic device 1A may be mounted on an RF board 10A that does not include a metal part 15. In this case, the heat of the semiconductor chip 110 is transferred to the pad 11B of the RF board 10 via the pad 111, the solder ball 140A, and the metal pillar 150, and is then released from the RF board 10 to the air. When the amount of heat dissipated by the semiconductor chip 110 is relatively small, a configuration like that of the electronic device 1A may be used.

[0083] Even when the semiconductor device 100 is mounted on an RF board 10A that does not include a metal part 15 and has no heat sink 20 attached, the risk of solder bridging can be significantly reduced, and the reliability of the semiconductor device 100 and the electronic device 1A can be increased.

[0084] <Second Modification> 5 is a diagram showing a semiconductor device 100B and an electronic device 1B according to a second modification of the embodiment. Here, the differences from the semiconductor device 100 and the electronic device 1A according to the first modification of the embodiment shown in FIG. 4 will be described.

[0085] The electronic device 1B includes a semiconductor device 100B and an RF board 10A. The semiconductor device 100B has a configuration in which the antenna 170 is omitted from the semiconductor device 100 (see FIGS. 1 and 4).

[0086] 1 and 2, the semiconductor device 100 is, for example, a wireless communication device that can be mounted on a front-end wireless unit of a base station, and the RF board 10 is, for example, a motherboard of the base station. However, even in applications other than these, for example, when the pitch between solder balls becomes smaller as the signal frequency becomes higher and the heat density of the semiconductor chip 110 becomes high, there is a risk of a decrease in reliability due to solder bridges.

[0087] In such a case, by providing solder balls 140A and metal pillars 150 within area A which includes the semiconductor chip 110 in a planar view, the risk of solder bridging can be significantly reduced, thereby improving the reliability of the semiconductor device 100B and electronic device 1B.

[0088] <Effects> The semiconductor device 100 includes a semiconductor chip 110 having a first surface (lower surface) located on the RF board 10 (substrate) side and a second surface (upper surface) opposite to the first surface, the semiconductor chip 110 having a circuit surface as the second surface, a rewiring layer 160 provided on the second surface side, solder balls 140A connecting the first surface of the semiconductor chip 110 to the RF board 10, and metal pillars 150 connecting the first surface of the semiconductor chip 110 to the RF board 10. Therefore, even if the solder balls 140A melt due to a temperature rise in a reflow process when mounting the semiconductor device 100 on the RF board 10, the occurrence of a solder bridge can be suppressed. Also, even if the solder balls 140A melt due to a temperature rise in the semiconductor chip 110, the occurrence of a solder bridge can be suppressed.

[0089] Therefore, it is possible to provide a highly reliable semiconductor device 100.

[0090] Furthermore, in the semiconductor device 100 of the embodiment, the high thermal conductivity of the metal pillars 150 in the region A is utilized to release heat in the reflow process to the RF board 10, thereby suppressing the occurrence of solder bridges in the region A. This allows a highly reliable semiconductor device 100 to be provided. Furthermore, the high thermal conductivity of the metal pillars 150 in the region A is utilized to suppress a rise in temperature of the semiconductor chip 110, and the metal pillars 150 provided between the solder balls 140A do not melt due to heat generated by the semiconductor chip 110. Therefore, even if the temperature of the semiconductor chip 110 rises, the occurrence of solder bridges in the region A can be suppressed. This allows a highly reliable semiconductor device 100 to be provided.

[0091] Furthermore, the self-alignment effect of the solder balls 140A can improve the mounting accuracy when mounting the semiconductor device 100 on the RF board 10. Therefore, the semiconductor device 100 can achieve both reduced thermal resistance and good mountability.

[0092] Moreover, the semiconductor device 100 may include a plurality of solder balls 140A and metal pillars 150, and the plurality of metal pillars 150 may be provided between the plurality of solder balls 140A in a plan view. By providing the plurality of metal pillars 150 between the plurality of solder balls 140A, even if the solder balls 140A melt due to a temperature rise in a reflow process when mounting the semiconductor device 100 on the RF board 10, the occurrence of a solder bridge can be suppressed. Also, even if any of the solder balls 140A melts due to a temperature rise of the semiconductor chip 110, the occurrence of a solder bridge can be suppressed. Therefore, it is possible to provide a semiconductor device 100 with higher reliability. Also, it is possible to provide a semiconductor device 100 that can achieve both reduced thermal resistance and good mountability.

[0093] Furthermore, the multiple metal pillars 150 and the multiple solder balls 140A may be alternately arranged in the X direction (first axis direction) in a plan view. Even if the solder balls 140A melt due to a temperature rise in the reflow process, the occurrence of a solder bridge in the X direction can be suppressed. Therefore, it is possible to provide a semiconductor device 100 with higher reliability in the X direction. It is also possible to provide a semiconductor device 100 that can achieve both reduced thermal resistance and good mountability. It is also possible to suppress the occurrence of a solder bridge even if the temperature of the semiconductor chip 110 rises. This makes it possible to provide a semiconductor device 100 with higher reliability in the X direction.

[0094] Furthermore, the multiple metal pillars 150 and the multiple solder balls 140A may be alternately arranged in a Y direction (second axis direction) intersecting with the X direction (first axis direction) in a plan view. Even if the solder balls 140A melt due to a temperature rise in the reflow process, the occurrence of a solder bridge in the Y direction can be suppressed. Therefore, it is possible to provide a semiconductor device 100 with higher reliability in the Y direction. It is also possible to provide a semiconductor device 100 that can achieve both reduced thermal resistance and good mountability. It is also possible to suppress the occurrence of a solder bridge even if the temperature of the semiconductor chip 110 rises. This makes it possible to provide a semiconductor device 100 with higher reliability in the Y direction.

[0095] Moreover, the plurality of solder balls 140A and the plurality of metal pillars 150 are provided in an area A (first area) including the semiconductor chip 110 in a plan view, and may further include a plurality of solder balls 140B provided in an area B (second area) outside the area A in a plan view. Even if the solder balls 140A melt due to a temperature rise in a reflow process when mounting the semiconductor device 100 on the RF board 10, the occurrence of a solder bridge can be suppressed in the area A. Even if the solder balls 140A melt due to a temperature rise of the semiconductor chip 110, the occurrence of a solder bridge can be suppressed in the area A. Furthermore, by adding the solder balls 140B in the area B, a higher self-alignment effect can be obtained, and the mounting accuracy when mounting the semiconductor device 100 on the RF board 10 can be further improved. Therefore, it is possible to provide a semiconductor device 100 that is more reliable and has both reduced thermal resistance and better mountability.

[0096] The semiconductor device 100 may further include a redistribution layer 160 provided on the second surface (upper surface). In a configuration in which the redistribution layer 160 is provided on the second surface (upper surface), even if the solder balls 140A melt due to a temperature rise in a reflow process when mounting the semiconductor device 100 on the RF board 10, the occurrence of a solder bridge can be suppressed. Even if the solder balls 140A melt due to a temperature rise of the semiconductor chip 110, the occurrence of a solder bridge can be suppressed. Therefore, a highly reliable semiconductor device 100 can be provided.

[0097] The semiconductor device 100 may further include an antenna 170 that is provided on the opposite side of the redistribution layer 160 from the semiconductor chip 110 and is connected to the semiconductor chip 110 via the redistribution layer 160. If the semiconductor chip 110 controls wireless communication, wireless communication with an external device can be performed through the antenna 170. Since the amount of heat generated by the semiconductor chip 110 increases when wireless communication is performed, the semiconductor device 100 that can suppress the occurrence of solder bridges is effective.

[0098] The electronic device 1 includes a semiconductor device 100 and an RF board 10 on which the semiconductor device 100 is mounted. The semiconductor device 100 is a semiconductor chip 110 having a first surface (lower surface) located on the RF board 10 (substrate) side and a second surface (upper surface) opposite to the first surface, the semiconductor chip 110 having a circuit surface on the second surface, a rewiring layer 160 provided on the second surface side, solder balls 140A connecting the first surface of the semiconductor chip 110 to the RF board 10, and a metal pillar 150 connecting the first surface of the semiconductor chip 110 to the RF board 10. Therefore, even if the solder balls 140A melt due to a temperature rise in a reflow process when mounting the semiconductor device 100 on the RF board 10, the occurrence of a solder bridge can be suppressed. Also, even if the solder balls 140A melt due to a temperature rise in the semiconductor chip 110, the occurrence of a solder bridge can be suppressed.

[0099] Therefore, it is possible to provide a highly reliable electronic device 1.

[0100] Furthermore, in the electronic device 1 of the embodiment, the high thermal conductivity of the metal pillars 150 in the region A is utilized to release heat from the semiconductor chip 110 to the RF board 10, thereby suppressing a rise in temperature of the semiconductor chip 110. Furthermore, since the metal pillars 150 are provided between the solder balls 140A and do not melt due to heat generated by the semiconductor chip 110, the occurrence of solder bridges in the region A can be suppressed. This makes it possible to provide a highly reliable electronic device 1.

[0101] Furthermore, the self-alignment effect of the solder balls 140A can improve the mounting accuracy when mounting the electronic device 1 on the RF board 10. Therefore, the electronic device 1 can achieve both reduced thermal resistance and good mountability.

[0102] Furthermore, the RF board 10 may have a metal part 15 connected to the metal pillar 150. By dissipating heat from the metal pillar 150 to the metal part 15, it is possible to effectively suppress a temperature rise in the semiconductor chip 110. Therefore, it is possible to provide an electronic device 1 with higher reliability. It is also possible to provide an electronic device 1 that can achieve both a further reduction in thermal resistance and good mountability.

[0103] The above describes semiconductor devices and electronic devices according to exemplary embodiments of the present disclosure. However, the present disclosure is not limited to the specifically disclosed embodiments, and various modifications and changes are possible without departing from the scope of the claims. Regarding the above embodiment, the following supplementary notes are further disclosed. (Appendix 1) A semiconductor chip having a first surface located on a substrate side and a second surface opposite to the first surface, the second surface being a circuit surface; a first bump connecting the first surface of the semiconductor chip to the substrate; a metal pillar connecting the first surface of the semiconductor chip and the substrate; 13. A semiconductor device comprising: (Appendix 2) The first bump and the metal pillar are included in a plurality of parts, 2. The semiconductor device according to claim 1, wherein, in a plan view, the metal pillars are provided between the first bumps. (Appendix 3) 3. The semiconductor device according to claim 2, wherein the metal pillars and the first bumps are arranged alternately in a first axis direction in a plan view. (Appendix 4) 4. The semiconductor device according to claim 3, wherein the metal pillars and the first bumps are arranged alternately in a second axis direction that intersects with the first axis direction in a plan view. (Appendix 5) 5. The semiconductor device according to claim 1, wherein the metal pillar is made of a metal having a higher thermal conductivity than the first bump. (Appendix 6) the first bumps and the metal pillars are provided in a first region including the semiconductor chip in a plan view, 3. The semiconductor device according to claim 2, further comprising a plurality of second bumps provided in a second region outside the first region in a plan view. (Appendix 7) The semiconductor device according to claim 1, further comprising a redistribution layer provided on the second surface side. (Appendix 8) 8. The semiconductor device according to claim 7, further comprising an antenna provided on the opposite side of the redistribution layer from the semiconductor chip, the antenna being connected to the semiconductor chip via the redistribution layer. (Appendix 9) 2. The semiconductor device according to claim 1, wherein the first bump is a solder ball. (Appendix 10) 8. The semiconductor device according to claim 7, wherein the second bump is a solder ball. (Appendix 11) A semiconductor device; a substrate on which the semiconductor device is mounted; Including, The semiconductor device includes: a semiconductor chip having a first surface located on a substrate side and a second surface opposite to the first surface, the second surface being a circuit surface; A redistribution layer provided on the second surface side; a first bump connecting the first surface of the semiconductor chip to the substrate; a metal pillar connecting the first surface of the semiconductor chip and the substrate; An electronic device having (Appendix 12) 12. The electronic device of claim 11, wherein the substrate has a metal portion connected to the metal pillar. [Explanation of symbols]

[0104] 1, 1A, 1B electronic equipment 10 RF board (example of circuit board) 15 Metal Parts 20 Heat sink 100 Semiconductor device 110 Semiconductor Chip 111, 112 Pads 120 Molding resin 130A, 130B Metal pillar 140A solder ball (example of first bump) 140B Solder ball (an example of a second bump) 150 Metal pillar (An example of a metal pillar) 160 Redistribution layer 170 Antenna

Claims

1. a semiconductor chip having a first surface located on a substrate side and a second surface opposite to the first surface, the second surface being a circuit surface; a first bump connecting the first surface of the semiconductor chip to the substrate; a metal pillar connecting the first surface of the semiconductor chip and the substrate; 13. A semiconductor device comprising:

2. The first bump and the metal pillar are included in a plurality of parts, The semiconductor device according to claim 1 , wherein the metal pillars are provided between the first bumps in a plan view.

3. The semiconductor device according to claim 2 , wherein the plurality of metal pillars and the plurality of first bumps are provided alternately in a first axis direction in a plan view.

4. The semiconductor device according to claim 3 , wherein the plurality of metal pillars and the plurality of first bumps are provided alternately in a second axis direction intersecting the first axis direction in a plan view.

5. The semiconductor device according to claim 1 , wherein the metal pillar is made of a metal having a higher thermal conductivity than the first bump.

6. the first bumps and the metal pillars are provided in a first region including the semiconductor chip in a plan view, The semiconductor device according to claim 2 , further comprising a plurality of second bumps provided in a second region outside the first region in a plan view.

7. The semiconductor device according to claim 1 , further comprising a redistribution layer provided on said second surface side.

8. 8. The semiconductor device according to claim 7, further comprising an antenna provided on an opposite side of said rewiring layer to said semiconductor chip, said antenna being connected to said semiconductor chip via said rewiring layer.

9. A semiconductor device; a substrate on which the semiconductor device is mounted; Including, The semiconductor device includes: a semiconductor chip having a first surface located on a substrate side and a second surface opposite to the first surface, the second surface being a circuit surface; A rewiring layer provided on the second surface side; a first bump connecting the first surface of the semiconductor chip to the substrate; a metal pillar connecting the first surface of the semiconductor chip and the substrate; An electronic device having

10. The electronic device according to claim 9 , wherein the substrate has a metal portion connected to the metal pillar.

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