Circuit device and method for setting circuit device

Abstract

To make it possible to set filters to users' desired characteristics according to the users' intended use.SOLUTION: A circuit device includes an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element, an interface circuit that receives filter setting data that determines characteristics of each of a plurality of digital filter processes, a memory circuit that stores the filter setting data, and a signal processing circuit that sequentially executes each of the plurality of digital filter processes having the characteristics determined by the filter setting data on a digital signal output from the A / D conversion circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device and a method for setting a circuit device. [Background technology]

[0002] Conventionally, there is known a technique for converting an analog signal output from a sensor element into a digital signal and performing digital filtering. For example, Patent Document 1 discloses a configuration for attenuating the component of a detuning frequency Δf corresponding to the difference between the drive-side resonant frequency fd and the detection-side resonant frequency fs of a vibrator by using a band elimination filter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-108566 A Summary of the Invention [Problem to be solved by the invention]

[0004] Conventionally, it has not been possible to set filter characteristics desired by the user according to the user's application. [Means for solving the problem]

[0005] The circuit device includes an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element, an interface circuit that receives filter setting data that determines the characteristics of each of a plurality of digital filter processes, a memory circuit that stores the filter setting data, and a signal processing circuit that sequentially executes each of the plurality of digital filter processes having characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit.

[0006] A method for setting a circuit device includes an A / D conversion circuit that performs A / D conversion of a signal output from a sensor element, an interface circuit, a memory circuit, and a signal processing circuit that performs digital filter processing on the digital signal output from the A / D conversion circuit, in which filter setting data that determines the characteristics of each of a plurality of digital filter processes is input to the interface circuit and stored in the memory circuit, and the signal processing circuit is caused to sequentially execute each of the plurality of digital filter processes having the characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a functional block diagram of a physical quantity sensor according to a first embodiment. [Diagram 2] FIG. 4 is a diagram showing an example of filter characteristics. [Diagram 3] FIG. 1 is a block diagram showing the configuration of a DSP. [Figure 4] FIG. 1 illustrates an example of the configuration of a programmable filter. [Diagram 5] FIG. 1 shows an example of the configuration of a second-order IIR filter. [Figure 6] 13 is a flowchart of a setting process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention. Below, a physical quantity sensor (angular velocity sensor) that detects angular velocity as a physical quantity will be described as an example.

[0009] 1. First embodiment FIG. 1 is a functional block diagram of a physical quantity sensor of the first embodiment. The physical quantity sensor 1 of the first embodiment includes a sensor element 2 and a circuit device 3. In this embodiment, the sensor element 2 is an angular velocity sensor. The angular velocity sensor can be realized by various known configurations. For example, the sensor element 2 can be configured by an element that outputs a signal indicating vibration based on the Coriolis force acting on the vibrating arm. Of course, the shape of the sensor is not limited, and sensors of various shapes such as a double T type, a tuning fork type, and an H type can be used.

[0010] The sensor element 2 has an input terminal to which the drive signal DRV is input from the drive circuit 20, and an output terminal to which a feedback signal DI is output to the drive circuit 20. In this embodiment, the input terminal is electrically connected to a pad DS. The output terminal is electrically connected to a pad DG. The sensor element 2 has two detection signal output terminals that output detection signals, and each detection signal output terminal is electrically connected to a pad S1, S2.

[0011] The circuit device 3 in this embodiment includes a reference voltage circuit 10, a drive circuit 20, a detection circuit 30, a digital processing unit 40, an oscillation circuit 50, a storage unit 60, an interface circuit 70, a temperature sensor 80, an A / D conversion circuit 82, and a temperature correction value calculation unit 84. The circuit device 3 may be, for example, a one-chip integrated circuit (IC). Note that the circuit device 3 may be configured such that some of these elements are omitted or modified, or other elements are added.

[0012] The reference voltage circuit 10 generates constant voltages such as reference voltages VR1 and VR2 and constant currents from the power supply voltage supplied from the VDD terminal of the circuit device 3, and supplies them to the drive circuit 20 and the detection circuit 30.

[0013] The drive circuit 20 drives the sensor element 2. The drive circuit 20 is electrically connected to the sensor element 2 via pads DS and DG. The drive circuit 20 receives a feedback signal DI from the sensor element 2 via the pad DG, and drives the sensor element 2 by outputting a drive signal DRV corresponding to the feedback signal DI via the pad DS. The drive circuit 20 also generates a detection signal SDET in phase with the drive signal DRV, and outputs it to the detection circuit 30.

[0014] The drive circuit 20 can be realized by various known circuits. For example, the drive circuit 20 can be realized by a configuration including a current-voltage converter (I / V converter), a gain control circuit, and two comparators. That is, the AC voltage signal output from the current-voltage converter is converted by each comparator to become the drive signal DRV and the detection signal SDET. The gain control circuit controls the reference voltage of the comparator so as to maintain the amplitude of the AC voltage signal input to the comparator that generates the drive signal DRV at a constant value. Note that here, the frequency of the drive signal DRV is referred to as the drive frequency fd.

[0015] The detection circuit 30 detects the angular velocity component contained in the AC charge input from the sensor element 2 via the S1 and S2 terminals, and outputs a detection signal Sr, which is an analog signal with a voltage level according to the magnitude of the angular velocity. In this embodiment, the frequency of the AC charge input from the sensor element 2 via the S1 and S2 terminals is called the detection frequency fr. The detection circuit 30 can be realized by various known circuits. For example, the detection circuit 30 can be realized by a configuration including a QV amplifier, a differential amplifier, a variable gain amplifier (PGA: Programmable Gain Amplifier), a synchronous detection circuit, and a low-pass filter. The synchronous detection circuit synchronously detects the angular velocity component contained in the signal output from the variable gain amplifier using the detection signal SDET.

[0016] The storage unit 60 has a register 61 and a non-volatile memory 62. The register 61 stores addresses and various data used in communication with an external device via the interface circuit 70. In this embodiment, the various data includes filter setting data. That is, the interface circuit 70 receives filter setting data that determines the characteristics of each of a plurality of digital filter processes (second-order IIR (Infinite Impulse Response) filters, which will be described later). The received filter setting data is stored in the register 61. The register 61 also stores angular velocity data and angle data output from the DSP 44, which will be described later.

[0017] The non-volatile memory 62 stores various adjustment data and correction data for the drive circuit 20 and the detection circuit 30, and various information for establishing communication with the outside via the interface circuit 70. The non-volatile memory 62 can be configured as, for example, a MONOS (Metal Oxide Nitride Oxide Silicon) type memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0018] The interface circuit 70 is electrically connected to the XCS terminal, the SCLK terminal, the SDI terminal, and the SDO terminal, and is a circuit for communicating with an external device via these terminals. In communication via the interface circuit 70, the external device functions as a master, and the physical quantity sensor 1 (circuit device 3) functions as a slave. The external device can write data to a specified address in the register 61, read data from a specified address in the register 61, and send various commands to control the operation of the circuit device 3 via the interface circuit 70.

[0019] The interface circuit 70 may function as either an SPI (Serial Peripheral Interface) interface circuit or an I2C (Inter-Integrated Circuit) interface circuit. For example, when the XCS terminal is at a low level, the interface circuit 70 functions as an SPI interface circuit, a clock signal is input via the SCLK terminal, a data signal is input via the SDI terminal, and a data signal is output via the SDO terminal. When the XCS terminal is at a high level, the interface circuit 70 functions as an I2C interface circuit, a clock signal is input via the SCLK terminal, and a data signal is input / output via the SDI terminal.

[0020] Communication with an external device via the interface circuit 70 is performed based on various information stored in the register 61. The external device can read angular velocity data from a predetermined address in the register 61 via the interface circuit 70. In this way, the physical quantity sensor 1 (circuit device 3) is configured to be able to output angular velocity data in response to a request from the external device.

[0021] In this embodiment, the frequency of the clock signal CLK is determined according to the inherent frequency of the sensor element 2 when the physical quantity sensor 1 is manufactured, and the sampling frequency fs in the A / D conversion described later is determined according to the frequency of the clock signal CLK. Specifically, when the sensor element 2 is driven at the time of shipment from the factory, as in the above-mentioned conventional technology, if the driving frequency of the driving signal used to drive the sensor element 2 is fd and the frequency of the clock signal CLK is fck, then j×fd≠fck / i (i and j are integers equal to or greater than 1) is satisfied. When the frequency fck of the clock signal is determined, the sampling frequency fs is set to be the same as the frequency fck of the clock signal or a frequency obtained by multiplying the frequency of the clock signal CLK. The frequency of the clock signal CLK and the sampling frequency fs are stored in the non-volatile memory 62, and the sampling frequency fs is stored at a predetermined address of the register 61. The user can read out the sampling frequency fs stored at the address using an external device. Here, the storage area in the register 61 in which the sampling frequency fs is stored is called the first area.

[0022] Furthermore, in this embodiment, digital filtering is performed by the DSP 44, which will be described later. In this embodiment, the digital filtering includes a programmable filter 44b, a selectable filter 44c, and a notch filter 44d, which will be described later. The programmable filter 44b is a filter that can be set to have any characteristics by the user setting a filter coefficient using filter setting data, and will be described in detail later.

[0023] The selectable filter 44c is a filter that allows the user to select a desired characteristic from a number of predetermined characteristics. Filter coefficients corresponding to each setting are stored in the non-volatile memory 62. The filter characteristics and the number of selectable characteristics are arbitrary, but here, an example is assumed in which the characteristics of the low-pass filter processing can be selected from 24 characteristics.

[0024] Specifically, the selectable filter 44c is configured by IIR filters of multiple orders, and filter coefficients corresponding to each combination of the order n and the cutoff frequency fc (24 combinations) are determined in advance and stored in the non-volatile memory 62. The filter coefficients are values ​​for setting the low-pass filter process to the order n and cutoff frequency fc associated with the filter coefficients.

[0025] In this embodiment, the characteristics of the low-pass filter processing realized by the combination of the order n and the cutoff frequency fc are shown in advance to the user in a manual, etc. Therefore, the user can understand the selectable characteristics of the low-pass filter processing by referring to the manual, etc.

[0026] Fig. 2 is a diagram showing an example of filter characteristics. In this embodiment, three kinds of orders (2nd to 4th orders) and eight kinds of cutoff frequencies fc can be selected, and a total of 24 different characteristics can be selected. Fig. 2 shows an example in which the phase delay characteristics when the input signal is 10 Hz and the group delay characteristics when the input signal is a DC signal are associated with each combination. For example, the phase delay characteristics of low-pass filter processing with an order of 2 and a cutoff frequency fc of 1 Hz are PD12 (deg) and the group delay characteristics are GD12 (ms).

[0027] The user is configured to select a desired characteristic from these low-pass filter processing characteristics and specify the order n and cutoff frequency fc by operating an external device. Since the non-volatile memory 62 has filter coefficients associated with the order n and cutoff frequency fc, the characteristics of the selectable filter 44c can be selected so that the low-pass filter processing with the characteristics specified by the user is executed by operating the selectable filter 44c using the filter coefficients. The detailed processing of the selectable filter 44c will be described later.

[0028] The notch filter 44d is a band elimination filter for attenuating a signal of a specific frequency. In this embodiment, the notch filter 44d is a filter for attenuating a component of a detuning frequency, which is the difference between the driving frequency fd and the detection frequency fr. The notch filter 44d can be realized by, for example, an IIR filter. The non-volatile memory 62 stores information indicating a filter coefficient to be applied to the notch filter 44d in order to attenuate the component of the detuning frequency. When the physical quantity sensor 1 is started, the information indicating the filter coefficient is transferred to the register 61 and is referred to by the DSP 44, which will be described later.

[0029] The oscillation circuit 50 generates a clock signal CLK and outputs the clock signal CLK to the digital processing unit 40. The oscillation circuit 50 includes a PLL (Phase Locked Loop) circuit and a DLL (Digital Locked Loop) circuit, and outputs the clock signal CLK at a frequency stored in the storage unit 60. That is, the frequency of the clock signal CLK is stored in the non-volatile memory 62, and when the physical quantity sensor 1 is started, the frequency is transferred to the register 61. The oscillation circuit 50 obtains the frequency stored in the register 61, and generates an oscillation signal at the frequency to generate the clock signal CLK.

[0030] The digital processing unit 40 includes an A / D (Analog to Digital) conversion circuit 42 and a DSP (Digital Signal Processor) 44 as a signal processing circuit. The A / D conversion circuit 42 operates at a sampling frequency fs synchronized with a clock signal CLK output by an oscillation circuit 50, and converts the output signal of the detection circuit 30 into a digital signal (angular velocity data) Da and outputs it. The sampling frequency fs, which is a period at which the A / D conversion circuit 42 converts an analog signal into a digital signal, may be the same as the frequency of the clock signal CLK, or may be a frequency obtained by multiplying the frequency of the clock signal CLK. The A / D conversion circuit 42 can be realized by various known circuits, and may be, for example, a delta-sigma type or successive approximation type A / D conversion circuit.

[0031] The DSP 44 operates in synchronization with the clock signal CLK output by the oscillation circuit 50, and performs digital processing, including digital filtering, on the digital signal (angular velocity data) Da output by the A / D conversion circuit 42. The configuration of the DSP 44 will be described later, but the digital processing includes digital filtering as well as digital processing for correcting fluctuations in the angular velocity data due to temperature. The value of the angular velocity data after these digital processing represents the angular velocity detected by the sensor element 2, and is updated sequentially at a predetermined rate. Furthermore, the DSP 44 may perform digital processing for correcting the offset of the zero point of the angular velocity data, and digital processing for calculating the angular velocity data by time integration (addition) of the sequentially updated angular velocity data. The angular velocity data output by the DSP 44 is stored in the register 61, and is transferred to an external device or the like via the interface circuit 70, for example.

[0032] The temperature sensor 80 is a sensor that outputs a signal (temperature signal) with a voltage level according to the temperature around it, and may be a positive polarity sensor that outputs a higher output voltage as the temperature increases, or a negative polarity sensor that outputs a lower output voltage as the temperature increases. The temperature sensor 80 may be, for example, a circuit that outputs a voltage proportional to absolute temperature (PTAT (Proportional To Absolute Temperature) voltage). The temperature signal output from the temperature sensor 80 is input to an A / D conversion circuit 82.

[0033] The A / D conversion circuit 82 operates in synchronization with the clock signal CLK output by the oscillation circuit 50, and converts the signal output by the temperature sensor 80 into a digital signal (temperature data) and outputs it. A sampling frequency fs, which is a period at which the A / D conversion circuit 82 converts an analog signal into a digital signal, may be the same as the frequency of the clock signal CLK, or may be a frequency obtained by multiplying the frequency of the clock signal CLK. The A / D conversion circuit 82 can be realized by various known circuits, and may be, for example, a delta-sigma type or successive approximation type A / D conversion circuit. The signal output from the A / D conversion circuit 82 is input to a temperature correction value calculation unit 84.

[0034] The temperature correction value calculation unit 84 calculates and outputs the temperature correction value Ta based on the signal output by the A / D conversion circuit 82. The temperature correction value Ta may be calculated by various methods, such as a method of calculating the temperature correction value Ta by a function with temperature as a variable, or a method of acquiring the temperature correction value Ta corresponding to the temperature based on information stored in the storage unit 60. The temperature correction value Ta output from the temperature correction value calculation unit 84 is input to the DSP 44. The temperature correction value calculation unit 84 may be any circuit that performs digital processing, and may be realized by various integrated circuits such as a CPU, or may be realized by an FPGA (Field Programmable Gate Array), for example.

[0035] 1.1 DSP Configuration Next, the configuration of the DSP 44 will be described in detail. FIG. 3 is a block diagram showing the configuration of the DSP 44. The DSP 44 includes a temperature correction unit 44a, a programmable filter 44b, a selectable filter 44c, a notch filter 44d, and selectors 44e and 44f. The temperature correction unit 44a corrects the digital signal Da based on a temperature correction value Ta output by a temperature correction value calculation unit 84. The temperature correction value Ta is a value for offsetting fluctuations in the output of the sensor element 2 due to temperature, and in this embodiment, the temperature correction unit 44a corrects the digital signal Da by executing a predetermined calculation based on the temperature correction value Ta, for example, Da+Ta, on the digital signal Da.

[0036] The programmable filter 44b is a filter that can be set to have any characteristics by the user setting the filter coefficients using filter setting data. The programmable filter 44b can be realized by various configurations, and in this embodiment, it is realized by connecting four second-order IIR filters in series.

[0037] Fig. 4 is a diagram for explaining the configuration of the programmable filter 44b. The programmable filter 44b has a configuration in which second-order IIR filters 44b1, 44b2, 44b3, and 44b4 are connected in series in this order. The second-order IIR filters 44b1, 44b2, 44b3, and 44b4 have the same configuration, and Fig. 5 shows the configuration of the second-order IIR filter 44b1.

[0038] The second-order IIR filter 44b1 includes adders 44b11-44b14, delayers 44b15 and 44b16, and multipliers 44b17-44b111. The delayers 44b15 and 44b16 provide a unit delay to the input signal and output the signal. The multipliers 44b17-44b111 multiply the input signal by a coefficient and output the result. The coefficients of the multipliers 44b17-44b111 are a11, a21, b01, b11, and b21 shown in FIG. 5 for the multipliers 44b17-44b111, respectively. The adders 44b11-44b14 add the codes shown in FIG. 5 to the input signals, add them, and output the results.

[0039] 5, the adder 44b11 adds the input signal and a signal obtained by making the fed-back signal a negative signal, and outputs the result. The signal output from the adder 44b11 is delayed by delay units 44b15 and 44b16. The signal delayed by delay unit 44b15 is input to multiplier units 44b17 and 44b110 and delay unit 44b16. The signal delayed by delay unit 44b16 is input to multiplier units 44b18 and 44b111.

[0040] The signals input to the multipliers 44b17 and 44b18 are multiplied by coefficients a11 and a21, the results are added by the adder 44b12, and the result is input to the adder 44b11. The signals input to the multipliers 44b110 and 44b111 are multiplied by filter coefficients b11 and b21, the results are added by the adder 44b14, and the result is input to the adder 44b13. The adder 44b13 receives as input a signal that has been multiplied by the filter coefficient b01 by the multiplier 44b19 with respect to the output of the adder 44b11. The adder 44b13 outputs the sum of both input signals.

[0041] The above-described second-order IIR filter 44b1 can be a filter with various characteristics by adjusting the filter coefficients b01, b11, b21, a11, and a21. In this embodiment, the user can specify these filter coefficients. That is, the user operates an external device to transmit filter setting data indicating the filter coefficients to the physical quantity sensor 1. When the interface circuit 70 receives the filter setting data, the filter setting data is stored in the register 61. The second-order IIR filter 44b1 refers to the register 61 and determines the filter coefficients b01, b11, b21, a11, and a21 so that the filter coefficients become the values ​​indicated by the acquired filter setting data.

[0042] The second-order IIR filter 44b1 may be set to perform various digital filtering processes, for example, band-pass filtering, notch filtering, low-pass filtering, or high-pass filtering, and the filter setting data may be defined so that the phase delay or group delay falls within a desired range.

[0043] The user may determine the filter coefficients using various methods, but in this embodiment, a simulator is used. Specifically, the simulator is executed in an external device. In this situation, the user operates the external device to provisionally determine the values ​​of the filter coefficients, simulates the characteristics of the digital filter processing using the provisionally determined filter coefficients, and displays them on a display unit or the like. If the displayed result is a desired result, the user uses the provisionally determined filter coefficients, and if not, changes the filter coefficients and repeats the simulation.

[0044] The simulation may be performed by various methods, for example, simulating the gain characteristic, phase delay characteristic, and group delay characteristic using the transfer function of the second-order IIR filter 44b1. The transfer function of the second-order IIR filter 44b1 can be expressed by the following formula (1).

number

[0045] Therefore, by changing the filter coefficients b01, b11, b21, a11, and a21, the user can change the characteristics of the digital filter processing represented by the transfer function, and the characteristics can be visualized using a simulator. As described above, by adjusting the filter coefficients, the characteristics of the second-order IIR filter 44b1 can be specified.

[0046] However, in this embodiment, by taking the sampling frequency fs into consideration, it is possible to perform adjustments so that the characteristics are accurately as desired by the user. Specifically, the filter characteristics are determined by the transfer function shown in the above formula (1), and 1 / z included in the transfer function depends on the sampling frequency fs. In other words, even if the filter coefficients are the same, if the sampling frequency fs is different, the characteristics of the digital filter processing expressed by the transfer function, such as the gain characteristic, phase delay characteristic, and group delay characteristic, may change.

[0047] Particularly, in this embodiment, the sampling frequency fs is a value determined according to the frequency fck of the clock signal, and the frequency fck of the clock signal is determined depending on the drive frequency fd of the drive signal of the sensor element 2. Therefore, the sampling frequency fs is individual data that differs for each individual sensor element 2, and different individual physical quantity sensors 1 may operate at different sampling frequencies fs. For this reason, the sampling frequency fs is a value that cannot be determined by the user.

[0048] In this way, since the sampling frequency fs may differ for each individual, in this embodiment, the sampling frequency fs is stored in the first area of ​​the register 61 in the initial state after the physical quantity sensor 1 is started. Therefore, before starting the simulation of the filter coefficient, the user operates the external device to read out the sampling frequency fs via the interface circuit 70. Then, when the above-mentioned simulation is performed, the characteristics of the 1 / z part in the formula (1) are determined using the acquired sampling frequency fs. Therefore, according to this embodiment, the filter coefficient for realizing the characteristics desired by the user can be determined according to the sampling frequency fs that differs for each individual. Therefore, the filter coefficient for realizing the characteristics desired by the user can be accurately determined.

[0049] In this embodiment, the sampling frequency fs is stored in the first area of ​​the register 61. Then, when the sampling frequency fs is read out and a filter coefficient is determined and transmitted as filter setting data, it is stored in the first area of ​​the register 61. That is, the sampling frequency fs stored in the register 61 is overwritten by the filter setting data. The amount of information of the sampling frequency fs and the amount of information of the filter setting data may be the same or different. In any case, by writing the filter setting data to the first area in which the sampling frequency fs was stored, the storage area of ​​the register 61 can be used efficiently.

[0050] The configuration of the second-order IIR filters 44b2 to 44b4 is the same as that of the second-order IIR filter 44b1. That is, the user uses an external device to simulate the characteristics indicated by the transfer functions of the second-order IIR filters 44b2 to 44b4, and determines the filter coefficients. In FIG. 4, the filter coefficients of the second-order IIR filter 44b2 are indicated as b02, b12, b22, a12, and a22, and the filter coefficients of the second-order IIR filter 44b3 are indicated as b03, b13, b23, a13, and a23. The filter coefficients of the second-order IIR filter 44b4 are indicated as b04, b14, b24, a14, and a24.

[0051] The transfer functions of these second-order IIR filters 44b2 to 44b4 are expressed by equations (2) to (4), respectively.

number

number

number

[0052] The simulation may be performed for each of the second-order IIR filters 44b1 to 44b4, or the characteristics obtained by combining the second-order IIR filters 44b1 to 44b4 may be simulated. As shown in FIG. 4, the programmable filter 44b, which is composed of a plurality of second-order IIR filters 44b1 to 44b4 connected in series, functions to sequentially execute each digital filter process. The characteristics of the programmable filter 44b can be described by a transfer function obtained by multiplying the transfer functions of each filter. Therefore, the simulation may be performed for each transfer function, or the characteristics of the combination of each filter may be simulated based on the product of the transfer functions. Since the characteristics obtained by connecting filters in series can be described by the product of the transfer functions, the processing order of the second-order IIR filters 44b1 to 44b4 is arbitrary.

[0053] Once the filter coefficients have been determined by the simulation, the user operates the external device to transmit filter setting data indicating the determined filter coefficients to the physical quantity sensor 1. Once the filter setting data has been transmitted, the interface circuit 70 acquires the filter setting data and stores it in a first area of ​​the register 61. Once the filter setting data has been stored in the register 61, the programmable filter 44b applies each filter coefficient to each of the second-order IIR filters 44b1 to 44b4. As a result, the programmable filter 44b functions as a filter having characteristics desired by the user.

[0054] For example, the programmable filter 44b is set to perform any one or a combination of band-pass filtering, notch filtering, low-pass filtering, and high-pass filtering. If a21 and b21 of the filter coefficients of the second-order IIR filter 44b1 are set to 0, the second-order IIR filter 44b1 functions as a first-order filter. Therefore, the user can adjust the filter coefficients of the second-order IIR filters 44b1 to 44b4 to cause the programmable filter 44b to function as a filter of any order from first to eighth order.

[0055] The selectable filter 44c is a filter that allows the user to select digital filter processing with predetermined characteristics. The user refers to a manual or the like and selects a desired characteristic from among the predetermined characteristics as shown in FIG. 2. That is, the user specifies a desired order n and cutoff frequency fc based on the phase delay characteristic, group delay characteristic, etc. After specifying the order n and the cutoff frequency fc, the user operates an external device to transmit the order n and the cutoff frequency fc to the physical quantity sensor 1.

[0056] When the order n and the cutoff frequency fc are transmitted, the interface circuit 70 acquires the order n and the cutoff frequency fc and stores them in a predetermined area of ​​the register 61. When the order n and the cutoff frequency fc are stored in the register 61, the selectable filter 44c refers to the non-volatile memory 62 and transfers a filter coefficient corresponding to the order n and the cutoff frequency fc to the register 61. The selectable filter 44c then applies the filter coefficient to the selectable filter 44c. As a result, the selectable filter 44c functions as a filter having characteristics selected by the user.

[0057] The output signals of the programmable filter 44b and the selectable filter 44c are input to the selector 44e. The selector 44e selects and outputs one of two types of input signals based on a selection setting value sel1. The selection setting value sel1 is a value determined according to a mode set at the time of starting up the physical quantity sensor 1. In this embodiment, when the selection setting value sel1 is on, the output of the programmable filter 44b is output from the selector 44e. When the selection setting value sel1 is off, the output of the selectable filter 44c is output from the selector 44e. Therefore, in this embodiment, digital filter processing of either the programmable filter 44b or the selectable filter 44c is applied to the signal output from the sensor element 2. According to the above configuration, it is possible to select various filters according to the needs of the user. That is, if the default characteristics prepared as the selectable filter 44c are sufficient, a filter with the default characteristics can be easily selected by specifying the order n and the cutoff frequency fc. If the desired characteristics are not present in the selectable filter 44c, a filter with the user's desired characteristics can be used by specifying filter coefficients in the programmable filter 44b.

[0058] The output signal of the selector 44e is input to the selector 44f and the notch filter 44d. The notch filter 44d is a band elimination filter for attenuating signals of a specific frequency. A filter coefficient to be applied to the notch filter 44d is specified in advance and stored in the non-volatile memory 62, and is transferred to the register 61 when the physical quantity sensor 1 is started. The notch filter 44d applies the filter coefficient to the notch filter 44d. As a result, the notch filter 44d functions as a filter that attenuates the component of the detuning frequency, which is the difference between the drive frequency fd and the detection frequency fr.

[0059] The selector 44f selects and outputs one of two types of input signals based on the selection setting value sel2. The selection setting value sel2 is a value determined according to a mode set at the time of starting up the physical quantity sensor 1. In this embodiment, when the selection setting value sel2 is on, the output of the selector 44e is output from the selector 44f. When the selection setting value sel2 is off, the output of the notch filter 44d is output from the selector 44f. Therefore, in this embodiment, the selector 44f selects whether or not to apply the notch filter 44d to the signal output from the selector 44e. When the output of the selector 44e is the output of the programmable filter 44b, the output from the selector 44f is either the output of the programmable filter 44b or the output when the notch filter 44d is applied to the programmable filter 44b. In addition, in the programmable filter 44b, it is also possible to select a setting in which the programmable filter 44b does not actually function, depending on the filter coefficient. Therefore, when the output of selector 44e is the output of programmable filter 44b, the output from selector 44f is a signal Da' obtained by applying at least one of programmable filter 44b and notch filter 44d to the signal output from sensor element 2. The above configuration makes it possible to select from a variety of filters according to the needs of the user.

[0060] The digital signal after the digital filter process by the DSP 44 is output from the DSP 44 as a digital signal Da' in which the digital signal (angular velocity data) indicating the detection result detected by the sensor element 2 is corrected. The output manner is not limited, and the DSP 44 may output the generated digital signal Da' to an external device using the interface circuit 70, or may store it in the storage unit 60. In this case, the digital signal Da' is output to the external device via the interface circuit 70 in response to a request from the external device at any timing.

[0061] 2. Setting process Next, a setting process for making a desired filter function in the DSP 44 of the physical quantity sensor 1 will be described. FIG. 6 is a flowchart of a process executed after power supply to the physical quantity sensor 1 is started from the VDD terminal. When power supply to the physical quantity sensor 1 is started, the DSP 44 executes a predetermined start sequence (step S100). The start sequence may include various processes. In this embodiment, the start sequence includes the transfer of information from the non-volatile memory 62 to the register 61. That is, the DSP 44 reads out the sampling frequency fs used in the physical quantity sensor 1 from the non-volatile memory 62 and stores it in the first area. In addition, the DSP 44 reads out the filter coefficient of the notch filter 44d from the non-volatile memory 62 and stores it in the register 61.

[0062] After the power supply is started, a predetermined period becomes a mode setting acceptance period. During this acceptance period, the user operates the external device to set information indicating a desired mode. The external device transmits the information indicating the mode to the physical quantity sensor 1. The interface circuit 70 acquires the information indicating the mode and stores it in a predetermined area of ​​the register 61. When the information indicating the mode is stored in the predetermined area of ​​the register 61, the DSP 44 accepts the mode setting based on the information (step S105).

[0063] The information indicating the mode may be defined in any manner, but in this embodiment, the information indicating the mode includes information specifying whether to use the programmable filter 44b or the selectable filter 44c. Also, in this embodiment, the information indicating the mode includes information specifying whether to use the notch filter 44d.

[0064] The DSP 44 identifies the mode set by the user based on the information indicating the mode (step S110). If the mode set by the user is identified as a mode using the programmable filter 44b in step S110, the DSP 44 executes the processes of steps S115 to S125. On the other hand, if the mode set by the user is identified as a mode using the selectable filter 44c in step S110, the DSP 44 executes the processes of steps S130 to S140.

[0065] If the mode set by the user is the mode using the programmable filter 44b, the DSP 44 outputs the sampling frequency to the external device in step S115. That is, the user operates the external device to read out the sampling frequency fs stored in the first area of ​​the register 61.

[0066] Next, the DSP 44 writes the filter coefficients in the register 61 (step S120). That is, the user operates the external device to simulate the characteristics of the programmable filter 44b using the sampling frequency fs, and determines the filter coefficients of the second-order IIR filters 44b1 to 44b4. Then, the user operates the external device to transmit filter setting data indicating the filter coefficients to the physical quantity sensor 1. In the physical quantity sensor 1, the interface circuit 70 receives the filter setting data and stores it in the first area of ​​the register 61. That is, the sampling frequency fs is overwritten with the filter setting data.

[0067] Next, the DSP 44 performs filter initialization (step S125). The filter initialization in step S125 is a process for applying the filter coefficients stored in the first area to the programmable filter 44b. The filter initialization includes a setting process for applying the filter coefficients acquired in step S120 to the second-order IIR filters 44b1 to 44b4, and a process for turning on the selection setting value sel1. If the setting for using the notch filter 44d is set in the information indicating the mode, the process includes a process for turning off the selection setting value sel2. If the setting for using the notch filter 44d is not set, the process includes a process for turning on the selection setting value sel2. When the filter initialization is performed, the DSP 44 goes to sleep for a predetermined period. When the predetermined period has elapsed, the programmable filter 44b enters a state in which it performs digital filter processing using the filter coefficients specified by the user.

[0068] If the mode set by the user is a mode using the selectable filter 44c, in step S130, the DSP 44 accepts the order n and cutoff frequency fc of the selectable filter 44c. That is, the user specifies the order n and cutoff frequency fc for making the filter have the desired characteristics based on a manual or the like. Then, the user operates an external device to transmit the order n and the cutoff frequency fc to the physical quantity sensor 1. In the physical quantity sensor 1, the interface circuit 70 receives the order n and the cutoff frequency fc and stores them in a predetermined area of ​​the register 61.

[0069] Next, the DSP 44 writes the filter coefficient to the register 61 (step S135). That is, the DSP 44 refers to a predetermined area of ​​the non-volatile memory 62, and transfers to the register 61 the filter coefficient corresponding to the order n and the cutoff frequency fc.

[0070] Next, the DSP 44 performs filter initialization (step S140). The filter initialization in step S140 is a process for applying the filter coefficient stored in the register 61 in step S135 to the selectable filter 44c. The filter initialization includes a setting process for applying the filter coefficient acquired in step S135 to the selectable filter 44c and a process for turning off the selection setting value sel1. In addition, if the setting for using the notch filter 44d is made in the information indicating the mode, the process includes a process for turning off the selection setting value sel2. If the setting for using the notch filter 44d is not made, the process includes a process for turning on the selection setting value sel2. When the filter initialization is performed, the DSP 44 goes to sleep for a predetermined period. When the predetermined period has elapsed, the selectable filter 44c becomes in a state for performing digital filter processing using the filter coefficient specified by the user.

[0071] 3. Other embodiments The above-described embodiment is an example for carrying out the present invention, and various other embodiments can be adopted. For example, the processing order of the DSP 44 is not limited to the processing order in the above-described embodiment, and the processing order may be changed arbitrarily, such as a processing order of the notch filter 44d and the programmable filter 44b. Furthermore, the selectable filter 44c and the notch filter 44d may be omitted as necessary. Of course, other digital filter processes may be added. Furthermore, the filter coefficient of the notch filter 44d may be selectable by the user.

[0072] The A / D conversion circuit only needs to be able to A / D convert the signal output from the sensor element. In other words, since an analog signal is output from the sensor element, the A / D conversion circuit only needs to be able to convert the detection value of the physical quantity indicated by the analog signal into a digital signal. The signal input to the A / D conversion circuit may be the signal itself output from the sensor element, or may be a signal that has been subjected to various processes on the signal output from the sensor element.

[0073] The interface circuit only needs to be able to receive filter setting data that determines the characteristics of each of the multiple digital filter processes. In other words, it only needs to be able to set the characteristics of each of the multiple digital filter processes by the filter setting data transmitted from an external device. The filter setting data may be set for all of the multiple digital filters, or may be set for some of the filters. In the latter case, for example, default filter setting data is applied to the digital filters that have not been set.

[0074] The filter setting data may be any data that defines the characteristics of the digital filter processing. Therefore, the configuration in which the characteristics of the above-mentioned second-order IIR filter are adjusted by using five filter coefficients as filter setting data is one example. For example, IIR filters of any order may be connected in series, and the characteristics may be defined by filter setting data according to the mode of the filter. The mode of the filter is not limited, and an IIR filter of a different mode from the above example may be used, or another filter such as an FIR filter may be used.

[0075] Furthermore, in the expression "multiple digital filter processes," when counting the digital filter processes, any processing unit may be counted as 1. In the above embodiment, a second-order IIR filter is counted as one digital filter process, but this is not limited to the configuration. For example, the first order of an n-th order digital filter process may be counted as one digital filter process.

[0076] The memory circuitry may be configured to store the filter setting data. In other words, the memory circuitry may store the filter setting data transmitted from an external device and hold the filter setting data so that the filter setting data can be referenced by the signal processing circuit. Of course, the memory circuitry may also store other data.

[0077] The signal processing circuit only needs to be able to sequentially execute each of a plurality of digital filter processes having characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit. That is, the plurality of digital filter processes are connected in series, and each digital filter process is executed in order. Such a configuration is equivalent to performing digital filter processing of a transfer function obtained by multiplying each of the plurality of digital filter processes by their respective transfer functions. Of course, the order of execution of each digital filter process is arbitrary. Also, if there is a digital filter process that is disabled by the filter setting data, that digital filter process does not need to be executed substantially.

[0078] The above-described embodiments are merely examples, and the present invention is not limited to these. The present invention includes configurations that are substantially the same as those described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments. [Explanation of symbols]

[0079] 1...physical quantity sensor, 2...sensor element, 3...circuit device, 10...reference voltage circuit, 20...drive circuit, 30...detection circuit, 40...digital processing unit, 42...A / D conversion circuit, 44a...temperature compensation unit, 44b...programmable filter, 44b1 to 44b4...second-order IIR filters, 44b11 to 44b14...addition unit, 44b17 to 44b111...multiplication unit, 44b15, 44b16...delay unit, 44c...selectable filter, 44d...notch filter, 44e...selector, 44f...selector, 50...oscillating circuit, 60...storage unit, 61...register, 62...non-volatile memory, 70...interface circuit, 80...temperature sensor, 82...A / D conversion circuit, 84...temperature compensation value calculation unit

Claims

1. An A / D conversion circuit that performs A / D conversion on a signal output from the sensor element; an interface circuit for receiving filter setting data for determining characteristics of each of a plurality of digital filters; a storage circuit for storing the filter setting data; a signal processing circuit that sequentially executes each of the plurality of digital filter processes, the characteristics of which are determined by the filter setting data, on the digital signal output from the A / D conversion circuit.

2. the signal processing circuit performs band-pass filtering as the digital filtering process. The circuit device according to claim 1 .

3. the signal processing circuit performs notch filtering as the digital filtering process. The circuit device according to claim 1 .

4. the signal processing circuit performs low-pass filtering as the digital filtering process. The circuit device according to claim 1 .

5. the signal processing circuit performs high-pass filtering as the digital filtering process. The circuit device according to claim 1 .

6. A drive circuit that vibrates the sensor element at a drive frequency in response to a drive signal; a detection circuit for acquiring a signal at a detection frequency from the sensor element; the signal processing circuit performs at least one of a notch filter process for attenuating a component of a detuning frequency that is a difference between the drive frequency and the detection frequency, and the plurality of digital filter processes. The circuit device according to claim 1 .

7. the memory circuit further stores information for setting the low-pass filter processing to a user-specified order and cutoff frequency; the signal processing circuit performs one of the low-pass filter processing of the order and the cutoff frequency corresponding to the information and the plurality of digital filter processings; The circuit device according to claim 1 .

8. the memory circuit stores individual data corresponding to a sampling frequency of the A / D conversion circuit in a first area in an initial state; the first area is overwritten with the filter setting data input from the interface circuit; The circuit device according to claim 1 .

9. A method for setting a circuit device including an A / D conversion circuit that performs A / D conversion on a signal output from a sensor element, an interface circuit, a memory circuit, and a signal processing circuit that performs digital filtering on the digital signal output from the A / D conversion circuit, comprising: inputting filter setting data for determining characteristics of each of a plurality of digital filter processes to the interface circuit and storing the data in the memory circuit; causing the signal processing circuit to sequentially execute each of the plurality of digital filter processes having characteristics determined by the filter setting data on the digital signal output from the A / D conversion circuit; How to set up a circuit device.

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