Multiplexing / demultiplexing device, manufacturing method therefor, design device, design program, and demultiplexer

Abstract

To provide a multiplexing / demultiplexing device capable of obtaining desired characteristics, a manufacturing method therefor, a design device, a design program, and a demultiplexer.SOLUTION: Provided is a method for manufacturing a multiplexing / demultiplexing device that includes a substrate and a first port for inputting light and a second port for outputting light that are disposed on the substrate. The method includes the steps of: designing the position of a plurality of holes so that three adjacent holes are aligned in shape of a triangular lattice; and forming the plurality of holes on one side of the substrate.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure relates to a multiplexer / demultiplexer, a manufacturing method thereof, a design device, a design program, and a demultiplexer. [Background technology]

[0002] Mosaic-shaped optical passive elements have been developed. By arranging multiple holes in a plane, light can be split at a specified intensity ratio, and a compact multiplexer / demultiplexer can be formed (Non-Patent Document 1, etc.). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] “Compact Power Splitters with Mosaic-based Structure Designed by Bayesian Direct-binary-search Method” Takuya Mitarai et.al.in Proc.OECC / PSS 2022,Toyama,Japan,Aug.2022,TuE2-4 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing process, the hole arrangement is designed and the silicon layer is dry etched to form the holes. Due to manufacturing errors, the walls between the holes may become thin. The walls may disappear and the holes may merge into one. In such cases, there is a risk of the characteristics deteriorating. Therefore, the object is to provide a multiplexer / demultiplexer that can obtain the desired characteristics, a manufacturing method thereof, a design device, a design program, and a demultiplexer. [Means for solving the problem]

[0005] A manufacturing method for a multiplexer / demultiplexer according to the present disclosure is a manufacturing method for a multiplexer / demultiplexer having a substrate, a first port for inputting light and a second port for outputting light, the method including the steps of: designing the positions of a plurality of holes so that three adjacent holes are arranged in a triangular lattice pattern; and forming the plurality of holes on one surface of the substrate. Effect of the Invention

[0006] According to the present disclosure, it is possible to provide a multiplexer / demultiplexer capable of obtaining desired characteristics, a manufacturing method thereof, a design device, a design program, and a demultiplexer. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 1A is a plan view illustrating a multiplexer / demultiplexer according to the first embodiment. [Figure 1B] FIG. 1B is an enlarged plan view of the hole. [Figure 2A] FIG. 2A is a cross-sectional view illustrating an example of a multiplexer / demultiplexer. [Figure 2B] FIG. 2B is a cross-sectional view illustrating an example of a multiplexer / demultiplexer. [Figure 3A] FIG. 3A is a block diagram illustrating an example of an apparatus for designing a multiplexer / demultiplexer. [Figure 3B] FIG. 3B is a block diagram showing the hardware configuration of the control unit. [Figure 3C] FIG. 3C is a flowchart illustrating a method for manufacturing a multiplexer / demultiplexer. [Figure 3D] FIG. 3D is a flowchart illustrating a method for manufacturing a multiplexer / demultiplexer. [Figure 4] FIG. 4 is a plan view illustrating a method for manufacturing a multiplexer / demultiplexer. [Figure 5A] FIG. 5A is a cross-sectional view illustrating a method for manufacturing a multiplexer / demultiplexer. [Figure 5B] FIG. 5B is a cross-sectional view illustrating a method for manufacturing the multiplexer / demultiplexer. [Figure 5C] FIG. 5C is a cross-sectional view illustrating a method for manufacturing the multiplexer / demultiplexer. [Figure 6]FIG. 6 is a diagram illustrating the branching ratio. [Figure 7A] FIG. 7A is an enlarged plan view of a hole in a multiplexer / demultiplexer according to a comparative example. [Figure 7B] FIG. 7B is an enlarged plan view of a hole in a multiplexer / demultiplexer according to a modified example. [Figure 8] FIG. 8 is a plan view illustrating the multiplexer / demultiplexer according to the second embodiment. [Figure 9] FIG. 9 is a plan view illustrating the multiplexer / demultiplexer according to the third embodiment. [Figure 10] FIG. 10 is a plan view illustrating the multiplexer / demultiplexer according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram illustrating the branching ratio. [Figure 12] FIG. 12 is a plan view illustrating a demultiplexer according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram illustrating the transmittance. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure is (1) a method for manufacturing a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the method including the steps of: designing the positions of a plurality of holes so that three adjacent holes are arranged in a triangular lattice; and forming the plurality of holes on one surface of the substrate. The walls between adjacent holes become thicker and less likely to break. Adjacent holes are less likely to be coupled together and are separated from each other. By providing holes in a designed number and layout, desired characteristics can be obtained. (2) In the above (1), the designing step may include a step of dividing the surface of the substrate into a plurality of regions arranged in a triangular lattice pattern, and a step of disposing the holes in some of the plurality of regions and not disposing the holes in another portion of the plurality of regions. The walls are thickened and the plurality of holes are separated. The desired characteristics can be obtained. (3) In the above (2), the planar shape of the region may be a regular hexagon, and the step of dividing the surface of the substrate into a plurality of regions may include a step of arranging the plurality of regions in a close-packed structure. The walls are thickened and the plurality of holes are separated. Desired characteristics can be obtained. (4) In any of the above (1) to (3), the designing step may be a step of designing the positions of the plurality of holes based on the characteristics of the multiplexer / demultiplexer. A multiplexer / demultiplexer having a triangular lattice arrangement and desired characteristics can be manufactured. (5) In any of the above (1) to (4), the step of forming the plurality of holes may include a step of forming the holes by dry etching the silicon layer of the substrate. The plurality of holes are separated by thick walls, and desired characteristics can be obtained. (6) A multiplexer / demultiplexer comprising a substrate and a first port and a second port provided on the substrate, in which light is input to the first port and output from the second port, a plurality of holes provided on one surface of the substrate, and three adjacent holes arranged in a triangular lattice pattern. The walls between adjacent holes are thick, making it less likely to break. Adjacent holes are less likely to be coupled to each other and are isolated from each other. By providing holes in a designed number and layout, desired characteristics can be obtained. (7) In the above (6), the substrate may have a silicon layer, and the plurality of holes may be provided on one surface of the silicon layer. The walls are thick, so that the plurality of holes are separated. Desired characteristics can be obtained. (8) In the above (6) or (7), three adjacent holes may be arranged in an equilateral triangle. The walls are thick to separate the holes. Desired characteristics can be obtained. (9) In any one of the above (6) to (8), one of the first ports and a plurality of the second ports may be provided, so that a branching ratio can be set to a desired value. (10) A demultiplexer comprising a first multiplexer / demultiplexer, a second multiplexer / demultiplexer, and a third multiplexer / demultiplexer, each of the first multiplexer / demultiplexer, the second multiplexer / demultiplexer, and the third multiplexer / demultiplexer comprises a substrate, a first port and a second port provided on the substrate, a plurality of holes are provided on one surface of the substrate, three adjacent holes are arranged in a triangular lattice pattern, the first multiplexer / demultiplexer has two of the second ports, one of the two second ports of the first multiplexer / demultiplexer is coupled to the first port of the second multiplexer / demultiplexer, and the other of the two second ports of the first multiplexer / demultiplexer is coupled to the first port of the third multiplexer / demultiplexer. A desired characteristic can be obtained. (11) A design device for a multiplexer / demultiplexer having a substrate and a first port provided on the substrate for inputting light and a second port for outputting light, the multiplexer / demultiplexer having a plurality of holes provided on a surface of the substrate, the design device designing positions of the plurality of holes such that three adjacent holes are arranged in a triangular lattice pattern within the surface of the substrate. The walls between adjacent holes become thicker and less likely to break. Adjacent holes are less likely to couple with each other and are isolated from each other. By providing holes in the designed number and layout, desired characteristics can be obtained. (12) A design program for a multiplexer / demultiplexer having a substrate and a first port provided on the substrate for inputting light and a second port for outputting light, the multiplexer / demultiplexer having a plurality of holes provided on a surface of the substrate, the design program causing a computer to function as a design unit that designs the positions of the plurality of holes so that three adjacent holes are arranged in a triangular lattice pattern within the surface of the substrate. The walls between adjacent holes become thicker and less likely to break. Adjacent holes are less likely to be coupled together and are separated from each other. By providing holes in the designed number and layout, desired characteristics can be obtained.

[0010] [Details of the embodiment of the present disclosure] Specific examples of a multiplexer / demultiplexer, a manufacturing method thereof, a design device, a design program, and a demultiplexer according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] First Embodiment (multiplexer / demultiplexer) 1A is a plan view illustrating a multiplexer / demultiplexer 100 according to a first embodiment. The multiplexer / demultiplexer is a passive optical element in a mosaic pattern. As will be described later, the mosaic pattern refers to a configuration in which a plurality of holes 30 are two-dimensionally arranged in a plane. The multiplexer / demultiplexer 100 branches and outputs incident light, or multiplexes and outputs multiple incident light beams.

[0012] The multiplexer / demultiplexer 100 is formed on a substrate 10. The substrate 10 is, for example, an SOI (Silicon on Insulator) substrate. Two sides of the substrate 10 are parallel to the X-axis direction. The other two sides are parallel to the Y-axis direction. The top surface of the substrate 10 is parallel to the XY plane. The Z-axis direction is a normal direction of the substrate 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other. The H1 axis and the H2 axis are parallel to the XY plane and inclined from the X-axis and the Y axis. The inclination angle of the H1 axis from the X-axis is, for example, 30°. The inclination angle of the H2 axis from the X-axis is, for example, -30°.

[0013] The planar shape of the substrate 10 is rectangular. The length L1 of the side in the X-axis direction of the substrate 10 is, for example, 2.4 μm. The length L2 of the side in the Y-axis direction is, for example, 2.4 μm.

[0014] The multiplexer / demultiplexer 100 has ports 20, 22, and 24. These ports are silicon waveguides formed in the silicon layer 16 described below. The width of the ports is, for example, 0.48 μm. Port 20 (first port) functions, for example, as an input port. Port 22 and port 24 (second port) function, for example, as an output port. Port 20 is provided on one side of the substrate 10. Port 22 and port 24 are provided on another side of the substrate 10.

[0015] The multiplexer / demultiplexer 100 has a plurality of holes 30. The plurality of holes 30 are arranged two-dimensionally within the plane of the substrate 10.

[0016] 1B is an enlarged plan view of hole 30. A plurality of holes 30 and a plurality of regions 32 (pixels) are arranged on the surface of substrate 10. Regions 32 (pixels) are set in the design of multiplexer / demultiplexer 100, and regions 32 do not necessarily have to be actually manufactured on substrate 10. Holes 30 are manufactured in substrate 10. The dashed lines in FIG. 1B are imaginary lines connecting the centers of regions 32.

[0017] The planar shape of the holes 30 is, for example, a circle. The planar shape of the regions 32 is, for example, a regular hexagon. Some of the multiple regions 32 have holes 30, and some do not. The regions 32 in which the holes 30 are provided are referred to as regions 32a. The regions 32 in which the holes 30 are not provided are referred to as regions 32b. One hole 30 is located in the center of region 32a. The center of the hole 30 coincides with the center of region 32.

[0018] The holes 30 and the regions 32 are periodically arranged in the Y-axis, H1-axis, and H2-axis directions. The regions 32 are arranged in a close-packed structure. One region 32 is surrounded by six other regions 32. Two adjacent regions 32 share one side and two vertices located at both ends of the side.

[0019] The triangle 33 is a virtual equilateral triangle formed by connecting the centers of three adjacent regions 32. The centers of the three regions 32a form the triangle 33. The triangle 33 is an equilateral triangle. In other words, the adjacent holes 30 are arranged in a triangular lattice pattern.

[0020] The length L3 between two opposing sides of the region 32 is, for example, 160 nm. The diameter D1 of the hole 30 is smaller than the length L3, for example, 120 nm. The distance L4 between the centers of two adjacent holes 30 is, for example, 160 nm. A wall 34 is located between two adjacent holes 30. The wall 34 is thinnest on the line connecting the centers of the two adjacent holes 30. The thickness T1 of the wall 34 at the thinnest point is, for example, 40 nm.

[0021] 2A and 2B are cross-sectional views illustrating an example of the multiplexer / demultiplexer 100. Fig. 2A illustrates a cross section including a port 20. Fig. 2B illustrates a cross section including a hole 30.

[0022] As shown in FIGS. 2A and 2B, the substrate 10 has a substrate 12, a box layer 14, and a silicon layer 16. The box layer 14 is laminated on one surface of the substrate 12. The silicon layer 16 is laminated on the surface of the box layer 14 opposite the substrate 12. The clad layer 18 is laminated on the surface of the silicon layer 16 opposite the box layer 14. The substrate 12 and the silicon layer 16 are made of silicon (Si). The box layer 14 and the clad layer 18 are made of an insulator such as silicon oxide (SiO2). The box layer 14 has a thickness of, for example, 3 μm. The silicon layer 16 has a thickness of, for example, 220 nm.

[0023] As shown in Fig. 2A, the silicon layer 16 has a waveguide core 15 and a terrace 17. The waveguide core 15 functions as a port 20. The terraces 17 are located on both sides of the waveguide core 15, and the waveguide core 15 is spaced from the terraces 17. The silicon layer 16 forms a flat surface at the terraces 17. A cladding layer 18 is embedded between the waveguide core 15 and the terraces 17. The ports 22 and 24 have the same configuration as the port 20.

[0024] In FIG. 2B, three holes 30 are provided in the silicon layer 16. The holes 30 penetrate the silicon layer 16 in the Z-axis direction, but they do not have to penetrate the silicon layer 16. The depth of the holes 30 can be controlled by the etching time, etc. The holes 30 are filled with the cladding layer 18. The refractive index of the holes 30 is different from the refractive index of the silicon layer 16. Since the refractive index changes periodically within the plane of the substrate 10, the substrate 10 functions as a photonic crystal. The holes 30 are hollow, and air may be trapped inside. No holes 30 are provided in the region 32b of the silicon layer 16.

[0025] The arrows in FIG. 1A represent the input and output of light. The multiplexer / demultiplexer 100 functions as a demultiplexer with one input and two outputs. Light is input to the multiplexer / demultiplexer 100 from port 20. The light propagates within the surface of the substrate 10 and is output from ports 22 and 24. The layout of the holes 30 determines the branching ratio of the light. If the branching ratio is X:Y, then of the light input from port 20, X% is output from port 22, and Y (=100-X)% is output from port 24. The arrangement of the holes 30 is designed according to the desired branching ratio.

[0026] (design equipment) 3A is a block diagram illustrating a design device 110 for the multiplexer / demultiplexer 100. The design device 110 designs the layout of the multiplexer / demultiplexer 100.

[0027] The design device 110 has a control unit 50. The control unit 50 is a computer or the like, and functions as a first design unit 51 and a second design unit 52. The first design unit 51 performs a design to divide the surface of the substrate 10 into a plurality of regions 32. The second design unit 52 designs the positions of a plurality of holes 30 by defining a region 32a and a region 32b from the plurality of regions 32.

[0028] Fig. 3B is a block diagram showing a hardware configuration of the control unit 50. As shown in Fig. 3B, the control unit 50 includes a CPU (Central Processing Unit) 54, a RAM (Random Access Memory) 56, a ROM (Read Only Memory) 58, a storage device 60, and an interface 62. The CPU 54, the RAM 56, the ROM 58, the storage device 60, and the interface 62 are connected to one another via a bus or the like. The RAM 56 is a volatile memory that temporarily stores programs, data, and the like. The storage device 60 is a solid state drive (SSD) such as a flash memory, a hard disk drive (HHD), or the like. The storage device 60 stores programs and the like.

[0029] The CPU 54 executes a program stored in the RAM 56, thereby realizing a first design unit 51 and a second design unit 52 in the control unit 50. Each unit of the control unit 50 may be hardware such as a circuit.

[0030] (Manufacturing method) 3C and 3D are flowcharts illustrating a method for manufacturing multiplexer / demultiplexer 100. As shown in FIG. 3C, characteristics required for multiplexer / demultiplexer 100 are determined (step S10). The characteristics include the branching ratio of light. The size of multiplexer / demultiplexer 100 is also determined. Conditions such as the characteristics and element sizes are input to design device 110.

[0031] Based on the characteristics determined in step S10, the multiplexer / demultiplexer 100 is designed (step S12). The design is performed by performing an inverse problem analysis using machine learning with the desired characteristics as input and the element structure as output. Specifically, the arrangement of the multiple holes 30 is designed using a Bayesian direct-binary-search method (Bayes DBS).

[0032] 3D is a flow chart illustrating the design process. The first design unit 51 divides the surface of the substrate 10 into a plurality of regions 32 (step S20). The regular hexagonal regions 32 are arranged in a close-packed structure. The second design unit 52 determines the arrangement of the plurality of holes 30 (step S22).

[0033] As shown in FIG. 3C, the substrate 10 is exposed to an electron beam or the like to pattern the resist (step S14). The silicon layer 16 is dry etched to form the waveguide cores 15 and the holes 30 (step S16). After the etching, the cladding layer 18 is deposited (step S18). The wafer is cut to form the multiplexer / demultiplexer 100.

[0034] Fig. 4 is a plan view illustrating a manufacturing method of the multiplexer / demultiplexer 100. In the design process (step S12 in Fig. 3C), the arrangement of holes 30 and regions 32 is determined on the surface of the substrate 10 as shown in Fig. 4. The planar shape of the regions 32 is a regular hexagon. For example, 255 regions 32 are laid out in a close-packed structure on the substrate 10 that is 2.4 µm square.

[0035] 4, the regions 32 marked with 0 are regions 32a, in which holes 30 are provided, and the regions 32 marked with 1 are regions 32b, in which holes 30 are not provided. The layout of the holes 30 is determined so as to realize the characteristics determined in step S10.

[0036] 5A to 5C are cross-sectional views illustrating a method for manufacturing the multiplexer / demultiplexer 100, illustrating a cross section including the hole 30. FIG 5A to 5C show the processes from step S14 to step S18 in FIG 3C.

[0037] As shown in FIG. 5A, a resist 40 is formed on the surface of the silicon layer 16 of the substrate 10 opposite the box layer 14. The resist 40 is patterned by an electron beam or the like. An opening 42 is formed in the resist 40 at a portion corresponding to the hole 30. As shown in FIG. 5B, the hole 30 is formed by removing the portion of the silicon layer 16 exposed from the opening 42 by, for example, inductively coupled plasma ion etching (ICP-RIE). After etching, the resist 40 is removed. As shown in FIG. 5C, a cladding layer 18 is provided by, for example, plasma-enhanced chemical vapor deposition (PECVD).

[0038] The port is also formed by the same process as in Figures 5A to 5C. The portions of the silicon layer 16 on both sides of the waveguide core 15 are removed by ICP-RIE, and the cladding layer 18 is provided.

[0039] FIG. 6 is a diagram illustrating branching ratios. The horizontal axis represents the wavelength of light. The vertical axis represents the branching ratio of light. FIG. 6 shows an example where the branching ratio is 80:20 and an example where the branching ratio is 60:40. In both examples, the dashed lines represent design values. The solid lines represent measured values. The multiplexer / demultiplexer 100 is designed and manufactured with the design values ​​as the desired branching ratios. The branching ratio of the manufactured multiplexer / demultiplexer 100 is measured. The design value of the diameter of the holes 30 is 120 nm, but due to etching precision and other factors, some holes 30 have a diameter of 140 nm.

[0040] As shown in Fig. 6, the measured values ​​are close to the designed values ​​over a wavelength band wider than the C-band (1530 nm to 1565 nm). The excess loss is about 0.5 dB. As shown in Fig. 3C, the desired characteristics can be realized by designing the arrangement of the holes 30 with the designed values ​​as the desired characteristics.

[0041] (Comparative Example) 7A is an enlarged plan view of holes 30 in a multiplexer / demultiplexer according to a comparative example. In the comparative example, regions 32 are square. A plurality of regions 32 are arranged in a square lattice pattern, and holes 30 are also arranged in a square lattice pattern. A square lattice pattern means that holes 30 are arranged periodically in the X-axis direction and the Y-axis direction. As in the embodiment, a plurality of holes 30 are arranged two-dimensionally in a multiplexer / demultiplexer that is 2.4 μm square.

[0042] The length L5 of one side of the region 32 is, for example, 150 nm. The diameter D2 of the hole 30 is, for example, 120 nm. The thickness T2 of the wall 34 between the two holes 30 is 30 nm, which is smaller than the thickness T1 of the wall 34 in the first embodiment.

[0043] In the comparative example, the wall 34 is thin. The wall disappears and the two holes 30 are combined into one, resulting in a deterioration in characteristics. The wall 34 can be thickened by enlarging the area 32. However, if the size of the multiplexer / demultiplexer is limited to, for example, 2.4 μm×2.4 μm, it is difficult to provide a predetermined number of holes 30, and there is a risk that the desired characteristics will not be obtained. If the number of holes 30 is maintained and the wall 34 is thickened, the multiplexer / demultiplexer will become large. The wall 34 can be thickened by reducing the size of the holes 30. However, if the size of the holes 30 is changed, there is a risk that the characteristics will also change.

[0044] According to the first embodiment, a design is made such that adjacent holes 30 are arranged in a triangular lattice pattern as shown in Fig. 4, and holes 30 are formed in the substrate 10. As shown in Figs. 1A and 1B, a plurality of holes 30 are arranged in a triangular lattice pattern within the plane of the multiplexer / demultiplexer 100. The walls 34 between adjacent holes 30 are thick. Because the walls 34 are thick and not easily broken, adjacent holes 30 are not easily coupled to each other and are separated from each other. By providing holes 30 in the designed number and layout, it is possible to obtain the desired characteristics as shown in Fig. 6.

[0045] By arranging the regions 32 in a triangular lattice pattern, the walls 34 can be thickened without increasing the size of the regions 32. The number of holes 30 does not need to be reduced, and can be maintained at, for example, 255. It is possible to provide a desired number and layout of holes 30 in a multiplexer / demultiplexer 100 that is, for example, 2.4 μm square. It is possible to obtain a multiplexer / demultiplexer 100 that is small, such as a few μm square, and has the desired characteristics.

[0046] As shown in Fig. 4, in the design process, the surface of the substrate 10 is divided into a plurality of regions 32. Of the plurality of regions 32, regions 32a in which holes 30 are provided and regions 32b in which holes 30 are not provided are defined. By arranging the regions 32 two-dimensionally in a triangular lattice shape, the holes 30 are also arranged in a triangular lattice shape. By manufacturing the holes 30 based on the design, the walls 34 become thicker and the plurality of holes 30 are separated. The desired characteristics can be obtained.

[0047] As shown in Figures 1B and 4, the planar shape of the region 32 is a regular hexagon, and multiple regions 32 are arranged in a close-packed structure. Multiple holes 30 are arranged in a lattice of equilateral triangles. The walls 34 are thickened to separate multiple holes 30. Desired characteristics can be obtained.

[0048] 3C, the characteristics are first determined, and a triangular lattice arrangement is designed based on the characteristics. A multiplexer / demultiplexer 100 having the triangular lattice arrangement and desired characteristics can be manufactured.

[0049] For example, the holes 30 are formed in the silicon layer 16 of the substrate 10 by dry etching. Due to an error in the position of the resist pattern, side etching, etc., the diameter D1 of the holes 30 may be larger than the design value. According to the first embodiment, the wall 34 is thick, so the tolerance is improved. Adjacent holes 30 are unlikely to be connected and are likely to be separated from each other. Even if an error occurs, the desired characteristics can be obtained. The thickness T1 of the wall 34 is 30 nm or more, 35 nm or more, 45 nm or more, 50 nm or more, etc.

[0050] As shown in FIG. 1A, a substrate 10 is provided with ports 20, 22, and 24. Light is input from port 20 and output from ports 22 and 24. The multiplexer / demultiplexer 100 functions as a power splitter that splits light into two. By providing a plurality of holes 30, the splitting ratio can be set to a desired value, and can be 80:20 as in the example of FIG. 6, or can be 60:40. As in the example described later, the splitting ratio can be set to a desired value.

[0051] The number of output ports is two or more, and may be three or more, or four or more. The multiplexer / demultiplexer 100 may multiplex light input from a plurality of ports. The multiplexer / demultiplexer 100 may multiplex light input from two or more ports and output the multiplexed light.

[0052] The planar shape of the hole 30 may be a circle, a polygon, etc. The planar shape of the region 32 may be a polygon such as a hexagon, a rectangle, or a triangle, or may be a shape including a curve such as a circle.

[0053] The multiplexer / demultiplexer may be formed on an SOI substrate, or may be formed on a component other than an SOI substrate. The waveguide may include a Si waveguide core 15, or may be formed of other materials.

[0054] (Modification) 7B is an enlarged plan view of a hole 30 in a multiplexer / demultiplexer according to a modified example. Regions 32 are square. Two adjacent regions 32 are arranged at a distance L6 from a square lattice. If the distance L6 is 40 nm, the thickness T3 of the wall 34 between the two holes 30 is 35 nm, which is larger than the thickness T2 in the comparative example.

[0055] By shifting the holes 30 and the regions 32 from a square lattice, a triangular lattice arrangement can be achieved. If the distance L6 is set to half the length L5 of one side of the square lattice, an equilateral triangular lattice arrangement can be achieved as shown in FIG. 1B.

[0056] <Second embodiment> FIG. 8 is a plan view illustrating a multiplexer / demultiplexer 200 according to the second embodiment. Description of the same configuration as in the first embodiment will be omitted. In the second embodiment, the branching ratio of the light intensity is set to 90:10. With the branching ratio of 90:10 as a desired characteristic, the process of FIG. 3C is performed. The arrangement of the holes 30 is determined according to the branching ratio, and the holes 30 as shown in FIG. 8 are formed.

[0057] The multiplexer / demultiplexer 200 splits the light input from the port 20 into two and outputs the split light. The ratio of the intensity of the light output from the port 22 to the intensity of the light output from the port 24 is 90:10.

[0058] <Third embodiment> 9 is a plan view illustrating a multiplexer / demultiplexer 300 according to the third embodiment. Description of the same configuration as in the first or second embodiment will be omitted. In the third embodiment, the branching ratio of light is 70:30. The ratio of the intensity of the light output from port 22 to the intensity of the light output from port 24 is 70:30.

[0059] <Fourth embodiment> 10 is a plan view illustrating a multiplexer / demultiplexer 400 according to the fourth embodiment. Description of the same configuration as any of the first to third embodiments will be omitted. In the fourth embodiment, the branching ratio of light is 50:50. The ratio of the intensity of the light output from port 22 to the intensity of the light output from port 24 is 70:30.

[0060] 8 and 9, more holes 30 are provided between port 20 and port 24 than between port 20 and port 22. In other words, more holes 30 are arranged near port 24, which has the lower output, than near port 22, which has the higher output of the two ports. As shown in Fig. 10, in an example where the branching ratio is 50:50, the arrangement of holes 30 is symmetrical with respect to the X-axis.

[0061] FIG. 11 is a diagram illustrating branching ratios. The dashed line represents an example of 90:10 (second embodiment). The solid line represents an example of 70:30 (third embodiment). The dotted line represents an example of 50:50 (fourth embodiment). In each example, the branching ratio is close to the design value. By designing the arrangement of the holes 30 based on the desired branching ratio, a multiplexer / demultiplexer according to the branching ratio can be manufactured. The excess loss is about 0.5 dB. Since the destruction of the wall 34 is suppressed and the multiple holes 30 are separated, the loss of light is reduced.

[0062] <Fifth embodiment> 12 is a plan view illustrating a demultiplexer 500 according to the fifth embodiment. Description of the same configuration as in any of the first to fourth embodiments will be omitted.

[0063] Demultiplexer 500 has three multiplexers / demultiplexers 510, 520, and 530. For example, the length L7 in the X-axis direction of one multiplexer / demultiplexer is 17.2 μm. The length L8 in the Y-axis direction is 7.5 μm. Multiplexer / demultiplexer 510 (first multiplexer / demultiplexer) has ports 20a, 22a, and 24a. Multiplexer / demultiplexer 520 (second multiplexer / demultiplexer) has ports 20b, 22b, and 24b. Multiplexer / demultiplexer 530 (third multiplexer / demultiplexer) has ports 20c, 22c, and 24c.

[0064] Port 22a of multiplexer / demultiplexer 510 is optically coupled to port 20a of multiplexer / demultiplexer 520. Port 24a of multiplexer / demultiplexer 510 is optically coupled to port 20c of multiplexer / demultiplexer 530. The ports may be coupled by, for example, a silicon waveguide, or may be coupled by a transmission path such as an optical fiber.

[0065] The three multiplexers / demultiplexers have a plurality of holes 30. The diameter of the holes 30 is 160 nm. The center-to-center distance between two holes 30 is 250 nm. In each multiplexer / demultiplexer, the plurality of holes 30 are arranged in a triangular lattice pattern. The layout of the holes 30 is determined according to the characteristics required of the multiplexer / demultiplexer. The three multiplexers / demultiplexers split light into two for each wavelength. The demultiplexer 500 is a device with one input and four outputs, and splits light into four for each wavelength.

[0066] The multiplexer / demultiplexer 510 splits the light input from port 20a into two according to the wavelength and outputs them. The light with wavelengths of 1590 nm and 1570 nm are output from port 22a and input to the multiplexer / demultiplexer 520 from port 20b. The light with wavelengths of 1550 nm and 1530 nm are output from port 24a and input to the multiplexer / demultiplexer 530 from port 20c.

[0067] The multiplexer / demultiplexer 520 outputs light having a wavelength of 1590 nm from the port 22b and outputs light having a wavelength of 1570 nm from the port 24b. The multiplexer / demultiplexer 530 outputs light having a wavelength of 1550 nm from the port 22c and outputs light having a wavelength of 1530 nm from the port 24c.

[0068] FIG. 13 is a diagram illustrating transmittance. The horizontal axis represents the wavelength of light. The vertical axis represents transmittance. The ratio of the intensity of the light output from each port to the light input to port 20a of the demultiplexer 500 is measured. The dashed and dotted line in FIG. 13 represents the transmittance of port 24c. The dashed line represents the transmittance of port 22c. The dotted line represents the transmittance of port 24b. The solid line represents the transmittance of port 22b.

[0069] The transmittance of port 24c has a peak near 1525 nm. The transmittance of port 22c has a peak near 1545 nm. The transmittance of port 24b has a peak near 1565 nm. The transmittance of port 22b has a peak near 1585 nm. The insertion loss of the entire demultiplexer 500 is about 7 dB. The extinction ratio is 3 dB or more.

[0070] According to the fifth embodiment, the port 22a of the multiplexer / demultiplexer 510 is coupled to the port 20b of the multiplexer / demultiplexer 520. The port 22b of the multiplexer / demultiplexer 510 is coupled to the port 20c of the multiplexer / demultiplexer 530. The multiplexer / demultiplexer 520 splits the light input to the port 20b into two, and outputs them from the ports 22b and 24b. The multiplexer / demultiplexer 530 splits the light input to the port 20c into two, and outputs them from the ports 22c and 24c. The demultiplexer 500 splits the light into four depending on the wavelength. In the three multiplexers / demultiplexers, the multiple holes 30 are arranged in a triangular lattice pattern. The wall 34 becomes thick, and adjacent holes 30 are difficult to connect. It is possible to suppress the deterioration of the characteristics of each multiplexer / demultiplexer, and the desired characteristics can be obtained in the demultiplexer 500.

[0071] Three or more multiplexers may be connected to form a demultiplexer. For example, four multiplexers are connected to the output ports of a one-input, four-output multiplexer. Each of the four multiplexers splits the light into two. The demultiplexer splits the light into eight depending on the wavelength.

[0072] The above design functions can be realized by a computer. In that case, a program is provided that describes the processing contents of the functions that a processing device should have. The above processing functions are realized on the computer by executing the program on the computer. The program describing the processing contents can be recorded on a computer-readable storage medium (excluding carrier waves).

[0073] When a program is distributed, it is sold in the form of a portable storage medium on which the program is recorded, such as a DVD (Digital Versatile Disc), a CD-ROM (Compact Disc Read Only Memory), etc. The program can also be stored in a storage device of a server computer and transferred from the server computer to other computers via a network.

[0074] A computer that executes a program stores, for example, a program recorded on a portable storage medium or a program transferred from a server computer in its own storage device. The computer then reads the program from its own storage device and executes processing in accordance with the program. The computer can also read the program directly from a portable storage medium and execute processing in accordance with that program. The computer can also execute processing in accordance with the received program each time a program is transferred from the server computer.

[0075] In addition to the description of the embodiments, the following notes are further disclosed. (Appendix 1) A method for manufacturing a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the method comprising the steps of: Designing the positions of the holes so that three adjacent holes are arranged in a triangular lattice pattern; and forming the plurality of holes on one surface of the substrate. (Appendix 2) The method for manufacturing a multiplexer / demultiplexer described in Appendix 1, wherein the designing step includes a step of dividing the surface of the substrate into a plurality of regions arranged in a triangular lattice pattern, and a step of arranging the holes in some of the plurality of regions and not arranging the holes in another portion of the plurality of regions. (Appendix 3) The planar shape of the region is a regular hexagon, 3. The method for manufacturing a multiplexer / demultiplexer according to claim 2, wherein the step of dividing the surface of the substrate into the plurality of regions includes a step of arranging the plurality of regions in a close-packed structure. (Appendix 4) 4. The method for manufacturing a multiplexer / demultiplexer according to claim 1, wherein the designing step is a step of designing positions of the plurality of holes based on characteristics of the multiplexer / demultiplexer. (Appendix 5) 5. The method for manufacturing a multiplexer / demultiplexer according to claim 1, wherein the step of forming the plurality of holes includes a step of forming the holes by dry etching a silicon layer of the substrate. (Appendix 6) A substrate; a first port and a second port provided on the substrate; Light is input to the first port and output from the second port; A plurality of holes are provided on one surface of the substrate, A multiplexer / demultiplexer in which three adjacent holes are arranged in a triangular lattice pattern. (Appendix 7) the substrate having a silicon layer; 7. The multiplexer / demultiplexer according to claim 6, wherein the plurality of holes are provided on one surface of the silicon layer. (Appendix 8) 8. The multiplexer / demultiplexer according to claim 6 or 7, wherein three adjacent holes are arranged in an equilateral triangle shape. (Appendix 9) 9. The multiplexer / demultiplexer according to claim 6, having one of the first ports and a plurality of the second ports. (Appendix 10) A first multiplexer / demultiplexer; A second multiplexer / demultiplexer; a third multiplexer / demultiplexer; Each of the first multiplexer / demultiplexer, the second multiplexer / demultiplexer, and the third multiplexer / demultiplexer comprises: A substrate; a first port and a second port provided on the substrate; A plurality of holes are provided on one surface of the substrate, Three adjacent holes are arranged in a triangular lattice pattern, the first multiplexer / demultiplexer has two of the second ports, one of the two second ports of the first multiplexer / demultiplexer is coupled to the first port of the second multiplexer / demultiplexer; a demultiplexer in which the other of the two second ports of the first multiplexer / demultiplexer is coupled to the first port of the third multiplexer / demultiplexer; (Appendix 11) the substrate of each of the first multiplexer / demultiplexer, the second multiplexer / demultiplexer, and the third multiplexer / demultiplexer has a silicon layer; 11. The demultiplexer of claim 10, wherein the plurality of holes are provided on one side of the silicon layer. (Appendix 12) 12. The demultiplexer according to claim 10, wherein in the first multiplexer / demultiplexer, the second multiplexer / demultiplexer, and the third multiplexer / demultiplexer, three adjacent holes are arranged in an equilateral triangle shape. (Appendix 13) A design device for a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the first port being provided on the substrate, the design device comprising: the multiplexer / demultiplexer has a plurality of holes provided on a surface of the substrate, The design device is a design device for a multiplexer / demultiplexer that designs the positions of the multiple holes so that three adjacent holes are arranged in a triangular lattice pattern within the surface of the substrate. (Appendix 14) The First Design Department, A second design department, the first design unit performs a design to divide the surface of the substrate into a plurality of regions arranged in a triangular lattice pattern; 14. The multiplexer / demultiplexer design device according to claim 13, wherein the second design unit performs a design in which the holes are arranged in some of the plurality of regions and the holes are not arranged in another portion of the plurality of regions. (Appendix 15) The planar shape of the region is a regular hexagon, 15. The apparatus for designing a multiplexer / demultiplexer according to claim 14, wherein the multiple regions are arranged in a close-packed structure on the surface of the substrate. (Appendix 16) 16. The apparatus for designing a multiplexer / demultiplexer according to claim 13, wherein positions of the plurality of holes are designed based on characteristics of the multiplexer / demultiplexer. (Appendix 17) A design program for a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the design program comprising: the multiplexer / demultiplexer has a plurality of holes provided on a surface of the substrate, The design program includes: A design program for a multiplexer / demultiplexer that functions as a design unit that designs the positions of the multiple holes so that three adjacent holes are arranged in a triangular lattice pattern within the surface of the substrate. (Appendix 18) The design program causes the computer to The First Design Department, It will function as a second design department. the first design unit performs a design to divide the surface of the substrate into a plurality of regions arranged in a triangular lattice pattern; 18. The design program for a multiplexer / demultiplexer according to claim 17, wherein the second design unit performs a design in which the holes are placed in a part of the plurality of regions and the holes are not placed in another part of the plurality of regions. (Appendix 19) The planar shape of the region is a regular hexagon, 19. A design program for a multiplexer / demultiplexer according to claim 18, in which the multiple regions are arranged in a close-packed structure on the surface of the substrate. (Appendix 20) 20. An apparatus for designing a multiplexer / demultiplexer according to claim 17, which designs positions of the plurality of holes based on characteristics of the multiplexer / demultiplexer.

[0076] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure described in the claims. [Explanation of symbols]

[0077] 1 Input port 2 Exit port 10, 12 Board 14. Box layer 15 Waveguide core 16 Silicon Layer 17 Terrace 20, 20a, 20b, 20c, 22, 22a, 22b, 22c, 24, 24a, 24b, 24c ports 30 holes 32, 32a, 32b area 34 Wall 40 Resist 42 Opening 50 Control section 51 1st Design Department 52 2nd Design Department 54 CPU 56 RAM 58 ROM 60 Storage device 62 Interface 100, 200, 300, 400, 510, 520, 530 multiplexer / demultiplexer 110 Design equipment 500 Demultiplexer

Claims

1. A method for manufacturing a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the method comprising the steps of: Designing the positions of the plurality of holes so that three adjacent holes are arranged in a triangular lattice pattern; and forming the plurality of holes on one surface of the substrate.

2. 2. The method for manufacturing a multiplexer / demultiplexer as described in claim 1, wherein the designing process includes the steps of: dividing the surface of the substrate into a plurality of regions arranged in a triangular lattice pattern; and arranging the holes in some of the plurality of regions and not arranging the holes in another portion of the plurality of regions.

3. The planar shape of the region is a regular hexagon, The method for manufacturing a multiplexer / demultiplexer according to claim 2 , wherein the step of dividing the surface of the substrate into the plurality of regions includes the step of arranging the plurality of regions in a close-packed structure.

4. 3. The method for manufacturing a multiplexer / demultiplexer according to claim 1, wherein the designing step is a step of designing positions of the plurality of holes based on characteristics of the multiplexer / demultiplexer.

5. 3. The method for manufacturing a multiplexer / demultiplexer according to claim 1, wherein the step of forming the plurality of holes includes the step of forming the holes by dry etching a silicon layer of the substrate.

6. A substrate; a first port and a second port provided on the substrate; Light is input to the first port and output from the second port; A plurality of holes are provided on one surface of the substrate, A multiplexer / demultiplexer in which three adjacent holes are arranged in a triangular lattice pattern.

7. the substrate having a silicon layer; 7. The multiplexer / demultiplexer according to claim 6, wherein the plurality of holes are provided on one surface of the silicon layer.

8. 8. The multiplexer / demultiplexer according to claim 6, wherein three adjacent holes are arranged in an equilateral triangle shape.

9. 8. The multiplexer / demultiplexer according to claim 6, comprising one first port and a plurality of second ports.

10. A first multiplexer / demultiplexer; A second multiplexer / demultiplexer; a third multiplexer / demultiplexer; Each of the first multiplexer / demultiplexer, the second multiplexer / demultiplexer, and the third multiplexer / demultiplexer comprises: A substrate; a first port and a second port provided on the substrate; A plurality of holes are provided on one surface of the substrate, Three adjacent holes are arranged in a triangular lattice pattern, the first multiplexer / demultiplexer has two of the second ports; one of the two second ports of the first multiplexer / demultiplexer is coupled to the first port of the second multiplexer / demultiplexer; a demultiplexer in which the other of the two second ports of the first multiplexer / demultiplexer is coupled to the first port of the third multiplexer / demultiplexer;

11. A design device for a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the first port being provided on the substrate, the design device comprising: the multiplexer / demultiplexer has a plurality of holes provided on a surface of the substrate, The design device is a design device for a multiplexer / demultiplexer that designs positions of the plurality of holes so that three adjacent holes are arranged in a triangular lattice pattern within the surface of the substrate.

12. A design program for a multiplexer / demultiplexer having a substrate, a first port for inputting light, and a second port for outputting light, the design program comprising: the multiplexer / demultiplexer has a plurality of holes provided on a surface of the substrate, The design program includes: a design program for a multiplexer / demultiplexer that functions as a design unit that designs the positions of the holes so that three adjacent holes are arranged in a triangular lattice pattern within the surface of the substrate;

Images