Semiconductor device

Abstract

To provide a technique of being able to protect transistors from thermal damage when overcurrent flows in the transistor.SOLUTION: A semiconductor device includes a semiconductor substrate including an element region where transistors are formed, an interlayer insulating film provided on the semiconductor substrate, and a semiconductor layer provided on the interlayer insulating film. The semiconductor layer includes a first semiconductor layer of a first conductivity type connected to a gate of the transistor, a second semiconductor layer of a second conductivity type connected to the first semiconductor layer, and a third semiconductor layer of the first conductivity type connected to the second semiconductor layer and connected to a low potential terminal of the transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a main transistor and a protection transistor. The protection transistor is connected between the gate and source of the main transistor, and the gate of the protection transistor is connected to the gate of the main transistor.

[0003] In this semiconductor device, the threshold voltage of the protection transistor is higher than the threshold voltage of the main transistor. Therefore, during normal operation, the protection transistor does not turn on and the operation of the main transistor is not hindered. On the other hand, when an overcurrent flows through the main transistor and the temperature of the main transistor rises, the temperature of the protection transistor also rises, and the threshold voltage of the protection transistor drops. This turns on the protection transistor, causing a short circuit between the gate and source of the main transistor, forcing the main transistor to turn off. As a result, the main transistor can be protected from thermal destruction. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-212738 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device of Patent Document 1, the main transistor and the protection transistor are formed adjacent to each other inside the same semiconductor substrate. Therefore, when the main transistor operates, there is a risk that the protection transistor will operate parasitically, hindering the operation of the main transistor. This specification provides a technology that can protect a transistor from thermal destruction when an overcurrent flows through the transistor, using a configuration different from that of Patent Document 1. [Means for solving the problem]

[0006] A semiconductor device (10) disclosed in this specification includes a semiconductor substrate (12) having an element region (60) in which a transistor (20) is formed, an interlayer insulating film (16) provided on the semiconductor substrate, and a semiconductor layer (14, 114) provided on the interlayer insulating film. The semiconductor layer includes a first semiconductor layer (22, 122) of a first conductivity type connected to a gate of the transistor, a second semiconductor layer (24, 124) of a second conductivity type connected to the first semiconductor layer, and a third semiconductor layer (26, 126) of a first conductivity type connected to the second semiconductor layer and connected to a low potential terminal of the transistor.

[0007] In the above semiconductor device, the semiconductor layers are connected between the gate and the low potential terminal in the order of the first semiconductor layer of the first conductivity type, the second semiconductor layer of the second conductivity type, and the third semiconductor layer of the first conductivity type. Therefore, during normal operation of the semiconductor device, no current flows through the semiconductor layer, and the operation of the transistor is not hindered. On the other hand, when an overcurrent flows through the transistor and the temperature of the semiconductor substrate rises, the temperature of the semiconductor layer also rises due to heat being propagated to the semiconductor layer through the interlayer insulating film. Then, electron-hole pairs are generated inside the second semiconductor layer, and the resistance of the second semiconductor layer decreases. As a result, a current flows from the gate of the transistor through the semiconductor layer to the low potential terminal of the transistor, and the gate and the low potential terminal of the transistor are short-circuited. As a result, the transistor is forcibly turned off. In this semiconductor device, the transistor and the semiconductor layer are physically separated by the interlayer insulating film. Therefore, during normal operation of the transistor, it is possible to suppress parasitic conduction of the semiconductor layer. Therefore, according to this semiconductor device, it is possible to suitably protect the transistor from thermal destruction while suppressing the inhibition of the operation of the transistor. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a top view of the semiconductor device of the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view of a main portion taken along line II-II in FIG. [Diagram 3] FIG. 2 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Figure 4] FIG. 3 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment, the cross-sectional view corresponding to FIG. 2 . [Diagram 5] FIG. 11 is an equivalent circuit diagram of a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment, the cross-sectional view corresponding to FIG. 2 . [Figure 7] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a fourth embodiment, the cross-sectional view corresponding to FIG. [Figure 8] FIG. 13 is a top view of a semiconductor layer of a semiconductor device according to a modified example. [Figure 9] FIG. 13 is a top view of a semiconductor layer of a semiconductor device according to another modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In one example semiconductor device disclosed in this specification, the semiconductor substrate may further include a peripheral region disposed around the element region when viewed from above the semiconductor substrate, and the semiconductor layer may be disposed in the peripheral region.

[0010] In such a configuration, since the semiconductor layer is disposed in the peripheral region where no main current flows, a large area for the element region can be secured.

[0011] In the semiconductor device disclosed in this specification as an example, the semiconductor layer may be disposed in a range sandwiched between two of the element regions when the semiconductor substrate is viewed from above.

[0012] When an overcurrent flows through a transistor, the element region generates heat. In this configuration, the semiconductor layer is disposed in an area sandwiched between the heat-generating element regions, so the temperature of the semiconductor layer easily rises, and the gate of the transistor and the low potential terminal can be quickly short-circuited.

[0013] In the semiconductor device according to the example disclosed in this specification, a material constituting the semiconductor layer may have a smaller band gap than a material constituting the semiconductor substrate.

[0014] In such a configuration, the semiconductor layer becomes conductive before the high potential terminal and the low potential terminal of the transistor are short-circuited, so that the gate and the low potential terminal of the transistor can be short-circuited.

[0015] In one example of the semiconductor device disclosed in the present specification, the peak concentration of the first conductive type impurity in the first semiconductor layer and the third semiconductor layer is 1×10 18 cm -3 or more, and the peak concentration of the second conductivity type impurity in the second semiconductor layer is 5×10 17 cm -3 It may be the following.

[0016] In this configuration, the contact resistance between the first and third semiconductor layers and each terminal can be reduced, and the second semiconductor layer can quickly reduce its resistance when its temperature increases.

[0017] In one example semiconductor device disclosed in this specification, the first conductivity type may be n-type, the second conductivity type may be p-type, and the first semiconductor layer may have an n-type impurity concentration in a region adjacent to the second semiconductor layer that is lower than the n-type impurity concentration in a region adjacent to the gate.

[0018] In this configuration, since there is a region with a relatively low concentration of n-type impurities in the n-type first semiconductor layer located on the gate side, a higher voltage can be maintained between the gate and the low potential terminal when a positive voltage is applied to the gate.

[0019] In one example semiconductor device disclosed in the present specification, the first conductivity type may be p-type, the second conductivity type may be n-type, and the third semiconductor layer may have a p-type impurity concentration in a range in contact with the second semiconductor layer lower than the p-type impurity concentration in a range in contact with the low potential terminal.

[0020] In this configuration, since there is a region with a relatively low concentration of p-type impurities in the p-type third semiconductor layer located on the low potential terminal side, a higher voltage can be maintained between the gate and the low potential terminal when a positive voltage is applied to the gate.

[0021] In the semiconductor device disclosed in this specification as an example, the semiconductor substrate may be made of a wide-gap semiconductor, and the semiconductor layer may be made of polysilicon.

[0022] Example 1 Hereinafter, a semiconductor device 10 of the first embodiment will be described with reference to the drawings. The semiconductor device 10 shown in FIG. 1 includes a semiconductor substrate 12, electrodes, an insulating layer, and the like. In the following, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction. As shown in FIG. 1, the semiconductor substrate 12 has two element regions 60 and a peripheral region 62. A transistor 20 (see FIG. 3) is formed in each element region 60, and the two element regions 60 are arranged with an interval in the x-direction. The transistor 20 of this embodiment is an n-type MOSFET (Metal-Oxide-Semiconductor Field-effect Transistor). The peripheral region 62 is arranged around each element region 60. The peripheral region 62 is a region between the element region 60 and the outer peripheral edge of the semiconductor substrate 12, and a region between the two element regions 60. 1, in order to make the drawing easier to see, some of the electrodes, insulating layers, etc. on the upper surface 12a of the semiconductor substrate 12 are omitted. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 is not limited to SiC, and may be made of, for example, GaN, Ga 2 O 3 The semiconductor substrate 12 may be made of another wide gap semiconductor such as diamond, or may be made of a semiconductor such as Si. In the peripheral region 62, a gate pad 50 is disposed on the upper surface 12a of the semiconductor substrate 12.

[0023] 2 is a cross-sectional view of a main part taken along line II-II in FIG. 1. In detail, FIG. 2 shows a cross section of the upper surface 12a side of the semiconductor substrate 12. As shown in FIG. 2, an interlayer insulating film 16 is provided on the upper surface 12a of the semiconductor substrate 12. Although not shown, an n-type MOSFET structure is formed inside the semiconductor substrate 12 in the element region 60. The n-type MOSFET may be of a trench type or a planar type. The interlayer insulating film 16 covers most of the upper surface 12a of the semiconductor substrate 12 across the element region 60 and the peripheral region 62.

[0024] The semiconductor layer 14 is provided on the interlayer insulating film 16. The semiconductor layer 14 is physically separated from the semiconductor substrate by the interlayer insulating film 16. The interlayer insulating film 16 is also in contact with the side and top surfaces of the semiconductor layer 14. In other words, the periphery of the semiconductor layer 14 is covered by the interlayer insulating film 16. As shown in FIG. 1, the semiconductor layer 14 is disposed in a range sandwiched between two element regions 60 within the peripheral region 62 when the semiconductor substrate 12 is viewed from above.

[0025] The band gap of the material constituting the semiconductor layer 14 is smaller than the band gap of the material constituting the semiconductor substrate 12. Specifically, the semiconductor layer 14 is made of polysilicon. As shown in FIG. 2, the semiconductor layer 14 includes a first semiconductor layer 22, a second semiconductor layer 24, and a third semiconductor layer 26.

[0026] The first semiconductor layer 22 is of n-type. The first semiconductor layer 22 is connected to a gate electrode 30 via a contact hole 16a provided in the interlayer insulating film 16. The gate electrode 30 functions as the gate electrode of a transistor (i.e., an n-type MOSFET) provided in the element region 60. The gate electrode 30 faces a body region (more specifically, a body region in a range between a source region and a drain region) provided inside the semiconductor substrate 12 via a gate insulating film at a position not shown. The peak concentration of n-type impurities in the first semiconductor layer 22 is 1×10 18 cm -3 That's all.

[0027] The second semiconductor layer 24 is p-type. The second semiconductor layer 24 is connected to the first semiconductor layer 22. The peak concentration of the p-type impurity in the second semiconductor layer 24 is 5×10 17 cm -3 The following is the result.

[0028] The third semiconductor layer 26 is of n-type. The third semiconductor layer 26 is connected to the second semiconductor layer 24. The second semiconductor layer 24 is provided between the third semiconductor layer 26 and the first semiconductor layer 22, and the third semiconductor layer 26 is separated from the first semiconductor layer 22 by the second semiconductor layer 24. The third semiconductor layer 26 is connected to a source electrode 32 via a contact hole 16b provided in the interlayer insulating film 16. The source electrode 32 functions as a source electrode of a transistor (i.e., an n-type MOSFET) provided in the element region 60. The source electrode 32 is in ohmic contact with a source region provided inside the semiconductor substrate 12 at a position not shown. The peak concentration of n-type impurities in the third semiconductor layer 26 is 1×10 18 cm -3 That's all.

[0029] As shown in FIGS. 1 and 2, the first semiconductor layer 22, the second semiconductor layer 24, and the third semiconductor layer 26 each extend along the y direction.

[0030] FIG. 3 shows an equivalent circuit diagram of the semiconductor device 10. As described above, the semiconductor device 10 of the first embodiment includes a semiconductor layer 14 in which the first semiconductor layer 22, the second semiconductor layer 24, and the third semiconductor layer 26 are connected in this order between the gate electrode 30 and the source electrode 32. That is, as shown in FIG. 3, in the semiconductor device 10, a diode 42 in the reverse direction from the gate G to the source S and a diode 44 in the forward direction can be considered to be connected in series in this order between the gate G and the source S of the transistor 20. That is, in other words, the semiconductor layer 14 can be said to have the cathode of the diode 42 connected to the gate G of the transistor 20, the anode of the diode 42 connected to the anode of the diode 44, and the cathode of the diode 44 connected to the source S of the transistor 20.

[0031] Next, the operation of the semiconductor device 10 will be described. During normal operation of the semiconductor device 10, a positive voltage is applied to the drain D in FIG. 3, and the source S is grounded. When a voltage higher than the threshold is applied to the gate G, the transistor 20 turns on. Since the semiconductor layer 14 is connected between the gate G and the source S in the order of the n-type first semiconductor layer 22, the p-type second semiconductor layer 24, and the n-type third semiconductor layer 26, no current flows through the semiconductor layer 14 at the normal operating temperature of the semiconductor device 10. Therefore, the gate G and the source S of the transistor 20 are not short-circuited, and the transistor 20 can operate normally.

[0032] On the other hand, when the semiconductor device 10 operates abnormally, for example, when a malfunction such as a short circuit occurs in a load connected to the semiconductor device 10, an overcurrent flows through the transistor 20. When an overcurrent flows through the transistor 20, the temperature of the semiconductor substrate 12 rises. As a result, heat is propagated to the semiconductor layer 14 through the interlayer insulating film 16, and the temperature of the semiconductor layer 14 also rises. Then, electron-hole pairs are generated in the second semiconductor layer 24, and the resistance of the second semiconductor layer 24 decreases. As a result, a current flows from the gate G to the source S of the transistor 20 through the semiconductor layer 14, and a short circuit occurs between the gate G and the source S, and the transistor 20 is forcibly turned off. This stops the temperature rise of the semiconductor substrate 12, and the transistor 20 is protected from thermal destruction.

[0033] In the semiconductor device 10 of this embodiment, the transistor 20 and the semiconductor layer 14 are physically separated by the interlayer insulating film 16. This makes it possible to suppress parasitic conduction of the semiconductor layer 14 during normal operation of the transistor 20. Therefore, according to the semiconductor device 10 of this embodiment, it is possible to appropriately protect the transistor 20 from thermal destruction while suppressing inhibition of the operation of the transistor 20.

[0034] Moreover, in this embodiment, the semiconductor layer 14 is disposed within the peripheral region 62. Since the semiconductor layer 14 is disposed in a region where no main current flows (i.e., outside the element region 60), a large area of ​​the element region 60 can be ensured. Furthermore, the semiconductor layer 14 is disposed within a range sandwiched between the element regions 60. Since the semiconductor layer 14 is disposed within a range sandwiched between the element regions 60 which generate heat when an overcurrent flows through the transistor 20, the temperature of the semiconductor layer 14 easily rises, and the gate G and source S of the transistor 20 can be quickly short-circuited.

[0035] In this embodiment, the material (polysilicon) constituting the semiconductor layer 14 has a smaller band gap than the material (SiC) constituting the semiconductor substrate 12. Therefore, the gate G and the source S of the transistor 20 can be short-circuited before the drain D and the source S of the transistor 20 are short-circuited.

[0036] In this embodiment, the peak concentration of the n-type impurity in the first semiconductor layer 22 and the third semiconductor layer 26 is 1×10 18 cm -3 or more, and the peak concentration of the p-type impurity in the second semiconductor layer 24 is 5×10 17 cm -3 This makes it possible to reduce the contact resistance between the first semiconductor layer 22 and the gate G, and between the third semiconductor layer 26 and the source S. Furthermore, when the temperature of the second semiconductor layer 24 rises, the resistance is quickly reduced.

[0037] Example 2 In the second embodiment, the configuration of the semiconductor layer 114 is different from that of the semiconductor layer 14 in the first embodiment. The semiconductor layer 114 in the second embodiment includes a first semiconductor layer 122, a second semiconductor layer 124, and a third semiconductor layer 126.

[0038] The first semiconductor layer 122 is of p-type. The first semiconductor layer 122 is connected to the gate electrode 30 via a contact hole 16a provided in the interlayer insulating film 16. The gate electrode 30 faces a body region (more specifically, a body region in a range between the source region and the drain region) provided inside the semiconductor substrate 12 via the gate insulating film at a position not shown. The peak concentration of p-type impurities in the first semiconductor layer 122 is 1×10 18 cm -3 That's all.

[0039] The second semiconductor layer 124 is an n-type semiconductor. The second semiconductor layer 124 is connected to the first semiconductor layer 122. The peak concentration of the n-type impurity in the second semiconductor layer 124 is 5×10 17 cm -3 The following is the result.

[0040] The third semiconductor layer 126 is of p-type. The third semiconductor layer 126 is connected to the second semiconductor layer 124. The third semiconductor layer 126 is also connected to the source electrode 32 via a contact hole 16b provided in the interlayer insulating film 16. The source electrode 32 is in ohmic contact with a source region provided inside the semiconductor substrate 12 at a position not shown. The peak concentration of p-type impurities in the third semiconductor layer 126 is 1×10 18 cm -3 That's all.

[0041] Fig. 5 shows an equivalent circuit diagram of the semiconductor device 100 of the second embodiment. In the semiconductor device 100 of the second embodiment, as shown in Fig. 5, it can be considered that a diode 142 in a forward direction from the gate G to the source S and a diode 144 in a reverse direction are connected in series between the gate G and the source S of the transistor 20. That is, it can be said that the semiconductor layer 114 has an anode of the diode 142 connected to the gate G of the transistor 20, a cathode of the diode 142 connected to the cathode of the diode 144, and an anode of the diode 144 connected to the source S of the transistor 20.

[0042] In the second embodiment, similarly to the first embodiment, the resistance of the second semiconductor layer 124 decreases during abnormal operation of the semiconductor device 100. As a result, the gate G and the source S are short-circuited, and the transistor 20 can be forcibly turned off. Also in the second embodiment, the semiconductor layer 114 is physically separated from the semiconductor substrate 12 by the interlayer insulating film 16, so that parasitic conduction of the semiconductor layer 114 can be suppressed during normal operation of the transistor 20.

[0043] Example 3 6, the third embodiment is different from the first embodiment in that the first semiconductor layer 22 has a high concentration region 22a and a low concentration region 22b. Other configurations of the third embodiment are similar to those of the first embodiment.

[0044] The n-type impurity concentration of the low concentration region 22b is lower than the n-type impurity concentration of the high concentration region 22a. The high concentration region 22a is disposed in a range in contact with the gate electrode 30. The low concentration region 22b is disposed in a range in contact with the second semiconductor layer 24. That is, in the third embodiment, the high concentration region 22a, the low concentration region 22b, the second semiconductor layer 24, and the third semiconductor layer 26 are connected in this order between the gate electrode 30 and the source electrode 32.

[0045] In the semiconductor device of Example 3, since the low concentration region 22b having a relatively low n-type impurity concentration is present in the n-type first semiconductor layer 22 located on the gate electrode 30 side, a higher voltage can be maintained between the gate electrode 30 and the source electrode 32 when a positive voltage is applied to the gate electrode 30.

[0046] Example 4 7, the fourth embodiment is different from the second embodiment in that the third semiconductor layer 126 has a high concentration region 126a and a low concentration region 126b. Other configurations of the fourth embodiment are similar to those of the second embodiment.

[0047] The p-type impurity concentration of the low concentration region 126b is lower than the p-type impurity concentration of the high concentration region 126a. The high concentration region 126a is disposed in a range in contact with the source electrode 32. The low concentration region 126b is disposed in a range in contact with the second semiconductor layer 124. That is, in the fourth embodiment, the first semiconductor layer 122, the second semiconductor layer 124, the low concentration region 126b, and the high concentration region 126a are connected in this order between the gate electrode 30 and the source electrode 32.

[0048] In the semiconductor device of Example 4, since the low concentration region 126b having a relatively low p-type impurity concentration is present in the p-type third semiconductor layer 126 located on the source electrode 32 side, a higher voltage can be maintained between the gate electrode 30 and the source electrode 32 when a positive voltage is applied to the gate electrode 30.

[0049] In the above-mentioned Example 1, the first semiconductor layer 22, the second semiconductor layer 24, and the third semiconductor layer 26 are each configured to extend linearly in the y direction. However, for example, as shown in FIG. 8, when the semiconductor layer 14 is viewed from above, the second semiconductor layer 24 may be configured to have a zigzag shape, and the first semiconductor layer 22 and the third semiconductor layer 26 may be disposed on both sides of the second semiconductor layer 24. Also, as shown in FIG. 9, when the semiconductor layer 14 is viewed from above, a plurality of second semiconductor layers 24 may be disposed to have a hollow rectangular shape, the first semiconductor layer 22 may be disposed on the outer periphery side of the second semiconductor layer 24, and the third semiconductor layer 26 may be disposed on the inner periphery side of the second semiconductor layer 24. In these configurations, the contact area between the first semiconductor layer 22 and the second semiconductor layer 24 and the contact area between the second semiconductor layer 24 and the third semiconductor layer 26 are increased, and the resistance of the semiconductor layer 14 can be reduced, so that the semiconductor layer 14 can be made smaller. Similar configurations may be applied to Examples 2 to 4.

[0050] In addition, in each of the above-described embodiments, when the semiconductor substrate 12 is viewed from above, the semiconductor layers 14, 114 are disposed in the peripheral region 62 sandwiched between the two element regions 60. However, the semiconductor layers 14, 114 may be disposed, for example, in the peripheral region 62 between the element region 60 and the outer periphery of the semiconductor substrate 12, or may be disposed in the element region 60.

[0051] In the above-described embodiments, there is no particular limitation on the impurity concentration of each semiconductor layer such as the first semiconductor layers 22 and 122. The impurity concentration can be appropriately selected according to the rated voltage of the transistor 20 and the like.

[0052] In addition, in each of the above-described embodiments, the band gap of the material constituting the semiconductor layers 14, 114 is smaller than the band gap of the material constituting the semiconductor substrate 12. However, for example, the semiconductor layers 14, 114 may be composed of the same material as the semiconductor substrate 12.

[0053] In addition, in each of the above-described embodiments, a MOSFET has been described as an example of the transistor 20. However, the transistor 20 may be, for example, an IGBT. In this modification, the low potential terminal and the high potential terminal are the emitter and the collector, respectively.

[0054] The configurations disclosed in this specification are listed below. (Configuration 1) A semiconductor device comprising: a semiconductor substrate having an element region in which a transistor is formed; an interlayer insulating film provided on the semiconductor substrate; a semiconductor layer provided on the interlayer insulating film; Equipped with The semiconductor layer is a first semiconductor layer of a first conductivity type connected to a gate of the transistor; a second semiconductor layer of a second conductivity type connected to the first semiconductor layer; a third semiconductor layer of the first conductivity type connected to the second semiconductor layer and to a low potential terminal of the transistor; Semiconductor device. (Configuration 2) the semiconductor substrate further includes a peripheral region disposed around the element region when viewed from above the semiconductor substrate; 2. The semiconductor device of claim 1, wherein the semiconductor layer is disposed in the peripheral region. (Configuration 3) 3. The semiconductor device according to claim 2, wherein the semiconductor layer is disposed in an area sandwiched between two of the element regions when the semiconductor substrate is viewed from above. (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein a material constituting the semiconductor layer has a smaller band gap than a material constituting the semiconductor substrate. (Configuration 5) The peak concentration of the first conductive type impurity in the first semiconductor layer and the third semiconductor layer is 1×10 18 cm -3 That's all. The peak concentration of the second conductive type impurity in the second semiconductor layer is 5×10 17 cm -3 The semiconductor device according to any one of configurations 1 to 4, which is as follows: (Configuration 6) The first conductivity type is n-type and the second conductivity type is p-type; 6. The semiconductor device according to any one of configurations 1 to 5, wherein the first semiconductor layer has an n-type impurity concentration in a region in contact with the second semiconductor layer lower than an n-type impurity concentration in a region in contact with the gate. (Configuration 7) The first conductivity type is p-type and the second conductivity type is n-type; 6. The semiconductor device according to any one of configurations 1 to 5, wherein the third semiconductor layer has a p-type impurity concentration in a region in contact with the second semiconductor layer lower than a p-type impurity concentration in a region in contact with the low potential terminal. (Configuration 8) the semiconductor substrate is made of a wide-gap semiconductor, 8. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor layer is made of polysilicon.

[0055] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0056] 10: semiconductor device, 12: semiconductor substrate, 12a: upper surface, 14: semiconductor layer, 16: interlayer insulating film, 20: transistor, 22: first semiconductor layer, 24: second semiconductor layer, 26: third semiconductor layer, 30: gate electrode, 32: source electrode, 60: element region, 62: peripheral region

Claims

1. A semiconductor device (10), A semiconductor substrate (12) having an element region (60) in which a transistor (20) is formed; an interlayer insulating film (16) provided on the semiconductor substrate; A semiconductor layer (14) provided on the interlayer insulating film; Equipped with The semiconductor layer is a first semiconductor layer (22) of a first conductivity type connected to the gate of the transistor; a second semiconductor layer (24) of a second conductivity type connected to the first semiconductor layer; a third semiconductor layer (26) of the first conductivity type connected to the second semiconductor layer and to a low potential terminal of the transistor; Semiconductor device.

2. The semiconductor substrate further includes a peripheral region (62) disposed around the element region when the semiconductor substrate is viewed from above, The semiconductor device according to claim 1 , wherein the semiconductor layer is disposed in the peripheral region.

3. The semiconductor device according to claim 2 , wherein the semiconductor layer is disposed in a range sandwiched between two of the element regions when the semiconductor substrate is viewed from above.

4. The semiconductor device according to claim 1 , wherein a material constituting said semiconductor layer has a smaller band gap than a material constituting said semiconductor substrate.

5. The peak concentration of the first conductive type impurity in the first semiconductor layer and the third semiconductor layer is 1×10 １８ cm －３ That's all. The peak concentration of the second conductive type impurity in the second semiconductor layer is 5×10 １７ cm －３ 2. The semiconductor device according to claim 1, wherein:

6. The first conductivity type is n-type and the second conductivity type is p-type; 2 . The semiconductor device according to claim 1 , wherein the first semiconductor layer has an n-type impurity concentration in a region in contact with the second semiconductor layer lower than an n-type impurity concentration in a region in contact with the gate.

7. The first conductivity type is p-type and the second conductivity type is n-type; 2 . The semiconductor device according to claim 1 , wherein a p-type impurity concentration in a region of said third semiconductor layer that contacts said second semiconductor layer is lower than a p-type impurity concentration in a region of said third semiconductor layer that contacts said low potential terminal.

8. the semiconductor substrate is made of a wide-gap semiconductor, 8. The semiconductor device according to claim 1, wherein the semiconductor layer is made of polysilicon.

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