Semiconductor device

Abstract

To provide a semiconductor device that is equipped with multiple heat generating components and that has high heat radiation properties.SOLUTION: An embodiment includes a first substrate, a second substrate, a third substrate, a first semiconductor element, and a second semiconductor element. The third substrate is provided between the first substrate and the second substrate. The first semiconductor element is provided on the first substrate. The second semiconductor element is provided on the second substrate. The third substrate includes a first connection member and a second connection member that have thermal conductivity. The first connection member and the second connection member penetrate through the third substrate. The first semiconductor element is thermally coupled to the first substrate and thermally coupled through the first connection member to the second substrate. The second semiconductor element is thermally coupled to the second substrate and thermally coupled through the second connection member to the first substrate.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] There are power modules (semiconductor devices) equipped with multiple heat-generating components such as semiconductor elements for power generation. In such power modules, the multiple heat-generating components are sometimes distributed and arranged on two substrates to improve heat dissipation.

[0003] In the power module, further improvement of the heat dissipation property increases the packaging density of the device or apparatus in which the power module is mounted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5434914 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a semiconductor device having a plurality of heat-generating components mounted thereon and high heat dissipation properties. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a first substrate including a first base material having a first surface and a second surface opposite to the first surface and having thermal conductivity, a second substrate including a second base material having a third surface facing the first surface and a fourth surface opposite to the third surface, a first semiconductor element provided on the first surface side, a second semiconductor element provided on the third surface side, and a third substrate including a third base material provided between the first substrate and the second substrate and having a fifth surface facing the first surface and a sixth surface opposite to the fifth surface. The third substrate includes a first connecting member having thermal conductivity and penetrating from the fifth surface to the sixth surface, and a second connecting member having thermal conductivity and penetrating from the fifth surface to the sixth surface and provided apart from the first connecting member. The first semiconductor element is thermally coupled to each of the first substrate and the first connecting member between the first substrate and the first connecting member. The second semiconductor element is between the second substrate and the second connection member and is thermally coupled to each of the second substrate and the second connection member. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a schematic side view illustrating the power module according to the embodiment. [Diagram 2] 1 is a schematic cross-sectional view illustrating a power module according to an embodiment; [Diagram 3] 3(a) to 3(c) are schematic perspective views illustrating a first connection member that is a part of the power module according to the embodiment. [Figure 4] FIG. 2 is a schematic equivalent circuit diagram of a power module according to an embodiment. [Diagram 5] Fig. 5(a) is a schematic side view illustrating a power module according to an embodiment, and Fig. 5(b) is a schematic side view illustrating a power module of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals and detailed explanations are omitted as appropriate.

[0009] FIG. 1 is a schematic side view illustrating the power module according to the first embodiment. FIG. 2 is a schematic cross-sectional view illustrating the power module according to the first embodiment. As shown in FIGS. 1 and 2, a power module 1 according to the embodiment includes a first substrate 10, a second substrate 20, a third substrate 30, a first semiconductor element 41, and a second semiconductor element .

[0010] The first semiconductor element 41 is provided on the first substrate 10. The second semiconductor element 42 is provided on the second substrate 20. The third substrate 30 is provided between the first substrate 10 and the second substrate 20. The power module 1 has a case 80 that houses the first substrate 10, the second substrate 20, the third substrate 30, the first semiconductor element 41, and the second semiconductor element 42. The case 80 is formed of an insulating material. The case 80 is formed of, for example, an epoxy resin. In FIG. 1, the case 80 is shown by a two-dot chain line so that the mutual relationship between the first substrate 10, the second substrate 20, the third substrate 30, the first semiconductor element 41, and the second semiconductor element 42 can be illustrated from the side.

[0011] The first substrate 10 includes a base material (first base material) 11 and a wiring layer (first wiring layer) 12. The base material 11 is a plate-like member having a first surface 11a and a second surface 11b. The second surface 11b is the surface opposite to the first surface 11a.

[0012] In the following, the configuration of the power module 1 may be described using a three-dimensional coordinate system. The three-dimensional coordinate system is an XYZ coordinate system. The first surface 11a of the substrate 11 is a flat surface, and the XY plane is parallel to the first surface 11a. In the example of FIG. 1, the first semiconductor element 41 and the second semiconductor element 42 are aligned in the X direction. The Z axis is perpendicular to the XY plane, and the direction from the first surface 11a to the second surface 11b is the positive direction, and the opposite direction is the negative direction.

[0013] 2, the lengths of some components in the Z-axis direction are exaggerated to more clearly show the relative positions of the first substrate 10, the second substrate 20, the third substrate 30, the first connecting member 33, the second connecting member 34, the first semiconductor element 41, and the second semiconductor element 42. In addition, to avoid cluttering the illustration, each component is shown as a single component even if it is made up of multiple components. Hereinafter, the length in the Z-axis direction may be referred to as thickness or height.

[0014] The base material 11 has insulating properties at least on the first surface 11a. The base material 11 is formed of a material having high thermal conductivity. The base material 11 includes, for example, Al2O3 or AlN. The base material 11 may include a metal such as Cu or Al.

[0015] The wiring layer 12 is provided on the first surface 11a. The wiring layer 12 may include a plurality of wirings. The plurality of wirings may be electrically connected to each other or may be electrically separated from each other. In the specific example of FIG. 2, the wiring layer 12 includes wirings 12a and 12b. The wiring 12a is electrically connected to the fourth connection member 52. The wiring 12b is electrically connected to the first semiconductor element 41. In this example, the wiring 12a is electrically separated from the wiring 12b.

[0016] The second substrate 20 includes a base material (second base material) 21 and a wiring layer (second wiring layer) 22. The base material 21 is a plate-like member having a third surface 21a and a fourth surface 21b. The fourth surface 21b is the surface opposite to the third surface 21a. The first substrate 10 and the second substrate 20 are disposed so that the first surface 11a to the fourth surface 21b are substantially parallel. The second substrate 20 is disposed in a position where the third surface 21a faces the first surface 11a.

[0017] The base material 21 has insulating properties at least on the third surface 21a. The base material 21 is formed of a material having high thermal conductivity. The base material 21 includes, for example, Al2O3 or AlN. The base material 21 may include a metal such as Cu or Al. The base materials 11 and 21 may be formed of the same material or different materials.

[0018] The wiring layer 22 may include a plurality of wirings. The plurality of wirings may be electrically connected to each other or may be electrically separated from each other. In the example of FIG. 2, the wiring layer 22 includes a wiring 22a. The wiring 22a is electrically connected to each of the third connection member 51 and the second semiconductor element 42. Although not shown in FIG. 2, the wiring layer 22 may include, for example, another wiring electrically separated from the wiring 22a.

[0019] The first semiconductor element 41 is electrically connected to the wiring layer 12. The second semiconductor element 42 is electrically connected to the wiring layer 22. The first semiconductor element 41 and the second semiconductor element 42 are, for example, power semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a GTO (Gate Turn-Off thyristor), or a diode. Power semiconductor elements include Si, SiC, GaN, or the like. The first semiconductor element 41 and the second semiconductor element 42 may be the same type of power semiconductor element or different types of power semiconductor elements.

[0020] The first semiconductor element 41 is provided between the first substrate 10 and the third substrate 30, and the second semiconductor element 42 is provided between the third substrate 30 and the second substrate 20. The first semiconductor element 41 and the second semiconductor element 42 are arranged apart in the X-axis direction.

[0021] The third substrate 30 includes a base material 31, a first connecting member 33, and a second connecting member 34. The base material 31 is a plate-like member having a fifth surface 31a and a sixth surface 31b. The sixth surface 31b is a surface located opposite to the fifth surface 31a. The fifth surface 31a and the sixth surface 31b are disposed so as to be substantially parallel to the first surface 11a. The fifth surface 31a faces the first surface 11a, and the sixth surface 31b faces the third surface 21a.

[0022] The base material 31 is made of an insulating material, for example, a glass epoxy board material such as FR-4 or a glass composite board material such as CEM-3.

[0023] The first connecting member 33 and the second connecting member 34 are provided so as to penetrate from the fifth surface 31a to the sixth surface 31b, respectively.

[0024] The first connection member 33 has a mounting surface 33S1 and a heat dissipation surface 33S2. The mounting surface 33S1 is exposed from the base material 31 on the fifth surface 31a side. The heat dissipation surface 33S2 is exposed from the base material 31 on the sixth surface 31b side.

[0025] The second connection member 34 has a mounting surface 34S1 and a heat dissipation surface 34S2. The mounting surface 34S1 is exposed from the base material 31 on the sixth surface 31b side. The heat dissipation surface 34S2 is exposed from the base material 31 on the fifth surface 31a side.

[0026] 2, a third connection member 51 is provided between the heat dissipation surface 33S2 and the wiring layer 22. The third connection member 51 thermally couples the first connection member 33 and the wiring layer 22. The third connection member 51 functions as a spacer that adjusts the length in the Z-axis direction between the third substrate 30 and the second substrate 20. The thickness of the third connection member 51 is equal to the thickness of the second semiconductor element 42, for example.

[0027] A fourth connection member 52 is provided between the heat dissipation surface 34S2 and the wiring layer 12. The fourth connection member 52 thermally couples the second connection member 34 and the wiring layer 12. The fourth connection member 52 functions as a spacer that adjusts the length in the Z-axis direction between the third substrate 30 and the first substrate 10. The thickness of the fourth connection member 52 is equal to the thickness of the first semiconductor element 41, for example.

[0028] The first semiconductor element 41 is provided between the first substrate 10 and the first connecting member 33. The first semiconductor element 41 is thermally coupled to the first substrate 10. The first semiconductor element 41 is also thermally coupled to the first connecting member 33 on the mounting surface 33S1. The first connecting member 33 is thermally coupled to the second substrate 20 via the third connecting member 51 on the heat dissipation surface 33S2.

[0029] The heat generated by the first semiconductor element 41 is dissipated by the first substrate 10. In addition, the heat generated by the first semiconductor element 41 is conducted to the second substrate 20 via the first connecting member 33 and the third connecting member 51, and is dissipated by the second substrate 20.

[0030] The second semiconductor element 42 is provided between the second connecting member 34 and the second substrate 20. The second semiconductor element 42 is thermally coupled to the second substrate 20. The second semiconductor element 42 is also thermally coupled to the second connecting member 34 on the mounting surface 34S1. The second connecting member 34 is thermally coupled to the first substrate 10 via the fourth connecting member 52 on the heat dissipation surface 34S2.

[0031] The heat generated by the second semiconductor element 42 is dissipated by the second substrate 20. In addition, the heat generated by the second semiconductor element 42 is conducted to the first substrate 10 via the second connecting member 34 and the fourth connecting member 52, and is dissipated by the first substrate 10.

[0032] The first connecting member 33, the second connecting member 34, the third connecting member 51, and the fourth connecting member 52 are made of a material having high thermal conductivity. The thermal conductivity of the first connecting member 33, the second connecting member 34, the third connecting member 51, and the fourth connecting member 52 is sufficiently higher than the thermal conductivity of the base material 31.

[0033] Of the heat generated by the first semiconductor element 41, most of the heat conducted via the first connection member 33 and the third connection member 51 is conducted to the second substrate 20 side. Of the heat generated by the second semiconductor element 42, most of the heat conducted via the second connection member 34 and the fourth connection member 52 is conducted to the first substrate 10 side. Since the first semiconductor element 41 and the second semiconductor element 42 are disposed apart in the X-axis direction, the heat generated by the first semiconductor element 41 and the heat generated by the second semiconductor element 42 are conducted and dissipated via different paths. Therefore, the power module 1 achieves high heat dissipation properties.

[0034] As shown in FIG. 2, the second surface 11b may be provided with a first heat sink 110. The first substrate 10 is thermally coupled to the first heat sink 110. Preferably, the fourth surface 21b is further provided with a second heat sink 120. The first heat sink 110 and the second heat sink 120 have a thermal resistance sufficiently lower than that of the first base material 11 and the second base material 21. Therefore, the heat generated by the first semiconductor element 41 is dissipated more efficiently by the first heat sink 110 and the second heat sink 120. The heat generated by the second semiconductor element 42 is dissipated more efficiently by the first heat sink 110 and the second heat sink 120.

[0035] The first heat sink 110 and the second heat sink 120 may be air-cooled or water-cooled. When providing air-cooled heat sinks, only one heat sink or both heat sinks may be provided depending on the convection caused by the arrangement of the power module 1.

[0036] The circuit components 61 and 62 are provided on the third substrate 30. In the example of FIG. 1 and FIG. 2, the circuit component 61 is provided on the fifth surface 31a side, and the circuit component 62 is provided on the sixth surface 31b side. The circuit components 61 and 62 are, for example, passive components such as capacitors and resistors, functional modules including integrated circuits and various sensors, and have smaller input / output currents and smaller amplitudes of input / output voltages than the first semiconductor element 41 and the second semiconductor element 42. The circuit components 61 and 62 are, for example, circuit elements that drive the first semiconductor element 41 and the second semiconductor element 42, or control circuits that drive the first semiconductor element 41 and the second semiconductor element 42.

[0037] The third substrate 30 has a conductive layer 36 on the inner layer of the base material 31. The conductive layer 36 is provided between the fifth surface 31a and the sixth surface 31b. In this specific example, the conductive layer 36 is electrically isolated from the first connecting member 33 and the second connecting member 34. The conductive layer 36 is also provided between the circuit components 61 and 62. For example, a ground potential is applied to the conductive layer 36. The conductive layer 36 functions as a shielding layer against electromagnetic radiation and the like caused by the switching operations of the first semiconductor element 41 and the second semiconductor element 42. The circuit components 61 and 62 are provided on the conductive layer 36 that functions as a shielding layer, so that malfunctions and the like caused by electromagnetic radiation and the like can be suppressed.

[0038] The third substrate 30 includes a wiring layer (third wiring layer) 32a. The wiring layer 32a is provided on the fifth surface 31a side. The wiring layer 32a may include a plurality of wirings 32a1, 32a2, and 32a3. The plurality of wirings 32a1, 32a2, and 32a3 may be electrically connected to each other or may be separated from each other.

[0039] In the wiring layer 32a, the thicknesses of the wirings 32a1, 32a2, and 32a3 can be different. The thicknesses of the wirings 32a1 and 32a3 are thick. The thickness of the wiring 32a2 is thinner than the thicknesses of the wirings 32a1 and 32a3. The thick wiring 32a1 is electrically connected to, for example, a main electrode of the first semiconductor element 41. The main electrode is, for example, an emitter electrode of an IGBT. The wiring 32a1 can be used as a lead wire for connecting the emitter electrode of the first semiconductor element 41 to an external circuit. As will be described later in relation to FIG. 4, when the power module 1 is configured as a half-bridge circuit 101, the wiring 32a1 can be used as a lead wire to serve as a terminal for extracting a neutral point potential (AC output voltage) VAC.

[0040] The thick wiring 32a3 is electrically connected to the wiring 12b via the fifth connection member 53. The fifth connection member 53 is disposed between the wiring 32a3 and the wiring 12b on the positive side in the Y direction of the first semiconductor element 41, and electrically connects the wiring 32a3 and the wiring 12b. The thickness of the fifth connection member 53 is the same as the thickness of the first semiconductor element 41 and the thickness of the fourth connection member 52, and also functions as a spacer. As in the specific example of FIG. 2, the wiring 32a3 may be drawn out as a lead wire for connecting to an external circuit. In this way, the wiring 32a3 is connected to the DC voltage source V of the half bridge circuit 101 described later in relation to FIG. 4. + It can also be used as a terminal for connecting

[0041] In this manner, by increasing the thickness of the wirings 32a1 and 32a3, a large current can be passed through the wirings 32a1 and 32a3.

[0042] The thin wiring 32a2 electrically connects, for example, the control electrode of the first semiconductor element 41 and the circuit component 61. The control electrode is, for example, a gate electrode of an IGBT. A current that is sufficiently smaller than the currents flowing through the wirings 32a1 and 32a3 can flow through the wiring 32a2.

[0043] The third substrate 30 includes a wiring layer (fourth wiring layer) 32b. The wiring layer 32b is provided on the sixth surface 31b side. The wiring layer 32b may include a plurality of wirings 32b1, 32b2. The plurality of wirings 32b1, 32b2 may be electrically connected to each other or may be separated from each other.

[0044] In the wiring layer 32b, the thicknesses of the wirings 32b1 and 32b2 can be made different. The thickness of the wiring 32b1 is thick. The thickness of the wiring 32b2 is thinner than the thickness of the wiring 32b1.

[0045] The thick wiring 32b1 is electrically connected to, for example, a main electrode of the second semiconductor element 42. The main electrode is, for example, an emitter electrode of an IGBT. A large current can be passed through the wiring 32b1. As in the specific example of FIG. 2, the wiring 32b1 may be used as a lead wire for connecting to an external circuit. When the power module 1 is configured as a half-bridge circuit 101, which will be described later with reference to FIG. 4, the wiring 32b1 is connected to a DC voltage source V - It can also be used as a terminal for connecting

[0046] The thin wiring 32b2 is electrically connected to, for example, a control electrode of the second semiconductor element 42. The control electrode is, for example, a gate electrode of an IGBT. A current that is sufficiently smaller than the current flowing through the wiring 32b1 can be passed through the wiring 32b2.

[0047] By including wiring layers 32a and 32b with wirings having different thicknesses, thicker wirings can be applied to paths through which large currents flow, and thinner wirings can be applied to paths through which small currents flow. When thicker wirings are applied to paths through which large currents flow, it is not necessary to increase the length of the wirings in the X or Y directions. By applying thinner wirings to paths through which small currents flow, it becomes easier to set the spacing between the wirings narrower. As a result, the arrangement density of the circuit elements arranged on third substrate 30 can be improved.

[0048] The first connection member 33, the second connection member 34, the third connection member 51, and the fourth connection member 52 are preferably made of a material having electrical conductivity. The first connection member 33, the second connection member 34, the third connection member 51, and the fourth connection member 52 are made of a metal material such as Cu, Al, or an alloy containing these.

[0049] 4, in the third substrate 30, the first connection member 33 can electrically connect the first semiconductor element 41 to the wiring layer 22 of the second substrate 20, and the second connection member 34 can electrically connect the second semiconductor element 42 to the wiring layer 12 of the first substrate 10. The first connection member 33 and the second connection member 34 can also be electrically connected to the wiring layers 32a, 32b and the conductive layer 36 provided on the third substrate 30.

[0050] 3(a) to 3(c) are schematic perspective views illustrating a first connection member that is a part of the power module according to the embodiment. As shown in Fig. 3(a), the first connection member 33 may have a cylindrical shape. In the first connection member 33, the mounting surface 33S1 and the heat dissipation surface 33S2 are circular in the XY plane view. The areas of the mounting surface 33S1 and the heat dissipation surface 33S2 are preferably sufficiently large. For example, by making the areas of the mounting surface 33S1 and the heat dissipation surface 33S2 approximately equal to or larger than the area of ​​the main electrode connected to the mounting surface 33S1 of the first semiconductor element 41 in the XY plane view, it is possible to reduce the thermal resistance due to the connection between the first semiconductor element 41 and the first connection member 33 and improve the heat dissipation of the first semiconductor element 41.

[0051] The first connection member 33 is not limited to a cylindrical shape, and may be, for example, an elliptical cylindrical shape in accordance with the outer circumferential shape of the first semiconductor element 41 in the XY plane view.

[0052] 3(b), the first connection member 33a may have a quadrangular prism shape. In the first connection member 33a, the mounting surface 33aS1 and the heat dissipation surface 33aS2 are rectangular. By making the areas of the mounting surface 33aS1 and the heat dissipation surface 33aS2 equal to or larger than the area of ​​the main electrode connected to the mounting surface 33S1 of the first semiconductor element 41 in the XY plane view, it is possible to reduce the thermal resistance due to the connection between the first semiconductor element 41 and the first connection member 33a and improve the heat dissipation of the first semiconductor element 41.

[0053] Furthermore, the shapes of the outer peripheries of the mounting surface 33aS1 and the heat dissipation surface 33aS2 may be set so that they overlap with the outer periphery, in the XY plane view, of the main electrode connected to the mounting surface 33S1 of the first semiconductor element 41, or are outside the outer periphery, in the XY plane view, of the main electrode connected to the mounting surface 33S1 of the first semiconductor element 41. In this way, the thermal coupling between the first semiconductor element 41 and the first connecting member 33a can be strengthened, and the heat dissipation of the first semiconductor element 41 can be further improved.

[0054] Furthermore, by forming the mounting surface 33aS1 and the heat dissipation surface 33aS2 into a rectangular shape, the density of the wiring arrangement of each of the wiring layers 32a and 32b can be improved.

[0055] As shown in Fig. 3(c), the first connection member 33b may have a quadrangular pyramid shape. The mounting surface 33bS1 and the heat dissipation surface 33bS2 are rectangular. In this specific example, the area of ​​the heat dissipation surface 33bS2 is larger than the area of ​​the mounting surface 33bS1. In this way, the density of the wiring on the third substrate 30 is improved while the thermal resistance on the second substrate 20 side is reduced, thereby achieving sufficiently high heat dissipation.

[0056] The first connection member 33b is not limited to a truncated quadrangular pyramid, and may be, for example, a truncated circular cone or a truncated elliptical cone depending on the outer circumferential shape of the first semiconductor element 41 in the XY plane view.

[0057] Although the shape of the first connection member 33 has been described above, the shape of the second connection member 34 can be set in a similar manner. In addition, the shapes of the above-mentioned first connection members 33, 33a, 33b are merely examples, and any appropriate shape can be set depending on the arrangement of the wires in the wiring layer on the third substrate 30, the size of the semiconductor element, the shape of the electrodes, etc.

[0058] FIG. 4 is a schematic equivalent circuit diagram of the power module according to the embodiment. By appropriately connecting the wires in the wiring layer 12 formed on the first substrate 10 and the wiring layers 12, 22 formed on the second substrate 20, respectively, a power module having a desired circuit configuration can be constructed.

[0059] The circuit elements in FIG. 4 correspond to the components shown in FIG. 1 and FIG. 2 (hereinafter, FIG. 1, etc.). That is, the semiconductor element 141 and the semiconductor element 142 correspond to the first semiconductor element 41 and the second semiconductor element 42, respectively, in FIG. 1, etc. The connection members 133, 151 and the wiring 122a correspond to the first connection member 33, the third connection member 51 and the wiring 22a, respectively, in FIG. 1, etc. The wiring 132b1 corresponds to the wiring 32b1 in FIG. 1, etc. The connection member 153 and the wiring 132a3 correspond to the fifth connection member 53 and the wiring 32a3 in FIG. 1, etc. The wiring 132a1 corresponds to the wiring 32a1 in FIG. 1, etc.

[0060] As shown in Fig. 4, for example, the power module 1 shown in Fig. 1 etc. may include a half-bridge circuit 101. The half-bridge circuit 101 is a series circuit of semiconductor elements 141 and 142. The semiconductor elements 141 and 142 are, for example, IGBTs (Insulated Gate Bipolar Transistors). Each of the semiconductor elements 141 and 142 has a diode connected in anti-parallel to the IGBT.

[0061] The semiconductor element 141 has a collector electrode C1, an emitter electrode E1, and a gate electrode G1. The collector electrode C1 is connected to a DC voltage source V +The emitter electrode E1 is electrically connected to the connection member 133 on the mounting surface 133S1. The connection member 133 is electrically connected to the connection member 151 on the heat dissipation surface 133S2, and is further electrically connected to the wiring 122a. The emitter electrode E1 is electrically connected to one end of the wiring 132a1, and the neutral point potential VAC is output from the other end of the wiring 132a1.

[0062] The semiconductor element 142 has a collector electrode C2, an emitter electrode E2, and a gate electrode G2. The collector electrode C2 is electrically connected to the wiring 122a. The emitter electrode E2 is connected to a DC voltage source V - Electrically connected to a DC voltage source V + The voltage value of the DC voltage source V - higher than the voltage value.

[0063] The connection members 133, 151 and the wiring 122a have impedances Z1, Z2, and Z3, respectively. The wiring 132b1 has an impedance Z4. The connection member 153 and the wiring 132a3 have impedances Z5 and Z6, respectively. The wiring 132a1 has an impedance Z7. That is, the impedances of the first connection member 33, the third connection member 51, and the wiring 22a correspond to the impedances Z1, Z2, and Z3, respectively. The impedance of the wiring 32b1 corresponds to the impedance Z4. The impedances of the fifth connection member 53 and the wiring 32a3 correspond to the impedances Z5 and Z6, respectively. The impedance of the wiring 32a1 corresponds to the impedance Z7.

[0064] The areas of the mounting surface 33S1 and the heat dissipation surface 33S2 of the first connection member 33 can be made sufficiently large. The areas of the third connection member 51 and the wiring 22a in the XY plane view can be made sufficiently large. The areas of the wiring 32b1 in the XY plane view can be made sufficiently large. The areas of the fifth connection member 53 and the wiring 32a3 in the XY plane view can be made sufficiently large. The area of ​​the wiring 32a1 in the XY plane view can be made sufficiently large.

[0065] The first connecting member 33, the third connecting member 51, the wiring 22a, the wiring 32b1, the fifth connecting member 53, the wiring 32a3, and the wiring 32a1 can be made of a metal material such as Cu. Therefore, by making these have the above-mentioned shapes, the DC resistance values ​​corresponding to the impedances Z1, Z2, Z3, Z4, Z5, Z6, and Z7 can be sufficiently reduced.

[0066] Furthermore, the parasitic inductance values ​​corresponding to the impedances Z1, Z2, Z3, Z4, Z5, Z6, and Z7 can also be made sufficiently small by giving them the above-mentioned shapes.

[0067] By making the DC resistance values ​​corresponding to the impedances Z1, Z2, Z3, Z4, Z5, Z6, and Z7 sufficiently small, the loss caused by the DC resistance can be reduced. Also, since the voltage drop caused by the DC resistance can be suppressed, for example, the magnitude of the voltage applied to the control electrode of the semiconductor element can be sufficiently ensured.

[0068] By making the parasitic inductance values ​​corresponding to the impedances Z1, Z2, Z3, Z4, Z5, Z6, and Z7 sufficiently small, it is possible to suppress the generation of noise and surge voltages that accompany the high-speed switching operations of semiconductor elements.

[0069] Fig. 5(a) is a schematic side view illustrating a power module according to an embodiment, and Fig. 5(b) is a schematic side view illustrating a power module of a comparative example. FIG. 5(a) shows a model 201a for performing a thermal simulation in the configuration of the power module 1 shown in FIG. 1 and so on.

[0070] In the model 201a of FIG. 5(a), the semiconductor elements 241 and 242 correspond to the first semiconductor element 41 and the second semiconductor element 42 shown in FIG. 1 and the like. The base material 211 and the wiring layer 212 correspond to the base material 11 and the wiring layer 12 shown in FIG. 1 and the like. The base material 221 and the wiring layer 222 correspond to the base material 21 and the wiring layer 22 shown in FIG. 1 and the like. The connection members 233, 234, 251, and 252 correspond to the first connection member 33, the second connection member 34, the third connection member 51, and the fourth connection member 52 shown in FIG. 1 and the like. The wiring layers 232a and 232b correspond to the wiring layers 32a and 32b shown in FIG. 1 and the like.

[0071] FIG. 5(b) shows a model 201b obtained by removing the connecting member 234 from the model 201a in FIG. 5(a).

[0072] In models 201a and 201b, in order to avoid complexity in the illustration and to clearly show the configurations of connecting members 233 and 234, model elements corresponding to base material 31 of third substrate 30 shown in Fig. 1 etc. are omitted. In the simulation using models 201a and 201b, model elements according to the material and shape of base material 31 are provided.

[0073] In models 201a and 201b, the model elements are made of appropriate materials and shapes, a power loss of 1 W is applied to the model element of semiconductor element 241, and a heat transfer coefficient equivalent to forced cooling by water flow is applied to the model elements of substrates 211 and 221.

[0074] Under the above conditions, it has been confirmed that the model 201a corresponding to the power module 1 according to the embodiment has a thermal resistance reduced by about 40% compared to the model 201b of the comparative example.

[0075] The effects of the power module 1 according to the embodiment will be described. The power module 1 according to the embodiment includes a first substrate 10, a second substrate 20, a third substrate 30, a first semiconductor element 41, and a second semiconductor element 42. The third substrate 30 is provided between the first semiconductor element 41 provided on the first substrate 10 and the second semiconductor element 42 provided on the second substrate 20. The third substrate includes a first connection member 33 and a second connection member 34 that penetrate the base material 31.

[0076] The first connecting member 33 and the second connecting member 34 have high thermal conductivity. In addition, the base material 11 of the first substrate 10 and the base material 21 of the second substrate 20 have high thermal conductivity.

[0077] The first connection member 33 is thermally coupled to the first semiconductor element 41 at the mounting surface 33S1, and is thermally coupled to the second substrate 20 at the heat dissipation surface 33S2 via the third connection member 51. Therefore, the first semiconductor element 41 has heat dissipated by the first substrate 10, and also by the second substrate 20 via the first connection member 33 and the third connection member 51.

[0078] The second connecting member 34 is thermally coupled to the second semiconductor element 42 at the mounting surface 34S1, and is thermally coupled to the first substrate 10 at the heat dissipation surface 34S2 via the fourth connecting member 52. Therefore, the second semiconductor element 42 has heat dissipated by the second substrate 20, and also by the first substrate 10 via the second connecting member 34 and the fourth connecting member 52.

[0079] That is, the first semiconductor element 41 can dissipate heat from both the first substrate 10 side and the second substrate 20 side by the first connection member 33 and the second connection member 34 provided to penetrate the base material 31 of the third substrate 30. Similarly, the second semiconductor element 42 can dissipate heat from both the first substrate 10 side and the second substrate 20 side. Therefore, the power module 1 according to the embodiment achieves high heat dissipation performance.

[0080] In the first connecting member 33, the area of ​​the mounting surface 33S1 thermally coupled to the first semiconductor element 41 can be made sufficiently large and can be made approximately equal to the area of ​​the thermally coupled surface with the mounting surface 33S1 of the first semiconductor element 41. Therefore, the contact thermal resistance between the first semiconductor element 41 and the first connecting member 33 can be reduced, and the heat dissipation performance of the power module 1 can be improved.

[0081] Similarly, the area of ​​the mounting surface 34S1 of the second connecting member 34 can be made sufficiently large and can be made approximately the same as the area of ​​the thermally coupled surface with the mounting surface 34S1 of the second semiconductor element 42. Therefore, the contact thermal resistance between the second semiconductor element 42 and the second connecting member 34 can be reduced, and the heat dissipation performance of the power module 1 can be improved.

[0082] 3(a) to 3(c), it is possible to appropriately set the shapes of the first connecting member 33 and the second connecting member 34. This makes it possible to improve the heat dissipation performance of the power module 1, as well as to increase the degree of freedom in arranging the circuit elements including the first semiconductor element 41 and the second semiconductor element 42, and to increase the arrangement density.

[0083] For example, by forming the first connection member 33 and the second connection member 34 from Cu or an alloy containing Cu, the first connection member 33 and the second connection member 34 can achieve high electrical conductivity while achieving high thermal conductivity. In the third substrate 30, the first connection member 33 and the second connection member 34 can be used as a wiring member with low impedance. By using the first connection member 33 and the second connection member 34 as wiring members in the third substrate 30, in the circuit element including the first semiconductor element 41 and the second semiconductor element 42, the power module 1 can switch high voltages and large currents at high speed with low noise.

[0084] The base material 31 of the third substrate 30 includes a conductive layer 36. The conductive layer 36 is provided on an inner layer of the base material 31, and can be electrically isolated from the first connecting member and the second connecting member 34. The conductive layer 36 can be used as an electromagnetic shielding layer by connecting it to a specific potential. Providing the conductive layer 36 on the third substrate 30 makes it easy to provide circuit components 61 and 62 that handle low-level signals on the third substrate 30.

[0085] In the third substrate 30, the wiring layers 32a, 32b can include wirings of different thicknesses on at least one of the fifth surface 31a side and the sixth surface 31b side. By making the thickness of the wirings to which a low voltage is applied or through which a small current flows thinner than the thickness of the wirings to which a high voltage is applied or through which a large current flows, it becomes possible to form a finer wiring pattern. Therefore, the packaging density of the circuit elements in the power module 1 can be improved.

[0086] When the circuit configuration in the power module 1 is the half-bridge circuit 101 shown in Fig. 4, the wirings 32a1, 32a3, and 32b1 can be used as lead wires for connecting to an external circuit. In this case, by making the thickness of these wirings sufficiently large and making the area in the XY plane sufficiently large, it is possible to electrically connect to the external circuit with low resistance and low inductance.

[0087] In addition, by directly connecting the wiring 32b1 to the emitter electrode of the second semiconductor element 42, a direct current voltage source V - This allows current to flow through the second connection member 34. As a result, the second connection member 34 is less susceptible to the effects of copper loss and iron loss caused by the current of the switching operation of the second semiconductor element 42. Therefore, the second connection member 34 is less susceptible to the effects of heat generation caused by copper loss and iron loss, and the heat dissipation effect of the second semiconductor element 42 can be improved.

[0088] In this manner, a semiconductor device having a plurality of heat generating components and high heat dissipation properties can be realized.

[0089] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other.

[0090] The embodiments include the following aspects.

[0091] (Appendix 1) a first substrate including a first base material having a first surface and a second surface opposite to the first surface and having thermal conductivity; a second substrate including a second base material having a third surface facing the first surface and a fourth surface opposite to the third surface and having thermal conductivity; A first semiconductor element provided on the first surface side; A second semiconductor element provided on the third surface side; a third substrate including a third base material provided between the first substrate and the second substrate and having a fifth surface facing the first surface and a sixth surface opposite to the fifth surface; Equipped with The third substrate is a first connection member that penetrates from the fifth surface to the sixth surface and has thermal conductivity; a second connection member that penetrates from the fifth surface to the sixth surface, is spaced apart from the first connection member, and has thermal conductivity; Including, the first semiconductor element is thermally coupled to each of the first substrate and the first connection member between the first substrate and the first connection member; The second semiconductor element is a semiconductor device between the second substrate and the second connection member, and is thermally coupled to both the second substrate and the second connection member.

[0092] (Appendix 2) 2. The semiconductor device according to claim 1, wherein each of the first connection member and the second connection member has a shape selected from the group consisting of a circular cylinder, an elliptical cylinder, a rectangular prism, and a frustum.

[0093] (Appendix 3) 3. The semiconductor device according to claim 1, further comprising a first heat sink provided on the second surface side and thermally coupled to the first substrate.

[0094] (Appendix 4) 4. The semiconductor device according to claim 3, further comprising a second heat sink provided on the fourth surface side and thermally coupled to the second substrate.

[0095] (Appendix 5) each of the first connection member and the second connection member is electrically conductive; the first substrate includes a first wiring layer on the first surface; the second substrate includes a second wiring layer on the third surface; the first semiconductor element is electrically connected to the first wiring layer on the first surface side and is electrically connected to the first connection member on the fifth surface side; The semiconductor device according to any one of claims 1 to 4, wherein the second semiconductor element is electrically connected to the second wiring layer on the third surface side and electrically connected to the second connecting member on the sixth surface side.

[0096] (Appendix 6) the third substrate includes a third wiring layer provided on the fifth surface, a fourth wiring layer provided on the sixth surface, and a conductive layer provided on an inner layer of the base material; a first circuit component provided on the fifth surface side and electrically connected to the third wiring layer; a second circuit component provided on the sixth surface side and electrically connected to the fourth wiring layer; Further equipped with 6. The semiconductor device according to claim 5, wherein the conductive layer is provided between the first circuit component and the second circuit component.

[0097] (Appendix 7) the first semiconductor element has a plurality of main electrodes and a first control electrode; the first circuit component is electrically connected to the first control electrode; the second semiconductor element has a plurality of main electrodes and a second control electrode; 7. The semiconductor device according to claim 6, wherein the second circuit component is electrically connected to the second control electrode.

[0098] (Appendix 8) the third wiring layer includes a first wiring having a first thickness and a second wiring having a second thickness that is thinner than the first thickness; the fourth wiring layer includes a third wiring having a third thickness and a fourth wiring having a fourth thickness that is thinner than the third thickness; the second wiring electrically connects the first circuit component and the first control electrode; 8. The semiconductor device according to claim 7, wherein the fourth wiring electrically connects the second circuit component and the second control electrode.

[0099] (Appendix 9) one main electrode of the first semiconductor element is electrically connected to the first wiring layer; the other main electrode of the first semiconductor element is electrically connected to the first connection member; one main electrode of the second semiconductor element is electrically connected to the second wiring layer; 9. The semiconductor device according to claim 7, wherein another main electrode of the second semiconductor element is electrically connected to the second connection member.

[0100] (Appendix 10) 10. The semiconductor device of claim 9, wherein in the first wiring layer, one main electrode of the first semiconductor element and another main electrode of the second semiconductor element are respectively connected to a plurality of electrically separated wirings.

[0101] (Appendix 11) the first connection member has a first mounting surface thermally coupled to the first semiconductor element; 11. The semiconductor device according to claim 1, wherein an area of ​​the first mounting surface in a plan view is equal to or larger than an area of ​​a main electrode of the first semiconductor element on a surface facing the first mounting surface.

[0102] (Appendix 12) the second connection member has a second mounting surface thermally coupled to the second semiconductor element, 12. The semiconductor device according to claim 11, wherein an area of ​​the second mounting surface in a plan view is equal to or larger than an area of ​​a main electrode of a surface of the second semiconductor element facing the second mounting surface.

[0103] (Appendix 13) 13. The semiconductor device according to claim 1, wherein the first connection member and the second connection member contain Cu or Al.

[0104] (Appendix 14) the first semiconductor element is one of an IGBT, a MOSFET, a GTO, or a diode; 14. The semiconductor device according to claim 1, wherein the second semiconductor element is one of an IGBT, a MOSFET, a GTO, or a diode.

[0105] (Appendix 15) the first semiconductor element includes any one of Si, SiC, or GaN; 15. The semiconductor device according to claim 14, wherein the second semiconductor element includes any one of Si, SiC, or GaN.

[0106] (Appendix 16) the first substrate includes any one of Al2O3, AlN, Cu, or Al; 16. The semiconductor device according to claim 1, wherein the second base contains any one of Al2O3, AlN, Cu, and Al.

[0107] (Appendix 17) 17. The semiconductor device according to any one of claims 1 to 16, further comprising a case that houses the first substrate, the second substrate, the third substrate, the first semiconductor element, and the second semiconductor element.

[0108] (Appendix 18) 18. The semiconductor device according to claim 17, wherein the case contains an insulating resin.

[0109] (Appendix 19) 19. The semiconductor device according to any one of claims 1 to 18, wherein the third base has a thermal conductivity lower than both the thermal conductivity of the first connection member and the thermal conductivity of the second connection member.

[0110] (Appendix 20) 20. The semiconductor device according to claim 19, wherein the third base material includes glass fiber. [Explanation of symbols]

[0111] 1...power module, 10...first substrate, 11...base material, 12, 22, 32a, 32b...wiring layer, 20...second substrate, 21...base material, 30...third substrate, 31...base material, 33, 33a, 33b...first connecting member, 33S1, 33aS1, 33bS1, 34S1...mounting surface, 33S2, 33aS2, 33bS2, 34S2...heat dissipation surface, 34...second connecting member, 36...conductive layer, 41...first semiconductor element, 42...second semiconductor element, 51...third connecting member, 52...fourth connecting member, 61, 62...circuit component, 110...first heat sink, 120...second heat sink

Claims

1. a first substrate including a first base material having a first surface and a second surface opposite to the first surface and having thermal conductivity; a second substrate including a second base material having a third surface facing the first surface and a fourth surface opposite to the third surface and having thermal conductivity; A first semiconductor element provided on the first surface side; A second semiconductor element provided on the third surface side; a third substrate including a third base material provided between the first substrate and the second substrate and having a fifth surface facing the first surface and a sixth surface opposite to the fifth surface; Equipped with The third substrate is a first connection member that penetrates from the fifth surface to the sixth surface and has thermal conductivity; a second connection member that penetrates from the fifth surface to the sixth surface, is spaced apart from the first connection member, and has thermal conductivity; Including, the first semiconductor element is thermally coupled to each of the first substrate and the first connection member between the first substrate and the first connection member; The second semiconductor element is a semiconductor device between the second substrate and the second connection member, and is thermally coupled to each of the second substrate and the second connection member.

2. 2. The semiconductor device according to claim 1, wherein each of the first connection member and the second connection member has a shape selected from the group consisting of a circular cylinder, an elliptical cylinder, a rectangular prism, and a frustum.

3. 2. The semiconductor device according to claim 1, further comprising a first heat sink provided on the second surface side and thermally coupled to the first substrate.

4. 4. The semiconductor device according to claim 3, further comprising a second heat sink provided on the fourth surface side and thermally coupled to the second substrate.

5. each of the first connection member and the second connection member is electrically conductive; the first substrate includes a first wiring layer on the first surface; the second substrate includes a second wiring layer on the third surface; the first semiconductor element is electrically connected to the first wiring layer on the first surface side and is electrically connected to the first connection member on the fifth surface side; 2 . The semiconductor device according to claim 1 , wherein the second semiconductor element is electrically connected to the second wiring layer on the third surface side and is electrically connected to the second connection member on the sixth surface side.

6. the third substrate includes a third wiring layer provided on the fifth surface, a fourth wiring layer provided on the sixth surface, and a conductive layer provided on an inner layer of the base material, a first circuit component provided on the fifth surface side and electrically connected to the third wiring layer; a second circuit component provided on the sixth surface side and electrically connected to the fourth wiring layer; Further equipped with 6. The semiconductor device according to claim 5, wherein the conductive layer is provided between the first circuit component and the second circuit component.

7. the first semiconductor element has a plurality of main electrodes and a first control electrode; the first circuit component is electrically connected to the first control electrode; the second semiconductor element has a plurality of main electrodes and a second control electrode; 7. The semiconductor device according to claim 6, wherein the second circuit component is electrically connected to the second control electrode.

8. the third wiring layer includes a first wiring having a first thickness and a second wiring having a second thickness that is thinner than the first thickness; the fourth wiring layer includes a third wiring having a third thickness and a fourth wiring having a fourth thickness that is thinner than the third thickness; the second wiring electrically connects the first circuit component and the first control electrode; The semiconductor device according to claim 7 , wherein the fourth wiring electrically connects the second circuit component and the second control electrode.

9. one main electrode of the first semiconductor element is electrically connected to the first wiring layer; the other main electrode of the first semiconductor element is electrically connected to the first connection member; one main electrode of the second semiconductor element is electrically connected to the second wiring layer; 8. The semiconductor device according to claim 7, wherein the other main electrode of the second semiconductor element is electrically connected to the second connection member.

10. 10. The semiconductor device according to claim 9, wherein in the first wiring layer, one main electrode of the first semiconductor element and another main electrode of the second semiconductor element are respectively connected to a plurality of electrically separated wirings.

11. the first connection member has a first mounting surface thermally coupled to the first semiconductor element; 2 . The semiconductor device according to claim 1 , wherein an area of ​​the first mounting surface in a plan view is equal to or larger than an area of ​​a main electrode of the first semiconductor element on a surface facing the first mounting surface.

12. the second connection member has a second mounting surface thermally coupled to the second semiconductor element, The semiconductor device according to claim 11 , wherein an area of ​​the second mounting surface in a plan view is equal to or larger than an area of ​​a main electrode of the second semiconductor element on a surface facing the second mounting surface.

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