Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device in which the thicknesses of free patterns included in plural magnetic tunnel joint patterns can be adjusted by a simple process, and a method of manufacturing the semiconductor device.SOLUTION: The semiconductor device includes: a substrate 300; a first magnetic tunnel joint pattern MTJ-A' arranged on the substrate, the first magnetic tunnel joint pattern including a first free pattern 354A; a second magnetic tunnel joint pattern MTJ-B' arranged on the substrate, the second magnetic tunnel joint pattern including a second free pattern 354B thinner than the first free pattern; and a first hard mask pattern 372A on the first free pattern. There may be a conductive doping pattern 357 between a second hard mask pattern 372B on a second free pattern and a second hard mask pattern on a second free pattern.SELECTED DRAWING: Figure 3F

Description

[Technical field]

[0001] This patent document relates to semiconductor technology, and more particularly to semiconductor devices including magnetic tunnel junctions and methods for fabricating the same. [Background technology]

[0002] Recently, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, various electronic devices such as computers and portable communication devices are in demand for semiconductor devices capable of storing information, and research into this field is being conducted. Examples of such semiconductor devices include semiconductor devices capable of storing data by utilizing the characteristic of switching between different resistance states depending on an applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuses (E-fuses). Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that are capable of adjusting the thicknesses of free patterns included in a plurality of magnetic tunnel junction patterns to be different in a simple process. [Means for solving the problem]

[0004] In order to solve the above problems, a semiconductor device according to one embodiment of the present invention may include a substrate, a first magnetic tunnel junction pattern disposed on the substrate and including a first free pattern, a second magnetic tunnel junction pattern disposed on the substrate and including a second free pattern having a thickness smaller than that of the first free pattern, a first hard mask pattern on the first free pattern, a second hard mask pattern on the second free pattern, and a doping pattern interposed between the second free pattern and the second hard mask pattern and having conductivity.

[0005] In addition, in order to solve the above problems, a semiconductor device according to another embodiment of the present invention includes a substrate, a first magnetic tunnel junction pattern disposed on the substrate and including a first free pattern, a second magnetic tunnel junction pattern disposed on the substrate and including a second free pattern having a thickness smaller than that of the first free pattern, a first hard mask pattern on the first free pattern, and a second hard mask pattern on the second free pattern, wherein a thickness of the first hard mask pattern is smaller than a thickness of the second hard mask pattern.

[0006] In addition, in order to solve the above problem, a manufacturing method of a semiconductor device according to another embodiment of the present invention includes the steps of forming a magnetic tunnel junction layer including a fixed layer, a tunnel barrier layer, and a free layer on a substrate; forming a sacrificial hard mask pattern covering at least an area on the free layer where a first magnetic tunnel junction pattern is formed while exposing at least an area where a second magnetic tunnel junction pattern is formed; doping the free layer exposed by the sacrificial hard mask pattern with a dopant that causes the free layer to lose magnetism to form a doped region having a thickness smaller than a thickness of the free layer; removing the sacrificial hard mask pattern; forming a hard mask pattern covering the area on the free layer and the doped region where the first magnetic tunnel junction pattern is formed and the area on the free layer where the second magnetic tunnel junction pattern is formed; and etching the doped region, the free layer, the tunnel barrier layer, and the fixed layer.

[0007] In addition, in order to solve the above problem, a manufacturing method of a semiconductor device according to another embodiment of the present invention includes the steps of forming a magnetic tunnel junction layer including a fixed layer, a tunnel barrier layer, and a free layer on a substrate, forming a sacrificial hard mask pattern covering at least an area on the free layer where a first magnetic tunnel junction pattern is formed while exposing at least an area on the free layer where a second magnetic tunnel junction pattern is formed, etching the free layer exposed by the sacrificial hard mask pattern to reduce a thickness, removing the sacrificial hard mask pattern, forming a hard mask pattern covering an area on the free layer where the first magnetic tunnel junction pattern is formed and an area on the free layer where the second magnetic tunnel junction pattern is formed, and etching the free layer, the tunnel barrier layer, and the fixed layer using the hard mask pattern.

[0008] In addition, in order to solve the above problems, a method for manufacturing a semiconductor device according to another embodiment of the present invention includes the steps of forming a magnetic tunnel junction layer including a fixed layer, a tunnel barrier layer, and a free layer on a substrate; forming a sacrificial hard mask pattern covering at least an area on the free layer where a first magnetic tunnel junction pattern is formed and exposing at least an area where a second magnetic tunnel junction pattern is formed; etching the free layer exposed by the sacrificial hard mask pattern to reduce a thickness; forming a metal oxide layer on the sacrificial hard mask pattern and the free layer; removing the sacrificial hard mask pattern and the metal oxide layer formed on the sidewalls and upper surface of the sacrificial hard mask pattern to form a metal oxide pattern; forming a hard mask pattern covering the area where the first magnetic tunnel junction pattern is formed and the area where the second magnetic tunnel junction pattern is formed on the free layer and the metal oxide pattern; and etching the free layer, the tunnel barrier layer, and the fixed layer using the hard mask pattern. Effect of the Invention

[0009] According to the semiconductor device and the manufacturing method thereof of the embodiment of the present invention, the thicknesses of the free patterns included in the multiple magnetic tunnel junction patterns can be adjusted to be different in a simple process. [Brief description of the drawings]

[0010] [Figure 1A] 1 is a diagram illustrating a semiconductor device according to an embodiment of the present invention; [Figure 1B] 1 is a diagram illustrating a semiconductor device according to an embodiment of the present invention; [Figure 2A] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 2B] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 2C]11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 2D] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 2E] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 2F] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 2G] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 3A] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 3B] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 3C] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 3D] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 3E] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 3F] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 4A] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 4B] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 4C] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 4D] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. [Figure 4E] 11A to 11C are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Various embodiments will now be described in detail with reference to the accompanying drawings.

[0012] The drawings are not necessarily drawn to scale, and in some instances, the proportions of at least some of the structures depicted in the drawings may be exaggerated to clearly illustrate features of the embodiment. When a multi-layer structure having two or more layers is disclosed in the drawings or detailed description, the relative positions and order of the layers as shown reflects a particular embodiment only, and the invention is not limited thereto, and the relative positions and order of the layers may be different. Also, the drawings or detailed description of a multi-layer structure may not reflect all layers present in a particular multi-layer structure (e.g., there may be one or more additional layers between two layers shown). For example, when a multi-layer structure in a drawing or detailed description shows that a first layer is on a second layer or on a substrate, it may not only indicate that the first layer may be formed directly on the second layer or directly on the substrate, but may also indicate that one or more other layers may be present between the first and second layers, or between the first layer and the substrate.

[0013] 1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line AA' in FIG. 1A.

[0014] 1A and 1B, the semiconductor device of the present embodiment may include a substrate 100, a first conductive line 110 disposed on the substrate 100 and extending in a first direction, a second conductive line 140 disposed on the first conductive line 120 and extending in a second direction intersecting the first direction, a selector pattern 120 disposed in an intersection region between the first conductive line 110 and the second conductive line 140, and a magnetic tunnel junction pattern 130. Hereinafter, the first and second directions may refer to directions substantially parallel to the surface of the substrate 100. A direction substantially perpendicular to the surface of the substrate 100 will be referred to as a perpendicular direction.

[0015] The substrate 100 may include a semiconductor material such as silicon. In addition, a required substructure (not shown) is formed in the substrate 100. For example, an integrated circuit for driving the first conductive line 110 and / or the second conductive line 140 is formed in the substrate 100.

[0016] The first conductive lines 110 are arranged spaced apart from one another in the second direction. The first conductive lines 110 may include various conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof, and may have a single layer structure or a multi-layer structure.

[0017] The second conductive lines 140 are arranged spaced apart from each other in a first direction. The second conductive lines 140 may include various conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof, and may have a single layer structure or a multi-layer structure.

[0018] The selector pattern 120 may have a columnar shape overlapping an intersection region between the first conductive line 110 and the second conductive line 140. In this embodiment, the selector pattern 120 is shown to have a circular shape in a plan view, but the present disclosure is not limited thereto, and the selector pattern 120 may have various shapes such as an oval shape, a square shape, etc. in a plan view.

[0019] The selector pattern 120 may prevent current leakage that may occur between the magnetic tunnel junction patterns 130 sharing the first conductive line 110 or the second conductive line 140 while controlling the access to the magnetic tunnel junction patterns 130. To this end, the selector pattern 120 may have a threshold switching characteristic in which, when the magnitude of a voltage supplied to its upper and lower ends is less than a predetermined threshold voltage, the selector pattern 120 cuts off current or barely passes current, and when the voltage is equal to or greater than the threshold voltage, the selector pattern 120 suddenly passes current. That is, the selector pattern 120 is turned on when the voltage is equal to or greater than the threshold voltage and turned off when the voltage is less than the threshold voltage.

[0020] The selector pattern 120 may include an OTS (Ovonic Threshold Switching) material such as a diode, a chalcogenide-based material, a MIEC (Mixed Ionic Electronic Conducting) material such as a metal-containing chalcogenide-based material, a MIT (Metal Insulator Transition) material such as NbO2, VO2, or a tunneling insulating material having a relatively wide band gap such as SiO2, Al2O3, etc.

[0021] Alternatively, the selector pattern 120 may include an insulating material layer doped with a dopant. Here, the insulating material layer may include a silicon-containing insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., an insulating metal oxide, an insulating metal nitride, or a combination thereof. In the insulating material layer, deep traps having an energy level closer to the energy level of a valence band than the energy level of a conduction band of the insulating material layer may exist. The dopant may play a role in generating shallow traps that provide a path for the movement of conductive carriers, for example, electrons or holes, in the insulating material layer. The shallow traps may have an energy level closer to the energy level of the conduction band than the energy level of the valence band of the insulating material layer. For example, when the insulating material layer includes silicon, the dopant may include a metal having a different valence from silicon, such as gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), tungsten (W), or a combination thereof. Alternatively, when the insulating material layer includes a metal, the dopant may include a metal having a different valence from the metal, such as silicon. For example, the selector pattern 120 may include silicon oxide, such as silicon dioxide (SiO2), doped with arsenic (As). When a voltage equal to or greater than a threshold voltage is applied to the selector pattern 120, carriers trapped in deep traps may jump to shallow traps by thermal emission or tunneling, and carriers may move through the shallow traps, thereby realizing an on-state in which a current flows through the selector pattern 120. In contrast, when no voltage is applied to the selector pattern 120 or a voltage less than the threshold voltage is applied, the phenomenon of carriers jumping to shallow traps is reduced or prevented, and an off state in which no current flows through the selector pattern 120 can be achieved.

[0022] The magnetic tunnel junction pattern 130 may have a columnar shape overlapping an intersection region between the first conductive line 110 and the second conductive line 140. In this embodiment, the magnetic tunnel junction pattern 130 is shown to have a circular shape on a plane, but the present disclosure is not limited thereto, and the magnetic tunnel junction pattern 130 may have various shapes such as an elliptical shape, a rectangular shape, etc. on a plane. In addition, in this embodiment, the selector pattern 120 and the magnetic tunnel junction pattern 130 may be formed by separate patterning processes using different masks. In this case, the selector pattern 120 and the magnetic tunnel junction pattern 130 may not be aligned with each other while overlapping each other. However, the present disclosure is not limited thereto, and in other embodiments, the selector pattern 120 and the magnetic tunnel junction pattern 130 may be aligned with each other while overlapping each other by forming the selector pattern 120 and the magnetic tunnel junction pattern 130 by a patterning process using one mask.

[0023] The magnetic tunnel junction pattern 130 may include a laminated structure of a fixed pattern 131, a tunnel barrier pattern 133, and a free pattern 135. The fixed pattern 131 is a layer having a fixed magnetization direction that is contrasted with the magnetization direction of the free pattern 135, and is also called a reference layer. The free pattern 135 is a layer having a changeable magnetization direction that can store different data, and is also called a storage layer. The fixed pattern 131 and the free pattern 135 may each have a magnetization direction substantially parallel to the surface of the layer, for example, the top surface of the layer, or may have a magnetization direction substantially perpendicular to the surface of the layer. The tunnel barrier pattern 133 physically separates the fixed pattern 131 and the free pattern 135 while allowing tunneling of electrons between them. The fixed pattern 131 and the free pattern 135 may each have a single-layer or multi-layer structure containing a ferromagnetic material independently. For example, the fixed pattern 131 and the free pattern 135 may each independently include at least one of an alloy mainly composed of Fe, Ni, or Co, for example, an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Ni-Pt alloy, an Fe-Pd alloy, and a Co-Fe-B alloy, or may include at least one of a Co / Pt stack structure and a Co / Pd stack structure. The tunnel barrier pattern 133 may have a single layer or a multi-layer structure including an insulating material. For example, the tunnel barrier pattern 133 may include an insulating oxide such as MgO, CaO, SrO, TiO, VO, or NbO. Such a magnetic tunnel junction pattern 130 may store different data by switching between different resistance states depending on a voltage or current applied through the first conductive line 110 and the second conductive line 140.More specifically, when the magnetization direction of the free pattern 135 is changed to be parallel to the magnetization direction of the fixed pattern 131 by a voltage or a current applied to the magnetic tunnel junction pattern 130, the magnetic tunnel junction pattern 130 may have a low resistance state and may store data "1", for example. On the other hand, when the magnetization direction of the free pattern 135 is changed to be anti-parallel to the magnetization direction of the fixed pattern 131 by a voltage or a current applied to the magnetic tunnel junction pattern 130, the magnetic tunnel junction pattern 130 may have a high resistance state and may store data "0", for example.

[0024] As long as the magnetic tunnel junction pattern 130 includes the fixed pattern 131, the free pattern 135, and the tunnel barrier pattern 133 therebetween, the layer structure of the magnetic tunnel junction pattern 130 can be modified in various ways. For example, the positions of the fixed pattern 131 and the free pattern 135 can be reversed. Alternatively, for example, the magnetic tunnel junction pattern 130 can further include one or more layers for improving characteristics, although not shown. For example, the magnetic tunnel junction pattern 130 can further include one or more fixed patterns that are antiferromagnetically coupled with the fixed pattern 131 to form a synthetic anti-ferromagnetic structure (SAF structure). An SAF coupling pattern including a non-magnetic material may be interposed between the fixed pattern 131 adjacent to the fixed pattern 131 and / or between adjacent ones of the one or more fixed patterns. Alternatively, for example, the magnetic tunnel junction pattern 130 can further include one or more conductive patterns interposed between the fixed pattern 131 and the first conductive line 110 or between the free pattern 135 and the second conductive line 140. This conductive pattern is called an electrode layer, a hard mask layer, a capping layer, etc. depending on its function.

[0025] In the magnetic tunnel junction pattern 130, when the free pattern 135 has a magnetization direction substantially perpendicular to the surface of the layer, the perpendicular magnetic anisotropy of the free pattern 135 may be inversely proportional to the thickness of the free pattern 135. That is, as the thickness of the free pattern 135 increases, the perpendicular magnetic anisotropy decreases, and as the thickness of the free pattern 135 decreases, the perpendicular magnetic anisotropy increases. A large perpendicular magnetic anisotropy may mean that the data retention characteristic is improved, but the operating speed is slow and the power consumption is large. Therefore, by making the thicknesses of the free patterns 135 different in the magnetic tunnel junction patterns 130, magnetic tunnel junction patterns 130 having different characteristics from each other can be formed on one substrate 100. That is, it is possible to realize a semiconductor device including a magnetic tunnel junction pattern 130 having a relatively small thickness and excellent data retention characteristic and a magnetic tunnel junction pattern 130 having a relatively large thickness and fast operating speed and low power consumption at the same time.

[0026] In the following embodiments, a method for adjusting the thicknesses of free patterns included in a plurality of magnetic tunnel junction patterns to be different, and a semiconductor device manufactured thereby will be described.

[0027] 2A to 2G are cross-sectional views for explaining a semiconductor device and a manufacturing method thereof according to another embodiment of the present invention. These cross-sectional views are shown based on a cross section taken along line A-A' in FIG. 1A. Detailed descriptions of parts that are substantially the same as those in the above-mentioned embodiment will be omitted.

[0028] First, the manufacturing method will be described.

[0029] 2A, a first conductive line 210 extending in a first direction may be formed on a substrate 200. Although not shown, a plurality of first conductive lines 210 are arranged parallel to each other and spaced apart in a second direction passing through the cross section. The first conductive lines 210 are formed by depositing and patterning a conductive material. At the same time, spaces between the first conductive lines 210 in the second direction are filled with an insulating material (not shown).

[0030] Next, the selector pattern 220 and a first interlayer insulating layer 225 filling the gap between the selector patterns 220 may be formed on the first conductive lines 210 and the insulating material therebetween. In this embodiment, the selector pattern 220 and the first interlayer insulating layer 225 may be formed by forming a selector material for forming the selector pattern 220 on the first conductive lines 210 and the insulating material therebetween, selectively etching the selector material to form the selector pattern 220, forming a first interlayer insulating material with a thickness that sufficiently fills the gap between the selector patterns 220, and then performing a planarization process, for example, chemical mechanical polishing (CMP), to expose the top surface of the selector pattern 220. In this case, the selector pattern 220 may have a width that increases from top to bottom in the vertical direction. However, the present disclosure is not limited thereto, and in other embodiments, the selector pattern 220 and the first interlayer insulating layer 225 may be formed by forming a first interlayer insulating material on the first conductive line 210 and the insulating material therebetween, selectively etching the first interlayer insulating material to form the first interlayer insulating layer 225 providing a space in which the selector pattern 220 is to be formed, forming a selector material with a thickness sufficient to fill the space, and then performing a planarization process until the top surface of the first interlayer insulating layer 225 is exposed. In this case, the selector pattern 220 may have a width that decreases from top to bottom in the vertical direction, unlike that shown in the drawing.

[0031] Referring to FIG. 2B, a magnetic tunnel junction layer including a fixed layer 230 , a tunnel barrier layer 240 , and a free layer 250 may be formed on the selector pattern 220 and the first interlayer insulating layer 225 .

[0032] Next, a sacrificial hard mask pattern 260 may be formed on the free layer 250. The sacrificial hard mask pattern 260 may be formed to cover at least a region where a first magnetic tunnel junction pattern (see MTJ-A in FIG. 2F) will be formed, and to expose at least a region where a second magnetic tunnel junction pattern (see MTJ-B in FIG. 2F) will be formed. The first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern may be spaced apart from each other, and the sacrificial hard mask pattern 260 may not cover the space or may cover a part of the space. Based on this, the horizontal width and / or size of the sacrificial hard mask pattern 260 may be variously modified.

[0033] The sacrificial hard mask pattern 260 may include various materials that can function as an etching barrier during a subsequent etching process of the free layer 250 of FIG. 2C. In addition, the sacrificial hard mask pattern 260 may include a material that is easily removable, such as a photoresist that is easily removed by a strip process or a cleaning process.

[0034] 2C, the free layer 250 may be etched to a predetermined depth using the sacrificial hard mask pattern 260 as an etching barrier to form an initial free pattern 252. Here, the etching depth of the free layer 250 is less than the thickness of the free layer 250. Thus, a portion of the initial free pattern 252 overlapping with the sacrificial hard mask pattern 260 may have a first thickness T1, and a portion of the initial free pattern 252 exposed by the sacrificial hard mask pattern 260 may have a second thickness T2 less than the first thickness T1 and greater than 0. The first thickness T1 may be substantially the same as the thickness of the free layer 250.

[0035] 2D, after removing the sacrificial hard mask pattern 260, a hard mask layer 270 may be formed on the initial free pattern 252. The hard mask layer 270 is formed to cover the entire portion of the initial free pattern 252 having the first thickness T1 and the entire portion of the initial free pattern 252 having the second thickness T2.

[0036] Referring to FIG. 2E, the hard mask layer 270 may be patterned to form an initial hard mask pattern 272.

[0037] The initial hard mask pattern 272 functions as an etching barrier during an etching process of the initial free pattern 252, the tunnel barrier layer 240, and the fixed layer 230 for forming the magnetic tunnel junction pattern (see MTJ-A and MTJ-B in FIG. 2F) described later, and is formed to cover the region where these magnetic tunnel junction patterns are to be formed. Here, the horizontal width and / or size of the initial hard mask pattern 272 is smaller than that of the sacrificial hard mask pattern 260. Furthermore, the initial hard mask pattern 272 may function as a capping layer that remains after the etching process to protect the magnetic tunnel junction pattern on the magnetic tunnel junction pattern or improve the function of the magnetic tunnel junction pattern. The initial hard mask pattern 272 may include a conductive material. For example, the initial hard mask pattern 272 may include a metal, a conductive metal oxide, or a conductive metal nitride. The thickness of the initial hard mask pattern 272 on the portion of the initial free pattern 252 having the first thickness T1 is smaller than the thickness of the initial hard mask pattern 272 on the portion of the initial free pattern 252 having the second thickness T2.

[0038] 2F, the initial free pattern 252, the tunnel barrier layer 240, and the fixed layer 230 are etched using the initial hard mask pattern 272 as an etching barrier to form magnetic tunnel junction patterns MTJ-A and MTJ-B including free patterns 254A and 254B, tunnel barrier patterns 242A and 242B, and fixed patterns 232A and 232B. In this process, the initial hard mask pattern 272 may be partially lost to form hard mask patterns 274A and 274B.

[0039] Here, of the free patterns 254A and 254B, the one having the first thickness T1 is referred to as the first free pattern 254A, and the one having the second thickness T2 is referred to as the second free pattern 254B. In addition, of the tunnel barrier patterns 242A and 242B, the one overlapping with the first free pattern 254A is referred to as the first tunnel barrier pattern 242A, and the one overlapping with the second free pattern 254B is referred to as the second tunnel barrier pattern 242B. In addition, of the fixed patterns 232A and 232B, the one overlapping with the first free pattern 254A is referred to as the first fixed pattern 232A, and the one overlapping with the second free pattern 254B is referred to as the second fixed pattern 232B. The first free pattern 254A, the first tunnel barrier pattern 242A, and the first fixed pattern 232A can form the first magnetic tunnel junction pattern MTJ-A, and the second free pattern 254B, the second tunnel barrier pattern 242B, and the second fixed pattern 232B can form the second magnetic tunnel junction pattern MTJ-B. In addition, among the hard mask patterns 274A and 274B, the one overlapping with the first magnetic tunnel junction pattern MTJ-A is defined as the first hard mask pattern 274A, and the one overlapping with the second magnetic tunnel junction pattern MTJ-B is defined as the second hard mask pattern 274B.

[0040] The height of the top surface of the first hard mask pattern 274A and the height of the top surface of the second hard mask pattern 274B from the surface of the substrate 200 may be substantially the same. Because the first thickness T1 of the first free pattern 254A is greater than the second thickness T2 of the second free pattern 254B, the third thickness T3 of the first hard mask pattern 274A is smaller than the fourth thickness T4 of the second hard mask pattern 274B.

[0041] Referring to FIG. 2G, after forming an insulating material covering the process result of FIG. 2F, a planarization process may be performed until the top surfaces of the first and second hard mask patterns 274A and 274B are exposed, thereby forming a second interlayer insulating layer 280.

[0042] Next, a second conductive line 290 extending in a second direction may be formed on the first and second hard mask patterns 274A and 274B and the second interlayer insulating layer 280.

[0043] As a result, a semiconductor device as shown in FIG. 2G is manufactured.

[0044] Referring again to FIG. 2G, the semiconductor device of this embodiment may include a substrate 200, a plurality of first conductive lines 210 arranged on the substrate 200 and extending in a first direction, a plurality of second conductive lines 290 extending on the first conductive lines 210 in a direction intersecting the first conductive lines 210, and a selector pattern 220 and magnetic tunnel junction patterns MTJ-A and MJT-B overlapping with the intersection regions between the first conductive lines 210 and the second conductive lines 290, respectively.

[0045] The magnetic tunnel junction patterns MTJ-A, MTJ-B may include a first magnetic tunnel junction pattern MTJ-A including a first free pattern 254A having a first thickness T1 at its top, and a second magnetic tunnel junction pattern MTJ-B including a second free pattern 254B having a second thickness T2 at its top that is smaller than the first thickness T1.

[0046] A first hard mask pattern 274A having a third thickness T3 may be interposed between the first magnetic tunnel junction pattern MTJ-A and the second conductive line 290, and a second hard mask pattern 274B having a fourth thickness T4 larger than the third thickness T3 may be interposed between the second magnetic tunnel junction pattern MTJ-B and the second conductive line 290. The sum of the first thickness T1 and the third thickness T3 may be substantially equal to the sum of the second thickness T2 and the fourth thickness T4.

[0047] According to this embodiment, the first magnetic tunnel junction pattern MTJ-A includes the first free pattern 254A having a relatively large first thickness T1, and the second magnetic tunnel junction pattern MTJ-B includes the second free pattern 254B having a relatively small second thickness T2, so that the first magnetic tunnel junction pattern MTJ-A and the second magnetic tunnel junction pattern MTJ-B can have different characteristics. For example, the first magnetic tunnel junction pattern MTJ-A has a higher operating speed and lower power consumption than the second magnetic tunnel junction pattern MTJ-B, and the second magnetic tunnel junction pattern MTJ-B has a better data retention characteristic than the first magnetic tunnel junction pattern MTJ-A. As a result, a semiconductor device including the magnetic tunnel junction patterns MTJ-A and MTJ-B having different characteristics can be realized through a simple process.

[0048] 3A to 3F are cross-sectional views for explaining a semiconductor device and a manufacturing method thereof according to another embodiment of the present invention. These cross-sectional views are shown based on a cross section taken along line A-A' in FIG. 1A. Detailed descriptions of parts that are substantially the same as those in the above-mentioned embodiment will be omitted.

[0049] First, the manufacturing method will be described.

[0050] 3A, a first conductive line 310 extending in a first direction may be formed on a substrate 300. Although not shown, a plurality of the first conductive lines 310 may be arranged spaced apart and parallel to each other in a second direction passing through the cross section.

[0051] Next, the selector pattern 320 and the first interlayer insulating layer 325 filling the space between the selector patterns 320 may be formed on the first conductive lines 310 and the insulating material therebetween.

[0052] Referring to FIG. 3B, a magnetic tunnel junction layer including a fixed layer 330 , a tunnel barrier layer 340 , and a free layer 350 may be formed on the selector pattern 320 and the first interlayer insulating layer 325 .

[0053] Next, a sacrificial hard mask pattern 360 may be formed on the free layer 350. The sacrificial hard mask pattern 360 may be formed to cover at least a region where a first magnetic tunnel junction pattern (see MTJ-A' in FIG. 3E) to be described later is to be formed, and to expose at least a region where a second magnetic tunnel junction pattern (see MTJ-B' in FIG. 3E) to be described later is to be formed. Based on this, the horizontal width and / or size of the sacrificial hard mask pattern 360 may be variously modified.

[0054] The sacrificial hard mask pattern 360 may include various materials that function to prevent doping of the portion covered by the sacrificial hard mask pattern 360 during the subsequent doping process of Fig. 3C. In addition, the sacrificial hard mask pattern 360 may include a material that is easily removable, such as a photoresist that is easily removed by a stripping process or a cleaning process.

[0055] 3C, a doped layer 355 may be formed in the free layer 350 by doping a predetermined dopant using the sacrificial hard mask pattern 360 as a doping mask. The remaining portion of the free layer 350 excluding the doped layer 355 is hereinafter referred to as an initial free pattern 352.

[0056] Here, the doping depth and the thickness of the doped layer 355 formed thereby are smaller than the thickness of the free layer 350. Thus, the portion of the initial free pattern 352 overlapping with the sacrificial hard mask pattern 360 can have a first thickness T1', and the portion of the initial free pattern 352 located under the doped layer 355 by being exposed by the sacrificial hard mask pattern 360 can have a second thickness T2' smaller than the first thickness T1' and greater than 0. The first thickness T1' may be substantially the same as the thickness of the free layer 350.

[0057] The doping of the dopant is performed by an ion implantation process. The dopant may include an element that can cause the free layer 350 to lose magnetism while maintaining conductivity. Thus, the doping layer 355 may be formed of a material that includes the constituent elements of the free layer 350 and an element used as a dopant, and may be a magnetic loss region and a conductive region. As an example, the dopant may include an inert element such as Ar. Also, the doping layer 355 may be in an amorphous state.

[0058] 3D , after removing the sacrificial hard mask pattern 360, an initial hard mask pattern 370 may be formed on the initial free pattern 352 and the doping layer 355. Before the process of forming the initial hard mask pattern 370, a planarization process may be optionally further performed to ensure the flatness of the surfaces of the initial free pattern 352 and the doping layer 355.

[0059] The initial hard mask pattern 270 functions as an etching barrier during an etching process for forming magnetic tunnel junction patterns (see MTJ-A' and MTJ-B' in FIG. 3E) described later, and is formed to cover the area where the magnetic tunnel junction patterns are to be formed. Furthermore, it can function as a capping layer that remains after the etching process to protect the magnetic tunnel junction patterns on the magnetic tunnel junction patterns or improve the function of the magnetic tunnel junction patterns. The initial hard mask pattern 270 may be located on a portion of the initial free pattern 352 having a first thickness T1 and the doping layer 355, and can have a substantially constant thickness.

[0060] 3F, the doping layer 355, the initial free pattern 352, the tunnel barrier layer 340, and the fixed layer 330 are etched using the initial hard mask pattern 270 as an etching barrier to form magnetic tunnel junction patterns MTJ-A' and MTJ-B' including free patterns 354A and 354B, tunnel barrier patterns 342A and 342B, and fixed patterns 332A and 332B. In this process, the initial hard mask pattern 370 may be partially lost to form hard mask patterns 372A and 372B.

[0061] Here, of the free patterns 354A and 354B, the one having the first thickness T1' is referred to as the first free pattern 354A, and the one having the second thickness T2' is referred to as the second free pattern 354B. In addition, of the tunnel barrier patterns 342A and 342B, the one overlapping with the first free pattern 354A is referred to as the first tunnel barrier pattern 342A, and the one overlapping with the second free pattern 354B is referred to as the second tunnel barrier pattern 342B. In addition, of the fixed patterns 332A and 332B, the one overlapping with the first free pattern 354A is referred to as the first fixed pattern 332A, and the one overlapping with the second free pattern 354B is referred to as the second fixed pattern 332B. The first free pattern 354A, the first tunnel barrier pattern 342A, and the first fixed pattern 332A can form a first magnetic tunnel junction pattern MTJ-A', and the second free pattern 354B, the second tunnel barrier pattern 342B, and the second fixed pattern 332B can form a second magnetic tunnel junction pattern MTJ-B'. In addition, among the hard mask patterns 372A and 372B, one that overlaps with the first magnetic tunnel junction pattern MTJ-A' is defined as a first hard mask pattern 372A, and one that overlaps with the second magnetic tunnel junction pattern MTJ-B' is defined as a second hard mask pattern 372B. The first free pattern 354A and the first hard mask pattern 372A can be in direct contact with each other. In contrast, a doping pattern 357 may be interposed between the second free pattern 354B and the second hard mask pattern 372B. The doping pattern 357 is in a magnetic loss state and has conductivity, so that it can provide an electrical connection between the second free pattern 354B and the second hard mask pattern 372B. In addition, since the doping pattern 357 has an amorphous state, even if the doping pattern 357 is disposed on the second free pattern 354B, it does not adversely affect the properties of the second free pattern 354B, such as the perpendicular magnetic anisotropy.

[0062] Referring to FIG. 3F, after forming an insulating material covering the process result of FIG. 3E, a planarization process may be performed until the top surfaces of the first and second hard mask patterns 372A and 372B are exposed, thereby forming a second interlayer insulating layer 380.

[0063] Next, a second conductive line 390 extending in a second direction may be formed on the first and second hard mask patterns 372A and 372B and the second interlayer insulating layer 380.

[0064] As a result, a semiconductor device as shown in FIG. 3F is manufactured.

[0065] Referring again to FIG. 3F, the semiconductor device of this embodiment may include a substrate 300, a plurality of first conductive lines 310 arranged on the substrate 300 and extending in a first direction, a plurality of second conductive lines 390 extending on the first conductive lines 310 in a direction intersecting the first conductive lines 310, and a selector pattern 320 and magnetic tunnel junction patterns MTJ-A' and MJT-B' overlapping with the intersection regions between the first conductive lines 310 and the second conductive lines 390.

[0066] The magnetic tunnel junction patterns MTJ-A' and MTJ-B' may include a first magnetic tunnel junction pattern MTJ-A' including a first free pattern 354A having a first thickness T1' at its top, and a second magnetic tunnel junction pattern MTJ-B' including a second free pattern 354B having a second thickness T2' at its top that is smaller than the first thickness T1'.

[0067] A first and a second hard mask pattern 372A and 372B may be interposed between the first magnetic tunnel junction pattern MTJ-A' and the second conductive line 390 and between the second magnetic tunnel junction pattern MTJ-B' and the second conductive line 390, respectively. Furthermore, a doping pattern 357 may be further interposed between the second magnetic tunnel junction pattern MTJ-B' and the second hard mask pattern 372B. The doping pattern 357 may have non-magnetic and conductive properties while including the constituent elements of the free patterns 354A and 354B and a dopant. The sum of the second thickness T2' of the second free pattern 354B and the thickness of the doping pattern 357 may be substantially the same as the first thickness T1' of the first free pattern 354A.

[0068] In this embodiment as well, it is possible to realize a semiconductor device including magnetic tunnel junction patterns MTJ-A' and MTJ-B' having different characteristics through a simple process.

[0069] 4A to 4E are cross-sectional views for explaining a semiconductor device and a manufacturing method thereof according to another embodiment of the present invention. The cross-sectional views are shown based on a cross section taken along line A-A' in FIG. 1A. Detailed descriptions of parts that are substantially the same as those in the above-described embodiment will be omitted.

[0070] First, the manufacturing method will be described.

[0071] 4A, a first conductive line 410 extending in a first direction may be formed on a substrate 400. Although not shown, a plurality of the first conductive lines 410 may be arranged spaced apart and parallel to each other in a second direction passing through the cross section.

[0072] Next, the selector pattern 420 and the first interlayer insulating layer 425 filling the space between the selector patterns 420 may be formed on the first conductive lines 410 and the insulating material therebetween.

[0073] Next, a magnetic tunnel junction layer including a fixed layer 430, a tunnel barrier layer 440, and a free layer is formed on the selector pattern 420 and the first interlayer insulating layer 425, and a sacrificial hard mask pattern 460 is formed on the free layer. The sacrificial hard mask pattern 460 is then used as an etching barrier to etch the free layer to a predetermined depth, thereby forming an initial free pattern 452. The sacrificial hard mask pattern 460 is formed to cover at least a region where a first magnetic tunnel junction pattern (see MTJ-A″ in FIG. 4D ) described later is formed, while exposing at least a region where a second magnetic tunnel junction pattern (see MTJ-B″ in FIG. 4D ) described later is formed. A portion of the initial free pattern 452 overlapping with the sacrificial hard mask pattern 460 may have a first thickness T1″, and a portion of the initial free pattern 452 exposed by the sacrificial hard mask pattern 460 may have a second thickness T2″ smaller than the first thickness T1″ and larger than 0.

[0074] Next, a metal oxide layer 462 may be formed on the initial free pattern 452 and the sacrificial hard mask pattern 460 along a lower profile. The metal oxide layer 462 may be deposited by various deposition methods and may include a non-magnetic metal element and oxygen. As an example, the non-magnetic metal element of the metal oxide layer 462 may include at least one of Ta, Ti, Mg, Hf, Zr, W, and Mo. The metal oxide layer 462 may have a thickness equal to or greater than the difference between the first thickness T1″ and the second thickness T2″. In addition, the metal oxide layer 462 may have a conductive property.

[0075] Referring to FIG. 4B , a planarization process, for example, CMP, may be performed so that the upper surface of the portion of the initial free pattern 452 having the first thickness T1″ is exposed. As a result of this process, the sacrificial hard mask pattern 460 and the metal oxide layer 462 on the upper surface and sidewalls of the sacrificial hard mask pattern 460 are removed, and the metal oxide layer 462 on the portion of the initial free pattern 452 having the second thickness T2″ may remain to form an initial metal oxide pattern 464. The upper surface of the portion of the initial free pattern 452 having the first thickness T1″ and the upper surface of the initial metal oxide pattern 464 may be located at substantially the same height.

[0076] Referring to FIG. 4C, an initial hard mask pattern 470 may be formed on the initial free pattern 452 and the initial metal oxide pattern 464.

[0077] The initial hard mask pattern 470 functions as an etching barrier during an etching process for forming magnetic tunnel junction patterns (see MTJ-A″ and MTJ-B″ in FIG. 4D ) described below, and is formed to cover the area where these magnetic tunnel junction patterns are to be formed. Furthermore, it may remain after the etching process and function as a capping layer on the magnetic tunnel junction pattern to protect the magnetic tunnel junction pattern or improve the function of the magnetic tunnel junction pattern. The initial hard mask pattern 470 may be located on a portion of the initial free pattern 452 having a first thickness T1″ and the initial metal oxide pattern 464, and may have a substantially constant thickness.

[0078] 4D, the initial metal oxide pattern 464, the initial free pattern 452, the tunnel barrier layer 440, and the fixed layer 430 can be etched using the initial hard mask pattern 470 as an etching barrier to form magnetic tunnel junction patterns MTJ-A″, MTJ-B″ including free patterns 454A, 454B, tunnel barrier patterns 442A, 442B, and fixed patterns 432A, 432B. In this process, the initial hard mask pattern 470 can be partially lost to form hard mask patterns 472A, 472B.

[0079] Here, of the free patterns 454A, 454B, one having the first thickness T1" is referred to as a first free pattern 454A, and one having the second thickness T2" is referred to as a second free pattern 454B. Additionally, of the tunnel barrier patterns 442A, 442B, one that overlaps with the first free pattern 454A is referred to as a first tunnel barrier pattern 442A, and one that overlaps with the second free pattern 454B is referred to as a second tunnel barrier pattern 442B. Additionally, of the fixed patterns 432A, 432B, one that overlaps with the first free pattern 454A is referred to as a first fixed pattern 432A, and one that overlaps with the second free pattern 454B is referred to as a second fixed pattern 432B. The first free pattern 454A, the first tunnel barrier pattern 442A, and the first fixed pattern 432A may form a first magnetic tunnel junction pattern MTJ-A'', and the second free pattern 454B, the second tunnel barrier pattern 442B, and the second fixed pattern 432B may form a second magnetic tunnel junction pattern MTJ-B''. In addition, among the hard mask patterns 472A and 472B, one overlapping with the first magnetic tunnel junction pattern MTJ-A'' is defined as a first hard mask pattern 472A, and one overlapping with the second magnetic tunnel junction pattern MTJ-B'' is defined as a second hard mask pattern 472B. The first free pattern 454A and the first hard mask pattern 472A may be in direct contact with each other. In contrast, a metal oxide pattern 466 may be interposed between the second free pattern 454B and the second hard mask pattern 472B. The metal oxide pattern 466 has conductivity and can provide an electrical connection between the second free pattern 454B and the second hard mask pattern 472B. Furthermore, the metal oxide pattern 466 can bond with the second free pattern 454B to improve the perpendicular magnetic anisotropy of the second free pattern 454B. The perpendicular magnetic anisotropy can be caused by a bond between a metal element, for example, iron (Fe), of the second free pattern 454B and oxygen of the metal oxide pattern 466.

[0080] Referring to FIG. 4E, after forming an insulating material covering the process result of FIG. 4D, a planarization process may be performed until the top surfaces of the first and second hard mask patterns 472A and 472B are exposed, thereby forming a second interlayer insulating layer 480.

[0081] Next, a second conductive line 490 extending in a second direction may be formed on the first and second hard mask patterns 472A and 472B and the second interlayer insulating layer 480.

[0082] As a result, a semiconductor device as shown in FIG. 4E is manufactured.

[0083] Referring again to FIG. 4E, the semiconductor device of the present embodiment may include a substrate 400, a plurality of first conductive lines 410 arranged on the substrate 400 and extending in a first direction, a plurality of second conductive lines 490 extending on the first conductive lines 410 in a direction intersecting the first conductive lines 410, and a selector pattern 420 and magnetic tunnel junction patterns MTJ-A″, MJT-B″ overlapping the intersection regions between the first conductive lines 410 and the second conductive lines 490.

[0084] The magnetic tunnel junction patterns MTJ-A'', MTJ-B'' may include a first magnetic tunnel junction pattern MTJ-A'' including a first free pattern 454A having a first thickness T1'' at its top, and a second magnetic tunnel junction pattern MTJ-B'' including a second free pattern 454B having a second thickness T2'' at its top that is smaller than the first thickness T1''.

[0085] A first and a second hard mask pattern 472A, 472B may be interposed between the first magnetic tunnel junction pattern MTJ-A″ and the second conductive line 490 and between the second magnetic tunnel junction pattern MTJ-B″ and the second conductive line 490, respectively. Furthermore, a metal oxide pattern 466 may be further interposed between the second magnetic tunnel junction pattern MTJ-B″ and the second hard mask pattern 472B. The metal oxide pattern 466 is conductive and can further improve the perpendicular magnetic anisotropy of the second free pattern 454B. The sum of the second thickness T2″ of the second free pattern 454B and the thickness of the metal oxide pattern 466 may be substantially the same as the first thickness T1″ of the first free pattern 454A.

[0086] In this embodiment as well, it is possible to realize a semiconductor device including magnetic tunnel junction patterns MTJ-A'', MTJ-B'' having different characteristics through a simple process.

[0087] Although the technical concept of the present invention has been specifically recorded in the above preferred embodiment, it should be noted that the above embodiment is for the purpose of explanation and not for the purpose of limiting the present invention, and a person skilled in the art of the present invention can understand that various embodiments are possible within the scope of the technical concept of the present invention. [Explanation of symbols]

[0088] 200: Substrate 210: First conductive line 220: Selector Pattern 232A, 232B: Fixed pattern 242A, 242B: Tunnel barrier pattern 252A, 252B: Free pattern MTJ-A, MTJ-B: Magnetic tunnel junction patterns 274A, 274B: Hard mask pattern 290: Second conductive line

Claims

1. A substrate; a first magnetic tunnel junction pattern disposed on the substrate and including a first free pattern; a second magnetic tunnel junction pattern disposed on the substrate, the second magnetic tunnel junction pattern including a second free pattern having a thickness smaller than that of the first free pattern; a first hard mask pattern on the first free pattern; a second hard mask pattern on the second free pattern; a doping pattern having conductivity and interposed between the second free pattern and the second hard mask pattern. Semiconductor device.

2. the first free pattern and the first hard mask pattern are in direct contact with each other; The semiconductor device according to claim 1 .

3. the doped pattern includes a constituent element of the first free pattern and a dopant that causes the first free pattern to lose magnetism; The semiconductor device according to claim 1 .

4. The dopant includes an inert element. The semiconductor device according to claim 3 .

5. The doping pattern has an amorphous state. The semiconductor device according to claim 1 .

6. a thickness of the first free pattern is equal to a sum of a thickness of the second free pattern and a thickness of the doping pattern; The semiconductor device according to claim 1 .

7. a plurality of first conductive lines disposed on the substrate and extending in a first direction; a plurality of second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction; a stacked structure of the first magnetic tunnel junction pattern and the first hard mask pattern is disposed between the first conductive line and the second conductive line so as to overlap any one of the crossing regions thereof; the stacked structure of the second magnetic tunnel junction pattern, the doping pattern, and the second hard mask pattern is disposed between the first conductive line and the second conductive line so as to overlap with another one of the intersection regions thereof; The semiconductor device according to claim 1 .

8. a selector pattern disposed between the first conductive line and the first magnetic tunnel junction pattern and between the first conductive line and the second magnetic tunnel junction pattern, The semiconductor device according to claim 7.

9. A substrate; a first magnetic tunnel junction pattern disposed on the substrate and including a first free pattern; a second magnetic tunnel junction pattern disposed on the substrate, the second magnetic tunnel junction pattern including a second free pattern having a thickness smaller than that of the first free pattern; a first hard mask pattern on the first free pattern; a second hard mask pattern on the second free pattern; The first hard mask pattern has a thickness smaller than that of the second hard mask pattern. Semiconductor device.

10. a sum of a thickness of the first free pattern and a thickness of the first hard mask pattern is equal to a sum of a thickness of the second free pattern and a thickness of the second hard mask pattern; The semiconductor device according to claim 9.

11. a plurality of first conductive lines disposed on the substrate and extending in a first direction; a plurality of second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction; a stacked structure of the first magnetic tunnel junction pattern and the first hard mask pattern is disposed between the first conductive line and the second conductive line so as to overlap any one of the crossing regions thereof; the stacked structure of the second magnetic tunnel junction pattern and the second hard mask pattern is disposed between the first conductive line and the second conductive line so as to overlap with another one of the intersection regions thereof; The semiconductor device according to claim 9.

12. a selector pattern disposed between the first conductive line and the first magnetic tunnel junction pattern and between the first conductive line and the second magnetic tunnel junction pattern, The semiconductor device according to claim 11.

13. forming a magnetic tunnel junction layer including a pinned layer, a tunnel barrier layer, and a free layer on a substrate; forming a sacrificial hard mask pattern on the free layer, covering at least a region where a first magnetic tunnel junction pattern is to be formed, and exposing at least a region where a second magnetic tunnel junction pattern is to be formed; doping the free layer exposed by the sacrificial hard mask pattern with a dopant that causes the free layer to lose magnetism to form a doped region having a thickness smaller than a thickness of the free layer; removing the sacrificial hard mask pattern; forming a hard mask pattern on the free layer and the doped region to cover an area where the first magnetic tunnel junction pattern is to be formed and an area where the second magnetic tunnel junction pattern is to be formed; and etching the doped region, the free layer, the tunnel barrier layer, and the fixed layer. A method for manufacturing a semiconductor device.

14. The dopant includes an inert element. The method for manufacturing a semiconductor device according to claim 13.

15. The doped region has an amorphous state. The method for manufacturing a semiconductor device according to claim 13.

16. the first magnetic tunnel junction pattern includes the pinned layer, the tunnel barrier layer, and the free layer; the second magnetic tunnel junction pattern includes the pinned layer, the tunnel barrier layer, the free layer, and the doping region; The method for manufacturing a semiconductor device according to claim 13.

17. forming a magnetic tunnel junction layer including a pinned layer, a tunnel barrier layer, and a free layer on a substrate; forming a sacrificial hard mask pattern on the free layer, covering at least a region where a first magnetic tunnel junction pattern is to be formed, and exposing at least a region where a second magnetic tunnel junction pattern is to be formed; Etching the free layer exposed by the sacrificial hard mask pattern to reduce its thickness; removing the sacrificial hard mask pattern; forming a hard mask pattern on the free layer to cover an area where the first magnetic tunnel junction pattern is to be formed and an area where the second magnetic tunnel junction pattern is to be formed; and etching the free layer, the tunnel barrier layer, and the fixed layer using the hard mask pattern. A method for manufacturing a semiconductor device.

18. a thickness of the free layer of the first magnetic tunnel junction pattern is greater than a thickness of the free layer of the second magnetic tunnel junction pattern; a thickness of the hard mask pattern on the first magnetic tunnel junction pattern is smaller than a thickness of the hard mask pattern on the second magnetic tunnel junction pattern; The method for manufacturing a semiconductor device according to claim 17.

19. forming a magnetic tunnel junction layer including a pinned layer, a tunnel barrier layer, and a free layer on a substrate; forming a sacrificial hard mask pattern on the free layer, covering at least a region where a first magnetic tunnel junction pattern is to be formed, and exposing at least a region where a second magnetic tunnel junction pattern is to be formed; Etching the free layer exposed by the sacrificial hard mask pattern to reduce its thickness; forming a metal oxide layer over the sacrificial hardmask pattern and the free layer; removing the sacrificial hardmask pattern and the metal oxide layer formed on the sidewalls and top surface of the sacrificial hardmask pattern to form a metal oxide pattern; forming a hard mask pattern on the free layer and the metal oxide pattern to cover an area where the first magnetic tunnel junction pattern is to be formed and an area where the second magnetic tunnel junction pattern is to be formed; and etching the free layer, the tunnel barrier layer, and the fixed layer using the hard mask pattern. A method for manufacturing a semiconductor device.

20. the first magnetic tunnel junction pattern includes the pinned layer, the tunnel barrier layer, and the free layer; the second magnetic tunnel junction pattern includes the pinned layer, the tunnel barrier layer, the free layer, and the metal oxide pattern; The method for manufacturing a semiconductor device according to claim 19.

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