Substrate and method for manufacturing the same

Abstract

To provide a substrate that has entirely uniformly improved adhesive strength and can transmit signals efficiently even when high-frequency power is applied and embodies an electrically conductive layer, and a method for manufacturing the same.SOLUTION: A substrate 100 includes a glass core 10 having an upper surface 11. The upper surface of the glass core has an Rs / z value which is a value of the rate of the degree of asymmetry to the roughness in the following formula 1 and ranges from -5 nm-2 to 50 nm-2. In formula 1, the Rsk value is the degree of asymmetry, and the Rz value is the maximum height roughness (nm in unit). Such a substrate can embody an electrically conductive layer having substantially uniformly improved adhesion force to a glass core. The electrically conductive layer can transmit signals efficiently even when high frequency power is applied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The embodiment relates to a substrate and a manufacturing method thereof. [Background technology]

[0002] In manufacturing electronic components, the process of creating circuits on a semiconductor wafer is called the front-end process (FE: Front-End), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE: Back-End), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, over 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections, rather than the performance of the semiconductor technology itself.

[0004] The packaging substrate is made of ceramic or resin. Since the ceramic substrate has a high resistance or a high dielectric constant, it is not easy to mount a high-performance, high-frequency semiconductor element on it. Although a resin substrate can mount a relatively high-performance, high-frequency semiconductor element, there is a limit to how much the wiring pitch can be reduced.

[0005] Recently, research has been conducted into the application of silicon and glass to high-end packaging substrates. By forming through holes in silicon or glass substrates and filling the through holes with conductive materials, the length of the wiring between the device and the motherboard can be shortened, resulting in excellent electrical characteristics. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2014-201446 [Patent Document 2] International Patent Publication No. 2018 / 221379 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the embodiment is to provide a substrate and a manufacturing method thereof that can realize an electrically conductive layer that is substantially uniform and has improved adhesion and can efficiently transmit signals even when high frequency power is applied. [Means for solving the problem]

[0008] The substrate according to one embodiment of the present specification includes a glass core having an upper surface, the upper surface of the glass core having a ratio of the asymmetry degree to the roughness of the following formula 1, R s / z Value is -5nm -2 ~50nm -2 It is.

[0009] JPEG2025036113000002.jpg1594

[0010] In the above formula 1, the Rsk value is the value of the asymmetry degree, and the Rz value is the maximum height roughness (unit: nm).

[0011] The Rsk value may be in the range of −0.5 to 1.8.

[0012] The Rz value may be from 3 nm to 30 nm.

[0013] The top surface of the glass core can include a total of three arbitrarily selected measurement areas.

[0014] The standard deviation of the Rsk values ​​in each of the measurement regions may be 0.5 or less.

[0015] The standard deviation of the Rz values ​​in each of the measurement regions may be 1.5 nm or less.

[0016] The substrate can include an electrically conductive layer disposed on the glass core.

[0017] The electrically conductive layer can include a seed layer and a conductive layer disposed on the seed layer.

[0018] The seed layer may have a thickness of 50 nm to 1500 nm.

[0019] The electrically conductive layer may have a patterned shape.

[0020] The width of the electrically conductive layer may be from 1 μm to 5 μm.

[0021] The electrically conductive layer may have a thickness of 1 μm to 5 μm.

[0022] The electrically conductive layer may include a first electrically conductive layer formed on a top surface of the glass core.

[0023] When observed in a cross section of the first electrically conductive layer, the Rz value which is the maximum height roughness of the interface formed between the first electrically conductive layer and the glass core may be 5 nm to 200 nm.

[0024] The bonding strength between the first electrically conductive layer and the glass core measured by a 180° peel test may be 0.2 kgf to 3 kgf.

[0025] The substrate may have a semiconductor packaging application.

[0026] A method for manufacturing a substrate according to another embodiment of the present specification includes a preparation step of providing a base glass plate, and a roughening step of providing a substrate including a glass core formed by roughening the upper surface of the base glass plate.

[0027] The glass core has a top surface.

[0028] R is the ratio of the asymmetry to the roughness of the upper surface of the glass core according to the following formula 1. s / z Value is -5nm -2 ~50nm -2 It is.

[0029] JPEG2025036113000003.jpg1594

[0030] In the above formula 1, the Rsk value is the value of the asymmetry degree, and the Rz value is the maximum height roughness (unit: nm).

[0031] The roughening step may include a process of plasma treating the upper surface of the base glass plate to form a glass core. Effect of the Invention

[0032] In accordance with an embodiment of the present invention, a substrate may provide an electrically conductive layer having substantially uniformly improved adhesion to a glass core, and the electrically conductive layer may efficiently transmit signals even when high frequency power is applied thereto. [Brief description of the drawings]

[0033] [Figure 1] FIG. 1 is a plan view illustrating a substrate according to an embodiment of the present specification. [Diagram 2] FIG. 11 is a plan view illustrating a substrate according to another embodiment of the present specification. [Diagram 3] FIG. 13 is a plan view illustrating a substrate according to still another embodiment of the present specification. [Figure 4] FIG. 13 is a plan view illustrating a substrate according to still another embodiment of the present specification. BEST MODE FOR CARRYING OUT THEINVENTION

[0034] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. However, the present invention may be embodied in various different forms and is not limited to the preferred embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0035] Throughout this specification, the term "combinations thereof" in a Markush form phrase is intended to mean a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, including one or more selected from the group of elements.

[0036] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish identical terms from one another, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0037] In this specification, the term "-" may mean that the compound includes a compound that corresponds to "-" or a derivative of "-".

[0038] In this specification, the term "B is located on A" means that B is located on A in direct contact therewith, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0039] In this specification, the expression "B is linked to A" means that A and B are directly linked, or that A and B are linked via another component between them, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0040] In this specification, the term "singular" is to be construed as including the singular or plural as the context requires, unless otherwise specified.

[0041] In this specification, the shape, relative size, angle, etc. of each component in the drawings are illustrative and may be exaggerated for the purpose of explanation, and the rights should not be interpreted as being limited to the drawings.

[0042] In this specification, "A and B are adjacent" means that A and B are adjacent to each other, or A and B are not adjacent to each other but are located close to each other. In this specification, the expression "A and B are adjacent to each other" is not limited to being adjacent to each other unless otherwise specified.

[0043] In this specification, high frequency means a frequency of about 1 GHz to about 300 GHz. Specifically, it may mean a frequency of about 1 GHz to about 30 GHz, or may mean a frequency of about 1 GHz to about 15 GHz.

[0044] In this specification, unless otherwise specified, a fine line means a line having a width of 5 μm or less, and illustratively means a line having a width of 1 to 4 μm or less.

[0045] The inventors of the embodiment confirmed that by controlling the surface roughness characteristics of the glass core, the electrically conductive layer has a substantially uniformly improved adhesive strength to the glass core, and that the electrically conductive layer can efficiently transmit signals by suppressing an excessive increase in resistance of the electrically conductive layer when high frequency power is applied, thereby completing the embodiment.

[0046] Hereinafter, the embodiment will be described in detail.

[0047] 1 is a plan view illustrating a substrate according to an embodiment of the present disclosure, the substrate of the embodiment will be described with reference to FIG.

[0048] Glass Core Substrate 100 according to one embodiment of the present disclosure includes a glass core 10 having a top surface 11 .

[0049] The glass core 10 serves as a support in the substrate 100. The glass core 10 is separate from a core distribution layer (not shown) or a bump (not shown) disposed above or below the glass core 10.

[0050] In the embodiment, by using a core made of a glass material, it is possible to suppress the generation of parasitic elements and power loss in the core due to the application of high frequency power.

[0051] The material of the glass core 10 may be, for example, an alkali borosilicate, an alkali-free borosilicate, an alkali-free alkaline earth borosilicate, or the like, and any sheet glass material suitable for electronic components may be used.

[0052] The thickness of the glass core 10 may be 50 μm or more. The thickness may be 100 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. When a glass core 10 having such a thickness is used, it can be highly usable as a core for semiconductor packaging.

[0053] R is the ratio of the asymmetry to the roughness of the upper surface 11 of the glass core according to the following formula 1. s / z Value is -5nm -2 ~50nm -2 It is.

[0054] JPEG2025036113000004.jpg1594

[0055] In the above formula 1, the Rsk value is the value of the asymmetry degree, and the Rz value is the maximum height roughness (unit: nm).

[0056] If the roughness of the upper surface 11 of the glass core is simply increased in order to improve the bonding strength of the electrically conductive layer formed on the upper surface 11 of the glass core, the height deviation of the metal layer deposited on the upper surface of the core may become excessively large, or the contact area between the upper surface of the core and the electrically conductive layer may decrease, resulting in a problem that the electrically conductive layer formed on the upper surface exhibits an overall non-uniform bonding strength.

[0057] In addition, the electrical conductive layer formed on the upper surface 11 of the glass core having the above characteristics may have excessively high resistance in an environment where high frequency power is supplied. Specifically, when high frequency power is applied to the substrate 100 to improve the signal transmission speed and amount, a skin effect may occur in the electrical conductive layer. As a result, current may flow concentratedly in the surface portion of the electrical conductive layer.

[0058] When an electrically conductive layer is formed on the upper surface 11 of a glass core having excessive roughness, the cross-sectional profile of the electrically conductive layer may be rough and have an irregular shape. When a high-frequency current flows through an electrically conductive layer having such a shape, the area through which the current can actually flow within the electrically conductive layer is reduced, and the resistance of the electrically conductive layer may become significantly high. The degree of increase in the resistance of the electrically conductive layer due to the skin effect may become even greater as the electrically conductive layer becomes thinner.

[0059] In the embodiment, the ratio of the asymmetry to the roughness of the upper surface 11 of the glass core is R s / z In this case, the roughness of the upper surface 11 of the glass core is not excessively increased on the glass core 10, and a more stable interlocking structure is formed between the glass core 10 and the electrically conductive layer over the entire upper surface 11 of the glass core, thereby effectively improving the bonding strength of the electrically conductive layer. In addition, the substrate 100 having the above characteristics can efficiently transmit signals without excessive heat generation even when high frequency power is applied.

[0060] R s / zThe value is measured by the following method.

[0061] A total of three measurement regions (not shown) are identified that are arbitrarily selected on the upper surface 11 of the glass core. The measurement regions are 5 μm wide and 5 μm long, and the measurement regions are selected so as not to overlap each other.

[0062] In each of the measurement regions, the Rsk value, which is a value of the degree of asymmetry, and the Rz value, which is the maximum height roughness, are measured in a non-contact mode using an atomic force microscope in accordance with the method defined in ISO 4287. For example, the XE-100 model of Park Systems Inc. can be used as the atomic force microscope.

[0063] The average value of the Rsk values ​​of the respective measurement regions is defined as the Rsk value of the upper surface of the glass core, and the average value of the Rz values ​​of the respective measurement regions is defined as the Rz value of the upper surface of the glass core.

[0064] From the calculated Rsk and Rz values ​​of the upper surface of the glass core, R in Eq. s / z Calculate the value.

[0065] R of the top surface of the glass core 11 s / z The value is -5 nm -2 ~50nm -2 The R s / z The value is -3 nm -2 The R s / z The value is 0 nm -2 The R s / z The value is 5 nm -2 The R s / z The value is 45 nm -2 The R may be the following: s / z The value is 40 nm -2 The R may be the following: s / z The value is 30 nm -2 The R may be the following: s / z The value is 20 nm -2 The R may be the following: s / z The value is 15 nm-2 In this case, when forming a thinned electrically conductive layer on the glass core 10, the bonding strength of the electrically conductive layer to the glass core 10 can be substantially uniformly improved over the entire region of the upper surface 11 of the glass core, and the resistance of the electrically conductive layer can be prevented from becoming excessively high when high-frequency power is applied.

[0066] In the surface profile, a peak is a portion located higher than a reference line (average height of the surface profile), and a valley is a portion located lower than the reference line. In the embodiment, the asymmetry Rsk value of the upper surface 11 of the glass core is adjusted within a range preset in the embodiment, thereby controlling the shape and height distribution of the peaks and valleys distributed on the upper surface 11 of the glass core. When the glass core 10 has the above characteristics, it is possible to prevent the peaks and valleys from being relatively narrow and sharp in the profile of the upper surface 11 of the glass core. As a result, the surface area of ​​the contact between the upper surface 11 of the glass core and the metal layer deposited on the upper surface 11 is appropriately adjusted, so that the metal layer can have a stable bonding force. In addition, a metal layer having a more uniform height distribution can be formed on the upper surface 11 of the glass core.

[0067] The Rsk value of the upper surface 11 of the glass core may be -0.5 to 1.8. The Rsk value may be -0.2 or more. The Rsk value may be 0 or more. The Rsk value may be 0.2 or more. The Rsk value may be 1.5 or less. The Rsk value may be 1.2 or less. The Rsk value may be 1.0 or less. The Rsk value may be 0.8 or less. The Rsk value may be 0.6 or less. In such a case, by adjusting the shape of the lower surface of the electrically conductive layer in contact with the upper surface of the glass core, smooth signal transmission is possible even if a skin effect occurs in the electrically conductive layer.

[0068] The Rz value of the upper surface 11 of the glass core may be 4 nm to 30 nm. The Rz value may be 5 nm or more. The Rz value may be 20 nm or less. The Rz value may be 10 nm or less. In such a case, the peel resistance of the electrically conductive layer with respect to the surface of the glass core 10 can be stably adjusted. At the same time, even if high-frequency power is applied to the electrically conductive layer, the resistance characteristic of the electrically conductive layer can be prevented from becoming excessively high.

[0069] The embodiment may help to ensure that the adhesive strength and resistance characteristics of the electrically conductive layer formed on the glass core 10 are uniform across the entire top surface 11 of the glass core by controlling the deviation in the roughness characteristics of multiple different regions.

[0070] The standard deviation of the Rsk values ​​in each of the measurement regions may be 0.5 or less.

[0071] The standard deviation of the Rz values ​​in each of the measurement regions may be 1.5 nm or less.

[0072] The standard deviation is the sample standard deviation.

[0073] The standard deviation of the Rsk values ​​of each measurement region may be 0.5 or less. The standard deviation may be 0.4 or less. The standard deviation may be 0.3 or less. The standard deviation may be 0.2 or less. The standard deviation may be 0.001 or more.

[0074] The standard deviation of the Rz values ​​of each measurement region may be 1.5 nm or less. The standard deviation may be 1 nm or less. The standard deviation may be 0.5 nm or less. The standard deviation may be 0.3 nm or less. The standard deviation may be 0.15 nm or less. The standard deviation may be 0.08 nm or less. The standard deviation may be 0.001 nm or more.

[0075] In such a case, a generally uniform roughness profile can be formed on the top surface 11 of the glass core.

[0076] The lower surface of the glass core may have the same roughness characteristics as the above-mentioned upper surface 11 of the glass core. In this case, an electrically conductive layer having an improved bonding strength uniformly overall may be formed on the lower surface of the glass core, and the electrically conductive layer may transmit signals efficiently by applying high frequency power.

[0077] The description of the roughness characteristics of the lower surface of the glass core is omitted here since it overlaps with the above description.

[0078] Core Distribution Layer 2 is a plan view illustrating a substrate according to another embodiment of the present disclosure, and the substrate according to the embodiment will be described with reference to FIG.

[0079] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described above with reference to Fig. 1. The following description will focus on the differences.

[0080] The substrate of the embodiment may include an electrically conductive layer 20 disposed on the glass core. The electrically conductive layer 20 may have a pattern shape. The electrically conductive layer 20 may be formed above and / or below the glass core 10 and may perform a function of transmitting signals.

[0081] The width of the electrically conductive layer 20 may be between 1 μm and 5 μm. The width may be 4.5 μm or less. The width may be 4 μm or less.

[0082] The thickness of the electrically conductive layer 20 may be between 1 μm and 5 μm. The thickness may be 4.5 μm or less. The thickness may be 4 μm or less.

[0083] In this case, a high density pattern of the electrically conductive layer 20 can be implemented on the substrate 100, which can help the electrically conductive layer 20 to have stable resistance characteristics at high frequency currents.

[0084] 3 is a plan view illustrating a substrate according to still another embodiment of the present disclosure, and a substrate according to the embodiment will be described with reference to FIG.

[0085] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described above with reference to Figures 1 and 2. The following description will focus on the differences.

[0086] The electrically conductive layer 20 may include a seed layer 21 and a conductive layer 22 disposed on the seed layer 21 .

[0087] The seed layer 21 can exhibit a certain level or more of bonding strength to the surface to be bonded (particularly, the upper surface 11 of the glass core). The conductive layer 22 can be stably bonded to the surface of the glass core 10 via the seed layer 21.

[0088] The seed layer 21 may include an element different from the metal element applied to the conductive layer. The seed layer 21 may include both the metal element applied to the conductive layer and a metal element different from the metal element. The seed layer 21 may include a first seed layer (not shown) including an element different from the metal element applied to the conductive layer, and a second seed layer (not shown) disposed on the first seed layer and including the same element as the metal element applied to the conductive layer. Exemplarily, the first seed layer may include a material such as titanium, chromium, or nickel, and the second seed layer may include a material such as copper, nickel, aluminum, gold, or silver.

[0089] At least a portion of the seed layer 21 may be formed through a sputtering process. The seed layer 21 may help facilitate the formation of the conductive layer 22 on the glass core 10.

[0090] In the embodiment, by adjusting the thickness of the seed layer 21, a structure in which the upper surface 11 of the glass core having controlled roughness characteristics and the seed layer 21 are stably interlocked with each other can be formed.

[0091] The thickness of the seed layer 21 may be 50 nm to 1500 nm. The thickness may be 80 nm or more. The thickness may be 100 nm or more. The thickness may be 150 nm or more. The thickness may be 200 nm or more. The thickness may be 250 nm or more. The thickness may be 300 nm or more. The thickness may be 1200 nm or less. The thickness may be 1000 nm or less.

[0092] In such a case, the seed layer 21 may help ensure that the electrically conductive layer 20 has good adhesion, and the electrically conductive layer 20 may be formed efficiently.

[0093] The conductive layer 22 may be formed on the seed layer 21 through a plating process. An electrically conductive material may be applied as the material of the conductive layer 22. For example, the conductive layer 22 may include at least one of copper, nickel, aluminum, gold, and silver.

[0094] 4 is a plan view illustrating a substrate according to still another embodiment of the present disclosure, and a substrate according to the embodiment will be described with reference to FIG.

[0095] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described above with reference to Figures 1 to 3. The following description will focus on the differences.

[0096] The substrate 100 can include a core distribution layer 50 disposed on a glass core 10. The core distribution layer 50 can include an electrically conductive layer 20 and an insulating layer 30 surrounding at least a portion of the electrically conductive layer 20.

[0097] In the core distribution layer 50, the insulating layer 30 and the electrically conductive layer 20 may be arranged in a mixed manner. The core distribution layer 50 may be formed in a form in which the electrically conductive layer 20 having a predetermined position and shape is embedded in the insulating layer 30. The electrically conductive layer 20 may be formed of thin wires on at least a portion of the core distribution layer 50.

[0098] The core distribution layer 50 may be formed by a process of repeatedly forming and removing the insulating layer 30 and the electrically conductive layer 20 .

[0099] The insulating layer 30 can be applied to any material that can be used as an insulating layer for a semiconductor element or a packaging substrate. For example, an epoxy resin containing a filler may be applied to the insulating layer 30. For example, the insulating layer 30 may be formed using a build-up layer material such as Ajinomoto Build-up Film (ABF) by Ajinomoto Co., Ltd., an undercoat material, or the like, but is not limited thereto.

[0100] The insulating layer 30 can be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0101] Electrically conductive layer 20 can include a first electrically conductive layer 25 disposed adjacent a surface of glass core 10. Electrically conductive layer 20 can include a second electrically conductive layer 26 that is not adjacent a surface of glass core 10.

[0102] When observed in cross section, first electrically conductive layer 25 may have an Rz value that is the maximum height roughness of interface L formed between the first electrically conductive layer and the glass core of 5 nm to 200 nm.

[0103] In the embodiment, the roughness characteristics of the interface L formed between the first electrically conductive layer and the glass core can be controlled, thereby stably controlling the resistance and heat generation characteristics of the first electrically conductive layer 25 due to the skin effect, and further improving the bonding strength of the first electrically conductive layer 25 to the glass core 10 due to the anchor effect.

[0104] The Rz value of the interface L is measured by the following method.

[0105] A cross section of the first electrically conductive layer 25 is photographed using a TEM (Transmission Electron Microscope). The cross section of the first electrically conductive layer 25 refers to a cross section in a direction perpendicular to the top surface 11 of the glass core. When the first electrically conductive layer 25 has a pattern shape, the cross section of the first electrically conductive layer 25 refers to a cross section in a direction perpendicular to the top surface 11 of the glass core and perpendicular to the longitudinal direction of the first electrically conductive layer 25. From the cross-sectional image of the first electrically conductive layer 25, a profile of the interface L formed between the first electrically conductive layer and the glass core is traced, and then an Rz value, which is the maximum height roughness of the interface L, is calculated from the traced profile.

[0106] The Rz value is measured according to the method specified in ISO 4287. Specifically, the sum of the height value of the highest peak and the depth value of the deepest valley in the traced profile of the interface L is defined as the Rz value.

[0107] The Rz value of the interface L formed between the first electrically conductive layer and the glass core may be 200 nm or less. The Rz value may be 180 nm or less. The Rz value may be 150 nm or less. The Rz value may be 100 nm or less. The Rz value may be 5 nm or more. The Rz value may be 10 nm or more. In this case, a first electrically conductive layer 25 having excellent peeling resistance and suitable for application of high frequency power can be realized on the surface of the glass core 10.

[0108] In the embodiment, the adhesive strength of the first electrically conductive layer 25 to the surface of the glass core can be controlled to a certain level or more, which can contribute to preventing peeling of the first electrically conductive layer 25 during the manufacturing and processing of the substrate.

[0109] The adhesive strength between the first electrically conductive layer 25 and the glass core 10 measured by a 180° peel test is measured using a bond tester. The measurement speed (peel speed) is set to 10 mm / s, and the measurement distance (peel distance) is set to 70 mm. Exemplarily, the adhesive strength can be measured using a Condor Sigma bond tester manufactured by XYZ TEC.

[0110] The adhesive strength between the first electrically conductive layer 25 and the glass core 10 measured by a 180° peel test may be 0.2 kgf or more. The adhesive strength may be 0.3 kgf or more. The adhesive strength may be 0.4 kgf or more. The adhesive strength may be 3 kgf or less. In this case, it may be helpful to ensure that the electrically conductive layer 20 can be stably attached to the surface of the glass core 10 during the manufacturing and processing of the substrate.

[0111] Other components in the packaging substrate The glass core 10 may include a core via (not shown) penetrating the glass core 10 in the thickness direction. The core distribution layer 50 may be formed on the upper surface 11 of the glass core and in the core via. The core distribution layer 50 may be formed on the upper surface 11 of the glass core, under the lower surface 12 of the glass core, and in the core via. In this case, the core distribution layer 50 can connect the upper surface 11 and the lower surface 12 of the glass core with a very short distance. In addition, electrical signals between elements arranged on the upper part of the substrate 100 and a motherboard arranged on the lower part of the substrate 100 can be transmitted more quickly, and signal loss can be suppressed.

[0112] The core via may include an internal space and a side surface surrounding the internal space. In the core via, the electrically conductive layer may be formed in contact with the side surface of the core via. The electrically conductive layer may be formed by filling the internal space of the core via.

[0113] The core via may be formed by processing a predetermined region in the glass core 10. Specifically, the core via may be formed by etching the glass core 10 using a physical and / or chemical method. Exemplarily, the core via may be formed by forming a defect in the surface of the glass core 10 using a laser or the like, followed by chemical etching, laser etching, or the like.

[0114] A cavity region (not shown) in which an element is accommodated may be disposed in the glass core 10. The cavity region may include a receiving portion which is a space formed by recessing a part of the glass core 10. The receiving portion may be formed by penetrating the glass core 10 from above to below. The receiving portion may be formed by recessing a part of the upper or lower part of the glass core 10.

[0115] An element may be placed in the housing. The element may be a semiconductor element such as a CPU, a GPU, or a memory chip, or may be a capacitor element, a transistor element, an impedance element, or other module. In other words, any semiconductor element that is mounted on a semiconductor device may be used as the element without any restrictions.

[0116] The substrate 100 may further include a top layer (not shown) on the core distribution layer 50 disposed on the glass core 10 .

[0117] The upper layer may include an upper distribution layer and a top connection layer disposed on the upper distribution layer. The elements disposed on the substrate 100 may be electrically connected to the substrate 100 through the top connection layer.

[0118] The upper distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer. The electrically conductive layer and the insulating layer of the upper distribution layer may be made of the same material as the electrically conductive layer and the insulating layer of the core distribution layer, respectively. The upper distribution layer may electrically connect the element and the core distribution layer.

[0119] The substrate 100 may further include a bottom layer (not shown) below the core distribution layer (not shown) disposed on the lower surface 12 side of the glass core.

[0120] The lower layer may include a lower distribution layer and a board connection portion disposed under the lower distribution layer. A main board disposed under the substrate 100 may be electrically connected to the substrate 100 through the board connection portion. The core distribution layer may be electrically connected to the main board through the lower layer.

[0121] The lower distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer. The electrically conductive layer and the insulating layer of the lower distribution layer may be made of the same materials as the electrically conductive layer and the insulating layer of the core distribution layer, respectively.

[0122] The substrate 100 can be used for semiconductor packaging, and can be utilized for mounting a semiconductor element, protecting the semiconductor, and providing electrical connection between the element and a main board.

[0123] Semiconductor Package A semiconductor package according to yet another embodiment of the present disclosure includes a substrate 100 and a main board (not shown) electrically connected to the substrate.

[0124] The substrate 100 can be mounted on a main board and electrically connected to the main board. The main board is not limited as long as it is one that is commonly applied in the field of semiconductor devices.

[0125] The description of the substrate 100 will be omitted since it overlaps with the above description.

[0126] Substrate manufacturing method A method for manufacturing a substrate according to yet another embodiment of the present specification includes a preparation step of providing a base glass plate, and a roughening step of providing a substrate including a glass core formed by roughening the upper surface of the base glass plate.

[0127] The glass core has an upper surface, and R is a ratio of the degree of asymmetry to the roughness of the upper surface of the glass core according to the following formula 1: s / z Value is -5nm -2 ~50nm -2 It is.

[0128] JPEG2025036113000005.jpg1494

[0129] In the above formula 1, the Rsk value is the value of the asymmetry degree, and the Rz value is the maximum height roughness (unit: nm).

[0130] In a preparation step, an elementary glass sheet can be processed to provide a glass core.

[0131] The base glass plate can be any plate glass material that is used for electronic components. For example, an alkali borosilicate glass plate, an alkali-free borosilicate glass plate, an alkali-free alkaline earth borosilicate glass plate, etc. may be used as the base glass plate. For example, products manufactured by manufacturers such as Corning, Schott, and AGC as commercially available products may be used as the base glass plate.

[0132] The surface roughening step of the embodiment may include a process of forming a glass core by plasma-treating the upper surface of the base glass sheet using an inert gas to form a glass core. Through this, a glass core having an upper surface with controlled roughness characteristics so that the roughness is not excessively high and has an asymmetry degree within a preset range in the embodiment may be provided.

[0133] The inert gas may be any one selected from the group consisting of helium gas, argon gas, xenon gas, krypton gas, and combinations thereof. The inert gas may be argon gas. In this case, it may be useful to form a glass core having a desired surface roughness characteristic in the embodiment while suppressing chemical modification of the upper surface of the base glass sheet in the roughening step.

[0134] In the roughening step, the atmospheric pressure may be 100 mTorr or less. The atmospheric pressure may be 80 mTorr or less. The atmospheric pressure may be 50 mTorr or less. The atmospheric pressure may be 30 mTorr or less. The atmospheric pressure may be 1 mTorr or more. In such a case, in the roughening step, the ionized inert gas collides with the surface to be roughened without undue hindrance, and the roughness characteristics of the upper surface of the glass core can be easily adjusted.

[0135] In the roughening step, the flow rate of the inert gas introduced may be 100 sccm or more. The flow rate may be 150 sccm or more. The flow rate may be 200 sccm or more. The flow rate may be 1000 sccm or less. In such a case, a sufficient amount of ionized inert gas can impinge on the upper surface of the base glass sheet at a properly adjusted speed.

[0136] In the roughening step, the source power may be 0.1 kW or more. The source power may be 0.3 kW or more. The source power may be 0.5 kW or more. The source power may be 5 kW or less.

[0137] In the roughening step, the bias power may be 0.1 kW or more. The bias power may be 0.3 kW or more. The bias power may be 0.5 kW or more. The bias power may be 1 kW or more. The bias power may be 8 kW or less. The bias power may be 5 kW or less.

[0138] In such cases, it may be useful to adjust the velocity of motion of the ionized inert gas within an appropriate range to enable the formation of a glass core having the desired surface roughness characteristics in an embodiment.

[0139] The roughening step may be performed for 10 seconds or more. The roughening step may be performed for 15 seconds or more. The roughening step may be performed for 30 seconds or more. The roughening step may be performed for 1000 seconds or less. This may help form an upper surface of the glass core having roughness and asymmetry within a preset range in the embodiment.

[0140] The roughening step may be performed not only on the upper surface but also on the lower surface of the base glass plate, to which the roughening step of the above-mentioned type may be applied.

[0141] If necessary, a core via can be formed in the glass core. Specifically, a defect can be formed at a predetermined position on the surface of the glass core. The defect can be physically or chemically etched to form the core via. The method of forming the core via will not be described here as it overlaps with the above description.

[0142] The method for manufacturing a substrate according to the embodiment may further include a core distribution layer forming step of forming a core distribution layer on the glass core.

[0143] The explanation of the core distribution layer will be omitted since it overlaps with the above content.

[0144] The core distribution layer forming step may include an electrically conductive layer forming process of forming an electrically conductive layer on the glass core, and an insulating layer forming process of forming an insulating layer surrounding at least a portion of the electrically conductive layer.

[0145] In the process of forming the electrically conductive layer, the seed layer is formed by applying the sputtering process conditions preset in the embodiment, so that the roughness characteristics of the upper surface of the glass core can be prevented from excessively varying due to the collision of sputtered particles with the upper surface of the glass core. Thus, the seed layer formed by sputtering forms a stable interlocking structure with the surface of the glass core over the entire upper surface of the glass core, which can contribute to improving the bonding strength of the electrically conductive layer. In addition, it can be useful for effectively preventing an increase in the resistance of the electrically conductive layer due to the skin effect.

[0146] The seed layer may include a first seed layer including a different element from the metal element applied to the conductive layer, and a second seed layer disposed on the first seed layer including the same element as the metal element applied to the conductive layer. Exemplarily, the first seed layer may include a material such as titanium, chromium, or nickel, and the second seed layer may include a material such as copper, nickel, aluminum, gold, or silver.

[0147] The explanation of the seed layer is omitted since it overlaps with the above-mentioned content.

[0148] In the sputtering process for forming the seed layer, the atmospheric pressure may be 0.1 Pa or more. The pressure may be 0.3 Pa or more. The pressure may be 5 Pa or less. In such a case, the seed layer can be formed at a further improved deposition rate.

[0149] The sputtering power applied to the sputtering process for forming the seed layer may be 10 kW or more. The sputtering power may be 15 kW or more. The sputtering power may be 20 kW or more. The sputtering power may be 100 kW or less. The sputtering power may be 50 kW or less. In this case, the sputtered particles may collide with the surface of the deposition target with controlled kinetic energy. Through this, the seed layer can be more firmly formed on the glass core, and the roughness characteristics of the surface of the glass core can be prevented from fluctuating excessively.

[0150] In the sputtering process for forming the seed layer, the initial temperature of a bed serving as a substrate support may be 180° C. or less. The temperature may be 150° C. or less. The temperature may be 30° C. or more. In this case, the mobility characteristics of the sputtered particles to be deposited are controlled, thereby further improving the durability of the seed layer.

[0151] In the sputtering process for forming the seed layer, an inert gas may be used as the sputtering gas, and the inert gas may be argon.

[0152] The sputtering process for forming the first seed layer may be performed for 1 minute or more, 2 minutes or more, or 20 minutes or less.

[0153] The sputtering process for forming the second seed layer may be performed for 1 minute or more, 2 minutes or more, or 20 minutes or less.

[0154] In this case, a seed layer having a structure that is stably bonded to the upper surface of the glass core can be formed.

[0155] After the formation of the seed layer is completed, the portion of the seed layer where the formation of the electrically conductive layer is not required can be removed. The portion of the seed layer where the formation of the electrically conductive layer is required and the portion where the electrically conductive layer is not required can be subjected to a plating activation / deactivation treatment. For example, the plating activation / deactivation treatment may be a light irradiation treatment using a laser of a specific wavelength, a chemical treatment, or the like. However, a conductive layer can be formed on the seed layer without applying such treatment.

[0156] The structure and material of the seed layer will not be described here since they are the same as those described above.

[0157] The electrically conductive layer can be provided by forming a conductive layer on the seed layer through a plating process. The material of the conductive layer and other details are omitted since they are the same as those described above. After the conductive layer is formed, the electrically conductive layer can be etched so that the electrically conductive layer has a predesigned pattern shape.

[0158] After forming the electrically conductive layer, an insulating layer may be disposed to surround at least a portion of the electrically conductive layer to form a core distribution layer. The insulating layer may be formed, for example, using an epoxy resin containing a filler. The insulating layer may be formed, for example, using a build-up layer material such as Ajinomoto Build-up Film (ABF) by Ajinomoto Co., Inc., an undercoat material, or the like, but is not limited thereto.

[0159] The insulating layer can be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0160] The core distribution layer forming step may be a step of forming a core distribution layer on the glass core. The core distribution layer forming step may be a step of forming a core distribution layer above and below the glass core. The core distribution layer forming step may be a step of forming a core distribution layer above and below the glass core and in the core via. The explanation of the method of forming a core distribution layer below the glass core and in the core via will be omitted because it overlaps with the above content.

[0161] Optionally, the method of manufacturing a substrate of an embodiment may further include forming an upper distribution layer on the core distribution layer disposed on the glass core, the upper distribution layer including an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer.

[0162] The method for manufacturing a substrate according to an embodiment may further include forming a lower distribution layer and / or bumps under a core distribution layer disposed under a glass core. The lower distribution layer includes an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer.

[0163] The electrically conductive and insulating layers applied to the upper and lower distribution layers may be made of the same materials and be manufactured using the same methods as the electrically conductive and insulating layers applied to the core distribution layer.

[0164] The present invention will be described in more detail with reference to specific examples below. The following examples are merely illustrative to aid in understanding the present invention, and are not intended to limit the scope of the present invention.

[0165] Manufacturing example: PCB manufacturing Example 1: The surface of a base glass plate, which is an alkali-free glass plate manufactured by Schott Co., was subjected to argon plasma treatment for 10 to 30 seconds to provide a glass core. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 0.8 kW, and the bias power was 0.8 kW.

[0166] Example 2: The surface of a base glass plate, which is a soda lime glass plate manufactured by Schott, was subjected to argon plasma treatment for 10 to 30 seconds to provide a glass core. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 0.5 kW, and the bias power was 0.5 kW.

[0167] Example 3: The surface of a base glass plate, which is a Corning SG7.8 glass plate, was treated with argon plasma for 20 to 40 seconds to provide a glass core. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 0.5 kW, and the bias power was 0.5 kW.

[0168] Example 4: The surface of a base glass plate, which is an alkali-free glass plate manufactured by Schott Co., was subjected to argon plasma treatment for 20 to 40 seconds to provide a glass core. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.0 kW, and the bias power was 1.0 kW.

[0169] Example 5: The surface of a base glass plate, which is an alkali-free glass plate manufactured by Schott Co., was subjected to argon plasma treatment for 30 to 50 seconds to form a glass core. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.2 kW, and the bias power was 1.5 kW.

[0170] Comparative Example 1: A surface of a base glass plate, which is a Corning SG7.8 glass plate, was subjected to argon plasma treatment for 90 to 120 seconds to form a glass core. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.2 kW, and the bias power was 2.0 kW.

[0171] Comparative Example 2: A glass core was formed by subjecting the surface of a base glass plate, which was an alkali-free glass plate manufactured by Schott Co., to argon plasma treatment for 90 to 120 seconds. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.5 kW, and the bias power was 2.5 kW.

[0172] Evaluation example: Measurement of roughness characteristics A total of three measurement regions, each 5 μm wide and 5 μm long, were arbitrarily selected on the upper surface of the glass core of each of the examples and comparative examples. The measurement regions were selected so as not to overlap with each other.

[0173] The Rsk and Rz values ​​of each measurement area were measured in non-contact mode using an atomic force microscope XE-100 manufactured by Park Systems Corporation in accordance with ISO 4287.

[0174] The average value of the Rsk values ​​of each measurement region was taken as the Rsk value of the upper surface of the glass core, and the average value of the Rz values ​​of each measurement region was taken as the Rz value of the upper surface of the glass core.

[0175] From the Rsk value and the Rz value, s / z The value was calculated.

[0176] The measurement and calculation results for each of the examples and comparative examples are shown in Tables 1 and 2 below.

[0177] Evaluation example: Measurement of uniformity of roughness The standard deviations of the Rsk and Rz values ​​were calculated from the Rsk and Rz values ​​measured in each measurement region on the upper surface of the glass core of the example.

[0178] The calculated values ​​for each example are shown in Table 2 below.

[0179] Evaluation example: Evaluation of adhesive strength of electrically conductive layer A seed layer was formed on the upper surface of the glass core of each of the examples and comparative examples by sputtering a titanium layer having a thickness of 300 nm, and a copper layer having a thickness of 300 nm on the titanium layer. In the sputtering process for forming the seed layer, the atmospheric pressure was set to 0.4 Pa, the sputtering power was set to 30 kW, and the substrate temperature was set to 120°C. The titanium layer and the copper layer were each deposited by sputtering for 3 minutes under the above conditions. A conductive layer having a thickness of 20 μm was formed on the seed layer through a copper plating process to provide an electrically conductive layer.

[0180] Thereafter, the adhesive strength of the electrically conductive layer to the glass core was measured by a 180° peel test using a bond tester Condor Sigma manufactured by XYZ TEC.

[0181] The measurement results for each of the examples and comparative examples are shown in Table 1 below.

[0182] Evaluation example: Evaluation of the presence or absence of peeling of the electrically conductive layer A seed layer was formed on the upper surface of the glass core of each of the examples and comparative examples by sputtering a titanium layer having a thickness of 300 nm and a copper layer having a thickness of 300 nm on the titanium layer. A conductive layer having a thickness of 20 μm was formed on the seed layer through a copper plating process to provide an electrical conductive layer.

[0183] The glass core on which the electrically conductive layer was formed was subjected to singulation. Specifically, energy was irradiated to a dicing path on the upper surface of the glass core using a laser device, and the glass core was cut by applying a physical force. Then, the edge of the cut glass core was ground.

[0184] The cross section of the singulated glass core was examined using an optical microscope to check for peeling of the electrically conductive layer.

[0185] In each of the examples and comparative examples, a rating of P was given when no peeling of the electrically conductive layer occurred, and a rating of F was given when peeling of the electrically conductive layer occurred.

[0186] The measurement results for each of the examples and comparative examples are shown in Table 1 below.

[0187] JPEG2025036113000006.jpg53164

[0188] JPEG2025036113000007.jpg95165

[0189] In Table 1, R s / z Value is -5nm -2 ~50nm-2 In the cases of Examples 1 to 5 in which the bonding strength was controlled to 0.2 kgf or more, the electrically conductive layer exhibited a bonding strength of 0.2 kgf or more, and no peeling of the electrically conductive layer occurred in the evaluation of the presence or absence of peeling. s / z Value is -5nm -2 Less than or equal to 55 nm -2 In the case of Comparative Examples 1 and 2, where the adhesive strength of the electrically conductive layer was greater than 0.15 kgf, the adhesive strength was measured to be 0.15 kgf or less, and peeling of the electrically conductive layer was found to have occurred in the evaluation of the presence or absence of peeling.

[0190] In Table 2, the standard deviation of the Rsk value in each measurement region of Examples 1 to 5 was calculated to be 0.4 or less, and the standard deviation of the Rz value was calculated to be 0.9 nm or less, which means that the roughness characteristics of the upper surface of the glass core of the Examples are uniform overall.

[0191] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also fall within the scope of the present invention. [Explanation of symbols]

[0192] 100 Substrates 10 Glass Core 11 Top surface of glass core 12 Underside of glass core 20 Electrically Conductive Layer 21 Seed layer 22 Conductive Layer 25 First Electrically Conductive Layer 26 Second Electrically Conductive Layer 30 Insulating layer 50 Core Distribution Layer L An interface formed between the first electrically conductive layer and the glass core

Claims

1. a glass core having an upper surface; R is the ratio of the asymmetry to the roughness of the upper surface of the glass core according to the following formula 1: ｓ／ｚ Value is -5 nm －２ ~50nm －２ That is, the circuit board. In the above formula 1, the Rsk value is the value of the asymmetry degree, and the Rz value is the maximum height roughness (unit: nm).

2. The substrate according to claim 1 , wherein the Rsk value is −0.5 to 1.

8.

3. The substrate of claim 1 , wherein the Rz value is between 3 nm and 30 nm.

4. The upper surface of the glass core includes a total of three arbitrarily selected measurement areas, The substrate according to claim 1 , wherein the standard deviation of the Rsk values ​​in the measurement areas is 0.5 or less.

5. The upper surface of the glass core includes a total of three arbitrarily selected measurement areas, The substrate according to claim 1 , wherein the standard deviation of the Rz values ​​in the measurement areas is 1.5 nm or less.

6. The substrate of claim 1 comprising an electrically conductive layer disposed on the glass core.

7. the electrically conductive layer includes a seed layer and a conductive layer disposed on the seed layer; The substrate of claim 6, wherein the seed layer has a thickness of 50 nm to 1500 nm.

8. the electrically conductive layer has a pattern shape; The width of the electrically conductive layer is 1 μm to 5 μm; The substrate of claim 6, wherein the electrically conductive layer has a thickness of 1 μm to 5 μm.

9. the electrically conductive layer includes a first electrically conductive layer formed in contact with a surface of the glass core; 7. The substrate according to claim 6, wherein when observed in a cross section of the first electrically conductive layer, the Rz value, which is the maximum height roughness of the interface formed between the first electrically conductive layer and the glass core, is 5 nm to 200 nm or less.

10. the electrically conductive layer includes a first electrically conductive layer formed in contact with a surface of the glass core; 7. The substrate of claim 6, wherein the adhesive strength between the first electrically conductive layer and the glass core is between 0.2 kgf and 3 kgf as measured by a 180° peel test.

11. The substrate of claim 1 , wherein the substrate has a semiconductor packaging application.

12. A preparation step of providing a basic glass plate; and providing a substrate including a glass core formed by roughening an upper surface of the base glass plate. the glass core having an upper surface; R is the ratio of the asymmetry to the roughness of the upper surface of the glass core according to the following formula 1: ｓ／ｚ Value is -5 nm －２ ~50nm －２ The method for manufacturing a substrate is as follows. In the above formula 1, the Rsk value is the value of the asymmetry degree, and the Rz value is the maximum height roughness (unit: nm).

13. The method of claim 12 , wherein the roughening step comprises plasma treating the top surface of the base glass plate to form a glass core.

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