Semiconductor device and semiconductor package containing them

Abstract

To provide a semiconductor package having a test pad to be miniaturized.SOLUTION: A semiconductor device according to the present invention, contains: a wiring region containing a lower wiring on an element region; an insulation structure body on the wiring region; a lower conductive pattern in the insulation structure body; a first conductive via that electrically couples the lower conductive pattern with the lower wiring; an upper conductive pattern on the insulation structure body; and a second conductive via that is in the insulation structure body, and electrically couples the upper conductive pattern with the lower conductive pattern. The second conductive via contains a second metal layer and a second barrier layer. The upper conductive pattern is extended from the second barrier layer, contains a third barrier layer onto one part of an upper surface of the insulation structure body, a third metal layer that is onto the third barrier layer, and is extended from the second metal layer, an upper metal layer onto the third metal layer, and an upper reflection prevention layer of the upper metal layer.SELECTED DRAWING: Figure 3b

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a semiconductor package including the same. [Background technology]

[0002] As demands for higher performance, higher speed, and / or more functionality of semiconductor devices increase, the integration level of semiconductor devices is increasing. In manufacturing semiconductor devices that provide high integration, it is necessary to realize fine patterns, i.e., patterns having fine widths or fine separations. In addition, there is a demand for high integration of semiconductor devices mounted in semiconductor packages. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems to be solved by the technical concept of the present invention is to provide a semiconductor package having a miniaturized test pad. [Means for solving the problem]

[0004] A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a device region on the semiconductor substrate, a wiring region on the device region including lower wiring, an insulating structure on the wiring region, a lower conductive pattern in the insulating structure, a first conductive via electrically connecting at least one of the lower conductive patterns to the lower wiring of the wiring region, an upper conductive pattern on the insulating structure, and a second conductive via in the insulating structure electrically connecting the upper conductive pattern to at least one of the lower conductive patterns, , a first metal layer and a first barrier layer on a lower surface and side surfaces of the first metal layer, the second conductive vias respectively include a second metal layer within the insulating structure and a second barrier layer on a lower surface and side surfaces of the second metal layer, and the upper conductive patterns respectively include a third barrier layer extending from the second barrier layer and over a portion of a top surface of the insulating structure opposite the semiconductor substrate, a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer, an upper metal layer on the third metal layer, and an upper anti-reflective layer on the upper metal layer.

[0005] A semiconductor package according to an exemplary embodiment includes a plurality of semiconductor elements sequentially stacked on a buffer chip, an adhesive layer between the plurality of semiconductor elements, and an encapsulant on the buffer chip and the plurality of semiconductor elements, and the semiconductor elements each include an insulating structure on a semiconductor substrate, a via pad below the semiconductor substrate, a through electrode electrically connected to the via pad and penetrating the semiconductor substrate, a lower conductive pattern in the insulating structure, a first conductive via on a lower surface of the lower conductive pattern, an upper conductive pattern on the insulating structure, and an insulating structure electrically connecting the upper conductive pattern to at least one of the lower conductive patterns. and a connection pad electrically connected to one of the upper conductive patterns, the first conductive vias including a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, the second conductive vias including a second metal layer within the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer, and the upper conductive patterns including a third barrier layer extending from the second barrier layer and on a portion of a top surface of the insulating structure, a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer, an upper metal layer on the third metal layer, and an upper anti-reflective layer on the upper metal layer.

[0006] A semiconductor device according to an exemplary embodiment includes an insulating structure on a semiconductor substrate, a lower conductive pattern in the insulating structure, a first conductive via on a lower surface of the lower conductive pattern, an upper conductive pattern on the insulating structure, and a second conductive via in the insulating structure and electrically connecting the upper conductive pattern to the lower conductive pattern, the first conductive via including a first metal layer and a first barrier layer on a lower surface and a side surface of the first metal layer, the second conductive via including a second metal layer in the insulating structure and a second barrier layer on a lower surface and a side surface of the second metal layer, the upper conductive pattern including a first conductive layer extending from the second conductive via, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer. Effect of the Invention

[0007] According to an embodiment of the technical concept of the present invention, the upper conductive pattern includes a metal layer disposed under the upper metal layer, and the metal layer is connected to the conductive via (or is integral with the conductive via) to increase the contact area between the upper metal layer of the upper conductive pattern and the metal layer, thereby reducing the resistance of the semiconductor device. Also, the electromigration characteristics of the upper conductive pattern can be improved through or based on the material of the metal layer.

[0008] The various and beneficial advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view of a semiconductor substrate including a semiconductor device according to an illustrative embodiment; [Diagram 2] FIG. 2 is an enlarged plan view of a portion of FIG. [Figure 3a] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. [Figure 3b] 1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Figure 3c] 1 is a plan view of a semiconductor device in accordance with an illustrative embodiment; [Figure 4] 1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Diagram 5] 1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Figure 6] 1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Figure 7] 1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Figure 8] 1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Figure 9]1 is a partial enlarged cross-sectional view of a portion of a semiconductor device according to an illustrative embodiment. [Figure 10] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment. [Figure 11a] 1 is a cross-sectional view of a semiconductor package including a semiconductor device according to an exemplary embodiment. [Figure 11b] 11b is a partially enlarged cross-sectional view showing a part of the semiconductor package shown in FIG. [Figure 12] 1 is a cross-sectional view of a semiconductor package including a semiconductor device according to an exemplary embodiment. [Figure 13] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14a] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14b] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 15] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 16a] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 16b] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 17] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 18] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 19]1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 20] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 21] 1A to 1C are enlarged cross-sectional views of a semiconductor substrate illustrating a manufacturing process for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 22] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 23] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 24] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Diagram 25] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. [Figure 26] 1A to 1C are cross-sectional views of a semiconductor substrate shown in a sequence of manufacturing processes to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. In this specification, the terms "first", "second", etc. may be used simply to distinguish one component, layer, direction, etc. from another. The terms "comprises", "comprising", "includes" and / or "including" as used herein indicate the presence of the stated elements, but do not exclude the presence of additional elements. The term "and / or" includes any and all combinations of one or more of the listed things. In this specification, the term "connected" may be used to refer to a physical and / or electrical connection. In this specification, when a component or layer is described as "directly" on, "in direct contact with", or "directly connected", there is no intervening component or layer. Similarly, when components are "directly" adjacent to each other, there may be no intervening components.

[0011] Fig. 1 is a plan view of a semiconductor substrate including a semiconductor element according to an exemplary embodiment. Fig. 2 is an enlarged plan view of a portion of Fig. 1. Fig. 2 shows an enlarged view of region "A" of Fig. 1.

[0012] 1 and 2, a semiconductor substrate or wafer W may include a device region DR and a scribe line region SL between the device regions DR. The scribe line region SL may extend in a first horizontal direction D1 and a second horizontal direction D2 intersecting the first horizontal direction D1. The device regions DR may be spaced apart from each other in the first horizontal direction D1 and the second horizontal direction D2 and may be surrounded by the scribe line region SL. The device regions DR may be separated along the scribe line region SL by a dicing process described below to form a semiconductor device 100. The terms "surround", "cover", or "fill", as used herein, may not require a complete surrounding, covering, or filling of a described element or layer, and may, for example, represent a partial surrounding, covering, or filling of a described element or layer.

[0013] In one embodiment, the device region DR may be provided with a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory device such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In one embodiment, the device region DR may be provided with a logic device such as a microprocessor, an analog device, or a digital signal processor.

[0014] Figure 3a is a cross-sectional view of a semiconductor device according to an exemplary embodiment taken along line I-I' in Figure 2. Figure 3b is a partially enlarged view of a portion of a semiconductor device according to an exemplary embodiment, showing an enlarged view of region "B" in Figure 3a. Figure 3c is a plan view of a semiconductor device according to an exemplary embodiment.

[0015] 3a to 3c, the semiconductor device 100 may include a semiconductor substrate 102, an element region 110 on the semiconductor substrate 102, a wiring region 120 on the element region 110, an insulating structure 130 on the wiring region 120, an intermediate insulating layer 128 between the wiring region 120 and the insulating structure 130, a lower conductive pattern 137 disposed in the insulating structure 130, a first conductive via 129 connecting the lower conductive pattern 137 and the wiring region 120, an upper conductive pattern 150 on the insulating structure 130, and a second conductive via 138 connecting the upper conductive pattern 150 and the lower conductive pattern 137. The semiconductor device 100 may further include a passivation structure P including a protective layer 160, a first passivation layer 164 on the protective layer 160, and a second passivation layer 168 on the first passivation layer 164.

[0016] The semiconductor substrate 102 may include an element region DR and a scribe line region SL between the element region DR. The scribe line region SL may include an edge region ER and a cutting region CR between the edge region ER. The edge region ER may surround the element region DR. The cutting region CR may refer to a portion that is separated during a dicing process described below. The semiconductor substrate 102 may include a semiconductor material. For example, the semiconductor substrate 102 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon on insulator (SOI) substrate. The semiconductor substrate 102 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0017] The device region 110 may include integrated circuit elements 112, internal wiring 114, and a lower interlayer insulating layer 116. The integrated circuit elements 112 may include a memory cell array including switching elements and data storage elements, and logic elements including MOSFETs, capacitors, and resistors. The internal wiring 114 may be disposed on the integrated circuit elements 112 and may be electrically connected to at least one of the integrated circuit elements 112. The integrated circuit elements 112 may be disposed in the device region DR. The internal wiring 114 may be disposed in the device region DR and the edge region ER, and in some embodiments, the internal wiring 114 may also be disposed in the cutting region CR. The lower interlayer insulating layer 116 may cover the semiconductor substrate 102, the integrated circuit elements 112, and the internal wiring 114. The internal wiring 114 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. For example, the interconnect 114 may include copper (Cu). The lower interlayer insulating layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the lower interlayer insulating layer 116 may include silicon oxide.

[0018] The wiring region 120 may be formed on the device region 110. The wiring region 120 may include a lower insulating layer 122, a lower contact 124, and a lower wiring 126. The lower insulating layer 122 may be sequentially deposited on the lower interlayer insulating layer 116. The lower wiring 126 may be disposed in the device region DR and embedded inside the lower insulating layer 122. At least one of the lower wirings 126 may be electrically connected to the integrated circuit device 112. The lower wiring 126 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. For example, the lower wiring 126 may include copper (Cu).

[0019] The insulating structure 130 may be formed on the wiring region 120. The insulating structure 130 may include a first upper insulating layer 132, a second upper insulating layer 134, and a third upper insulating layer 136, and a lower conductive pattern 137 may be formed in the insulating structure 130. According to an exemplary embodiment, a portion of the second upper insulating layer 134 that vertically overlaps with the lower conductive pattern 137 may protrude upward. The second upper insulating layer 134 may include a material having an etch selectivity with respect to the first upper insulating layer 132. For example, the first upper insulating layer 132 may include a high density plasma (HDP) oxide. The second upper insulating layer 134 may include a silicon nitride, a silicon oxynitride, a silicon carbonitride, or a combination thereof. In one embodiment, the third upper insulating layer 136 may include a silicon oxide. For example, the third upper insulating layer 136 may include TetraEthyl OrthoSilicate (TEOS).

[0020] An intermediate insulating layer 128 may be formed between the wiring region 120 and the insulating structure 130. A first conductive via 129 may penetrate the intermediate insulating layer 128. The first conductive via 129 may connect the wiring region 120 to a lower insulating pattern 137 in the insulating structure 130. The intermediate insulating layer 128 may include an oxide, a nitride, or a combination thereof.

[0021] The lower conductive pattern 137 may include a lower metal layer 137a and a lower anti-reflection layer 137b on the lower metal layer 137a. The lower metal layer 137a may include a conductive material. The lower metal layer 137a may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. For example, the lower metal layer 137a may include aluminum (Al). The lower anti-reflection layer 137b may be formed to protect the lower conductive pattern 137 in a process of etching the first upper insulating layer 132, the second upper insulating layer 134, and the third upper insulating layer 136 to form a second conductive via 138 described below. The lower anti-reflection layer 137b may include at least one of titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and tungsten carbonitride (WCN). For example, the anti-reflection layer 137b may include titanium nitride (TiN).

[0022] The first conductive via 129 may include a first barrier layer 129b and a first metal layer 129a disposed along a sidewall. The first barrier layer 129b may cover the side and bottom surfaces of the first metal layer 129a. The first metal layer 129a may include a conductive material, for example, tungsten (W). The first metal layer 129a and the lower metal layer 137a may include different materials, but are not limited thereto. The first barrier layer 129b may include a metal nitride, such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN), for example, titanium nitride (TiN).

[0023] Hereinafter, the second metal layer 138a of the second conductive via 138 may include an upper vertical portion 138a1 that is a portion located at a level lower than the upper surface of the third upper insulating layer 136, and an upper horizontal portion 138a2 that is a portion located at a level higher than the upper surface of the third upper insulating layer 136, based on the upper surface of the third upper insulating layer 136. The second barrier layer 138b of the second conductive via 138 may include a first upper portion 138b1 that is a portion located at a level lower than the upper surface of the third upper insulating layer 136, and a second upper portion 138b2 that is a portion located at a level higher than the upper surface of the third upper insulating layer 136. In this specification, the terms "higher" and "lower" are used relative to a reference system, for example, relative to the substrate 102. The second upper portion 138b2 may be referred to as a third barrier layer 138b2, and the upper horizontal portion 138a2 may be referred to as a third metal layer 138a2.

[0024] The upper conductive pattern 150 may include a second upper portion 138b2 of the second barrier layer 138b covering a portion of the upper surface of the insulating structure 130, an upper horizontal portion 138a2 of the second metal layer 138a covering the second barrier layer 138b on the insulating structure 130, an upper metal layer 150a on the second metal layer 138a, and an upper anti-reflective layer 150b on the upper metal layer 150a. According to an exemplary embodiment, the upper conductive pattern 150 may include the upper horizontal portion 138a2 and the second upper portion 138b2. According to an exemplary embodiment, each of the upper conductive patterns 150 may include a third barrier layer 138b2 extending from the second barrier layer 138b and covering a portion of the upper surface of the insulating structure 130, and a third metal layer 138a2 disposed on the third barrier layer 138b2 and the second metal layer 138a1 and extending from the second metal layer 138a1. The upper conductive pattern 150 may include first conductive layers 138a2, 138b2 extending from the second conductive via 138, a second conductive layer 150a on the first conductive layers 138a2, 138b2, and a third conductive layer 150b on the second conductive layer 150a. The first conductive layers 138a2, 138b2 may include a third metal layer 138a2 (upper horizontal portion 138a2) extending from the second metal layer 138a and a third barrier layer 138b2 (second upper portion 138b2) extending from the second barrier layer 138b. The second conductive layer 150a and the third conductive layer 150b described in the claims may be referred to as an upper metal layer 150a and an upper anti-reflective layer 150b, respectively.

[0025] The thickness (Tu) of each of the upper conductive patterns 150 may be greater than the thickness (Tb) of each of the lower conductive patterns 137. The thickness (Duu) of the upper metal layer 150a may be greater than the thickness (Dub) of the second metal layer 138a on the upper surface of the insulating structure 130. For example, the thickness (Duu) of the upper metal layer 150a may be greater than the thickness (Dub) of the upper horizontal portion 138a2. According to an exemplary embodiment, since the upper horizontal portion 138a2 of the second metal layer 138a exists under the upper metal layer 150a, the upper metal layer 150a may be separated from the upper surface of the insulating structure 130. For example, the upper metal layer 150a may be separated from the upper surface of the third upper insulating layer 136. The second metal layer 138a in the upper conductive pattern 150, i.e., the upper horizontal portion 138a2, may be extended to the second metal layer 138a in the insulating structure 130, i.e., the upper vertical portion 138a1. In other words, the upper conductive pattern 150 may include a portion of the second metal layer 138a that is continuously extended into the via opening such that the upper vertical portion 138a1 in the via opening and the upper horizontal portion 138a2 outside the via opening form an integral or single structure. The semiconductor device 100 as described above may reduce contact resistance by increasing the contact area between the upper metal layer 150a and the first metal layer 129a (particularly, the contact area between the upper metal layer 150a and the upper horizontal portion 138a2), ​​and may improve the electromigration characteristics of the upper conductive pattern 150 by the second metal layer 138a in the upper conductive pattern 150. For example, the upper metal layer 150a may include aluminum (Al), and the first metal layer 129a or the second metal layer 138a may include tungsten (W), thereby improving the electromigration characteristics of the upper conductive pattern 150. As a result, a semiconductor device 100 with improved electrical characteristics and reliability may be provided.

[0026] The upper anti-reflection layer 150b may be formed to protect the upper conductive pattern 150 in a process of etching the passivation structure P to form the opening OP. The upper metal layer 150a may include a conductive material, for example, aluminum (Al). The upper anti-reflection layer 150b may include at least one of titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), and tungsten carbonitride (WCN). For example, the upper anti-reflection layer 150b may include titanium nitride (TiN).

[0027] The second conductive via 138 may include a second barrier layer 138b and a second metal layer 138a disposed along the sidewall. The second barrier layer 138b, i.e., a first upper portion 138b1, may cover the side and the lower surface of the second metal layer 138a. The second metal layer 138a may include a conductive material, for example, tungsten (W). The second metal layer 138a and the upper metal layer 150a may include different materials from each other, but are not limited thereto. The second barrier layer 138b may include a metal nitride, such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN), for example, titanium nitride (TiN). The first conductive via 129 and the second conductive via 138 may have a similar structure. According to an exemplary embodiment, the second barrier layer 138b may be disposed between the insulating structure 130 and the second metal layer 138a. For example, the second barrier layer 138b may cover a portion of the upper surface of the third upper insulating layer 136. That is, the second upper portion 138b2 may cover a portion of the upper surface of the third upper insulating layer 136.

[0028] The passivation structure P may include a protective layer 160, a first passivation layer 164, and a second passivation layer 168. The passivation structure P may cover the inner wall of a trench T formed along the cutting region CR.

[0029] The protective layer 160 may be conformally formed along at least a portion of the second barrier layer 138b and the upper conductive pattern 150. The protective layer 160 may include the same material as the third upper insulating layer 136, for example, TEOS. According to an exemplary embodiment, the protective layer 160 and the third upper insulating layer 136 may be separated due to the presence of the second barrier layer 138b, i.e., the second upper portion 138b2, between the protective layer 160 and the third upper insulating layer 136, but is not limited thereto.

[0030] A first passivation layer 164 may cover the protective layer 160. The first passivation layer 164 may include silicon oxide, for example, TEOS. A second passivation layer 168 may be conformally formed along the first passivation layer 164 and the trench T. The second passivation layer 168 may include silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. For example, the second passivation layer 168 may include silicon nitride.

[0031] The guard ring 140 disposed in the edge region ER may extend in a horizontal direction to surround the element region DR. As shown in FIG. 3c, the guard ring 140 is illustrated as a rectangle, but is not limited thereto. According to other embodiments, the guard ring 140 may be circular or elliptical. The cutting region CR may be disposed outside the guard ring 140 (i.e., outside the boundary of the guard ring 140) and may surround the guard ring 140. The trench T may extend in one or more horizontal directions along the cutting region CR.

[0032] 4 to 9 are partially enlarged cross-sectional views showing parts of semiconductor devices according to example embodiments.

[0033] 4, in the semiconductor device 100a, the thickness (Duu) of the upper metal layer 150a may be substantially equal to or smaller than the thickness (Dub) of the second metal layer 138a on the upper surface of the insulating structure 130. For example, the thickness (Duu) of the upper metal layer 150a may be substantially equal to or smaller than the thickness (Dub) of the upper horizontal portion 138a2 on the upper surface of the insulating structure 130. According to an exemplary embodiment, in the process of FIGS. 18 and 19 described below, the upper horizontal portion 138a2 of the second metal layer 138a may be formed thick, and the upper metal layer 150a may be formed thinner than the first metal layer 129a.

[0034] 5, in the semiconductor device 100b, the second metal layer 138a may be in direct contact with the upper surface of the insulating structure 130. This is because, in the process of FIG. 17 described below, the second barrier layer 138b is formed in the second via hole VH2 and is not formed on the upper surface of the third upper insulating layer 136, or, in the process of FIG. 18, the process is performed after removing the second upper portion 138b2 of the second barrier layer 138b on the third upper insulating layer 136 by a planarization process before forming the second metal layer 138a.

[0035] The protective layer 160 may be conformally formed along the insulating structure 130 and the upper conductive pattern 150. According to an exemplary embodiment, a boundary between the protective layer 160 and the third upper insulating layer 136 may not be identified, and since the second upper portion 138b2 of the second barrier layer 138b is not present on the upper surface of the third upper insulating layer 136, the protective layer 160 may be integral with the third upper insulating layer 136, i.e., connected as a single layer with no boundary therebetween.

[0036] 6, in the semiconductor device 100c, the upper conductive pattern 150 may further include an upper barrier layer 151 between the upper metal layer 150a and the upper horizontal portion 138a2 of the second metal layer 138a. The upper barrier layer 151 may be formed to cover an upper surface of the upper horizontal portion 138a2 of the second metal layer 138a. The upper barrier layer 151 may include Ti, TiN, Ta, TaN, WN, or a combination thereof.

[0037] 7, in the semiconductor device 100d, the upper conductive pattern 150 may further include an oxide layer 152 between the upper metal layer 150a and the upper anti-reflective layer 150b. In the process of forming the upper anti-reflective layer 150b on the upper metal layer 150a, the oxide layer 152 may be formed by a heat treatment process. The oxide layer 152 may include a conductive metal oxide.

[0038] 8, in the semiconductor device 100e, the lower conductive pattern 137 may further include a first barrier layer 129b covering a portion of an upper surface of the intermediate insulating layer 128 and a first metal layer 129a covering the first barrier layer 129b on the intermediate insulating layer 128. For example, the lower conductive pattern 137 may include a second lower portion 129b2 of the first barrier layer 129b, a lower horizontal portion 129a2 of the first metal layer 129a, a lower metal layer 137a, and a lower anti-reflective layer 127b.

[0039] The first metal layer 129a may include a lower vertical portion 129a1 that is located at a lower level than the upper surface of the intermediate insulating layer 128, and a lower horizontal portion 129a2 that is located at a higher level than the upper surface of the intermediate insulating layer 128, based on the upper surface of the intermediate insulating layer 128. The first barrier layer 129b may include a first lower portion 129b1 that is located at a lower level than the upper surface of the intermediate insulating layer 128, and a second lower portion 129b2 that is located at a higher level than the upper surface of the intermediate insulating layer 128.

[0040] According to an exemplary embodiment, the lower conductive pattern 137 and the upper conductive pattern 150 may have a similar structure. The first metal layer 129a in the lower conductive pattern 137, i.e., the lower horizontal portion 129a2, may be extended to the first metal layer 129a in the first conductive via 129, i.e., the first lower portion 129b1. The thickness (Dbu) of the lower metal layer 137a may be greater than the thickness (Dbb) of the first metal layer 129a on the upper surface of the intermediate insulating layer 128. For example, the thickness (Dbu) of the lower metal layer 137a may be greater than the thickness (Dbb) of the lower horizontal portion 129a2 on the upper surface of the intermediate insulating layer 128. The semiconductor device 100e may have a reduced contact resistance by increasing the contact area between the lower metal layer 137a and the lower horizontal portion 129a2 of the first metal layer 129a. As a result, the semiconductor device 100e having improved electrical characteristics and reliability may be provided.

[0041] 9, in the semiconductor device 100f, the thickness (Dbu) of the lower metal layer 137a may be substantially equal to or smaller than the thickness (Dbb) of the first metal layer 129a on the upper surface of the intermediate insulating layer 128. According to an exemplary embodiment, in the processes of FIGS. 15 to 16b described below, the first metal layer 129a (and in particular the lower horizontal portion 129a2) may be formed thick, and the lower metal layer 137a may be formed thinner than the lower horizontal portion 129a2 of the first metal layer 129a.

[0042] FIG. 10 is a cross-sectional view of a semiconductor device according to an illustrative embodiment.

[0043] 10, the semiconductor device 100g may further include a through electrode 170, a via insulating layer 172, a lower passivation layer 180, and a via pad 190. The through electrode 170 may vertically penetrate the semiconductor substrate 102 and the device region 110 to be connected to the wiring region 120. The via insulating layer 172 may cover a side of the through electrode 170. The through electrode 170 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination thereof. The via insulating layer 172 may include an insulating material such as silicon oxide.

[0044] The lower passivation layer 180 may cover a lower surface of the semiconductor substrate 102, and the through electrode 170 may penetrate the lower passivation layer 180. The via pad 190 may be disposed on a lower surface of the lower passivation layer 180 and may be connected to the through electrode 170. The via pad 190 may be electrically connected to the wiring region 120 through the through electrode 170. According to another embodiment, the via pad 190 may overlap the lower passivation layer 180 in a horizontal direction, and a side surface of the via pad 190 may contact the lower passivation layer 180.

[0045] Figure 11a is a cross-sectional view of a semiconductor package including a semiconductor device according to an exemplary embodiment. Figure 11b is a partially enlarged cross-sectional view of a portion of the semiconductor package shown in Figure 11a, where Figure 11b is an enlarged view of area "C" in Figure 11a.

[0046] 11a and 11b, the semiconductor package 1000 of the present disclosure may be a high bandwidth memory (HBM) package. The semiconductor package 1000 may include a package substrate PS, an interposer IP mounted on the package substrate PS, and a memory package 800 and a processor chip 900 mounted on the interposer IP. The interposer IP may electrically connect the memory package 800 and the processor chip 900.

[0047] The memory package 800 may include a buffer chip 805, a first semiconductor device 810, a second semiconductor device 820, a third semiconductor device 830, and a fourth semiconductor device 840, which are stacked in sequence. The buffer chip 805 and the first to fourth semiconductor devices 810, 820, 830, and 840 may have the same or similar structure as the semiconductor device 100 described with reference to Figures 3a and 3b, and may include configurations corresponding to the upper conductive pattern 150 and the lower conductive pattern 137, for example. In addition, the second to fourth semiconductor devices 820, 830, and 840 may include configurations corresponding to the through electrode 170, the via insulating layer 172, the lower passivation layer 180, and the via pad 190.

[0048] In one embodiment, the buffer chip 805 may be a different type of semiconductor chip from the first to fourth semiconductor elements 810, 820, 830, and 840. For example, the buffer chip 805 may be a logic chip, and the first to fourth semiconductor elements 810, 820, 830, and 840 may be memory chips. The logic chip may include a microprocessor, an analog element, or a digital signal processor. The memory chip may include a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0049] The memory package 800 may further include an adhesive layer 850 and an encapsulant 860. The adhesive layer 850 may be disposed between the buffer chip 805 and the first semiconductor element 810 and between the first to fourth semiconductor elements 810, 820, 830, and 840. The adhesive layer 850 may be a non-conductive film (NCF) or a non-conductive paste (NCP). The encapsulant 860 may be a resin including epoxy or polyimide. For example, the resin may include a bisphenol-group epoxy resin, a polycyclic aromatic epoxy resin, an o-cresol novolac epoxy resin, a biphenyl-group epoxy resin, or a naphthalene-group epoxy resin.

[0050] The processor chip 900 can be a central processing unit (CPU), a graphic processing unit (GPU), a mobile application, or a digital signal processor (DSP) chip.

[0051] 11b, the memory package 800 may further include bumps 855 between the second semiconductor device 820 and the third semiconductor device 830 and between the third semiconductor device 830 and the fourth semiconductor device 840. The first to fourth semiconductor devices 810, 820, 830, and 840 may further include connection pads 195 connected to the upper conductive pattern 150. The upper conductive pattern 150 and the lower conductive pattern 137 may be the same as or similar to the components of the semiconductor device 100 shown in FIGS. 3a and 3b. For example, the upper conductive pattern 150 and the lower conductive pattern 137 may be configured to be the same as the components of the semiconductor device 100e shown in FIG. 8 or the semiconductor device 100f shown in FIG. 9. The connection pad 195 may fill the opening OP shown in FIG. 10 and contact the upper conductive pattern 150. The connection pad 195 may penetrate the passivation structure P and contact the side surface thereof. The bump 855 may connect the via pad 190 and the connection pad 195 between the adjacent semiconductor devices 820, 830, and 840. The adhesive layer 850 may cover the via pad 190, the connection pad 195, and the side surface of the bump 855. According to another embodiment, the bump 855 may be omitted, and the via pad 190 and the connection pad 195 may directly contact each other.

[0052] FIG. 12 is a cross-sectional view of a semiconductor package including a semiconductor device according to an exemplary embodiment.

[0053] 12, a semiconductor package 1100 may include a substrate 2, an adhesive member 10, a bonding wire 20, and an encapsulant 30. The semiconductor package 1000 may also include a semiconductor element 100 on the substrate 2.

[0054] The substrate 2 may include upper pads 3, lower pads 5, internal wiring 6, and external connection terminals 7. In one embodiment, the substrate 2 may be a printed circuit board and may include an insulating material such as phenolic resin, epoxy resin, or prepreg. In another embodiment, the substrate 2 may be a redistribution layer in which an insulating material and a conductive material are laminated. The upper pads 3 and the lower pads 5 may be formed by forming a metal layer on a base of the substrate 2 and then patterning the metal layer.

[0055] The upper pads 3 may be disposed on an upper surface of the substrate 2 and may be electrically connected to the semiconductor device 100. The lower pads 5 may be disposed on a lower surface of the substrate 2 and the upper pads 3 may be electrically connected to corresponding lower pads 5 via internal wiring 6. The external connection terminals 7 may be disposed below the lower pads 5. The lower pads 5, the upper pads 3 and the wiring may include a metal such as copper (Cu). The external connection terminals 7 may be conductive bumps 855 (e.g., solder bumps).

[0056] The semiconductor device 100 may include an insulating structure 130, an upper conductive pattern 150, and a passivation structure P, which may be the same as or similar to the components of the semiconductor device 100 shown in FIGS. 3a and 3b. The insulating structure 130 may be disposed on the upper part of the semiconductor device 100. The passivation structure P may be disposed on the upper insulating structure 130 and may protect the upper insulating structure 130 from external physical impacts. The upper conductive pattern 150 may be embedded in the passivation structure P. The upper conductive pattern 150 may be connected to the upper pad 3 by a bonding wire 20.

[0057] The adhesive member 10 may be disposed between the substrate 2 and the semiconductor element 100. The adhesive member 10 may fix or attach the semiconductor element 100 onto the substrate 2. The adhesive member 10 may be, but is not limited to, a die attach film (DAF). The encapsulant 30 may cover the substrate 2, the semiconductor element 100, and the bonding wires 20.

[0058] Figures 13 to 26 are cross-sectional views and partially enlarged cross-sectional views of a semiconductor substrate shown in a process sequence to explain a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 13, 14a, 16a, and 22 to 26 show cross sections cut along II-II' in Figure 2. Figures 14b, 15, 16b, and 17 to 21 show the area corresponding to Figure 3b.

[0059] 13, a device region 110 and a wiring region 120 may be formed on a semiconductor substrate 102. The semiconductor substrate 102 may correspond to the semiconductor substrate or wafer W shown in FIG.

[0060] The semiconductor substrate 102 may include a device region DR and a scribe line region SL between the device region DR. The scribe line region SL may include an edge region ER and a cutting region CR between the edge region ER. The edge region ER may surround the device region DR. The cutting region CR may refer to a portion that is separated during a dicing process described below. The semiconductor substrate 102 may include a semiconductor material.

[0061] The element region 110 may include an integrated circuit element 112, an internal wiring 114, and a lower interlayer insulating layer 116. The integrated circuit element 112 may be disposed in the element region DR. The internal wiring 114 may be disposed in the element region DR and the edge region ER, and in some embodiments, the internal wiring 114 may also be disposed in the cutting region CR. The lower interlayer insulating layer 116 may cover the semiconductor substrate 102, the integrated circuit element 112, and the internal wiring 114.

[0062] The wiring region 120 may be formed on the device region 110. The wiring region 120 may include a lower insulating layer 122, a lower contact 124, and a lower wiring 126.

[0063] 14a and 14b, an intermediate insulating layer 128 and a first via hole VH1 vertically penetrating the intermediate insulating layer 128 may be formed on the wiring region 120, and a first barrier layer 129b may be formed in the first via hole VH1.

[0064] The first via hole VH1 may be formed using a dry etching, wet etching, laser drilling, or mechanical drilling method. The first lower portion 129b1 of the first barrier layer 129b may be formed with a uniform thickness on the lower surface and side surface of the first via hole VH1. According to an exemplary embodiment, the second lower portion 129b2 of the first barrier layer 129b may be formed to cover the intermediate insulating layer 128. For example, the second lower portion 129b2 of the first barrier layer 129b may be formed on the upper surface of the intermediate insulating layer 128. However, without being limited thereto, the first barrier layer 129b may not cover the upper surface of the intermediate insulating layer 128 or may be removed from the upper surface of the intermediate insulating layer 128 and may be formed in the first via hole VH1. The first barrier layer 129b may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0065] Referring to FIG. 15, a first metal layer 129a may be formed to fill the first via hole VH1.

[0066] The first metal layer 129a may be formed to fully fill the first via hole VH1. For example, the lower vertical portion 129a1 of the first metal layer 129a may be formed to fully fill the first via hole VH1. According to an exemplary embodiment, the lower horizontal portion 129a2 of the first metal layer 129a may be formed to cover the first barrier layer 129b on the upper surface of the intermediate insulating layer 128. In this case, the semiconductor device 100e of FIG. 8 may be manufactured, and when the first metal layer 129a is formed thick, the semiconductor device 100f of FIG. 9 may be manufactured. However, without being limited thereto, the lower horizontal portion 129a2 of the first metal layer 129a may be formed to cover the upper surface of the intermediate insulating layer 128 after the first barrier layer 129b on the upper surface of the intermediate insulating layer 128 is removed by a planarization process, and may be formed to fully fill the first via hole VH1. The first metal layer 129a may be formed by a PVD process, a CVD process, or an ALD process.

[0067] 16a and 16b, a first conductive via 129 may be formed, and a lower conductive pattern 137 may be formed on the first conductive via 129. Next, an insulating structure 130 may be formed on the wiring region 120.

[0068] The planarization process may be, but is not limited to, removing the first metal layer 129a and the first barrier layer 129b on the upper surface of the intermediate insulating layer 128 to form the first conductive via 129. The planarization process may be omitted to manufacture the semiconductor device 100e of FIG 8 or the semiconductor device 100f of FIG 9.

[0069] The lower conductive pattern 137 may be formed by forming a lower metal layer 137a on the intermediate insulating layer 128, forming a lower anti-reflective layer 137b on the lower metal layer 137b, and then performing a photolithography process and an etching process. The lower conductive pattern 137 may be formed by the same or similar process as the upper conductive pattern 150 described below, so that the same or similar process for forming the upper conductive pattern 150 described below may be applied. The lower conductive patterns 137 may be located in the device region DR and the edge region ER, and at least one of the lower conductive patterns 137 may be electrically connected to each of the lower wirings 126.

[0070] The insulating structure 130 may be formed on the wiring region 120. The insulating structure 130 may include a first upper insulating layer 132, a second upper insulating layer 134, and a third upper insulating layer 136, and a lower conductive pattern 137 may be disposed in the insulating structure 130. The lower conductive pattern 137 may be covered by the first upper insulating layer 132. According to an exemplary embodiment, a portion of the second upper insulating layer 134 that vertically overlaps with the lower conductive pattern 137 may protrude upward. The second upper insulating layer 134 may include a material having an etch selectivity with respect to the first upper insulating layer 132. For example, the first upper insulating layer 132 may include a high density plasma (HDP) oxide. The second upper insulating layer 134 may include a silicon nitride, a silicon oxynitride, a silicon carbonitride, or a combination thereof. In one embodiment, the third upper insulating layer 136 may include a silicon oxide. For example, the third upper insulating layer 136 may include TetraEthyl OrthoSilicate (TEOS). The lower conductive pattern 137 may form wiring extending in a horizontal direction and pads connected to the wiring.

[0071] Referring to FIG. 17, a second via hole VH2 may be formed vertically through the insulating structure 130, and a second barrier layer 138b may be formed in the second via hole VH2.

[0072] The second via hole VH2 may be formed using a dry etching method, a wet etching method, a laser drilling method, or a mechanical drilling method. The second barrier layer 138b may be formed on the lower surface and the side surface of the second via hole VH2 with a uniform thickness. According to an exemplary embodiment, the second upper portion 138b2 of the second barrier layer 138b may be formed to cover the third upper insulating layer 136. For example, the second upper portion 138b2 of the second barrier layer 138b may be formed on the upper surface of the third upper insulating layer 136. However, without being limited thereto, the second barrier layer 138b may not cover the upper surface of the third upper insulating layer 136, or may be removed from the upper surface of the third upper insulating layer 136, and may be formed in the second via hole VH2. The first upper portion 138b1 of the second barrier layer 138b may be formed to surround the lower surface and the side surface of the second via hole VH2. In this case, the semiconductor device 100b of FIG. 5 may be manufactured. The second barrier layer 138b can be formed by a PVD process, a CVD process, or an ALD process.

[0073] Referring to FIG. 18, a second metal layer 138a may be formed to fill the second via hole VH2.

[0074] The second metal layer 138a may be formed to fully fill the second via hole VH2. For example, the upper vertical portion 138a1 of the second metal layer 138a may fill the inside of the second via hole VH2. According to an exemplary embodiment, the upper horizontal portion 138a2 of the second metal layer 138a may be formed to cover the second barrier layer 138b on the third upper insulating layer 136. However, without being limited thereto, the second metal layer 138a may be formed to cover the upper surface of the third upper insulating layer 136 after the second barrier layer 138b on the upper surface of the third upper insulating layer 136 is removed by a planarization process, and may be formed to fully fill the second via hole VH2. In this case, the second metal layer 138a may contact the upper surface of the third upper insulating layer 136, and the semiconductor device 100b of FIG. 5 may be manufactured. The second metal layer 138a may be formed by a PVD process, a CVD process, or an ALD process. When the second metal layer 138a is formed thick, the semiconductor device 100a of FIG. 4 can be manufactured.

[0075] Next, if there is a step on the top surface of the second metal layer 138a, i.e., if there is a step on the top surface of the upper horizontal portion 138a2 of the second metal layer 138a, a planarization process may be selectively performed to remove the step on the top surface of the second metal layer 138a. According to an exemplary embodiment, a buffing CMP may be performed.

[0076] Referring to FIG. 19, an upper metal layer 150a may be formed on the second metal layer 138a and an upper anti-reflective layer 150b may be formed on the upper metal layer 150a.

[0077] The upper metal layer 150a and the upper anti-reflection layer 150b can be formed by a PVD process, a CVD process, or an ALD process. The thickness of the upper metal layer 150a can be formed to be greater than the thickness of the second metal layer 138a on the insulating structure 130 (and in particular, greater than the thickness of the upper horizontal portion 138a2), ​​but is not limited thereto.

[0078] 6, before forming the upper metal layer 150a on the second metal layer 138a, an upper barrier layer 151 may be formed on the second metal layer 138a. The upper barrier layer 151 may be disposed between an upper surface of the second metal layer 138a and a lower surface of the upper metal layer 150a. The upper barrier layer 151 may include Ti, TiN, Ta, TaN, WN, or a combination thereof.

[0079] To manufacture the semiconductor device 100d of FIG. 7, an oxide layer 152 may be formed before forming the upper anti-reflection layer 150b on the upper metal layer 150a. The oxide layer 152 may be formed to a uniform thickness. The oxide layer 152 may include a conductive metal oxide, for example, aluminum (Al) oxide. The oxide layer 152 may be formed by, but is not limited to, a PVD process, a CVD process, or an ALD process.

[0080] Referring to FIG. 20, a photoresist pattern 200 may be formed on the upper anti-reflective layer 150b.

[0081] In some embodiments, a photoresist layer may be formed on the upper anti-reflective layer 150b to form the photoresist pattern 200. Next, the photoresist layer may be irradiated with light to perform an exposure and development process, and the photoresist pattern 200 may be formed to define an area where a pattern is to be formed using a photomask. When irradiated with light, the upper metal layer 150a may be protected by the upper anti-reflective layer 150b.

[0082] 21, the upper metal layer 150a, the upper anti-reflective layer 150b, the second metal layer 138a, and the second barrier layer 138b may be patterned using the photoresist pattern 200 as an etching mask, thereby forming the upper conductive pattern 150.

[0083] After the etching process, the photoresist pattern 200 may be removed by an ashing and stripping process. The upper anti-reflective layer 150b may include the same metal element as the upper metal layer 150a, but is not limited to this.

[0084] 22, a protective layer 160 may be formed to cover the second barrier layer 138b, the insulating structure 130, and the upper conductive pattern 150. The protective layer 160 may be conformally formed along the second barrier layer 138b, the insulating structure 130, and the upper conductive pattern 150. The protective layer 160 may include the same material as the third upper insulating layer 136, for example, TEOS. According to an exemplary embodiment, the boundary between the protective layer 160 and the third upper insulating layer 136 may not be identified, and the protective layer 160 may be integrally connected to the third upper insulating layer 136.

[0085] After the protective layer 160 is formed, the wiring region 120, the insulating structure 130, the second barrier layer 138b, and the protective layer 160 may be separated from one another with the top surface of the device region 110 exposed therebetween. The sides of the wiring region 120, the insulating structure 130, the second barrier layer 138b, and the protective layer 160 and the top surface of the device region 110 may define a trench T. The trench T may extend horizontally to surround the device region DR and the edge region ER. According to other embodiments, the trench T may not completely cut through the wiring region 120.

[0086] 23, an insulating material layer 164p may be formed to cover the protective layer 160. The insulating material layer 164p may fill spaces between the upper conductive patterns 150 and completely cover the upper conductive patterns 150. The insulating material layer 164p may include silicon oxide, and in one embodiment, may include TEOS. In one embodiment, the insulating material layer 164p may not have a flat top surface, for example, a portion corresponding to the upper conductive pattern 150 may protrude.

[0087] 24, a planarization process may be performed, and the insulating material layer 164p may be etched to form the first passivation layer 164. The planarization process may include a chemical mechanical polishing (CMP) process. For example, a CMP process may be performed starting from the top of the insulating material layer 164p, and the insulating material layer 164p may be etched. As a result, the first passivation layer 164 may be formed, and the top surface of the first passivation layer 164 may be flat.

[0088] 25, a second passivation layer 168 may be formed on the first passivation layer 164. The second passivation layer 168 may be conformally formed along the first passivation layer 164 and the trench T. The protective layer 160, the first passivation layer 164, and the second passivation layer 168 may form a passivation structure P. The passivation structure P may cover the inner wall of the trench T formed along the cutting region CR. The second passivation layer 168 may include silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. For example, the second passivation layer 168 may include silicon nitride.

[0089] 26, the protective layer 160, the first passivation layer 164, and the second passivation layer 168 may be partially etched to form an opening OP. At least one of the upper conductive patterns 150 may be exposed by the opening OP. The term "exposed" may be used to describe relationships between elements and / or intermediate steps in creating a finished semiconductor device, but does not necessarily require exposure of particular regions, layers, structures, and other elements in the context of the finished device.

[0090] 3a and 3b, the semiconductor substrate 102 may be separated from the lower interlayer insulating layer 116, the first passivation layer 164, and the second passivation layer 168 by a dicing process to form the semiconductor device 100. A laser may be irradiated onto the rear surface of the semiconductor substrate 102. For example, a thin film tape (not shown) may be attached to the semiconductor substrate 102, and a laser may be irradiated onto a portion of the semiconductor substrate 102 in a cutting region CR. The physical properties of the semiconductor substrate 102 may change at the laser spot where the laser is irradiated, for example, the physical strength of the semiconductor substrate 102 may be weakened. The thin film tape attached to the semiconductor substrate 102 may be extended in the horizontal direction, and the semiconductor substrate 102 may be separated along the cutting region CR. Alternatively, in some embodiments, the dicing process may be a process of cutting the semiconductor substrate 102 using a sawing wheel.

[0091] Spatial terms such as "top," "upper," "top surface," "bottom," "lower," "underside," and the like may be used with reference numerals to refer to the drawings unless otherwise indicated. It should be understood that such spatial terms are intended to encompass different orientations of an element in use or operation in addition to the orientation of the element depicted in the drawings. For example, an element described as "below" another element or feature would be oriented "above" that other element if the element in the drawings were flipped over. Thus, the term "below" may encompass both an orientation of above and below. Elements may be oriented in other directions (rotated 90 degrees or otherwise) and the spatial descriptors used herein may be interpreted accordingly.

[0092] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications and changes can be made by a person skilled in the art without departing from the technical spirit of the present invention described in the claims, and these also belong to the scope of the present invention. [Explanation of symbols]

[0093] 102: Semiconductor substrate 110: Element area 120: Wiring area 129: First conductive via 130: Insulating structure 132: First upper insulating layer 134: second upper insulating layer 136: Third upper insulating layer 137: Lower conductive pattern 138: second conductive via 150: Upper conductive pattern P: Passivation structure 160:Protective layer 164: First passivation layer 168: Second passivation layer 170:Through electrode 180: Lower passivation layer 190: Via Pad

Claims

1. A semiconductor substrate; a device region on the semiconductor substrate; a wiring region including lower wiring on the element region; an insulating structure on the wiring region; a lower conductive pattern within the insulating structure; a first conductive via electrically connecting at least one of the lower conductive patterns to the lower wiring in the wiring region; an upper conductive pattern on the insulating structure; a second conductive via in the insulating structure electrically connecting the upper conductive pattern to at least one of the lower conductive patterns; the first conductive via includes a first metal layer and a first barrier layer on a bottom surface and a side surface of the first metal layer; the second conductive vias each include a second metal layer within the insulating structure and a second barrier layer on a bottom surface and a side surface of the second metal layer; The upper conductive patterns each include a third barrier layer extending from the second barrier layer and overlying a portion of an upper surface of the insulating structure opposite the semiconductor substrate; a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer; a top metal layer on the third metal layer; and an upper antireflective layer on the upper metal layer.

2. The semiconductor device of claim 1 , wherein a thickness of the top metal layer is greater than a thickness of the third metal layer on the top surface of the insulating structure.

3. 2. The semiconductor device of claim 1, wherein a thickness of the top metal layer is substantially the same as or less than a thickness of the third metal layer on the top surface of the insulating structure.

4. The insulating structure includes: a first upper insulating layer on a side surface and an upper surface of the lower conductive pattern; a second upper insulating layer on the first upper insulating layer; a third upper insulating layer on the second upper insulating layer; The semiconductor device of claim 1 , wherein a material of the second upper insulating layer is different from a material of the first and third upper insulating layers.

5. The semiconductor device of claim 1 , wherein each of the upper conductive patterns further comprises an upper barrier layer between the upper metal layer and the third metal layer.

6. further comprising an intermediate insulating layer between the wiring region and the insulating structure; 2. The semiconductor device of claim 1, wherein the lower conductive pattern includes the first barrier layer on a portion of the upper surface of the intermediate insulating layer, the first metal layer on the first barrier layer on a portion of the upper surface of the intermediate insulating layer, a lower metal layer on the first metal layer, and a lower anti-reflective layer on the lower metal layer, stacked in sequence on the upper surface of the intermediate insulating layer.

7. The semiconductor device of claim 6 , wherein a thickness of the lower metal layer is greater than a thickness of the first metal layer on the top surface of the intermediate insulating layer.

8. 7. The semiconductor device of claim 6, wherein a thickness of the lower metal layer is substantially the same as or less than a thickness of the first metal layer on the top surface of the intermediate insulating layer.

9. 2. The semiconductor device of claim 1, wherein the top metal layer and the second metal layer comprise different materials, and the third metal layer and the second metal layer are contiguous parts of a single structure.

10. the upper metal layer comprises aluminum (Al); The semiconductor device of claim 9 , wherein the second metal layer comprises tungsten (W).

11. The semiconductor device of claim 1 , wherein a thickness of each of the upper conductive patterns is greater than a thickness of each of the lower conductive patterns.

12. a protective layer overlying the insulating structure and the upper conductive pattern; a first passivation layer on the protective layer; The semiconductor device of claim 1 , further comprising a second passivation layer on the first passivation layer.

13. The semiconductor device of claim 1 , further comprising a via pad under the semiconductor substrate, and a through electrode electrically connected to the via pad and passing through the semiconductor substrate.

14. The semiconductor device of claim 1 , wherein the upper metal layer is spaced apart from the top surface of the insulating structure with the third metal layer and the third barrier layer interposed therebetween.

15. The semiconductor device of claim 1 , wherein each of the upper conductive patterns further comprises an oxide layer between the upper metal layer and the upper anti-reflective layer.

16. A plurality of semiconductor elements sequentially stacked on a buffer chip; an adhesive layer between the semiconductor elements; an encapsulant over the buffer chip and the plurality of semiconductor elements; The semiconductor elements each include an insulating structure on a semiconductor substrate; a via pad underlying the semiconductor substrate; a through electrode electrically connected to the via pad and passing through the semiconductor substrate; a lower conductive pattern within the insulating structure; a first conductive via on a lower surface of the lower conductive pattern; an upper conductive pattern on the insulating structure; a second conductive via within the insulating structure, electrically connecting the upper conductive pattern to at least one of the lower conductive patterns; a connection pad electrically connected to one of the upper conductive patterns, the first conductive vias each include a first metal layer and a first barrier layer on a bottom surface and a side surface of the first metal layer; the second conductive vias each include a second metal layer within the insulating structure and a second barrier layer on a bottom surface and a side surface of the second metal layer; The upper conductive patterns each include a third barrier layer extending from the second barrier layer and overlying a portion of a top surface of the insulating structure; a third metal layer on the third barrier layer and the second metal layer and extending from the second metal layer; a top metal layer on the third metal layer; and an upper anti-reflective layer on the upper metal layer.

17. further comprising an intermediate insulating layer between the semiconductor substrate and the insulating structure; 17. The semiconductor package of claim 16, wherein the lower conductive pattern includes the first barrier layer covering a portion of the upper surface of the intermediate insulating layer, the first metal layer covering the first barrier layer on the intermediate insulating layer, a lower metal layer on the first metal layer, and a lower anti-reflective layer on the lower metal layer, stacked sequentially on the upper surface of the intermediate insulating layer.

18. an insulating structure on a semiconductor substrate; a lower conductive pattern within the insulating structure; a first conductive via on a lower surface of the lower conductive pattern; an upper conductive pattern on the insulating structure; a second conductive via in the insulating structure electrically connecting the upper conductive pattern to the lower conductive pattern; the first conductive vias each include a first metal layer and a first barrier layer on a bottom surface and a side surface of the first metal layer; each of the second conductive vias includes a second metal layer within the insulating structure and a second barrier layer covering a bottom surface and a side surface of the second metal layer; The upper conductive pattern is a first conductive layer extending from the second conductive via; a second conductive layer on the first conductive layer; a third conductive layer on the second conductive layer.

19. a passivation structure on the insulating structure and the upper conductive pattern; an opening through the passivation structure exposing the upper conductive pattern; 20. The semiconductor device of claim 18, further comprising a connection pad disposed within the opening and electrically connected to the upper conductive pattern.

20. 20. The semiconductor device of claim 18, wherein the first conductive layer comprises a third metal layer that is continuously extended from the second metal layer and a third barrier layer that is continuously extended from the second barrier layer.

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