Gate driver stage and method for operating the same

Abstract

To overcome the disadvantages of a field effect transistor.SOLUTION: A gate driver stage (100) includes a first power transistor (101) and a second power transistor (102). A first source terminal is connected to a second drain terminal. A first drain terminal is connected to a first voltage terminal (103). A second source terminal is connected to a second voltage terminal (104). A second voltage value is lower than a first voltage value. A node (105) is disposed between the first power transistor (101) and the second power transistor (102). The node (105) is connected to a third gate terminal of a normally-off power transistor (109). The third gate terminal is controllable via the node (105). The node (105) is connected to a third voltage terminal (110). A third voltage value is between the first and second voltage values.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a gate driver stage and a method for operating a gate driver stage. [Background technology]

[0002] Field effect transistors can have instabilities during gate switching due to the device switching between voltages significantly above the threshold voltage and below the flat band voltage during operating modes, which can adversely affect the conductive path of the device.

[0003] In vehicle inverters, normally-off SiC-MOSFETs are usually used as switches. Normally-off SiC-MOSFETs are turned off when a negative voltage is applied. Here, when the SiC-MOSFET operates, it switches between a positive gate voltage and a negative gate voltage.

[0004] The drawback here is that the threshold voltage may increase over time. This can be prevented by turning off the SiC MOSFET at 0V.

[0005] However, the drawback here is that the SiC MOSFET can turn on again unintentionally, i.e. the so-called parasitic turn-on. The object of the present invention is to overcome these drawbacks. Summary of the Invention

[0006] The gate driver stage includes a first power transistor and a second power transistor. The first power transistor has a first drain terminal and a first source terminal. The second power transistor has a second drain terminal and a second source terminal. The first source terminal is conductively connected to the second drain terminal. The first drain terminal is conductively connected to a first voltage terminal, and the second source terminal is conductively connected to a second voltage terminal. The first voltage terminal has a first voltage value, and the second voltage terminal has a second voltage value, the second voltage value being lower than the first voltage value. A node is disposed between the first power transistor and the second power transistor, the node is conductively connected to a third gate terminal of the normally-off power transistor, and the third gate terminal is controllable via the node. According to the present invention, the node is conductively connected to the third voltage terminal, the third voltage terminal has a third voltage value, and the third voltage value is between the first voltage value and the second voltage value.

[0007] The advantage here is that the threshold voltage of the driven power transistor is stable in the long term and parasitic turn-on of the power transistor is prevented. In a further development, the third voltage value depends on the drain-source leakage current of the normally-off power transistor.

[0008] Here, the advantage is that an optimum voltage can be used so that the third voltage value only needs to be applied for a short period of time to avoid or significantly reduce gate voltage instability. In a further aspect, the third voltage value depends on a temperature of the normally-off power transistor.

[0009] In a further development, the voltage value is a fixed value in the range between 0V and the threshold voltage of the normally-off power transistor. The advantage here is that the switching process of the controlled power transistors is low loss.

[0010] In a further development, a parallel circuit is arranged between the node and the third gate terminal, the parallel circuit comprising a first resistor, a second resistor, a first diode, and a second diode, the first resistor and the first diode being connected in parallel to the second resistor and the second diode, and the second diode having a forward direction opposite to that of the first diode.

[0011] It is advantageous here that the switching processes in the controlled power transistor are controllable, in other words oscillations of the controlled power transistor are prevented. In a further embodiment, the normally-off power transistor is a SiC MOSFET.

[0012] A gate driver stage including a first power transistor including a first drain terminal and a first source terminal, a second power transistor including a second drain terminal and a second source terminal, the first source terminal is conductively connected to a second drain terminal, the first drain terminal is conductively connected to a first voltage terminal, the second source terminal is conductively connected to a second voltage terminal, the first voltage terminal has a first voltage value, the second voltage terminal has a second voltage value, the second voltage value being lower than the first voltage value, a node is disposed between the first power transistor and the second power transistor, A method for operating a gate driver stage, in which a node is conductively connected to a third gate terminal of a normally-off power transistor, the third gate terminal being controllable via a node, the node being conductively connected to a third voltage terminal, the third voltage terminal having a third voltage value, the third voltage value being between a first voltage value and a second voltage value, and the first power transistor, the second power transistor, and the normally-off power transistor being turned off, according to the present invention includes turning on the second power transistor at a first time, the method further includes turning off the second power transistor at a second time, and turning on the first power transistor at a third time.

[0013] Here, the advantage is that the voltage of the third gate terminal is adjustable. In a further development, a drain-source leakage current of the normally-off power transistor is sensed by means of a current-sense terminal and the third voltage value is adjusted in dependence on the drain-source leakage current of the normally-off power transistor.

[0014] Here, the third voltage value is advantageously optimally adjustable. In a further embodiment, a temperature sensor detects a temperature of the normally-off power transistor, and the third voltage value is adjusted in dependence on the temperature of the normally-off power transistor.

[0015] Further advantages become apparent from the following description of exemplary embodiments and the dependent claims. The present invention will now be described with reference to preferred embodiments and the accompanying drawings. [Brief description of the drawings]

[0016] [Figure 1] FIG. 2 shows a gate driver stage according to the present invention. [Diagram 2] FIG. 2 illustrates a method for operating a gate driver according to the present invention. [Diagram 3] FIG. 2 shows the voltage waveform according to the present invention at the gate of a normally-off power transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] FIG. 1 shows a gate driver stage 100 comprising a first power transistor 101 and a second power transistor 102. The first power transistor 101 comprises a first drain terminal and a first source terminal. The second power transistor 102 comprises a second drain terminal and a second source terminal. The first source terminal and the second drain terminal are conductively connected, i.e. the first power transistor 101 and the second power transistor 102 are connected in series. The first drain terminal is connected to a first voltage terminal 103 having a first voltage value. The second source terminal is connected to a second voltage terminal 104 having a second voltage value, where the second voltage value is smaller than the first voltage value. A node 105 is arranged between the first power transistor 101 and the second power transistor 102. The node 105 is conductively connected to a third gate terminal of a normally-off power transistor 109 (e.g. a SiC-MOSFET). This means that the third gate terminal is controllable via node 105. Node 105 is also conductively connected to a third voltage terminal 110, which has a third voltage value, which is between the first and second voltage values. In other words, the third gate terminal is driven by three voltage levels. The intermediate voltage or the third voltage value is used just before switching on or turning on the normally-off power transistor 109, charging the interface state with electrons and reducing the positive interface charge. This reduces the electric field after switching on at the interface, thereby reducing the threshold voltage drift, the so-called gate switching instability, or GSI for short.

[0018] In one exemplary embodiment (not shown), the node 105 and the third gate terminal are directly connected by a line. In another exemplary embodiment (not shown), a resistor is arranged between the node 105 and the third gate terminal. This arrangement turns on the power transistor 109 slowly, so that no oscillation occurs during the switching process. In a further exemplary embodiment, as shown in FIG. 1, a parallel circuit 106 having a first resistor 111, a second resistor 113, a first diode 112, and a second diode 114 is arranged between the node 105 and the third gate terminal, where the first resistor 111 and the first diode 112 are connected in parallel with the second resistor 113 and the second diode 114, and the second diode 114 has a forward direction opposite to that of the first diode 112. This means that the first diode 112 is connected in anti-parallel with the second diode 114.

[0019] Both the resistor and the parallel circuit 106 can be implemented within the driver ASIC or as discrete elements integrated between the driver ASIC and the power transistor or power MOSFET to be controlled.

[0020] The gate driver stage according to the invention is used in the electric drive train of electric or hybrid vehicles, i.e. in DC / DC converters and inverters, and furthermore in vehicle chargers.

[0021] FIG. 2 shows a method 200 for operating a gate driver stage. In an initial state of the gate driver stage, the first power transistor, the second power transistor and the normally-off power transistor are turned off. The method 200 starts with step 210, in which the second power transistor is turned on at a first time instant. Thus, a second voltage terminal is conductively connected to the third gate terminal, to which a second voltage value is applied for a first period of time. This second voltage value is preferably negative. In a next step 220, the second power transistor is turned off at a second time instant. Thus, a third voltage terminal is conductively connected to the third gate terminal, to which a third voltage value is applied for a second period of time. This third voltage value has a fixed value, for example in the range between 0V and a threshold voltage. This value is determined by measurements on a normally-off power transistor or on a module during the manufacturing process and is set fixedly in the module or in a gate driver stage that is part of the module. Alternatively, the third voltage value has a small positive value that depends on the drain-source leakage current of the normally-off power transistor or the temperature of the normally-off power transistor. In the next step 230, the first power transistor is turned on at a third time point. Thus, the first voltage terminal is conductively connected to the third gate terminal. This first voltage value is positive and exceeds the threshold voltage, so that the third gate terminal is applied with the first voltage value for a third time period, switching or turning on the normally-off power transistor. Then the method is terminated or starts again from step 210. In other words, the gate voltage of the normally-off power transistor is adjustable in steps.

[0022] FIG. 3 shows a voltage waveform 300 generated at the third gate terminal using the method 200 of FIG. 2. On the x-axis is time and on the y-axis is the voltage value applied to the third gate terminal. In an initial state of the method for operating a gate driver stage, the first power transistor, the second power transistor and the normally-off power transistor are turned off. This means that no drain-source current flows through the normally-off power transistor. Alternatively, a small drain-source leakage current flows below a certain limit value. The certain limit value is determined by power loss or early switching on of the normally-off power transistor. The first voltage value is, for example, 18V, the second voltage value is, for example, −5V and the third voltage value is, for example, 0V. After the second power transistor turns on, a second voltage value is applied to the third gate terminal. This means that the normally-off power transistor is turned off. After the first period of time, at a second time point, the second power transistor is turned off, for example, by a control signal of a control device. Thus, a third voltage value is applied to the third gate terminal, which serves to prepare the normally-off power transistor for switching on. There is still no significant drain-source current flowing through the normally-off power transistor, but the interface state is charged with electrons. This directly influences the electric field at the interface immediately after switching on. After the second period of time, at a third time point, the first power transistor is turned on, for example by a further control signal of the control device. This turns on the normally-off power transistor and a drain-source current flows therethrough. In other words, with the aid of the intermediate voltage value used immediately before switching on of the normally-off power transistor, the interface state is charged with electrons, which reduces the electric field at the interface immediately after switching on and creates a lower threshold voltage drift. [Explanation of symbols]

[0023] 100 Gate Driver Stages 101 First power transistor 102 Second power transistor 103 First voltage terminal 104 Second voltage terminal 105 nodes 106 parallel circuit 109 Normally-off type power transistor 110 Third voltage terminal 111 First Resistor 112 First Diode 113 Second Resistor 114 Second Diode Methods for operating 200 gate driver stages 210 turning on a second power transistor at a first time 220 turning off a second power transistor at a second time 230 turning on the first power transistor at a third time 300 Voltage Waveform

Claims

1. A gate driver stage (100) comprising a first power transistor (101) having a first drain terminal and a first source terminal, and a second power transistor (102) having a second drain terminal and a second source terminal, the first source terminal being conductively connected to the second drain terminal, the first drain terminal being conductively connected to a first voltage terminal (103), and the second source terminal being conductively connected to a second voltage terminal (104), the first voltage terminal (103) having a first voltage value and the second voltage terminal (104) having a second voltage value, the second voltage value being lower than the first voltage value; a node (105) disposed between the first power transistor (101) and the second power transistor (102), the node (105) conductively connected to a third gate terminal of a normally-off power transistor (109), the third gate terminal being controllable via the node (105); the node (105) conductively connected to a third voltage terminal (110), the third voltage terminal (110) having a third voltage value, the third voltage value being between the first voltage value and the second voltage value.

2. 2. A gate driver stage (100) according to claim 1, wherein the third voltage value depends on the drain-source leakage current of the normally-off power transistor (109).

3. 3. A gate driver stage (100) according to claim 1 or 2, characterized in that the third voltage value depends on the temperature of the normally-off power transistor (109).

4. 4. A gate driver stage (100) according to any one of claims 1 to 3, characterized in that the third voltage value is a fixed value in a range between 0 V and the threshold voltage of the normally-off power transistor (109).

5. 5. The gate driver stage (100) of claim 1, wherein a parallel circuit (106) comprising a first resistor (111), a second resistor (113), a first diode (112) and a second diode (114) is arranged between the node (105) and the third gate terminal, the first resistor and the first diode being connected in parallel to the second resistor and the second diode, the second diode having an opposite forward direction to the first diode.

6. A gate driver stage (100) according to any one of claims 1 to 5, characterized in that the normally-off power transistor (109) is a SiC-MOSFET.

7. A gate driver stage comprising a first power transistor having a first drain terminal and a first source terminal, and a second power transistor having a second drain terminal and a second source terminal, the first source terminal is conductively connected to the second drain terminal, the first drain terminal is conductively connected to a first voltage terminal, the second source terminal is conductively connected to a second voltage terminal, the first voltage terminal has a first voltage value, the second voltage terminal has a second voltage value, the second voltage value is lower than the first voltage value, and 1. A method (200) for operating a gate driver stage, the gate driver stage having a node conductively connected between a first power transistor and a second power transistor, the node conductively connected to a third gate terminal of a normally-off power transistor, the third gate terminal being controllable via the node, the node conductively connected to a third voltage terminal, the third voltage terminal having a third voltage value, the third voltage value being between the first voltage value and the second voltage value, the first power transistor, the second power transistor, and the normally-off power transistor being turned off, turning on the second power transistor at a first time (210); turning off the second power transistor at a second time (220); turning on the first power transistor at a third time (230); The method (200).

8. 8. The method (200) for operating a gate driver stage as claimed in claim 7, characterized in that a current-sense terminal detects a drain-source leakage current of the normally-off power transistor, and the third voltage value is adjusted in dependence on the drain-source leakage current of the normally-off power transistor.

9. 9. The method (200) for operating a gate driver stage according to claim 7 or 8, characterized in that by means of a temperature sensor a temperature of the normally-off power transistor is detected and the third voltage value is adjusted in dependence on the temperature of the normally-off power transistor.

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