Display device

Abstract

To provide: a display device with reduced alignment defect; a display device including a capacitive element with a high numerical aperture and enhanced charge capacity; and a display device including a capacitive element with a high numerical aperture, large charge capacity, but with reduced alignment defect.SOLUTION: The display device comprises: a pixel electrode; a transistor including a translucent semiconductor layer connected to the pixel electrode; a capacitive element connected to the transistor; a scan line; and a data line. The transistor is arranged in a position overlapping the scan line, one electrode of the capacitive element is formed on the same front face as the semiconductor layer and formed on a region zoned by the scan line and the data line. The other electrode of the capacitive element is the pixel electrode and arranged extending to intersect the scan line.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification and elsewhere relates to a display device and an electronic device having the display device. [Background technology]

[0002] In recent years, the use of liquid crystal displays and other Flat panel displays are becoming more and more popular. In the display device, a switching element is provided in each pixel arranged in the row and column directions. A transistor, a liquid crystal element electrically connected to the transistor, and a liquid crystal element in parallel with the liquid crystal element A connected capacitive element is provided.

[0003] The semiconductor material constituting the semiconductor film of the above transistor is amorphous (non-crystalline) Silicon semiconductors such as silicon or polysilicon (polycrystalline) are widely used.

[0004] Metal oxides that exhibit semiconductor properties (hereinafter, referred to as oxide semiconductors) are used in transistors. It is a semiconductor material that can be applied to the semiconductor film of the following: zinc oxide or In-Ga-Zn system oxide Techniques for fabricating transistors using nitride semiconductors have been disclosed (Patent Document 1 and Patent Document 2). (See patent document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] In liquid crystal displays, alignment defects are likely to occur if there are large unevenness such as steps around pixels. The alignment defect occurs, for example, in the vicinity of the scanning line and data line connected to the transistor and the pixel electrode. This is likely to occur along the edges of the step. It is necessary to cover a part of the display with a light-shielding film (also called a black matrix, BM). The aperture ratio of the pixel is reduced, and the display quality of the image is degraded.

[0007] In order to reduce the above-mentioned alignment defects, unevenness such as steps caused by transistors, etc. is effectively The surface is often flattened using a resin or similar material.

[0008] However, when an oxide semiconductor is used as a semiconductor material for a transistor, When impurities (typically moisture) contained in the organic resin are absorbed into the oxide semiconductor, Since organic resins have a negative effect on semiconductor characteristics, semiconductor devices are manufactured using structures that do not use organic resins as much as possible. There was a problem with wanting to manufacture it.

[0009] In addition, the capacitance element used in the liquid crystal display has a dielectric film provided between a pair of electrodes. At least one of the pair of electrodes is a gate electrode constituting a transistor. In many cases, the source electrode or the drain electrode is formed of a conductive film.

[0010] In addition, the larger the capacitance of the capacitance element, the more the liquid crystal element will dissipate when an electric field is applied. The period during which the orientation of the crystal molecules can be kept constant can be extended. In a display device in which the period can be extended, the number of times image data is rewritten can be reduced. This makes it possible to reduce power consumption.

[0011] In order to increase the charge capacity of the capacitance element, the area occupied by the capacitance element is increased. However, there is a method for increasing the area where the pair of electrodes overlap. In a display device, the area of ​​a conductive film is increased in order to increase the area where a pair of electrodes overlap. If the pixel aperture is increased, the pixel aperture ratio decreases, and the image display quality decreases.

[0012] In addition, when the area occupied by the capacitive element is increased, the area of ​​the recess in the pixel becomes large. If a flattening process is not performed using an organic resin or the like, the concave portions will cause poor alignment of the liquid crystal. It gives birth.

[0013] In view of the above problems, one embodiment of the present invention is to provide a display device in which alignment defects are reduced. Another object of one embodiment of the present invention is to provide a semiconductor device having a high aperture ratio and an increased charge capacity. Another object of the present invention is to provide a display device having a capacitor. Display device having high aperture ratio, large charge capacity, and reduced alignment defects - Patents.com One of our goals is to provide the following: [Means for solving the problem]

[0014] One embodiment of the present invention includes a pixel electrode and a light-transmitting semiconductor layer connected to the pixel electrode. A transistor, a capacitance element, a scanning line, and a data line connected to the transistor. The transistor is disposed in a position overlapping with the scan line, and one electrode of the capacitor is a semiconductor a capacitance element formed on the same surface as the layer and in an area partitioned by the scanning lines and the data lines; The other electrode is a pixel electrode, and the pixel electrode is arranged so as to extend and cross the scanning line. The display device is characterized in that

[0015] The pixel electrodes are arranged so as to extend and cross the scanning lines, so that, for example, Approximately half of the pixels are located in an area defined by the scan lines and the data lines, and the other half are located in an area defined by the adjacent The pixel electrodes can be located in an area defined by the scanning lines and the data lines. Therefore, since the end of the pixel electrode is located away from the scanning line, the liquid crystal layer is prevented from being affected by the scanning line. Therefore, the scanning line Therefore, it is possible to reduce the alignment defects of the liquid crystal layer caused by the above-mentioned problems.

[0016] Note that a manufacturing method of a display device according to one embodiment of the present invention is also described. Included. Effect of the Invention

[0017] According to one embodiment of the present invention, a display device in which alignment defects are reduced can be provided. It is therefore possible to provide a display device having a capacitive element with a high aperture ratio and an increased charge capacity. In addition, the display device has a high aperture ratio, a capacitance element with a large charge capacity, and reduced alignment defects. It is possible to provide a display device having such a structure. [Brief description of the drawings]

[0018] [Figure 1] FIG. 2 is a top view illustrating a pixel and its periphery in a display device according to one embodiment of the present invention. [Diagram 2] FIG. 1 is a cross-sectional view illustrating a pixel of a display device according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional view illustrating a pixel of a display device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a pixel of a display device according to one embodiment of the present invention. [Diagram 5]FIG. 1 is a cross-sectional view illustrating a pixel of a display device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 9] FIG. 13 is a top view illustrating the periphery of a pixel of a display device for comparison. [Figure 10] FIG. 11 is a cross-sectional view illustrating a pixel of a display device for comparison. [Figure 11] FIG. 11 is a cross-sectional view illustrating a pixel of a display device for comparison. [Figure 12] FIG. 11 is a cross-sectional view illustrating a pixel of a display device for comparison. [Figure 13] FIG. 1 is a circuit diagram illustrating a display device. [Figure 14] FIG. 2 is a diagram illustrating a display module. [Figure 15] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and it is understood by those skilled in the art that various modifications may be made to the modes and details. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0020] In the configuration of the present invention described below, the same parts or parts having similar functions are designated by the same reference numerals. The same reference numerals are used in different drawings, and the repeated explanations are omitted. When referring to a part having a function, the hatch pattern is the same and no symbol is attached. be.

[0021] In each figure described in this specification, the size of each structure, the thickness of the film, or the area is not shown for the sake of clarity. The figures may be exaggerated for illustrative purposes and are not necessarily limited to that scale.

[0022] In this specification and elsewhere, ordinal numbers such as 1st, 2nd, etc. are used for convenience. Therefore, for example, "first" may be changed to "second" or " " can be appropriately replaced with "the third" etc. The ordinal numbers used to identify an aspect of the present invention may not match those used in the present invention. be.

[0023] In addition, the function of the "source" and "drain" in the present invention is to control the flow of current during circuit operation. In cases where the direction is changed, the positions may be reversed. The terms "source" and "drain" may be used interchangeably.

[0024] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described with reference to FIGS. The following explanation is provided.

[0025] <Example of display device configuration> FIG. 1 shows a top view of the periphery of a pixel in a display device. In order to avoid complicating the drawings, some of the components are omitted.

[0026] In FIG. 1, the scanning lines 107 are arranged in a direction substantially perpendicular to the data lines 109 (the left-right direction in the figure). The data lines 109 extend in a direction substantially perpendicular to the scanning lines 107 (up and down in the figure). The capacitance line 115 extends in a direction substantially parallel to the data line 109. It is set up as such.

[0027] The transistor 103 is formed at a position overlapping the scanning line 107. The transistor 103 is provided near the area where the data lines 109 intersect. A semiconductor layer 111 having a channel formation region, a gate electrode, and a gate insulating layer (shown in FIG. 1) are provided. The semiconductor device includes a gate insulating film (not shown), a source electrode, and a drain electrode.

[0028] The scanning line 107 also functions as the gate electrode of the transistor 103, and the data line 1 The conductive layer 113 also functions as a source electrode of the transistor 103. It functions as a drain electrode of the photodiode 103 and is electrically connected to the pixel electrode 121 through the opening 117. In the following description, when the gate electrode of the transistor 103 is indicated, The source electrode of the transistor 103 is also referred to as the data line. It may be written as 109.

[0029] The capacitor 105 is formed using a light-transmitting oxide semiconductor. The semiconductor layer 119 has a higher conductivity than the semiconductor layer 111 that is adjacent to the semiconductor layer 119, and the pixel electrode 12 has a light-transmitting property. 1, and a light-transmitting insulating layer (see FIG. 1) included in the transistor 103 as a dielectric layer. That is, the capacitor 105 has a light-transmitting property. The line 115 is provided on the semiconductor layer 119 so as to be in contact with the semiconductor layer 119. 119 is electrically connected.

[0030] In addition, in FIG. 1, the pixel 101 is arranged so that the scanning line 107 is located in the center. In the area defined by the scanning line 107 and the data line 109, approximately half of two different pixels are The semiconductor layer 119 which is one electrode of the capacitor 105 is formed on the transistor. The semiconductor layer 111 constituting the resistor 103 is formed on the same surface as the scanning line 107 and the data line. The pixel electrode 105 is formed in an area partitioned by the capacitance line 109. The electrodes 121 are provided so as to extend and intersect with the scanning lines 107 .

[0031] Here, the cross-sectional shape of the pixel 101 in the long side direction is taken along the dashed line X1-X2 shown in FIG. 2 shows cross-sectional views taken along dashed lines X3-X4 and X5-X6. Regarding the cross-sectional shape of the pixel 101 in the short side direction, the area between the dashed dotted line Y1-Y2 shown in FIG. A cross-sectional view is shown in FIG. Regarding the cross-sectional shape of the conductor, the area between the dashed dotted lines A1-A2, A3-A4, and A cross-sectional view taken along dashed line A5-A6 is shown in FIG.

[0032] The cross-sectional structure of the display device shown in FIG. 2 is as follows.

[0033] A scanning line 107 is provided on a substrate 102. An insulating layer 127 is provided on the scanning line 107. A pair of semiconductor layers 119 is provided on the insulating layer 127. A conductive layer 113 is provided on the insulating layer 127 at a position where the conductive layer 113 overlaps the scanning line 107. 27, insulating layers 129 and 131 are provided over the semiconductor layer 119 and the conductive layer 113. The insulating layers 129 and 131 are formed so as to cover one end of the semiconductor layer 119. In addition, an insulating layer 133 is provided so as to cover the semiconductor layer 119 and the insulating layer 131. In addition, a pixel electrode 121 is provided on the insulating layer 133 at a position where it overlaps with the semiconductor layer 119. In addition, an alignment film 135 is provided on the insulating layer 133 and the pixel electrodes 121.

[0034] The cross-sectional structure of the display device shown in FIG. 4 is as follows.

[0035] An insulating layer 127 is provided on the substrate 102. In addition, the data line 10 is provided on the insulating layer 127. 9 and a semiconductor layer 119 are provided. The capacitor line 115 is provided. In addition, the insulating layer 127, the data line 109, the capacitor line 115, Insulating layers 129 and 131 are provided on the semiconductor layer 119. 1 is formed so as to cover the end of the semiconductor layer 119. Also, the semiconductor layer 119 and the insulating layer An insulating layer 133 is provided to cover the layer 131. A pixel electrode 121 is provided at a position overlapping with the insulating layer 133 and the pixel electrode 121. An alignment film 135 is provided on the element electrodes 121 .

[0036] The cross-sectional structure of the display device shown in FIG. 5 is as follows.

[0037] A scanning line 107 that functions as a gate electrode of a transistor 103 is provided on a substrate 102. An insulating layer 102 serving as a gate insulating layer of the transistor 103 is formed on the scan line 107. A semiconductor layer 111 is provided at a position on the insulating layer 127 where the semiconductor layer 111 overlaps the scanning line 107. The semiconductor layer 111 functions as a semiconductor layer of the transistor 103. In addition, a semiconductor layer 119 formed in the same process as the semiconductor layer 111 is provided on the insulating layer 127. In addition, a source electrode of the transistor 103 is provided on the semiconductor layer 111 and the insulating layer 127. A data line 109 serving as an electrode and a drain electrode of the transistor 103 A conductive layer 113 is provided over the semiconductor layer 119. A capacitor line 115 is provided over the semiconductor layer 119. In addition, the data line 109, the semiconductor layer 111, the semiconductor layer 119, and the insulating layer 127 Insulating layers 129 and 131 that function as protective insulating layers for the transistor 103 are provided thereon. The insulating layers 129 and 131 are arranged so that a part of the end portion thereof covers the end portion of the semiconductor layer 119. In addition, a metal film is formed so as to cover the insulating layer 131, the semiconductor layer 119, and the capacitance line 115. An insulating layer 133 is formed on the insulating layers 129, 131, and 133. An opening 117 is provided so as to reach the insulating layer 133. The pixel electrode 1 is disposed on the opening 117 and the insulating layer 133. An alignment film 135 is provided on the insulating layer 133 and the pixel electrodes 121. It is being done.

[0038] In addition, in the display device shown in FIG. 2, FIG. 4, and FIG. 5, a substrate 152 is provided opposite to the substrate 102. A liquid crystal layer 164 is sandwiched between the substrate 102 and the substrate 152. Below the substrate 152, there are a light-shielding layer 154, a colored layer 156, an insulating layer 158, a conductive layer 160, The color layer 156 is formed in the region corresponding to the display region. It functions as a region.

[0039] The pixel electrode 121, the alignment film 135, the liquid crystal layer 164, the alignment film 162, and the conductive layer 160 form a pixel electrode. A voltage is applied to the pixel electrode 121 and the conductive layer 160. By doing so, the alignment state of the liquid crystal layer 164 can be controlled. 5 and 162 are not necessarily provided, and depending on the material used for the liquid crystal layer 164, the alignment The membranes 135 and 162 may not be provided.

[0040] The semiconductor layer 119, the insulating layer 133, and the pixel electrode 121 form a capacitor element 105. The semiconductor layer 119 functions as one electrode of the capacitor 105 and is The pixel electrode 121 can be used in common with one electrode of the capacitor element. It functions as the other electrode of the element 105 and is formed separately from the other electrode of the adjacent capacitor element. It has been made.

[0041] 2 and 4 indicate the influence of the alignment caused by the step portion on the liquid crystal layer 164. Specifically, the liquid crystal layer 164 is formed by a step caused by the capacitance line 115, The influence of the step caused by the data line 109 and the step caused by the scanning line 107 and the conductive layer 113 Therefore, the liquid crystal layer 164 is oriented under the influence of the steps from three directions. It becomes.

[0042] Here, an example of a conventional pixel configuration will be described below with reference to FIGS. 9 to 12. cormorant.

[0043] <Example of the configuration of a comparison display device> FIG. 9 shows a top view of the periphery of a pixel in a display device.

[0044] In FIG. 9, the scanning lines 507 are arranged in a direction substantially perpendicular to the data lines 509 (the left-right direction in the figure). The data lines 509 extend in a direction substantially perpendicular to the scanning lines 507 (up and down in the figure). The capacitance line 515 extends in a direction substantially parallel to the scanning line 507. It is set up as follows.

[0045] Moreover, pixels 501 are formed in areas defined by scanning lines 507 and data lines 509. .

[0046] The transistor 503 is disposed in the area where the scan line 507 and the data line 509 intersect in the pixel 501. The transistor 503 is provided in a semiconductor device having at least a channel formation region. A conductor layer 511, a gate electrode, a gate insulating layer (not shown in FIG. 9), a source electrode and a drain electrode. and a rain electrode.

[0047] The scanning line 507 also functions as the gate electrode of the transistor 503, and the data line 5 The conductive layer 513 also functions as a source electrode of the transistor 503. It functions as a drain electrode of the photodiode 503 and is electrically connected to the pixel electrode 521 through the opening 517. In the following, the gate electrode of a transistor is also referred to as a scanning gate. The line 507 is used to indicate the source electrode of the transistor, and the data line 509 is used to indicate the source electrode of the transistor. This may be the case.

[0048] The capacitance element 505 is connected to a capacitance line 515, a data line 509, and a scanning line 507 in the pixel 501. The capacitor element 505 is provided in a region partitioned by a conductive layer provided in the opening 523. The capacitor element 505 is electrically connected to the capacitor line 515 through a light-transmitting A semiconductor layer 519 formed of an oxide semiconductor having a conductivity higher than that of the semiconductor layer 511 and a transparent insulating layer 520. A pixel electrode 521 having a light-transmitting property and a dielectric layer included in the transistor 503 are In other words, the capacitance element 505 is made up of a transparent insulating layer (not shown in FIG. 9). It has photochemical properties.

[0049] Here, the cross-sectional shape of the pixel 501 in the long side direction is taken along the dashed line X7-X8 in FIG. 10 shows a cross-sectional view taken along the dashed line X9-X10 of the pixel 501. The cross-sectional shape in the direction of the arrow is shown in FIG. 11, which is a cross-sectional view taken along the dashed line Y3-Y4 in FIG. 9. In addition, the cross-sectional shape of the periphery of the transistor 503 of the pixel 501 and the edge of the pixel 501 Regarding the cross-sectional view taken along dashed lines B1-B2 and B3-B4 in FIG. Shown in Figure 12.

[0050] The cross-sectional structure of the display device shown in FIG. 10 is as follows.

[0051] A scanning line 507 and a capacitance line 515 are provided on a substrate 502. An insulating layer 527 is provided on the capacitance line 515. A conductive layer 513 is provided at a position where the insulating layer 527 is to be formed. In addition, an insulating layer 529 is formed over the insulating layer 527, the conductive layer 513, and the semiconductor layer 519. , 531 are provided. The insulating layers 529, 531 cover the ends of the semiconductor layer 519. In addition, an insulating layer is formed so as to cover the semiconductor layer 519 and the insulating layer 531. A pixel electrode 533 is provided on the insulating layer 533 at a position overlapping with the semiconductor layer 519. A pixel electrode 521 is provided. An alignment film 53 is provided on the insulating layer 533 and the pixel electrode 521. 5 is provided.

[0052] The cross-sectional structure of the display device shown in FIG. 11 is as follows.

[0053] An insulating layer 527 is provided on the substrate 502. In addition, the data line 50 is provided on the insulating layer 527. 9 is provided. Also, a semiconductor layer 519 is provided between the data lines 509 on the insulating layer 527. In addition, an insulating layer 527 is formed on the data line 509 and the semiconductor layer 519. The insulating layers 529 and 531 are provided at the end of the semiconductor layer 519. In addition, an insulating film is formed so as to cover the semiconductor layer 519 and the insulating layer 531. A border layer 533 is provided. In addition, a border layer 533 is provided at a position on the insulating layer 533 where the border layer 533 overlaps with the semiconductor layer 519. A pixel electrode 521 is provided. An alignment film 5 is provided on the insulating layer 533 and the pixel electrode 521. 35 is provided.

[0054] The cross-sectional structure of the display device shown in FIG. 12 is as follows.

[0055] On the substrate 502, a scanning line 507 which functions as a gate electrode of a transistor 503 and a scanning A capacitance line 515 is formed on the same surface as the scanning line 507. An insulating layer 527 is provided on the scanning line 507 and the capacitance line 515. A semiconductor layer 511 is provided on the region corresponding to the insulating layer 527, and a semiconductor layer 519 is provided on the insulating layer 527. A source electrode of the transistor 503 is provided on the semiconductor layer 511 and the insulating layer 527. a data line 509 functioning as a drain electrode of the transistor 503; An opening 523 is provided in the insulating layer 527, and the opening 523 reaches the capacitance line 515. A conductive layer 525 is provided on the opening 523, the insulating layer 527, and the semiconductor layer 519. The insulating layer 527, the data line 509, the semiconductor layer 511, the conductive layer 513, and the conductive layer 5 25, and an insulating layer 5 serving as a protective insulating layer for the transistor 503 is formed on the semiconductor layer 519. In addition, a part of the insulating layers 529 and 531 is removed, and a semiconductor An opening is provided on a part of the insulating layer 531 and the semiconductor layer 519. An insulating layer 533 is provided on the insulating layers 529, 531, and 533. An opening 517 reaching the insulating layer 533 is provided. The pixel electrode 5 is disposed on the opening 517 and the insulating layer 533. 21 is provided.

[0056] In addition, in the display device shown in FIG. 10 to FIG. 12, a substrate 152 is provided opposite to the substrate 502. A liquid crystal layer 164 is sandwiched between the substrate 502 and the substrate 152. Below the plate 152 are a light-shielding layer 154, a colored layer 156, an insulating layer 158, a conductive layer 160, and An alignment film 162 is formed. The region where the color layer 156 is formed is used as a display region. It works like this.

[0057] The pixel electrode 521, the alignment film 535, the liquid crystal layer 164, the alignment film 162, and the conductive layer 160 A liquid crystal element 570 is formed by applying a voltage to the pixel electrode 521 and the conductive layer 160. By this, the alignment state of the liquid crystal layer 164 can be controlled.

[0058] The semiconductor layer 519, the insulating layer 533, and the pixel electrode 521 form a capacitor element 505. The semiconductor layer 519 functions as one electrode of the capacitor 505. The pixel electrode 521 functions as the other electrode of the capacitor element 505. 9 and the pixel electrode 521 are formed separately from the adjacent pixels.

[0059] 10 and 11 indicate alignment changes caused by steps that the liquid crystal layer 164 receives. Specifically, the liquid crystal layer 164 is connected to the capacitance line 515 and the conductive layer 51 3, a step caused by the scanning line 507, and a step caused by the pair of data lines 509. Therefore, the liquid crystal layer 164 is affected by the steps from four directions. This will lead to a shift in the direction.

[0060] Therefore, the pixel 501 in the example of the configuration of the conventional display device is affected by the shadows of steps from four directions. This structure is highly likely to cause alignment defects in the liquid crystal layer 164 due to the influence of the polarizing beam. Therefore, alignment defects in the liquid crystal layer 164 tend to occur in the vicinity of the center of the pixel 501 .

[0061] On the other hand, the display device according to one embodiment of the present invention has a structure similar to that of the conventional display devices shown in FIGS. In comparison, it has the following excellent effects:

[0062] In the pixel 101 of the display device according to one embodiment of the present invention, the end of the pixel electrode 121 in the long side direction is a scan line. The pixel electrode 107 and the data line 109 are located near the center of the area defined by the pixel electrode 107 and the data line 109. As a result, the end of the pixel electrode 121 is located away from the scanning line 107, It is not affected by the step caused by 07, or is very unlikely to be affected by it.

[0063] In the vicinity of the center of the area defined by the scanning lines 107 and the data lines 109, By providing the portion, the shadow of the step in one direction (the scanning line 107 in this embodiment) can be eliminated. Since the influence of the step is not or is reduced, the alignment of the liquid crystal layer 164 caused by the step is prevented. The good can be reduced.

[0064] In addition, the pixel 101 of the display device described in this embodiment has a step due to a transistor or the like. To reduce the noise, a planarizing film such as an organic resin is not used. Even when an oxide semiconductor layer is used as the conductor layer, for example, the oxide semiconductor layer may be contaminated with Reliable due to reduced impurities (e.g. water in organic resins) that may cause defects. Therefore, by using the display device of one embodiment of the present invention, This reduces alignment defects and uses highly reliable transistors, improving display quality. It is possible to provide a high quality display device.

[0065] In addition, in the display device according to one embodiment of the present invention shown in FIG. Since the pixel electrode 121 is extended, the liquid crystal layer on approximately half of the pixel electrode 121 The alignment direction of the liquid crystal layer 164 on the pixel electrode 121 and the alignment direction of the liquid crystal layer 164 on the other half of the pixel electrode 121 can be made different. In other words, the display device according to one embodiment of the present invention can have different alignment states in one pixel. This allows for the so-called MVA (Multidomain Vertical Alignment) The display device may be an illumination type display device.

[0066] For example, when the display device shown in FIG. 2 is used as an MVA type display device, the structure shown in FIG. 3 is a cross-sectional view in which only the hatching of the liquid crystal layer 164 in the cross-sectional view shown in FIG. Cross-sectional view.

[0067] In the cross-sectional view shown in FIG. 3, the hatching of the liquid crystal layer 164 represents the alignment state of the liquid crystal molecules. It represents the objective.

[0068] In FIG. 3, the liquid crystal layer 164 on the left pixel electrode 121 is In addition, in FIG. 3, the pixel electrode on the right side The liquid crystal layer 164 on the scanning line 121 is aligned in the right direction where there is no step due to the step of the scanning line 107. It is possible.

[0069] In this way, the display device according to one embodiment of the present invention has protrusions such as ribs that control the alignment state of the liquid crystal. 3, which is disposed above the scanning line 107 by utilizing the step of the scanning line 107. The alignment direction of the liquid crystal layer 164 on the left pixel electrode 121 and the alignment direction of the liquid crystal layer 164 on the left pixel electrode 121 on the left side of the scanning line 107 are In FIG. 3, the alignment direction of the liquid crystal layer 164 on the pixel electrode 121 on the right side can be changed. Therefore, the viewing angle dependency is also improved, and a more excellent display device can be obtained. .

[0070] Note that other components of the display device according to one embodiment of the present invention shown in FIGS. 1 to 5 are as follows: A method for manufacturing the display device will be described in detail below.

[0071] <Manufacturing method of display device> A method for manufacturing the display device shown in FIGS. 1 to 5 will be described below with reference to FIGS. 6 to 8. 6 to 8, the cross-sectional structure of the display device shown in FIG. 5 will be described as an example.

[0072] First, a substrate 102 is prepared. The substrate 102 is made of aluminosilicate glass, aluminum. Glass materials such as minoborosilicate glass and barium borosilicate glass are used. Above, the substrate 102 is 8th generation (2160mm x 2460mm), 9th generation (2400 mm x 2800mm, or 2450mm x 3050mm, 10th generation (2950mm It is preferable to use mother glass such as 3400 mm × 3400 mm. Since the temperature is high and the processing time is long, the glass shrinks significantly. The heat treatment in the manufacturing process is preferably performed at 600° C. or less, more preferably at 450° C. or less, and It is more preferable to set the temperature at 350° C. or lower.

[0073] Next, a conductive layer is formed on the substrate 102, and the conductive layer is processed into a desired region, thereby performing scanning. The lines 107 are then formed. Then, an insulating layer 127 is formed on the substrate 102 and the scan lines 107. (See Figure 6(A)).

[0074] The scanning line 107 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, etc. A metal element selected from stainless steel, or an alloy containing the above-mentioned metal elements, or the above-mentioned alloys The scanning line 107 can be formed by using an alloy or the like in which metal elements are combined. For example, a titanium film may be formed on an aluminum film. A two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; A two-layer structure in which a tantalum nitride film is laminated on a tungsten nitride film, or a tungsten nitride film is laminated on a tantalum nitride film or a tungsten nitride film A two-layer structure with a stainless steel film, a titanium film, and an aluminum film laminated on top of the titanium film. There is also a three-layer structure in which a titanium film is formed on top of the aluminum. An element selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium A base film, an alloy film made by combining a plurality of layers, or a nitride film may be used. The film 107 can be formed by using, for example, a sputtering method.

[0075] The insulating layer 127 may be, for example, a silicon oxynitride film, a silicon nitride film, or an aluminum oxide film. A PE-CVD device can be used to form a multilayer or single layer. When the insulating layer 127 has a laminated structure, a silicon nitride film having few defects is used as the first silicon nitride film. A silicon nitride film was formed on the first silicon nitride film, and a second silicon nitride film was formed on the first silicon nitride film. It is preferable to provide a silicon nitride film that emits less ammonia. Hydrogen and nitrogen contained in the insulating layer 27 move or diffuse into the semiconductor layer 111 to be formed later. This can suppress the following.

[0076] The insulating layer 127 may be a silicon oxide film, a silicon oxynitride film, or the like. It is formed in a multilayer or single layer using an E-CVD device.

[0077] As the insulating layer 127, for example, a silicon nitride film having a thickness of 400 nm is formed, and then, A laminated structure in which a silicon oxynitride film having a thickness of 50 nm is formed can be used. When the silicon film and the silicon oxynitride film are formed successively in a vacuum, the inclusion of impurities is suppressed. Note that the insulating layer 127 overlapping with the scan line 107 is preferably It is to be noted that silicon nitride oxide is a material in which the nitrogen content is less than the oxygen content. Silicon oxynitride is an insulating material with a higher oxygen content than nitrogen. This refers to insulating material with a larger content.

[0078] By configuring the gate insulating layer as described above, the following effects can be obtained, for example: Silicon nitride film has a higher dielectric constant than silicon oxide film, and has the same static Since a large film thickness is required to obtain a large capacitance, the gate insulating film can be made thicker. This suppresses the decrease in the dielectric strength of the transistor 103 and further improves the dielectric strength of the transistor. Electrostatic damage to the transistor 103 can be suppressed.

[0079] Next, a semiconductor layer is formed on the insulating layer 127, and the semiconductor layer is processed into a desired region. Then, semiconductor layers 111 and 119 are formed (see FIG. 6(B)).

[0080] The semiconductor layers 111 and 119 are preferably made of an oxide semiconductor. contains at least indium (In), zinc (Zn) and M (Al, Ga, Ge, Y, Zr The film is represented by In-M-Zn oxide containing metals such as In, Sn, La, Ce or Hf. It is preferable that the oxide contains both In and Zn. In order to reduce the variation in the electrical characteristics of semiconductor transistors, It is preferred to include a riser.

[0081] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminium. Aluminum (Al) or zirconium (Zr), etc. Also, other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er) Er, Thulium, Tm, Ytterbium, Lutetium, etc. do.

[0082] The oxide semiconductor constituting the semiconductor layers 111 and 119 is, for example, an In-Ga-Zn system Oxides, In-Al-Zn oxides, In-Sn-Zn oxides, In-Hf-Zn oxides oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide , In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, I n-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide , In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-A l-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide can be used.

[0083] In this case, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than n may be present.

[0084] The semiconductor layers 111 and 119 are formed by sputtering, MBE (Molecular Beam Induction), r Beam Epitaxy, CVD, Pulsed Laser Deposition, ALD (Atom A suitable method for this purpose may be used, for example, a thin-film deposition (SbD) method.

[0085] When an oxide semiconductor film is formed as the semiconductor layers 111 and 119, it is preferable that the oxide semiconductor film is not contained as much as possible. It is preferable to reduce the hydrogen concentration in the oxidized gas. When forming a film using the sputtering method, not only is the inside of the film formation chamber evacuated to a high vacuum, but High-purity gases are also required. Oxygen gas and argon gas used as sputtering gases are The temperature is -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, and even more preferably By using a gas that has been highly purified to a temperature of −120° C. or lower, moisture and the like can be prevented from being absorbed into the oxide semiconductor film. It is possible to prevent capture as much as possible.

[0086] In order to remove residual moisture in the deposition chamber, an adsorption type vacuum pump, e.g. It is preferable to use an opto-pump, an ion pump, or a titanium sublimation pump. Alternatively, a turbomolecular pump with a cold trap may be used. For example, hydrogen molecules, water (H2O) and other compounds containing hydrogen atoms (more preferably carbon atoms) Since the pumping capacity of the film-forming chamber is high, the film can be formed in a chamber evacuated using a cryopump. The concentration of impurities contained in the deposited film can be reduced.

[0087] In addition, an oxide semiconductor film is formed as the semiconductor layers 111 and 119 by a sputtering method. In this case, the relative density (filling rate) of the metal oxide target used for film formation is 90% or more and 100% or less. The relative density of the metal oxide target is preferably 95% or more and 100% or less. By using this, the film to be formed can be made dense.

[0088] In addition, while the substrate 102 is maintained at a high temperature, the semiconductor layers 111 and 119 are made of oxide semiconductor. Forming a thin film on the oxide semiconductor film is also effective in reducing the concentration of impurities that may be contained in the oxide semiconductor film. The temperature to which the substrate 102 is heated may be set to 150° C. or higher and 450° C. or lower. Preferably, the substrate temperature is set to 200° C. or higher and 350° C. or lower.

[0089] Next, a first heat treatment is preferably performed. ℃ or less, preferably 300 ℃ to 500 ℃, in an inert gas atmosphere, an oxidizing gas atmosphere The first heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine or under reduced pressure. The atmosphere is an inert gas atmosphere, and then an oxidizing gas is introduced to replenish the oxygen that has been removed. The first heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine. The crystallinity of the oxide semiconductor used for the insulating layer 127 and the semiconductor layer 111, Impurities such as hydrogen and water can be removed from the semiconductor layers 111 and 119. Before processing 9 into islands, a first heating step may be carried out.

[0090] Next, a conductive film is formed on the insulating layer 127 and the semiconductor layers 111 and 119, and the conductive film is By processing the area, the data line 109, the conductive layer 113, and the capacitance line 115 are formed. At this stage, the transistor 103 is formed (see FIG. 6C).

[0091] Materials of Conductive Films That Can Be Used for the Data Line 109, the Conductive Layer 113, and the Capacitive Line 115 Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium , molybdenum, silver, tantalum, or tungsten, or The alloy may be used as a single layer or a multilayer structure. Two-layer structure with titanium film laminated on tungsten film, two-layer structure with titanium film laminated on tungsten film , a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film or A titanium nitride film and an aluminum film or a copper film overlaid on the titanium film or the titanium nitride film. A three-layer structure in which a titanium film or titanium nitride film is formed on top of the molybdenum A molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film. A aluminum or copper film is laminated, and then a molybdenum or molybdenum nitride film is laminated on top of it. A three-layer structure is formed. The conductive film may be formed by using, for example, a sputtering method. This can be done.

[0092] Next, the insulating layer 127, the semiconductor layers 111 and 119, the data line 109, the conductive layer 113, and Insulating layers 129 and 131 are formed on the capacitance line 115 (see FIG. 7(A)).

[0093] The insulating layers 129 and 131 are made of the oxide semiconductor used for the semiconductor layers 111 and 119. In order to improve the interface characteristics of the insulating material, inorganic insulating materials containing oxygen can be used. The edge layers 129, 131 can be formed, for example, by using a PE-CVD method.

[0094] The thickness of the insulating layer 129 is 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the insulating layer 131 can be set to 10 nm or less and preferably 30 nm or less. The thickness can be set to 30 nm or more and 500 nm or less, preferably 150 nm or more and 400 nm or less. Cut.

[0095] In addition, the insulating layers 129 and 131 can be made of insulating films of the same material. In some cases, the interface between the layer 129 and the insulating layer 131 may not be clearly visible. In this embodiment, the interface between the insulating layer 129 and the insulating layer 131 is shown by a dashed line. In the embodiment, a two-layer structure of insulating layer 129 and insulating layer 131 has been described. For example, the insulating layer 129 may have a single layer structure, the insulating layer 131 may have a single layer structure, or A laminated structure of three or more layers may also be used.

[0096] Next, the insulating layers 129 and 131 are processed into desired regions to form openings 140 ( See Figure 7(B).

[0097] The opening 140 is formed so that at least the semiconductor layer 119 is exposed. In the embodiment, the semiconductor layer 119 and the capacitance line 115 are exposed through the opening 140. The opening 140 can be formed by, for example, dry etching. However, the method for forming the opening 140 is not limited to this, and may be a wet etching method or the like. Alternatively, a combination of dry etching and wet etching may be used.

[0098] Next, the insulating layer 133 is formed on the insulating layer 131, the semiconductor layer 119, and the capacitance line 115. (See Figure 7(C)).

[0099] The insulating layer 133 is formed to prevent impurities from the outside, such as water, alkali metals, alkaline earth metals, etc. The film is formed of a material that prevents diffusion of the impurities into the oxide semiconductor layer and further contains hydrogen. Therefore, when hydrogen in the insulating layer 131 diffuses into the semiconductor layer 119, Hydrogen combines with oxygen, or hydrogen combines with an oxygen vacancy to generate electrons, which act as carriers. As a result, the semiconductor layer 119 becomes a conductive layer having high conductivity and light-transmitting properties.

[0100] In this embodiment, hydrogen is introduced from the insulating layer 133 in contact with the semiconductor layer 119. The method of inserting the transistor 103 is described above, but is not limited to this. A mask is provided on the semiconductor layer 111 that functions as a channel, and the area not covered by the mask For example, hydrogen may be introduced into the semiconductor layer 119 using an ion doping device or the like. Hydrogen can be introduced into the semiconductor layer 119 in advance. A conductive film, for example, ITO, may be formed on the insulating layer.

[0101] An example of the insulating layer 133 is a silicon nitride film having a thickness of 150 nm or more and 400 nm or less. A silicon nitride oxide film or the like can be used. In this embodiment, the insulating layer 133 and A silicon nitride film having a thickness of 150 nm is used.

[0102] In addition, the silicon nitride film is preferably formed at a high temperature in order to enhance blocking properties. Preferably, the substrate temperature is 100° C. or higher and lower than the distortion point of the substrate, more preferably 300° C. or higher and 400° C. or higher. It is preferable to form the film by heating at a temperature of 00°C or less. The phenomenon that oxygen is desorbed from the oxide semiconductor used as the oxide layer 111 and the carrier concentration increases Since this phenomenon may occur, the temperature is set to a level at which this phenomenon does not occur.

[0103] Next, the insulating layers 129, 131, and 133 are processed into desired regions to form the openings 117. (See FIG. 8(A)).

[0104] The opening 117 is formed so as to expose the conductive layer 113. As a method for forming the opening 11, for example, a dry etching method can be used. The method for forming the 7 is not limited to this, and may be a wet etching method or a dry etching method. A combination of the rubbing method and the wet etching method may also be used.

[0105] Next, a conductive layer is formed on the insulating layer 133 so as to cover the opening 117, and the conductive layer is The pixel electrode 121 is formed by processing the substrate 104 in the same manner as in the first embodiment. (See FIG. 8(B)).

[0106] A conductive layer that can be used for the pixel electrode 121 is an indium tin oxide layer. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide (ITO) The transparent conductive films include indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material having optical properties can be used. The conductive layer can be formed by using a sputtering method, for example.

[0107] One electrode of the capacitor 105 is formed in the same process as the semiconductor layer 111 used for the transistor 103. The semiconductor layer 119 is a light-transmitting semiconductor film. The dielectric film of the capacitance element 105 is disposed above the semiconductor layer 111 of the transistor 103. The other electrode of the capacitor 105 is a transistor. The pixel electrode 121 is electrically connected to the transistor 103 and has a light-transmitting property. The capacitor 105 can be formed in the same process as the transistor 103 .

[0108] Therefore, since the capacitor 105 has a light-transmitting property, a transistor in the pixel is formed. Therefore, the present invention can be applied to a large area other than the area where the According to one embodiment, a semiconductor device having an increased aperture ratio and an increased charge capacity can be obtained. Moreover, by improving the aperture ratio, a semiconductor device with excellent display quality can be obtained. do.

[0109] Through the above steps, the transistor 103 and the capacitor 105 can be formed over the substrate 102 .

[0110] Next, the structure formed on the substrate 152 provided opposite the substrate 102 will be described below. Make a statement.

[0111] First, a substrate 152 is prepared. The substrate 152 is made of the same material as that of the substrate 102. Next, a light-shielding layer 154 and a colored layer 156 are formed in contact with the substrate 152.

[0112] The light-shielding layer 154 may be made of a metal or other material as long as it has a function of blocking light in a specific wavelength range. Alternatively, an organic insulating film containing a black pigment or the like can be used.

[0113] The color layer 156 may be any color layer that transmits light in a specific wavelength range. For example, A red (R) color filter that transmits light in the red wavelength range, and a green (G) color filter that transmits light in the green wavelength range. A green (G) color filter transmits light in the blue wavelength range, and a blue (B) color filter transmits light in the blue wavelength range. Each color filter can be made of various materials using printing methods, Inkjet method, etching method using photolithography technology, etc. Formed at the position.

[0114] Next, the insulating layer 158 is formed in contact with the light-shielding layer 154 and the colored layer 156 .

[0115] The insulating layer 158 may be an organic insulating film made of, for example, an acrylic resin. By forming the insulating layer 158, for example, impurities contained in the color layer 156 can be removed. However, the insulating layer 158 must be It is not necessary to form the insulating layer 158, and the insulating layer 158 may not be formed.

[0116] Next, a conductive layer 160 is formed in contact with the insulating layer 158. Any material that can be used for the pole 121 can be used.

[0117] Through the above steps, the structure to be formed on the substrate 152 can be formed.

[0118] Next, an alignment film 135 is formed in contact with the insulating layer 133 and the pixel electrode 121. An alignment film 162 is formed in contact with the layer 160. The alignment films 135 and 162 are formed by a rubbing method, a light alignment method, and the like. Then, the liquid crystal is formed between the substrate 102 and the substrate 152 by using a liquid crystal display. The liquid crystal layer 164 is formed by a dispenser method (dropping method) or A method in which the substrate 102 and the substrate 152 are bonded together and then liquid crystal is injected using capillary action. can be used.

[0119] Through the above steps, the display device shown in FIGS. 1 and 5 can be manufactured.

[0120] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0121] (Embodiment 2) In this embodiment, the transistor and the capacitor of the display device described in Embodiment 1 can be applied to An example of an oxide semiconductor layer that can be formed using the oxide semiconductor layer will be described.

[0122] <Crystallineness of oxide semiconductor layer> The structure of the oxide semiconductor layer will be described below.

[0123] Oxide semiconductor layers are roughly classified into non-single-crystal oxide semiconductor layers and single-crystal oxide semiconductor layers. The non-single-crystal oxide semiconductor layer is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). (stalline oxide semiconductor) film, polycrystalline oxide semiconductor The oxide semiconductor layer may be a semiconductor layer, a microcrystalline oxide semiconductor layer, an amorphous oxide semiconductor layer, or the like.

[0124] First, we will explain the CAAC-OS film.

[0125] The CAAC-OS film is one of the oxide semiconductor layers having multiple crystal parts. The crystal part is small enough to fit inside a cube with one side less than 100 nm. The crystal parts contained in the OS film are cubes with one side less than 10 nm, 5 nm, or 3 nm. This also includes cases where the size fits within the

[0126] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz crystal microscope, clear boundaries between crystal parts were observed, i.e. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0127] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on a surface on which the film is to be formed (also called a surface on which the film is to be formed) or on a concave surface on the upper surface. The shape reflects a convexity, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0128] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle between 80° and 100°. Therefore, cases between 85° and 95° are also included.

[0129] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0130] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0131] X-ray diffraction (XRD) of CAAC-OS film When the structure was analyzed using the device, for example, CAAC-OS with InGaZnO4 crystals was In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0132] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0133] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0134] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. For example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the face or top surface normal vector.

[0135] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to the AC-OS film, the crystallinity of the region to which the impurities are added changes, resulting in a partial In some cases, regions of differing crystallinity may be formed.

[0136] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have 2θ of around 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0137] The CAAC-OS film is an oxide semiconductor layer with a low concentration of impurities. The impurities are hydrogen, carbon, and The oxide semiconductor layer is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor layer. Elements such as copper that bond more strongly with oxygen than the metal elements that make up the oxide semiconductor layer are By removing oxygen from the oxide semiconductor layer, the atomic arrangement of the oxide semiconductor layer is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor layer, the oxide semiconductor layer The impurities contained in the oxide semiconductor layer are disturbed, which causes a decrease in crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0138] In addition, the CAAC-OS film is an oxide semiconductor layer with a low density of defect states.

[0139] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0140] Next, a microcrystalline oxide semiconductor layer will be described.

[0141] In the microcrystalline oxide semiconductor layer, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor layer may have a thickness of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 to 3 nm or less. The oxide semiconductor layer having tal was The nc-OS film is called a T In EM images, grain boundaries may not be clearly visible.

[0142] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor layer depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the nc-OS film had a diameter larger than that of the crystalline part (e.g. When electron beam diffraction (also called selected area electron beam diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for the nc-OS film, the diffraction pattern is crystalline. The electron beam diameter is close to the size of the crystal part or smaller than the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron diffraction) is performed, spots are observed. In addition, when nanobeam electron diffraction was performed on the nc-OS film, a circular (ring-shaped) ) Bright areas may be observed. When diffraction occurs, multiple spots may be observed within the ring-shaped area.

[0143] The nc-OS film is an oxide semiconductor layer with higher regularity than the amorphous oxide semiconductor layer. Therefore, the nc-OS film has a lower density of defect energy levels than the amorphous oxide semiconductor layer. However, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher density of defect energy levels than the CAAC-OS film.

[0144] Note that the oxide semiconductor layer may be, for example, a laminated film having two or more of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, and a C AAC-OS film.

[0145] <Method for forming a CAAC-OS film> The CAAC-OS film is formed, for example, by a sputtering method using a target for sputtering an oxide semiconductor that is polycrystalline. When ions collide with the sputtering target, the crystal regions contained in the sputtering target are cleaved from the a-b plane and peeled off as plate-shaped or pellet-shaped sputtering particles having a plane parallel to the a-b plane. In this case, the CAAC-OS film can be formed by the plate-shaped or pellet-shaped sputtering particles reaching the substrate while maintaining the crystal state.

[0146] The plate-shaped or pellet-shaped sputtering particles have, for example, a circular equivalent diameter of the plane parallel to the a-b plane of 3 nm or more and 10 nm or less, and a thickness (length in the direction perpendicular to the a-b plane) of 0.7 nm or more and less than 1 nm. Note that the plate-shaped or pellet-shaped sputtering particles may have a plane parallel to the a-b plane that is an equilateral triangle or a regular hexagon. Here, the circular equivalent diameter of the plane means the diameter of a perfect circle equal to the area of the plane.

[0147] ​​​​​​In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0148] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is suppressed. Specifically, the substrate temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or lower. The film is formed at a temperature of 500°C or less. By increasing the substrate temperature during film formation, flat or pellet-shaped films can be formed. When the sputtered particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtered particle adheres to the substrate. By being charged, the sputtering particles repel each other while adhering to the substrate, The ring particles do not overlap unevenly due to bias, and a CAAC-OS film with uniform thickness is formed. It is possible.

[0149] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0150] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. Expressed as volume percent.

[0151] Alternatively, the CAAC-OS film is formed by the following method.

[0152] First, a first oxide semiconductor layer is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor layer is formed by sputtering. The temperature is set to 500° C. or less, preferably 150° C. to 450° C., and the oxygen ratio in the deposition gas is set to 30 % by volume or more, preferably 100% by volume.

[0153] Next, heat treatment is performed to convert the first oxide semiconductor layer into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor layer can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor layer by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be performed at 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor layer from the first oxide semiconductor layer may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0154] The first oxide semiconductor layer has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0155] Next, a second oxide semiconductor layer having the same composition as the first oxide semiconductor layer is formed to a thickness of 10 nm or more. The second oxide semiconductor layer is formed to a thickness of 0 nm or less by a sputtering method. Specifically, the substrate temperature is set to 100° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower. The oxygen ratio in the deposition gas is set to 30% by volume or more, preferably 100% by volume. To film.

[0156] Next, heat treatment is performed to form a second oxide semiconductor layer from the first CAAC-OS film by solid phase growth. The second CAAC-OS film is formed with high crystallinity by the heat treatment at a temperature of 350 The temperature is from 450°C to 650°C, preferably from 450°C to 650°C. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After that, a heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor layer can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor layer by the heat treatment. The oxygen vacancies can be reduced by heat treatment in a reactive atmosphere. The pressure may be reduced to 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration in the second oxide semiconductor layer can be reduced in a shorter time. Cut.

[0157] In this manner, a CAAC-OS film having a total thickness of 10 nm or more is formed. The CAAC-OS film can be suitably used as an oxide semiconductor layer in an oxide stack. There can be.

[0158] Next, for example, the substrate is not heated, so that the surface to be formed is kept at a low temperature (for example, less than 130°C). , oxide film at temperatures below 100℃, below 70℃, or room temperature (20℃ to 25℃) A method for forming the above will be described.

[0159] When the surface to be formed is at a low temperature, the sputtered particles rain down irregularly on the surface to be formed. For example, because there is no migration, there are no areas where other sputtered particles have already accumulated. That is, the oxide film obtained by deposition has a uniform thickness, for example. The oxide film obtained in this way is not only a simple structure, but also has a disordered crystal orientation. In order to maintain the crystallinity of the putter particles to a certain extent, the putter particles have crystalline portions (nanocrystals).

[0160] In addition, for example, when the pressure during film formation is high, the flying sputtered particles may be mixed with other gases such as argon. The frequency of collisions with other particles (atoms, molecules, ions, radicals, etc.) increases. However, the crystal structure may be destroyed by collisions with other particles during flight (resputtering). For example, sputtered particles collide with other particles and form into flat or pellet-like shapes. In some cases, the solid cannot maintain its shape and may be broken down (e.g., separated into individual atoms). At this time, the atoms separated from the sputtered particles are deposited on the surface to be formed, forming an amorphous oxide. A nitride film may be formed.

[0161] Also, instead of a sputtering method using a target having a polycrystalline oxide as a starting point, In the case of a method of forming a film using a liquid, or by gasifying a solid such as a target, a film is formed. In the case of the method, the atoms fly in a split state and deposit on the surface to be formed, so amorphous oxide In the laser ablation method, for example, the target Atoms, molecules, ions, radicals, clusters, etc. emitted from the As a result, an amorphous oxide film may be formed.

[0162] The oxide semiconductor layer included in the resistor and the transistor of one embodiment of the present invention may be any one of the above-described In addition, the oxide semiconductor layer may have a stacked structure. In this case, the crystal state of each oxide semiconductor layer may be different from that of the other oxide semiconductor layers. For the oxide semiconductor layer functioning as a panel, a CAAC-OS film is preferably used. In addition, the oxide semiconductor layer included in the resistor element has a larger Since the impurity concentration is higher than that of the conventional silicon nitride, the crystallinity may decrease.

[0163] The structures, methods, etc. described in this embodiment may be different from the structures, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0164] (Embodiment 3) In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. In addition, parts having the same functions as those in the first embodiment are denoted by the same reference numerals, and their details are described below. The explanation will be omitted.

[0165] The display device shown in FIG. 13A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 302). ) and a circuit section ( 303) and a circuit having a function of protecting the element (hereinafter, referred to as a protection circuit 304). 6) and a terminal portion 307. Note that the protection circuit 306 is not provided in the configuration. This is also fine.

[0166] A part or the whole of the driver circuit portion 304 is formed on the same substrate as the pixel portion 302. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 302 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 304 can be implemented by COG or TAB.

[0167] The pixel units 302 are arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). A driving circuit section includes a circuit for driving a plurality of display elements (hereinafter referred to as pixels 101). 304 is a circuit that outputs a signal (scanning signal) for selecting a pixel (hereinafter, a gate driver 30 4a), a circuit for supplying a signal (data signal) for driving the display element of the pixel, The pixel 304 includes a driving circuit such as a source driver 304b.

[0168] The gate driver 304a includes a shift register and the like. A signal for driving the shift register is input via the terminal unit 307, and a signal is output via the terminal unit 307. For example, the gate driver 304a receives a start pulse signal, a clock signal, etc. The gate driver 304a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 304a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 304a may control the GL_X by dividing it. However, the gate driver 30 has a function of supplying 4a may also provide another signal.

[0169] The source driver 304b includes a shift register and the like. Through the terminal section 307, a signal for driving the shift register as well as a source of a data signal are transmitted. The source driver 304b outputs a signal (image signal) to the pixel 10 based on the image signal. The source driver 304b has a function of generating a data signal to be written to the source 1. A data signal is generated according to a pulse signal obtained by inputting a start pulse signal, a clock signal, etc. The source driver 304b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 304b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 304b may supply other signals. It is possible.

[0170] The source driver 304b is configured using, for example, a plurality of analog switches. The source driver 304b sequentially turns on a number of analog switches, A signal obtained by time-sharing an image signal can be output as a data signal.

[0171] Each of the plurality of pixels 101 is supplied with a scanning signal via one of a plurality of scanning lines GL. A pulse signal is input to the data line DL, and a data signal is applied to one of the data lines DL. Each of the pixels 101 is connected to a gate driver 304a. For example, the pixel in the mth row and nth column 101 is supplied from the gate driver 304a via the scanning line GL_m (m is a natural number equal to or smaller than X). A pulse signal is input, and the data line DL_n (n is a value below Y) is changed according to the potential of the scanning line GL_m. A data signal is input from the source driver 304b via a corresponding one of the inputs (natural number).

[0172] The protection circuit 306 shown in FIG. 13A is, for example, a gate driver 304a and a pixel 101. The protection circuit 306 is electrically connected to the scanning line GL, which is a wiring between the source It is electrically connected to the data line DL, which is the wiring between the driver 304b and the pixel 101. Alternatively, the protection circuit 306 may electrically connect the wiring between the gate driver 304a and the terminal unit 307. Alternatively, the protection circuit 306 may be connected to the source driver 304b and the terminal The terminal portion 307 can be electrically connected to the wiring between the terminal portion 307 and the external circuit. A part provided with terminals for inputting power, control signals, and image signals to the display device from the line. It refers to minutes.

[0173] When a potential outside a certain range is applied to the wiring to which the protection circuit 306 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0174] As shown in FIG. 13A, a protection circuit 30 is provided in each of a pixel section 302 and a driver circuit section 304. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 306 is not limited to this. For example, A configuration in which the protection circuit 306 is electrically connected, or a configuration in which the protection circuit 30 Alternatively, the protection circuit 30 may be electrically connected to the terminal portion 307. 6 may also be electrically connected.

[0175] In FIG. 13A, the gate driver 304a and the source driver 304b Therefore, although an example in which the driver circuit portion 304 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 304a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0176] In addition, the pixels 101 shown in FIG. 13(A) may have a configuration shown in FIG. 13(B), for example. It is possible.

[0177] The pixel 101 shown in FIG. 13B includes a liquid crystal element 170, a transistor 103, and a capacitor. A liquid crystal element 170, a transistor 103, and a capacitor 10 5, a display device having the structure shown in FIG. 1 in the embodiment mode 1 can be used.

[0178] The potential of one of the pair of electrodes of the liquid crystal element 170 is appropriately set according to the specifications of the pixel 101. The alignment state of the liquid crystal element 170 is set by the written data. A common potential (common potential) is applied to one of a pair of electrodes of the liquid crystal element 170 of each pixel 101. A potential may be applied to one of a pair of electrodes of the liquid crystal element 170 of the pixel 101 in each row. Different potentials may be applied.

[0179] For example, the display device including the liquid crystal element 170 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0180] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be configured by the liquid crystal that exhibits the blue phase. Since it is short and optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0181] In the pixel 101 in the mth row and the nth column, one of the source and drain of the transistor 103 is The other end is electrically connected to the other of the pair of electrodes of the liquid crystal element 170. The gate of the transistor 103 is electrically connected to the scanning line GL_m. The transistor 103 is turned on or off to receive the data signal. The EEPROM has a function for controlling the writing of data.

[0182] One of a pair of electrodes of the capacitor 105 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 170. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel 101. The capacitance element 105 functions as a storage capacitor that stores written data.

[0183] For example, in a display device having the pixel 101 shown in FIG. 13A, the gate driver 304a The pixels 101 in each row are selected in sequence, and the transistors 103 are turned on to output data signals. Write data.

[0184] The pixel 101 to which the data has been written is held by turning off the transistor 103. By performing this process row by row, an image can be displayed.

[0185] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0186] (Embodiment 4) In this embodiment, a display module and a display device in which the display device of one embodiment of the present invention can be used will be described. The electronic device will be described with reference to FIGS. 14 and 15. FIG.

[0187] The display module 8000 shown in FIG. 14 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board It has a board 8010 and a battery 8011 .

[0188] The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0189] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 8006.

[0190] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0191] The backlight unit 8007 includes a light source 8008. Alternatively, the light diffusing plate may be provided at the end of the light unit 8007.

[0192] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0193] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if commercial power is used.

[0194] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0195] 15(A) to 15(H) are diagrams showing electronic devices. These electronic devices are A body 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, and an operation key 50 05 (including a power switch or an operation switch), a connection terminal 5006, a sensor 5007 ( Force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances , sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, 5008, etc.) can.

[0196] FIG. 15A shows a mobile computer, which includes, in addition to the above, a switch 5009. , an infrared port 5010, etc. FIG. 15(B) shows a mobile phone equipped with a recording medium. A portable image reproducing device (e.g., a DVD reproducing device) and, in addition to the above, the following devices are also included: The display unit 5002, the recording medium reading unit 5011, etc. In addition to the above, the display includes a second display unit 5002 and a support unit 5012. , earphones 5013, etc. FIG. 15(D) shows a portable game machine. In addition to the above, the recording medium reading unit 5011 and the like can be included. FIG. 15(E) shows This is a digital camera with a television receiving function, and in addition to the above, it also has an antenna 5014, The mobile phone may have a shutter button 5015, an image receiving unit 5016, etc. This is a slot machine, and in addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, , etc. FIG. 15(G) shows a television receiver, which, in addition to the above, The portable television receiver may include a tuner, an image processor, etc. In addition to the above, the device includes a charger 5017 capable of transmitting and receiving signals. can be done.

[0197] The electronic devices illustrated in FIGS. 15A to 15H can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software (platform A function to control processing by a program, a wireless communication function, and a function to control various Functions for connecting to computer networks, wireless communication functions for transmitting various data, The function of receiving, reading out the program or data recorded on the recording medium and displaying it on the display Furthermore, in an electronic device having a plurality of display units, In this case, one display section is used mainly to display image information, and the other display section is used mainly to display text information. A function to display images with parallax taken into account on multiple displays to create a stereoscopic effect. In addition, the electronic device having an image receiving unit may have a function of displaying an image. These include functions for taking still images, taking videos, and automatically or manually correcting the images. The camera has a function to correct the captured image, a function to save the captured image on a recording medium (external or built-in to the camera), The image displayed on the display unit can have a function of displaying the image. The functions that the electronic device shown in 5(H) can have are not limited to these, and various functions may be included. It is possible to have.

[0198] The electronic device described in this embodiment has a display unit for displaying some information. It is characterized by the above.

[0199] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done. [Explanation of symbols]

[0200] 101 pixels 102 Substrate 103 Transistor 105 Capacitive element 107 Scan Lines 109 Data Line 111 Semiconductor layer 113 Conductive Layer 115 Capacitive Line 117 Aperture 119 Semiconductor layer 121 Pixel electrode 127 Insulating Layer 129 Insulating Layer 131 Insulating layer 133 Insulating Layer 135 Orientation Film 140 Aperture 152 Substrate 154 Light blocking layer 156 colored layer 158 Insulating Layer 160 Conductive layer 162 Orientation Film 164 Liquid crystal layer 170 Liquid crystal element 302 Pixel section 304 Drive circuit section 304a Gate Driver 304b source driver 306 Protection circuit 307 Terminal section 501 pixels 502 Substrate 503 Transistor 505 Capacitive element 507 scan lines 509 Data Line 511 Semiconductor layer 513 Conductive Layer 515 Capacitive Line 517 Aperture 519 Semiconductor Layer 521 Pixel electrode 523 Aperture 525 Conductive Layer 527 Insulating Layer 529 Insulating Layer 531 Insulating layer 533 Insulating Layer 535 Orientation Film 570 Liquid crystal element 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. A pixel electrode; a transistor including a first oxide semiconductor layer; a capacitor including a second oxide semiconductor layer; A scan line, Data lines and wiring, the first oxide semiconductor layer has a region in contact with an upper surface of a first insulating layer; the second oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer; the first oxide semiconductor layer has a region in contact with a lower surface of a second insulating layer; the second oxide semiconductor layer has a region in contact with a lower surface of the second insulating layer, the second oxide semiconductor layer has a region in contact with a lower surface of the wiring, a channel formation region of the transistor is provided in the first oxide semiconductor layer, the channel forming region has an area overlapping with the scan line, the second oxide semiconductor layer functions as one electrode of the capacitor, the pixel electrode has a function as the other electrode of the capacitance element, The pixel electrodes are arranged to extend so as to intersect with the scanning lines, The data lines are arranged to extend so as to intersect with the scanning lines.

2. The first oxide semiconductor layer and the second oxide semiconductor layer have an oxide represented by In-M-Zn oxide, which contains at least indium (In), zinc (Zn) and M (a metal selected from the group consisting of Al, Ga, Ge, Y, Zr, Sn, La, Ce and Hf).

Images