Oscillator circuit and electronic apparatus

Abstract

To realize low power consumption and fast oscillation startup of an oscillator circuit.SOLUTION: An oscillator circuit includes an oscillator (X1), capacitors (C1, C2) connected between both terminals of the oscillator (X1), and an amplifier circuit (A1) whose input terminal is connected to the connection point of the oscillator (X1) and the capacitor (C1), and whose output terminal is connected to the connection point of the capacitor (C1) and the capacitor (C2). The amplifier circuit (A1) includes an N-type transistor (M1) and a P-type transistor (M2) whose connection point of source terminals is connected to the output terminal of the amplifier circuit (A1), a P-type transistor (M3) for connecting the gate terminal of the N-type transistor (M1) to a power supply terminal during oscillation stop and disconnecting the gate terminal of the N-type transistor (M1) from the power supply terminal during oscillation operation, and an N-type transistor (M4) for connecting the gate terminal of the P-type transistor (M2) to the ground during oscillation stop and disconnecting the gate terminal of the P-type transistor (M2) from the ground terminal during oscillation operation.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an oscillator circuit using a resonator. [Background technology]

[0002] In recent years, there has been a demand for longer battery life in small electronic devices with wireless circuits, such as mobile phones and IoT (Internet-Of-Things) devices, making reducing the power consumption of the electronic circuits and electronic components used in the devices an important technological issue.

[0003] In small electronic devices, an inverter-based Pierce oscillator circuit using a quartz crystal resonator as shown in FIG. 10 has been widely used (see Patent Documents 1, 2, and 3). 10 and inverter INV 10 and capacity C 10 ,C 11 It consists of:

[0004] The Pierce oscillator circuit has been used for a long time because of its simple structure. However, the Pierce oscillator circuit has the problem that it cannot generate a large voltage component for oscillation and consumes a large amount of power because it constantly flows current. Another problem with the Pierce oscillator circuit is that it takes a long time to start up oscillation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 3409061 [Patent Document 2] JP 2004-328257 A [Patent Document 3] International Publication No. WO2013 / 035346 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made to solve the above problems, and an object of the present invention is to provide an oscillation circuit that can realize low power consumption and high-speed oscillation startup. [Means for solving the problem]

[0007] The oscillator circuit of the present invention is characterized in that it includes an amplifier circuit having a power supply terminal, a ground terminal, a vibrator, first and second capacitances connected in series between both ends of the vibrator, an input terminal connected to the vibrator and the first capacitance, an output terminal connected to the first capacitance and the second capacitance, a first N-type transistor having a source terminal connected to the output terminal, a drain terminal connected to a first switch connected to the power supply terminal, and a gate terminal connected to the input terminal, a first P-type transistor having a source terminal connected to the output terminal, a drain terminal connected to a second switch connected to the ground terminal, and a gate terminal connected to the input terminal, a second P-type transistor having a source terminal connected to the power supply terminal and a drain terminal connected to the gate terminal of the first N-type transistor and the input terminal, and a second N-type transistor having a source terminal connected to the ground terminal and a drain terminal connected to the gate terminal of the first P-type transistor and the input terminal.

[0008] In addition, in one configuration example of the oscillator circuit of the present invention, the first switch connects the drain of the first N-type transistor to the power supply terminal during oscillation operation and disconnects the drain of the first N-type transistor from the power supply terminal when oscillation stops, the second switch connects the drain of the first P-type transistor to the ground terminal during oscillation operation and disconnects the drain of the first P-type transistor from the ground terminal when oscillation stops, the gate of the second P-type transistor is controlled to be off during oscillation operation and on when oscillation stops, and the gate of the second N-type transistor is controlled to be off during oscillation operation and on when oscillation stops. Moreover, an electronic device according to the present invention is characterized by including the above-mentioned oscillator circuit. Effect of the Invention

[0009] According to the present invention, the gate terminal of the first N-type transistor in the amplifier circuit is connected to the power supply voltage when the second P-type transistor is ON, and the output voltage of the amplifier circuit is fed back to the gate terminal of the first N-type transistor via the first capacitance and the third capacitance, and the gate terminal of the first P-type transistor in the amplifier circuit is connected to ground when the second N-type transistor is ON, and the output voltage of the amplifier circuit is fed back to the gate terminal of the first P-type transistor via the first capacitance and the fourth capacitance, thereby achieving low power consumption and fast oscillation startup. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a conventional Colpitts oscillator circuit. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration of an oscillator circuit according to an embodiment of the present invention. [Diagram 3] FIG. 3 is an equivalent circuit diagram of the oscillator circuit according to the embodiment of the present invention when the bias PMOS transistor and NMOS transistor are OFF. [Figure 4] FIG. 4 is a diagram showing the variation range of the output voltage of the oscillator circuit according to the embodiment of the present invention, and the variation ranges of the gate voltage and gate-source voltage of the bias PMOS transistor and NMOS transistor. [Diagram 5] FIG. 5 is a diagram showing an oscillation waveform after oscillation starts in the oscillator circuit according to the embodiment of the present invention. [Figure 6] FIG. 6 is a diagram showing waveforms of an output voltage and a transistor current in a conventional Pierce oscillator circuit and an oscillator circuit according to an embodiment of the present invention. [Figure 7] FIG. 7 is a circuit diagram showing a configuration of an inverter of a Pierce oscillator circuit. [Figure 8]FIG. 8 is a diagram showing phase noise characteristics of a conventional Pierce oscillator circuit and an oscillator circuit according to an embodiment of the present invention. [Figure 9] FIG. 9 is an equivalent circuit diagram of a Langasite type piezoelectric single crystal resonator and a quartz crystal resonator. [Figure 10] FIG. 10 is a circuit diagram showing the configuration of a conventional Pierce oscillator circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the configuration of a Colpitts oscillator circuit on which the oscillator circuit of this embodiment is based is shown in Fig. 1. The Colpitts oscillator circuit is composed of an oscillator X1, an amplifier circuit A1, and two capacitors C1 and C2.

[0012] <Oscillation circuit configuration> Fig. 2 shows an oscillator circuit of this embodiment, which is based on this Colpitts oscillator circuit and has an amplifier with low power consumption. The oscillator circuit of this embodiment includes a power supply terminal (not shown), a ground terminal (not shown), an oscillator X1, capacitances C1 and C2 connected in series between both terminals of the oscillator X1, and an amplifier circuit A1 having an input terminal connected to the connection point between the oscillator X1 and the capacitance C1 and an output terminal connected to the connection point between the capacitance C1 and the capacitance C2. The power supply terminal refers to the high potential side of the power supply voltage (for example, V dd ) and the ground terminal is the terminal that is connected to the low potential side of the power supply voltage (such as the earth potential or V ss ) is connected to the

[0013] The amplifier circuit A1 is composed of an NMOS transistor (N-type transistor) M1 whose source terminal is connected to the output terminal of the amplifier circuit A1, a PMOS transistor (P-type transistor) M2 whose source terminal is connected to the output terminal of the amplifier circuit A1, a bias reset signal BR input to its gate terminal, a drain terminal connected to the gate terminal of the NMOS transistor M1, and a source terminal connected to the power supply voltage V ddA PMOS transistor M3 is connected to the gate terminal of the PMOS transistor M2, and a bias reset signal BR is input to the gate terminal of the PMOS transistor M3. 、 The source terminal of the NMOS transistor M4 is connected to the ground, one end of the capacitor C is connected to the input terminal of the amplifier circuit A1, and the other end of the capacitor C is connected to the gate terminal of the NMOS transistor M1. cut1 A capacitance C1 has one end connected to the input terminal of the amplifier circuit A1 and the other end connected to the gate terminal of the PMOS transistor M2. cut2 When oscillation stops, the drain terminal of the NMOS transistor M1 and the power supply voltage V dd During oscillation, the drain terminal of the NMOS transistor M1 is disconnected from the power supply voltage V dd and a switch SW2 that disconnects the drain terminal of the PMOS transistor M2 from the ground when oscillation is stopped and connects the drain terminal of the PMOS transistor M2 to the ground when oscillation is in operation.

[0014] Capacity C cut1 is connected between the gate terminal of the NMOS transistor M1 and the drain terminal of the PMOS transistor M3 and the input terminal of the amplifier circuit. cut2 are connected between the gate terminal of the PMOS transistor M2 and the drain terminal of the NMOS transistor M4 and the input terminal of the amplifier circuit. cut1 and capacity C cut2 functions as a circuit component that removes noise such as DC current components. CMOS may be used as the N-type transistors (M1, M4) and the P-type transistors (M2, M3).

[0015] In the specification and claims of this application, when it is explicitly stated that "A and B are connected," this includes cases where A and B are electrically connected, where A and B are functionally connected, and where A and B are directly connected. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, this is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, but also includes connection relationships other than those shown in a figure or text.

[0016] For example, in the case where A and B are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, etc.) that enable the electrical connection between A and B may be connected between A and B.

[0017] Furthermore, when an N-type or P-type transistor is used as a switch, the switch has an input terminal (either the source terminal or the drain terminal), an output terminal (either the source terminal or the drain terminal), and a terminal that controls conduction (gate terminal). By applying a positive or negative voltage to the gate terminal, the current that flows from the input terminal to the output terminal can be controlled, and so it functions as a switch. When the switch is turned on, the terminals on both ends of the switch are connected, and when the switch is turned off, the terminals on both ends of the switch are disconnected.

[0018] The NMOS transistor M1 and the PMOS transistor M2 form a cascode-connected complementary pair. When the PMOS transistor M3 is ON, the gate terminal of the NMOS transistor M1 is connected to the power supply voltage V dd and capacitance C1, C cut1 The output voltage of the amplifier circuit A1 is fed back via the PMOS transistor M2. The gate terminal of the PMOS transistor M2 is connected to the ground when the NMOS transistor M4 is ON, and the capacitances C1 and C cut2 The output voltage of the amplifier circuit A1 is fed back via this.

[0019] <Oscillation circuit operation> The bias reset signal BR and the bias reset signal BR input to the gate terminals of the PMOS transistor M3 and the NMOS transistor M4, and the oscillation enable signal EN which controls the switches SW1 and SW2, can be realized by providing a control circuit (not shown) inside or outside the oscillation circuit that controls the start and stop operation of oscillation and the oscillation operation.

[0020] Since a high transconductance gm is required to start oscillation, the bias reset signal BR is High when oscillation stops, and the bias reset signal BR is Low when oscillation stops. Therefore, the PMOS transistor M3 and the NMOS transistor M4 are ON, and the NMOS transistor M1 and the PMOS transistor M2 are ON.

[0021] When oscillation is stopped, the oscillation enable signal EN goes low, and the switches SW1 and SW2 are turned off. For example, NMOS transistors can be used as the switches SW1 and SW2. The oscillation enable signal EN is input to the gate terminal of the NMOS transistor that serves as the switch SW1, and the drain terminal is connected to the power supply voltage V dd The NMOS transistor serving as switch SW2 has a gate terminal to which the oscillation enable signal EN is input, a drain terminal to which the PMOS transistor M2 has been connected, and a source terminal to which the ground has been connected.

[0022] On the other hand, during oscillation, the bias reset signal BR is low and the bias reset signal BR is high. Therefore, the PMOS transistor M3 and the NMOS transistor M4 are in the OFF state. In this OFF state, the PMOS transistor M3 is represented by an equivalent circuit consisting of a diode D1 and a resistor R1 as shown in FIG. 3(A). Also, the NMOS transistor M4 is represented by an equivalent circuit consisting of a diode D2 and a resistor R2 as shown in FIG. 3(B).

[0023] In other words, when the PMOS transistor M3 is in the OFF state, the gate voltage V gN is biased by the voltage due to the leakage current of the diode D1. Similarly, when the NMOS transistor M4 is in the OFF state, the gate voltage V gP is biased by the voltage due to the leakage current of the diode D2. The resistor R1 represents the resistance component through which the leakage current of the diode D1 flows, and the resistor R2 represents the resistance component through which the leakage current of the diode D2 flows.

[0024] Taking the PMOS transistor M3 as an example, the leakage current of the diode D1 is always equal to the gate voltage V of the NMOS transistor M1. gN When oscillation starts due to a large signal, the gate terminal of the NMOS transistor M1 is pulled up by the capacitances C1 and C2. cut1 However, the gate voltage V of the NMOS transistor M1 is dynamically biased by feedback from the output of the amplifier circuit A1 via the diode D1. gN The highest value is V th3 +V dd The voltage will be clamped to the value of V th3 is the threshold voltage of the PMOS transistor M3). Similarly, the gate voltage V gP The minimum value is -V th4 The voltage will be clamped to the value of V th4 is the threshold voltage of NMOS transistor M4).

[0025] The output voltage V of the oscillator circuit (amplifier circuit A1) during oscillation out , the gate voltage V of the NMOS transistor M1 gN , the gate voltage V of the PMOS transistor M2 gP , the gate-source voltage V of the NMOS transistor M1 gsN , the gate-source voltage V of the PMOS transistor M2 gsP The range of variation is shown in Figure 4. During oscillation, the oscillation enable signal EN goes high, and the switches SW1 and SW2 are turned on.

[0026] <Oscillation waveform of oscillator circuit> The oscillation waveform after oscillation starts is shown in Figure 5. N is the source current of the NMOS transistor M1, I P is the source current of the PMOS transistor M2. The gate-source voltage V of the NMOS transistor M1 gsN and the gate-source voltage V of the PMOS transistor M2 gsP starts at a relatively high voltage when oscillation starts (when the bias reset signal BR and the oscillation enable signal EN go high), and then drops to -V th4 From V th3 Therefore, the current flowing through the NMOS transistor M1 and the PMOS transistor M2 is very small in the steady state.

[0027] Figure 6 shows the output voltage V of the oscillator circuit in a steady state. out , the source current I of the NMOS transistor M1 N , and the source current I P Here, C1=18 pF, C2=9 pF, and the capacitance of the load connected to the output terminal of the oscillation circuit (amplifier circuit A1) is 6 pF.

[0028] For comparison, the output voltage V of the Pierce oscillator circuit when the capacitances C1, C2 and the load capacitance are set to the same values ​​as in this embodiment is out10 and the inverter transistor current I N10 ,I P10 The inverter INV of the Pierce oscillator circuit shown in FIG. 10 As shown in FIG. 7, the transistor M5 is composed of a PMOS transistor M5 and an NMOS transistor M6.

[0029] As can be seen from Figure 6, the current I N10 ,I P10 In comparison, the current IN ,I P is the output voltage V out becomes an extreme value, and the amount of current is very small. Therefore, according to this embodiment, it is possible to achieve a significant reduction in power consumption in the oscillation state. In fact, it was found that the steady-state power consumption Pss of the oscillation circuit of this embodiment is approximately 1 / 10 of the steady-state power consumption of the Pierce oscillator circuit.

[0030] <Phase noise characteristics of oscillator circuits> Fig. 8 shows the phase noise characteristics of the oscillator circuit of this embodiment and the conventional Pierce oscillator circuit. In Fig. 8, N0 shows the phase noise of the Pierce oscillator circuit, and N1 shows the phase noise of the oscillator circuit of this embodiment. It was found that the phase noise, which is an important oscillator circuit performance for communication devices, is improved by about 9 dB in the range of offset frequencies up to 100 Hz with respect to the fundamental frequency of the oscillator circuit, compared to the conventional Pierce oscillator circuit. In this way, it has become clear that the use of the oscillator circuit of this embodiment can contribute to lowering the phase noise of communication devices.

[0031] <Resonators in oscillator circuits> As the oscillator X1 of the oscillation circuit, various oscillators such as a quartz oscillator and a Langasite type piezoelectric single crystal oscillator can be used. In order to start the oscillation circuit oscillating faster and achieve lower oscillation startup energy, in this embodiment, a Langasite type piezoelectric single crystal oscillator is used as the oscillator X1. There are various types of Langasite type piezoelectric single crystals, but in the experiment, Ca3TaGa3Si2O 14 We used a transducer using CTGS. In addition to CTGS, Langasite is also known as Ca3NbGa3Si2O 14 (called CNGS), Ca3Ta(Ga 1-X Al X )3Si2O 14 (called CTGAS), Ca3Nb(Ga 1-X Al X )3Si2O 14The Langasite type piezoelectric single crystal is expressed by a chemical composition such as CTGS (called CNGAS), and the Langasite type piezoelectric single crystal is not limited to the vibrator using CTGS. The equivalent circuits of the CTGS vibrator used and the quartz vibrator used for reference are shown in Fig. 9(A) and Fig. 9(B). Fig. 9(B) is a simplified equivalent circuit diagram of Fig. 9(A). The left side of the line 100 in Fig. 9(A) and Fig. 9(B) shows the equivalent circuit of the vibrator, and the right side of the line 100 shows the equivalent circuit of the oscillation circuit. Capacitance C L , inductance L m , resistance R m , capacity C m , resistance R x , and the Q value are shown in Table 1.

[0032] [Table 1]

[0033] As a result of an experiment using a CTGS resonator as the resonator X1, the oscillation startup time Ts of the oscillation circuit of this embodiment was 0.37 ms and the oscillation startup energy Es was 30 nJ. On the other hand, when a quartz crystal resonator was used as the resonator X1, the oscillation startup time Ts of the oscillation circuit of FIG. 2 was 3.6 ms and the oscillation startup energy Es was 320 nJ.

[0034] Therefore, it was confirmed that when a CTGS resonator is used as resonator X1, it is possible to achieve an oscillation startup time that is approximately one order of magnitude faster than when a quartz crystal resonator is used, and the oscillation startup energy can also be reduced by approximately one order of magnitude, thereby achieving low power consumption.

[0035] As described above, according to this embodiment, it is possible to realize high-speed oscillation startup and an oscillation circuit with low power consumption in a steady oscillation state after oscillation startup. Therefore, if the oscillator circuit of this embodiment is applied to electronic devices such as mobile phones and IoT devices, it can contribute to the realization of electronic devices with low power consumption. [Industrial Applicability]

[0036] The present invention can be applied to an oscillator circuit used in a small electronic device. [Explanation of symbols]

[0037] A1: Amplification circuit, C1, C2, C cut1 ,C cut2 ...capacitor, M1~M4...transistors, SW1, SW2...switches, X1...oscillator.

Claims

1. A power supply terminal, a ground terminal, and a vibrator, an amplifier circuit including: first and second capacitances connected in series between both ends of the vibrator; an input terminal connected to the vibrator and the first capacitance; an output terminal connected to the first capacitance and the second capacitance; a first N-type transistor having a source terminal connected to the output terminal, a drain terminal connected to a first switch connected to the power supply terminal, and a gate terminal connected to the input terminal; a first P-type transistor having a source terminal connected to the output terminal, a drain terminal connected to a second switch connected to the ground terminal, and a gate terminal connected to the input terminal; a second P-type transistor having a source terminal connected to the power supply terminal and a drain terminal connected to the gate terminal of the first N-type transistor and the input terminal; and a second N-type transistor having a source terminal connected to the ground terminal and a drain terminal connected to the gate terminal of the first P-type transistor and the input terminal. An oscillator circuit including:

2. 2. The oscillator circuit of claim 1, an oscillation circuit in which the first switch connects the drain of the first N-type transistor to the power supply terminal during oscillation operation and disconnects the drain of the first N-type transistor from the power supply terminal when oscillation stops, the second switch connects the drain of the first P-type transistor to the ground terminal during oscillation operation and disconnects the drain of the first P-type transistor from the ground terminal when oscillation stops, the gate of the second P-type transistor is controlled to be off during oscillation operation and on when oscillation stops, and the gate of the second N-type transistor is controlled to be off during oscillation operation and on when oscillation stops.

3. 3. An electronic device comprising the oscillator circuit according to claim 1.

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