Ink jet head drive circuit

Abstract

To provide an ink jet head drive circuit which suppresses generation of unnecessary high frequency vibration of an actuator in an ink jet head.SOLUTION: An ink jet head drive circuit includes: a waveform pattern generation section which generates a waveform pattern on the basis of input data; and a drive waveform generation section which generates a drive waveform for driving an actuator on the basis of the waveform pattern. The drive waveform generation section has a power source for supplying drive voltage to be applied to the actuator, a plurality of switch elements for connecting the power source to the actuator, and a drive waveform output section for outputting the drive waveform to drive the actuator by switching ON / OFF of the plurality of switch elements on the basis of the waveform pattern. The waveform pattern changes the number of switch elements to be turned ON of the plurality of switch elements in at least one section of a plurality of sections in one period of the drive waveform for causing the actuator to discharge one drop of ink.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] An embodiment of the present invention relates to an inkjet head drive circuit. [Background technology]

[0002] Generally, an inkjet head has a pressure chamber that contains ink, an actuator that expands and contracts the pressure chamber, and an inkjet head drive circuit that drives the actuator. The inkjet head drive circuit expands and contracts the pressure chamber with the actuator, causing ink to be ejected from a nozzle that communicates with the pressure chamber. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-164677 Summary of the Invention [Problem to be solved by the invention]

[0004] A piezoelectric actuator is usually used as the actuator. A fast rise and fall of the actuator drive waveform is desirable in terms of the actuator's fast response. However, if the rise and fall of the actuator drive waveform is too fast, it will generate unnecessary high-frequency vibrations in the actuator. The generation of such unnecessary high-frequency vibrations will result in a decrease in the quality of printing by the inkjet head.

[0005] An object of the present invention is to provide an inkjet head drive circuit that suppresses the generation of unnecessary high-frequency vibrations in the actuator of the inkjet head. [Means for solving the problem]

[0006] An inkjet head driving circuit according to an embodiment drives an inkjet head having a pressure chamber that contains ink, a nozzle communicating with the pressure chamber, and an actuator that expands and contracts the pressure chamber to eject ink from the nozzle. The inkjet head driving circuit has a waveform pattern generating unit that generates a waveform pattern based on input data, and a drive waveform generating unit that generates a drive waveform for driving the actuator based on the waveform pattern. The drive waveform generating unit has a power source that supplies a drive voltage to be applied to the actuator, multiple switch elements that connect the power source and the actuator, and a drive waveform output unit that outputs a drive waveform for driving the actuator by switching the multiple switch elements ON / OFF based on the waveform pattern. The waveform pattern changes the number of switch elements to be turned ON among the multiple switch elements in at least one section out of multiple sections in one period of the drive waveform that causes the actuator to eject one drop of ink. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an inkjet printer including an inkjet head drive circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of an inkjet head driving circuit according to an embodiment of the present invention. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of a gate driver included in the inkjet head driving circuit according to the embodiment. [Figure 4] FIG. 4 is a diagram showing a list of gate levels, waveform output levels, and ON resistances for each of a plurality of switch elements included in the gate driver shown in FIG. [Diagram 5] FIG. 5 is a diagram showing a list of waveform output levels, switch sizes, ON switches, and parallel resistors for each of the three pairs of switch elements included in the gate driver shown in FIG. [Figure 6] FIG. 6 is a block diagram showing an example of the configuration of a waveform pattern generating section in a conventional inkjet head driving circuit. [Figure 7] FIG. 7 is a diagram showing a list of timer setting times and waveform output levels in one period of a waveform pattern corresponding to one period of a drive waveform in an example of operation of a conventional inkjet head drive circuit. [Figure 8] FIG. 8 is a diagram showing a driving waveform output by the gate driver shown in FIG. 3 in response to the input of the waveform pattern shown in FIG. 7 when the switch size is set to 3 in an example of operation of the inkjet head driving circuit according to the conventional example. [Figure 9] FIG. 9 is a diagram showing a driving waveform output by the gate driver shown in FIG. 3 in response to the input of the waveform pattern shown in FIG. 7 when the switch size is set to 1 in an example of operation of the inkjet head driving circuit according to the conventional example. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a waveform pattern generating section according to a first example of the configuration of an inkjet head driving circuit according to an embodiment. [Figure 11] FIG. 11 is a block diagram showing a configuration example of a waveform pattern generating section according to a second configuration example of the inkjet head driving circuit according to the embodiment. [Figure 12] FIG. 12 is a diagram showing a list of timer setting times, waveform output levels, and switch sizes in one period of a waveform pattern corresponding to one period of a drive waveform in a first operation example of an inkjet head drive circuit according to an embodiment. [Figure 13] FIG. 13 is a diagram showing a driving waveform output by the gate driver shown in FIG. 3 in response to an input of the waveform pattern shown in FIG. 12 in a first operation example of the inkjet head driving circuit according to this embodiment. [Figure 14] FIG. 14 is a diagram showing a list of timer setting times, waveform output levels, and switch sizes in one period of a waveform pattern corresponding to one period of a drive waveform in a second operation example of an inkjet head drive circuit according to an embodiment. [Figure 15]FIG. 15 is a diagram showing a driving waveform output by the gate driver shown in FIG. 3 in response to an input of the waveform pattern shown in FIG. 14 in a second operation example of the inkjet head driving circuit according to this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] (Inkjet printer) First, an inkjet printer 200 having an inkjet head 100 including an inkjet head driving circuit 101 according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of the inkjet printer 200. In the following description, the inkjet printer 200 will be abbreviated as printer 200, the inkjet head 100 will be abbreviated as head 100, and the inkjet head driving circuit 101 will be abbreviated as head driving circuit 101.

[0009] The printer 200 has a head 100. The head 100 has a head drive circuit 101 and an actuator group 102. The actuator group 102 has a plurality of actuators. Each actuator is a drive element for expanding and contracting a pressure chamber that contains ink, and ejecting ink droplets from a nozzle that communicates with the pressure chamber. For example, each actuator is a piezoelectric drive element made of PZT (lead zirconate titanate). The head drive circuit 101 is a circuit that generates a drive signal for the actuator group 102. Each actuator of the actuator group 102 operates according to the drive signal supplied from the head drive circuit 101 to expand and contract a pressure chamber, and eject ink droplets from a nozzle.

[0010] In addition to the head 100, the printer 200 has a processor 201, a ROM (Read Only Memory) 202, a RAM (Random Access Memory) 203, an operation panel 204, a communication interface 205, a conveying motor 206, a motor drive circuit 207, a pump 208, and a pump drive circuit 209. In the drawings, the interface is abbreviated as "IF."

[0011] The printer 200 also has bus lines 210 such as an address bus and a data bus. The processor 201, ROM 202, RAM 203, operation panel 204, communication interface 205, motor drive circuit 207, pump drive circuit 209, and head drive circuit 101 are connected to the bus line 210 directly or via an input / output circuit, and can transmit and receive data among them.

[0012] The processor 201 corresponds to the central part of a computer. The processor 201 controls each part to realize various functions of the printer 200 according to an operating system and application programs. The processor 201 is, for example, a CPU (Central Processing Unit).

[0013] The ROM 202 corresponds to a read-only main memory of the computer. The ROM 202 stores the operating system and application programs. The ROM 202 may also store data necessary for the processor 201 to execute processes for controlling each unit.

[0014] The RAM 203 corresponds to a rewritable main memory portion of the computer. The RAM 203 stores data necessary for the processor 201 to execute processing. The RAM 203 is also used as a work area where information is appropriately rewritten by the processor 201. The work area includes an image memory where print data is expanded.

[0015] The operation panel 204 has an operation section and a display section. The operation section has function keys such as a power key, a paper feed key, an error reset key, etc. The display section can display various states of the printer 200.

[0016] The communication interface 205 receives print data from a client terminal connected via a network such as a LAN (Local Area Network). For example, when an error occurs in the printer 200, the communication interface 205 transmits a signal notifying the client terminal of the error.

[0017] A motor drive circuit 207 controls the drive of the transport motor 206. The transport motor 206 functions as a drive source for a transport mechanism that transports a recording medium such as printing paper. When the transport motor 206 starts, the transport mechanism starts transporting the recording medium. The transport mechanism transports the recording medium to a printing position by the head 100. The transport mechanism ejects the recording medium after printing has been completed from an ejection port (not shown) to the outside of the printer 200.

[0018] A pump drive circuit 209 controls the drive of the pump 208. When the pump 208 is driven, ink in an ink tank (not shown) is supplied to the head 100.

[0019] The head drive circuit 101 drives the actuator group 102 of the head 100 based on the print data. The actuator group 102 expands and contracts pressure chambers that contain ink, causing ink droplets to be ejected from nozzles that communicate with the pressure chambers. In this way, the head 100 ejects ink onto a recording medium transported by a transport mechanism, and prints an image or the like on the recording medium.

[0020] (Head drive circuit) Next, the head drive circuit 101 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the head drive circuit 101 according to the embodiment.

[0021] The head driving circuit 101 includes an I / O section 110, a logic section 120, and an analog section .

[0022] The I / O unit 110 includes a comparator 111 and a serial-to-parallel conversion unit 112. In the drawings, the "serial-to-parallel conversion unit" is abbreviated to "conversion unit."

[0023] A clock signal CLK and a data signal DI of low voltage differential signaling (LVDS) are input to the comparator 111. The data signal DI includes print data, setting data, etc. The comparator 111 outputs the data of the clock signal CLK and the data of the data signal DI to a serial-parallel conversion unit 112.

[0024] The serial-parallel conversion unit 112 converts the serial format data input from the comparator 111 into parallel format data. It acquires the data of the data signal DI at the rising edge of the clock signal CLK. More specifically, it acquires the value (0 or 1) of the setting data and print data included in the data signal DI at the timing when the clock signal CLK changes from 0 to 1. The serial-parallel conversion unit 112 outputs the data of the parallel format data signal DI to the logic unit 120. In addition, the serial-parallel conversion unit 112 outputs the data of the clock signal CLK to the logic unit 120 and the analog unit.

[0025] The logic section 120 includes a start byte recognition section 121, a setting data register 122, a print data register 123, and a waveform pattern generation section .

[0026] Start byte recognition unit 121 recognizes a start byte in the data of parallel data signal DI input from serial-parallel conversion unit 112, and separates the data into setting data and print data. Start byte recognition unit 121 outputs the setting data to setting data register 122, and outputs the print data to print data register 123.

[0027] The setting data register 122 stores the setting data input from the start byte recognition unit 121 .

[0028] The print data register 123 stores the print data input from the start byte recognition unit 121 .

[0029] The waveform pattern generating unit 124 obtains the setting data from the setting data register 122 and the print data from the print data register 123, and generates a waveform pattern based on the setting data and the print data. The waveform pattern generating unit 124 outputs the generated waveform pattern to the analog unit 130.

[0030] In other words, the analog section 130 is a drive waveform generating section that generates a drive waveform based on a waveform pattern. The analog section 130 includes a level shifter 131, a pre-buffer 132, and a gate driver 133.

[0031] The level shifter 131 converts the waveform pattern input from the waveform pattern generating unit 124 into a high voltage waveform pattern. The level shifter 131 outputs the waveform pattern converted into a high voltage waveform pattern to the pre-buffer 132.

[0032] The pre-buffer 132 appropriately amplifies and shapes the waveform pattern input from the level shifter 131. The pre-buffer 132 outputs the appropriately amplified and shaped waveform pattern to the gate driver 133.

[0033] The gate driver 133 outputs a drive waveform for driving the actuator group 102 of the head 100 by controlling ON / OFF of a plurality of switch elements that the gate driver 133 has based on the waveform pattern input from the pre-buffer 132. In other words, the gate driver 133 is a drive waveform output unit that outputs a drive waveform based on the waveform pattern. For example, the switch element is a MOSFET, and the gate driver 133 controls ON / OFF of the MOSFET by applying a control signal (gate voltage) to the gate of the MOSFET.

[0034] (Gate driver) Next, the gate driver 133 included in the head drive circuit 101 according to the embodiment will be described with reference to Fig. 3. Fig. 3 is a block diagram showing an example of the configuration of the gate driver 133 included in the head drive circuit 101 according to the embodiment. The gate driver 133 shown in Fig. 3 is for one actuator PZT in the actuator group 102.

[0035] The gate driver 133 includes a power supply PS and a plurality of switch elements QA, QB, QC, QD, QE, and QF.

[0036] The power supply PS includes a first power supply PSA and a second power supply PSB. The first power supply PSA provides a first voltage VA relative to a reference potential VSS. The second power supply PSB provides a second voltage VB relative to the reference potential VSS. The first voltage VA and the second voltage VB are different voltages. For example, the reference potential VSS is a negative potential, and the first voltage VA is higher than the second voltage VB.

[0037] The multiple switch elements QA to QF include six switch elements QA to QF. The six switch elements QA to QF include a first pair of switch elements QA, QB, a second pair of switch elements QC, QD, and a third pair of switch elements QE, QF. The first pair of switch elements QA, QB connects in parallel between a pair of electrodes of the actuator PZT. The second pair of switch elements QC, QD connects in parallel between the actuator PZT and a first power supply PSA. The third pair of switch elements QE, QF connects in parallel between the actuator PZT and a second power supply PSB.

[0038] Specifically, one electrode of the actuator PZT is connected to one power supply terminal of the first power supply PSA and one power supply terminal of the second power supply PSB and is maintained at the reference potential VSS. A second pair of switch elements QC, QD connects the other electrode of the actuator PZT to the other power supply terminal of the first power supply PSA in parallel. A third pair of switch elements QE, QF connects the other electrode of the actuator PZT to the other power supply terminal of the second power supply PSB in parallel.

[0039] The ON resistance of one switch element QA of the first pair of switch elements QA and QB is different from the ON resistance of the other switch element QB. The ON resistance of one switch element QC of the second pair of switch elements QC and QD is different from the ON resistance of the other switch element QD. The ON resistance of one switch element QE of the third pair of switch elements QE and QF is different from the ON resistance of the other switch element QF.

[0040] For example, the ON resistance of one switch element QA of the first pair of switch elements QA, QB, the ON resistance of one switch element QC of the second pair of switch elements QC, QD, and the ON resistance of one switch element QE of the third pair of switch elements QE, QF are equal to each other.

[0041] In addition, the ON resistance of the other switch element QB of the first pair of switch elements QA, QB, the ON resistance of the other switch element QD of the second pair of switch elements QC, QD, and the ON resistance of the other switch element QF of the third pair of switch elements QE, QF are equal to each other.

[0042] For example, each of the switch elements QA to QF is a MOSFET. Figure 4 shows a list of the gate level, waveform output level, and ON resistance for each of the six switch elements QA to QF. The gate level is the level of the voltage applied to the gate to turn each switch element ON, the waveform output level is the level of the voltage applied to each switch element, and the ON resistance is the resistance when each switch element is ON.

[0043] For switch element QA, the gate level is NAg, the waveform output level is VSS, and the ON resistance is 1000Ω. For switch element QB, the gate level is NBg, the waveform output level is VSS, and the ON resistance is 200Ω. For switch element QC, the gate level is PCg, the waveform output level is VA, and the ON resistance is 1000Ω. For switch element QD, the gate level is PDg, the waveform output level is VA, and the ON resistance is 200Ω. For switch element QE, the gate level is PEg, the waveform output level is VB, and the ON resistance is 1000Ω. For switch element QF, the gate level is PFg, the waveform output level is VB, and the ON resistance is 200Ω.

[0044] For each of the first pair of switch elements QA and QB, the second pair of switch elements QC and QD, and the third pair of switch elements QE and QF, the waveform output level, switch size, ON switch, and parallel resistance are shown in Fig. 5. The ON switch indicates the switch that is turned ON for each pair of switch elements, and the parallel resistance indicates the resistance of each pair of switch elements at that time.

[0045] For example, for the first pair of switch elements QA, QB, the parallel resistance is 167 Ω when both switch elements QA and QB are turned ON, the parallel resistance is 200 Ω when switch element QA is turned OFF and switch element QB is turned ON, and the parallel resistance is 1000 Ω when switch element QA is turned ON and switch element QB is turned OFF. The same is true for the second pair of switch elements QC, QD and the third pair of switch elements QE, QF, as shown in Fig. 5.

[0046] The switch size is an index that indicates the speed of the rise and fall of the drive waveform that drives the actuator PZT. Switch size 3 has a faster rise and fall than switch size 2. Also, switch size 1 has a slower rise and fall than switch size 2.

[0047] The switch size is related to the parallel resistance of each pair of switch elements. More specifically, the switch size of each pair of switch elements is larger when the parallel resistance is low than when the parallel resistance is high. In other words, the rise and fall of each pair of switch elements is faster when the parallel resistance is low than when the parallel resistance is high.

[0048] (Waveform pattern generating section in a head driving circuit according to a conventional example) Next, the waveform pattern generating section 140 in the head drive circuit 101 according to the conventional example will be described with reference to Fig. 6. Fig. 6 is a block diagram showing an example of the configuration of the waveform pattern generating section 140 in the head drive circuit 101 according to the conventional example.

[0049] The waveform pattern generating section 140 has six AND circuits 151 to 156 for controlling the ON / OFF of six switch elements QA to QF in the gate driver 133, respectively.

[0050] The AND circuit 151 outputs a gate signal NAg to be input to the gate of the switch element QA in order to control the ON / OFF of the switch element QA of the first pair of switch elements QA and QB of the gate driver 133. Moreover, the AND circuit 152 outputs a gate signal NBg to be input to the gate of the switch element QB in order to control the ON / OFF of the switch element QB of the first pair of switch elements QA and QB of the gate driver 133. Note that, for convenience, in Fig. 6, the gate levels NAg and NBg shown in Fig. 4 are used to represent the gate signals of the switch element QB of the switch elements QA and QB.

[0051] Similarly, the AND circuits 153 and 154 output gate signals PCg and PDg, respectively, of a second pair of switch elements QC and QD of the gate driver 133. In addition, the AND circuits 155 and 156 output gate signals PEg and PFg, respectively, of a third pair of switch elements QE and QF of the gate driver 133.

[0052] The waveform pattern generating section 140 further includes a waveform timer 141 , a decoder state machine 142 , a waveform level selector 143 , a waveform level selector 144 , and a SW selecting section 146 .

[0053] The waveform timer 141 is a timer circuit that generates a pulse signal for forming ink drops in a multi-drop system. Fire1, Fire2, ..., Fire14 each correspond to an ink drop (tone). Timer [7:0] indicates that the pulse signal is 8-bit data.

[0054] Decoder state machine 142 outputs data specifying the waveform output level to waveform level selector 143 and waveform level selector 144 based on the pulse signal generated by waveform timer 141. FW[2:0] represents 3-bit data corresponding to the waveform output levels VSS, VA, and VB shown in Figures 4 and 5.

[0055] The waveform level selector 143 supplies a control signal VA to the AND circuits 153, 154 for causing the AND circuits 153, 154 to output a waveform output level VA based on the print data.

[0056] The waveform level selector 144 supplies a control signal VB to the AND circuits 155, 156 for causing the AND circuits 155, 156 to output a waveform output level VB based on the print data.

[0057] Furthermore, the waveform pattern generating unit 140 supplies a control signal VSS to the AND circuits 151, 152, by a waveform level selector (not shown), for causing the AND circuits 151, 152 to output a waveform output level VSS based on print data.

[0058] Based on the setting data, the SW selection unit 146 selects a switch element to be turned ON from among six switch elements QA to QF in the gate driver 133. Furthermore, the SW selection unit 146 supplies a control signal Z to the AND circuits 151 to 156 corresponding to the switch elements to be turned ON, causing the switch elements to be turned ON to output a gate signal of a gate level.

[0059] Through the control described above, the logic unit 120 controls the ON / OFF of six switch elements QA to QF in the gate driver 133 in the analog unit 130 based on the print data and setting data, and outputs a drive waveform that drives one actuator PZT in the actuator group 102 of the head 100.

[0060] (Example of operation of a conventional head drive circuit) 6, the SW selector 146 sets the switch size to a constant value based on the setting data when setting (configuring) the head 100. Therefore, the rise and fall speeds of the drive waveform output by the gate driver 133 are constant based on the waveform pattern generated by the waveform pattern generator 140 according to the conventional example.

[0061] Next, the driving waveform output by the head driving circuit 101 according to the conventional example will be described with reference to Fig. 7 to Fig. 9. That is, the driving waveform output by the gate driver 133 based on the waveform pattern generated by the waveform pattern generating unit 140 will be described. For convenience, an example in which one actuator PZT is caused to eject one drop of ink (an example of gradation 1) will be described here.

[0062] FIG. 7 is a diagram showing a list of timer setting times and waveform output levels in one period of a waveform pattern corresponding to one period of a drive waveform for causing one actuator PZT to eject one drop of ink.

[0063] One cycle of the waveform pattern has four sections SA, SB, SC, and SD. The time length of each of the sections SA, SB, SC, and SD is 2.00 μs. The waveform output level in the section SA is VSS, the waveform output level in the section SB is VB, the waveform output level in the section SC is VA, and the waveform output level in the section SD is VSS.

[0064] For example, VSS is a negative potential, VB is a zero potential, and VA is a positive potential. Furthermore, with respect to the pressure chamber that contains ink, section SA corresponds to the expansion section, section SB to the release section, section SC to the contraction section, and section SD to the release section.

[0065] Fig. 8 is a diagram showing the drive waveform of the actuator PZT output by the gate driver 133 in response to the input of the waveform pattern shown in Fig. 7 when the SW selection unit 146 sets the switch size to switch size 3. Also, Fig. 9 is a diagram showing the drive waveform of the actuator PZT output by the gate driver 133 in response to the input of the waveform pattern shown in Fig. 7 when the SW selection unit 146 sets the switch size to switch size 1. Figs. 8 and 9 show the waveform output levels in addition to the drive waveforms.

[0066] As can be seen by comparing Figures 8 and 9, at any switching point in the section where the waveform output level changes, the rise and fall of the drive waveform in Figure 8 is faster than that of the drive waveform in Figure 9. This means that the drive waveform in Figure 8 drives the actuator PZT with a faster response than the drive waveform in Figure 9. This is desirable in terms of improving print quality. However, if the rise and fall of the drive waveform is too fast, it may generate unnecessary high-frequency vibrations in the actuator PZT. The generation of unnecessary high-frequency vibrations may cause a decrease in print quality.

[0067] (Waveform Pattern Generator According to First Configuration Example of Head Driving Circuit According to Embodiment) Next, a waveform pattern generating unit 160 according to a first configuration example in the head driving circuit 101 according to the embodiment will be described with reference to Fig. 10. Fig. 10 is a block diagram showing a configuration example of the waveform pattern generating unit 160 according to the first configuration example in the head driving circuit 101 according to the embodiment. In Fig. 10, members with the same reference symbols as those shown in Fig. 6 are similar members, and detailed description thereof will be omitted. The following description will focus on the differences.

[0068] The waveform pattern generating section 160 according to the first configuration example includes, like the waveform pattern generating section 140, a waveform timer 141, a decoder state machine 142, a waveform level selector 143, a waveform level selector 144, and six AND circuits 151-156.

[0069] The details of the waveform timer 141, the decoder state machine 142, the waveform level selector 143, the waveform level selector 144, and the six AND circuits 151 to 156 are as described above.

[0070] The waveform pattern generating section 160 according to the first configuration example has a SW selecting section 166 instead of the SW selecting section 146 of the waveform pattern generating section 140. The SW selecting section 166 selects a switching element to be turned ON from among six switching elements QA to QF in the gate driver 133 based on setting data. Furthermore, the SW selecting section 166 supplies a control signal Z to the AND circuits 151 to 156 corresponding to the switching elements to be turned ON, the control signal Z causing the switching elements to be turned ON to output a gate signal of a gate level. In this respect, the SW selecting section 166 is similar to the SW selecting section 146.

[0071] As described above, the SW selection unit 146 sets the switch size to a constant value based on the setting data when setting up (configuring) the head 100. In other words, the SW selection unit 146 cannot change the switch size. For this reason, the head drive circuit 101 having the conventional waveform pattern generation unit 140 outputs the drive waveform from the gate driver 133 with a constant rise and fall speed.

[0072] In contrast to this, the head driving circuit 101 having the waveform pattern generating unit 160 according to the first configuration example is able to change the rise and fall speed of the driving waveform output from the gate driver 133. In other words, the head driving circuit 101 having the waveform pattern generating unit 160 according to the first configuration example can change the switch size during one period of the driving waveform that causes the actuator PZT to eject one drop of ink.

[0073] In other words, the head driving circuit 101 having the waveform pattern generating section 160 according to the first configuration example can change the parallel resistance of the switch element pairs in the gate driver 133 during one period of the driving waveform, i.e., during one period of the waveform pattern. Therefore, the head driving circuit 101 having the waveform pattern generating section 160 according to the first configuration example can change the number of switch elements that are turned ON, among the switch elements QA to QF in the gate driver 133, during one period of the waveform pattern. More specifically, the head driving circuit 101 having the waveform pattern generating section 160 can change the switch element pairs that are turned ON, among the multiple switch element pairs in the gate driver 133, during one period of the waveform pattern.

[0074] For this reason, the SW selection section 166 of the waveform pattern generation section 160 according to the first configuration example has a timer 167 and a decoder state machine 168.

[0075] The set time of timer 167 is the same as the set time of waveform timer 141. For this reason, Timer [7:0] indicating the set time of timer 167 is the same as Timer [7:0] indicating the set time of waveform timer 141, and the pulse signal is 8-bit data.

[0076] The decoder state machine 168 outputs a control signal Z that changes the number of switch elements to be turned ON among the six switch elements QA to QF in the gate driver 133 during one period of the waveform pattern, to the six AND circuits 151 to 156, based on the set time of the timer 167. In other words, the control signal Z is selection data that selects the switch elements to be turned ON among the switch elements QA to QF in the gate driver 133 during one period of the waveform pattern.

[0077] That is, in the waveform pattern generating unit 160 according to the first configuration example, the SW selecting unit 166 generates selection data for selecting, during one period of the waveform pattern, switch elements to be turned ON from among the switch elements QA to QF in the gate driver 133. That is, the SW selecting unit 166 is a selection data generating unit that generates selection data for selecting, during one period of the waveform pattern, switch elements to be turned ON from among the switch elements QA to QF in the gate driver 133.

[0078] (Waveform Pattern Generator in Second Configuration Example of Head Driving Circuit According to Embodiment) Next, a waveform pattern generating unit 170 according to a second configuration example in the head driving circuit 101 according to the embodiment will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a configuration example of the waveform pattern generating unit 170 according to the second configuration example in the head driving circuit 101 according to the embodiment.

[0079] The waveform pattern generating section 170 according to the second configuration example includes a waveform timer 171, a decoder state machine 172, a waveform level selector 173, and a waveform level selector 174.

[0080] The functions of the waveform timer 171 are similar to those of the waveform timer 141 of the waveform pattern generating unit 140 .

[0081] Decoder state machine 172 outputs data specifying the waveform output level to waveform level selector 173 and waveform level selector 174 based on the pulse signal generated by waveform timer 171. Furthermore, decoder state machine 172 outputs data specifying which of six switch elements QA to QF in gate driver 133 is to be turned ON to waveform level selector 173 and waveform level selector 174 based on the setting data.

[0082] For this reason, decoder state machine 172 outputs 5-bit data FW[4:0] to waveform level selector 173 and waveform level selector 174. As described above, the data specifying the waveform output level is 3-bit data. Also, each pair of switch elements in gate driver 133 is turned ON / OFF together. For this reason, the data specifying the switch element to be turned ON is 2-bit data.

[0083] Based on the data input from the decoder state machine 172 and the print data, the waveform level selector 173 sets the waveform output level of the second pair of switch elements QC, QD in the gate driver 133 to VA, and controls the ON / OFF of the second pair of switch elements QC, QD.

[0084] Based on the data input from the decoder state machine 172 and the print data, the waveform level selector 174 sets the waveform output level of the third pair of switch elements QE, QF in the gate driver 133 to VB, and controls the ON / OFF of the third pair of switch elements QE, QF.

[0085] Furthermore, the waveform pattern generating unit 170 uses a waveform level selector (not shown) to set the waveform output level of a first pair of switch elements QA, QB in the gate driver 133 to VSS based on the data input from the decoder state machine 172 and the print data, and also controls the ON / OFF of the first pair of switch elements QA, QB.

[0086] With this configuration, the waveform pattern generating section 170 according to the second configuration example can operate in the same manner as the waveform pattern generating section 160 according to the first configuration example.

[0087] That is, the head driving circuit 101 having the waveform pattern generating unit 170 according to the second configuration example can change the switch size during one period of the driving waveform that causes the actuator PZT to eject one drop of ink. In other words, the head driving circuit 101 having the waveform pattern generating unit 170 according to the second configuration example can change the parallel resistance of the switch element pairs in the gate driver 133 during one period of the driving waveform. Therefore, the head driving circuit 101 having the waveform pattern generating unit 170 according to the second configuration example can change the number of switch elements that are turned ON among the switch elements QA to QF in the gate driver 133 during one period of the driving waveform. More specifically, the head driving circuit 101 having the waveform pattern generating unit 170 can change the switch element pairs that are turned ON among the multiple switch element pairs in the gate driver 133 during one period of the driving waveform.

[0088] (First Operation Example of Head Driving Circuit According to Embodiment) Next, a first operation example of the head driving circuit 101 according to the embodiment will be described with reference to Fig. 12 and Fig. 13. That is, a driving waveform output by the gate driver 133 based on a waveform pattern generated by the waveform pattern generating unit 160 according to the first configuration example or the waveform pattern generating unit 170 according to the second configuration example will be described. For convenience, an example in which one actuator PZT is made to eject one drop of ink (an example of gradation 1) will be described here.

[0089] FIG. 12 is a diagram showing a list of timer setting times, waveform output levels, and switch sizes in one period of a waveform pattern corresponding to one period of a drive waveform for causing one actuator PZT to eject one drop of ink in the first operation example.

[0090] One cycle of the waveform pattern in the first operation example has four sections SA, SB, SC, and SD. The time length of each of the sections SA, SB, SC, and SD is 2.00 μs. The waveform output level in the section SA is VSS, the waveform output level in the section SB is VB, the waveform output level in the section SC is VA, and the waveform output level in the section SD is VSS.

[0091] For example, VSS is a negative potential, VB is zero potential, and VA is a positive potential. Also, for the pressure chamber that contains ink, section SA corresponds to the expansion section, section SB corresponds to the release section, section SC corresponds to the contraction section, and section SD corresponds to the release section. The pressure chamber ejects ink when switching from the expansion section of section SA to the release section of section SB.

[0092] As described above, the waveform pattern generating unit 160 according to the first configuration example or the waveform pattern generating unit 170 according to the second configuration example can change the switch size. The switch size in the section SA is 1, the switch size in the section SB is 3, the switch size in the section SC is 1, and the switch size in the section SD is 1.

[0093] Fig. 13 is a diagram showing the drive waveform of the actuator PZT output by the gate driver 133 in response to the input of the waveform pattern shown in Fig. 12. Fig. 13 also shows the waveform output level and switch size in addition to the drive waveform.

[0094] The actuator PZT exhibits a fast response to switch size 3 and a slow response to switch size 1. For this reason, the drive waveform shown in Fig. 13 has a fast rise only in section SB for switch size 3, and a slow rise and fall in the other sections SA, SC, and SD for switch size 1.

[0095] Therefore, in the sections SA, SC, and SD, it is possible to suppress the generation of unnecessary high-frequency vibrations in the actuator PZT. On the other hand, in the section SB, the rise of the drive waveform is fast, so it is possible to suppress the deterioration of print quality due to distortion of the drive waveform.

[0096] Thus, in the first operation example, the head driving circuit 101 according to the embodiment changes the number of switch elements QA to QF in the gate driver 133 that are turned ON between multiple sections of a waveform pattern that corresponds to one cycle of a drive waveform that causes the actuator PZT to eject one drop of ink. More specifically, the head driving circuit 101 according to the embodiment can change the switch element pairs that are turned ON between multiple switch element pairs in the gate driver 133 during one cycle of the drive waveform.

[0097] As a result, the head driving circuit 101 in the first operation example can suppress the occurrence of unnecessary high-frequency vibrations in the actuator PZT while suppressing deterioration of print quality by changing the parallel resistance of the switch element pair in the gate driver 133.

[0098] (Second Operation Example of Head Driving Circuit According to Embodiment) Next, a second operation example of the head driving circuit 101 according to the embodiment will be described with reference to Figures 14 and 15. That is, a driving waveform output by the gate driver 133 based on a waveform pattern generated by the waveform pattern generating unit 160 according to the first configuration example or the waveform pattern generating unit 170 according to the second configuration example will be described. For convenience, an example in which one actuator PZT is made to eject one drop of ink (an example of gradation 1) will be described here.

[0099] FIG. 14 is a diagram showing a list of timer setting times, waveform output levels, and switch sizes in one period of a waveform pattern corresponding to one period of a drive waveform for causing one actuator PZT to eject one drop of ink in the second operation example.

[0100] One cycle of the waveform pattern in the second operation example has seven sections SA, SB, SC, SD, SE, SF, and SG. The time length of the sections SA, SD, and SF is 0.20 μs, the time length of the sections SB, SE, and SG is 1.80 μs, and the time length of the section SC is 2.00 μs. The waveform output level in the sections SA and SB is VSS, the waveform output level in the section SC is VB, the waveform output level in the sections SD and SE is VA, and the waveform output level in the sections SF and SG is VB. The switch size in the sections SA, SD, and SF is 1, and the switch size in the sections SB, SC, SE, and SG is 3.

[0101] For example, VSS is a negative potential, VB is zero potential, and VA is a positive potential. Also, for the pressure chamber that contains ink, sections SA and SB correspond to expansion sections, section SC corresponds to release sections, sections SD and SE correspond to contraction sections, and sections SF and SG correspond to release sections. The pressure chamber ejects ink when switching from the expansion section of section SB to the release section of section SC.

[0102] Fig. 15 is a diagram showing the drive waveform of the actuator PZT output by the gate driver 133 in response to the input of the waveform pattern shown in Fig. 14. Fig. 15 also shows the waveform output level and switch size in addition to the drive waveform.

[0103] In one cycle of the drive waveform, in sections SA and SB where the initial waveform output level is VSS, the switch size in the initial 0.20 μs section SA is 1, so the fall of the drive waveform changes relatively slowly. In contrast, in the 1.80 μs section SB following section SA, the switch size is 3, so the fall of the drive waveform changes relatively quickly.

[0104] In section SC of 2.00 μs following section SB where the waveform output level is VB, the switch size is 3, so that the rising edge of the drive waveform changes quickly.

[0105] In sections SD and SE following section SC, where the waveform output level is VA, the switch size in the initial 0.20 μs section SE is 1, so the rise of the drive waveform changes relatively slowly. In contrast, in the 1.80 μs section SE following section SD, the switch size is 3, so the rise of the drive waveform changes relatively quickly.

[0106] In sections SF and SG following section SE where the waveform output level is VB, the switch size in the initial 0.20 μs section SF is 1, so the fall of the drive waveform changes relatively slowly. In contrast, in the 1.80 μs section SG following section SF, the switch size is 3, so the fall of the drive waveform changes relatively quickly.

[0107] Thus, in the second operation example, the head drive circuit 101 according to the embodiment changes the switch size in at least one of the multiple sections based on the waveform output level in one period of the waveform pattern corresponding to one period of the drive waveform for ejecting one drop of ink from one actuator PZT. Specifically, the head drive circuit 101 according to the second operation example changes the switch size in each of the three sections SA, SB, SD, SE, and SF, SG based on the waveform output level.

[0108] More specifically, the head driving circuit 101 according to the second operation example changes the switch size, i.e., the number of switch elements QA to QF in the gate driver 133 that are turned ON, during the initial period and the subsequent period in each of the three sections SA, SB, SD, SE, and SF, SG. More specifically, the head driving circuit 101 according to the second operation example changes which switch element pairs are turned ON, among the multiple switch element pairs in the gate driver 133, during one period of the driving waveform.

[0109] More specifically, the head driving circuit 101 in the second operation example increases the switch size throughout the entire section SC that contributes to ink ejection, and in other sections, decreases the switch size during the initial period and increases the switch size during the subsequent period.

[0110] As a result, the head driving circuit 101 according to the second operation example can suppress the occurrence of unnecessary high-frequency vibrations in the actuator PZT, while suppressing the deterioration of print quality.

[0111] (effect) As described above, the head driving circuit 101 according to the embodiment changes the number of switch elements QA to QF in the gate driver 133 to be turned on during a plurality of sections of a waveform pattern corresponding to one cycle of a driving waveform that causes the actuator PZT to eject one drop of ink. For example, the head driving circuit 101 according to the embodiment changes the number of switch elements to be turned on during at least one of a plurality of sections based on a waveform output level. This makes it possible to appropriately adjust the rise and fall speeds at appropriate points during one cycle of the driving waveform. As a result, it becomes possible to suppress the generation of unnecessary high-frequency vibrations in each actuator PZT of the actuator group 102 of the head 100 by lowering the rise and fall speeds at appropriate points during one cycle of the driving waveform, while suppressing deterioration of print quality by increasing the rise and fall speeds at appropriate points during one cycle of the driving waveform.

[0112] (Modification) In the description of the embodiment, an example has been described in which the gate driver 133 has six switch elements, i.e., three pairs of switch elements, and the waveform output level input to the gate driver 133 has three potentials. However, this is merely an example, and the present invention is not limited to this. That is, the gate driver 133 may have more than three pairs of switch elements, and the waveform output level input to the gate driver 133 may have more than three potentials. For example, the gate driver 133 may have five pairs of switch elements, and the waveform output level input to the gate driver 133 may have five potentials.

[0113] (others) The program according to the present embodiment may be transferred in a state where it is stored in an electronic device, or in a state where it is not stored in an electronic device. In the latter case, the program may be transferred via a network, or in a state where it is stored in a storage medium. The storage medium is a non-transitory tangible medium. The storage medium is a computer-readable medium. The storage medium may be in any form, such as a CD-ROM or a memory card, as long as it is capable of storing a program and is computer-readable.

[0114] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0115] 100...inkjet head, 101...inkjet head drive circuit, 102...actuator group, 110...I / O section, 111...comparator, 112...serial-to-parallel conversion section, 120...logic section, 121...start byte recognition section, 122...setting data register, 123...print data register, 124...waveform pattern generation section, 130...analog section, 131...level shifter, 132...pre-buffer, 133...gate driver, 140...waveform pattern generation section, 141...waveform timer, 142...decoder state machine, 143...waveform level selector, 144...waveform level selector, 146 ...selection unit, 151 to 156...AND circuits, 160...waveform pattern generation unit, 166...selection unit, 167...timer, 168...decoder state machine, 170...waveform pattern generation unit, 171...waveform timer, 172...decoder state machine, 173...waveform level selector, 174...waveform level selector, 200...inkjet printer, 201...processor, 202...ROM, 203...RAM, 204...operation panel, 205...communication interface, 206...conveyor motor, 207...motor drive circuit, 208...pump, 209...pump drive circuit, 210...bus line, QA to QF...switching elements.

Claims

1. An inkjet head drive circuit for driving an inkjet head having a pressure chamber for storing ink, a nozzle communicating with the pressure chamber, and an actuator for expanding and contracting the pressure chamber to eject ink from the nozzle, comprising: a waveform pattern generating unit for generating a waveform pattern based on input data; a drive waveform generating unit that generates a drive waveform for driving the actuator based on the waveform pattern, The drive waveform generating unit includes: a power source for supplying a drive voltage to be applied to the actuator; a plurality of switch elements connecting the power source and the actuator; a drive waveform output unit that outputs the drive waveform for driving the actuator by switching ON / OFF of the plurality of switch elements based on the waveform pattern, the waveform pattern varies the number of switch elements to be turned ON among the plurality of switch elements in at least one section of a plurality of sections in one cycle of the drive waveform that causes the actuator to eject one drop of ink; Inkjet head drive circuit.

2. the power supply includes a first power supply providing a first voltage relative to a reference potential and a second power supply providing a second voltage relative to the reference potential; The plurality of switch elements include a first pair of switch elements connecting the actuators in parallel; a second pair of switch elements connecting in parallel between the actuator and the first power source; a third pair of switch elements connecting in parallel between the actuator and the second power source; an ON resistance of one of the first pair of switch elements is different from an ON resistance of the other of the first pair of switch elements; an ON resistance of one of the second pair of switch elements is different from an ON resistance of the other of the second pair of switch elements; an ON resistance of one of the third pair of switch elements is different from an ON resistance of the other of the third pair of switch elements; 2. The inkjet head drive circuit according to claim 1.

3. the ON resistance of the one switch element of the first pair of switch elements, the ON resistance of the one switch element of the second pair of switch elements, and the ON resistance of the one switch element of the third pair of switch elements are equal to each other, the ON resistance of the other switch element of the first pair of switch elements, the ON resistance of the other switch element of the second pair of switch elements, and the ON resistance of the other switch element of the third pair of switch elements are equal to each other; 3. The inkjet head drive circuit according to claim 2.

4. the waveform pattern generating unit has a selection data generating unit that generates selection data for selecting the switch element to be turned ON during one cycle of the waveform pattern.

2. The inkjet head drive circuit according to claim 1.

5. The waveform pattern generated by the waveform pattern generating unit includes selection data for selecting the switch element to be turned ON.

2. The inkjet head drive circuit according to claim 1.

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