Wiring board and manufacturing method therefor, and semiconductor device

Abstract

To provide a wiring board that reduces a risk of short-circuiting between adjacent projection electrodes.SOLUTION: A wiring board has an insulation layer, a recessed part which is open to the side of an upper surface of the insulation layer, a projection electrode including a part embedded in the insulation layer and a part projecting into the recessed part. In cross-sectional view, the width of the part projecting into the recessed part is equal to the width of the part embedded in the insulation layer, and an upper surface of the projection electrode is located below the upper surface of the insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board, a manufacturing method thereof, and a semiconductor device. [Background technology]

[0002] As semiconductor elements become more highly functional, the electrodes of the semiconductor elements are being spaced at narrower pitches, which has led to a demand for narrower pitches of protruding electrodes connected to the semiconductor elements in wiring boards on which the semiconductor elements can be mounted (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6608108 Summary of the Invention [Problem to be solved by the invention]

[0004] As the pitch of the protruding electrodes becomes narrower, adjacent protruding electrodes are more likely to short-circuit when connected to a semiconductor element.

[0005] The present invention has been made in view of the above-mentioned points, and has an object to provide a wiring board in which the risk of short-circuiting between adjacent protruding electrodes is reduced. [Means for solving the problem]

[0006] This wiring board has an insulating layer, a recess opening to the upper surface of the insulating layer, and a protruding electrode including a portion embedded in the insulating layer and a portion protruding into the recess, and in a cross-sectional view, the width of the portion protruding into the recess is equal to the width of the portion embedded in the insulating layer, and the upper surface of the protruding electrode is located below the upper surface of the insulating layer. Effect of the Invention

[0007] According to the disclosed technique, it is possible to provide a wiring board in which the risk of short-circuiting between adjacent protruding electrodes is reduced. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Diagram 2] 1A to 1C are diagrams illustrating a manufacturing process of the wiring board according to the first embodiment (part 1). [Diagram 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 5A to 5C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; [Diagram 5] 1A to 1C are diagrams illustrating a manufacturing process of a wiring board according to a comparative example. [Figure 6] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to a comparative example. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 8] 6 is a cross-sectional view illustrating a wiring board according to a modified example of the first embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated explanations may be omitted.

[0010] [Wiring board structure] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. Referring to FIG 1, wiring board 1 has insulating layer 11, wiring layer 12, protruding electrodes 13, and insulating layer 17.

[0011] In this embodiment, for convenience, the insulating layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the insulating layer 11 side is referred to as the lower side or the other side. Also, the surface of each part facing the insulating layer 17 is referred to as the upper surface or one side, and the surface facing the insulating layer 11 is referred to as the lower surface or the other side. However, the wiring board 1 can be used upside down or placed at any angle. Also, the planar view refers to the object being viewed from the normal direction of the upper surface of the insulating layer 17, and the planar shape refers to the shape of the object being viewed from the normal direction of the upper surface of the insulating layer 17.

[0012] The insulating layer 11 is an insulating layer that can be formed by using a build-up method, for example, as an interlayer insulating layer of multilayer wiring. Therefore, other wiring layers or other insulating layers may be laminated as layers below the insulating layer 11. In this case, via holes can be appropriately provided in the insulating layer 11 or other insulating layers, and the wiring layers can be connected to each other through the via holes.

[0013] The material of the insulating layer 11 may be, for example, a non-photosensitive (thermosetting resin) epoxy insulating resin or polyimide insulating resin. The material of the insulating layer 11 may be, for example, a photosensitive epoxy insulating resin or an acrylic insulating resin. The thickness of the insulating layer 11 may be, for example, about 20 to 40 μm. The insulating layer 11 may contain a filler such as silica (SiO2).

[0014] The wiring layer 12 is formed on the insulating layer 11. The wiring layer 12 may have a structure in which an electrolytic plating layer 12b is laminated on a seed layer 12a. The seed layer 12a is, for example, a copper layer having a thickness of about 100 to 350 nm. The seed layer 12a may be a laminate film in which a copper layer having a thickness of about 100 to 300 nm is laminated on a titanium layer having a thickness of about 20 to 50 nm. The electrolytic plating layer 12b is, for example, a copper layer having a thickness of about 10 to 20 μm. Since the seed layer 12a is extremely thin, the thickness of the electrolytic plating layer 12b may be regarded as the total thickness of the wiring layer 12.

[0015] The protruding electrode 13 is formed on a part of the upper surface of the wiring layer 12. The protruding electrode 13 can include a first metal layer 14, a second metal layer 15, and a third metal layer 16. The first metal layer 14 is laminated on the upper surface of the wiring layer 12. The second metal layer 15 is laminated on the upper surface of the first metal layer 14, and does not extend to the side of the first metal layer 14. That is, the upper surface of the first metal layer 14 is covered by the second metal layer 15, but the side of the first metal layer 14 is exposed from the second metal layer 15. The third metal layer 16 is laminated on the upper surface of the second metal layer 15, and does not extend to the side of the second metal layer 15. That is, the upper surface of the second metal layer 15 is covered by the third metal layer 16, but the side of the second metal layer 15 is exposed from the third metal layer 16.

[0016] The bump electrode 13 may be formed from only the first metal layer 14, or may be formed from only the first metal layer 14 and the second metal layer 15.

[0017] The first metal layer 14 is, for example, a copper layer. The first metal layer 14 has a thickness of, for example, about 5 to 10 μm. The second metal layer 15 is, for example, a nickel layer. The second metal layer 15 has a thickness of, for example, about 0.1 to 3 μm. The third metal layer 16 includes, for example, a gold layer. The third metal layer 16 may be composed of only a gold layer, or may have a configuration in which a gold layer is laminated on a palladium layer. The third metal layer 16 has a thickness of, for example, about 0.01 to 0.1 μm.

[0018] The insulating layer 17 is laminated on the upper surface of the insulating layer 11, and covers the upper surface and side surface of the wiring layer 12 and a part of the side surface of the protruding electrode 13. The insulating layer 17 has a recess 17x that opens to the upper surface side. In a cross-sectional view, the connection portion between the bottom surface and the side surface of the recess 17x may be rounded as shown in FIG. 1, or may be a shape close to a right angle. In a plan view, the outer edge of the recess 17x is located outside the outer edge of the protruding electrode 13. A space exists between the entire circumference of the side surface of the protruding electrode 13 in the portion protruding into the recess 17x and the inner side surface of the recess 17x. The width of the space is, for example, about 0.5 to 5 μm.

[0019] The protruding electrode 13 includes a portion embedded in the insulating layer 17 and a portion protruding into the recess 17x. In the first embodiment, the lower portion of the first metal layer 14 constituting the protruding electrode 13 is embedded in the insulating layer 17, and the upper portion of the first metal layer 14, the second metal layer 15, and the third metal layer 16 protrude into the recess 17x.

[0020] The protruding electrode 13 is, for example, cylindrical. In the cross-sectional view, the width W1 of the portion of the protruding electrode 13 protruding into the recess 17x is equal to the width W2 of the portion embedded in the insulating layer 17. Here, "equal" refers to the case where the larger of the widths W1 and W2 is 1.1 times or less the smaller of the widths. The upper surface of the protruding electrode 13 is located below the upper surface of the insulating layer 17. In the first embodiment, the upper surface of the protruding electrode 13 is the upper surface of the third metal layer 16. The interval L1 between adjacent protruding electrodes 13 can be, for example, about 5 to 30 μm.

[0021] [Method of manufacturing wiring board] Next, a method for manufacturing the wiring board according to the first embodiment will be described. Figures 2 to 4 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.

[0022] First, in the step shown in FIG. 2(a), an insulating layer 11 is prepared. Then, a seed layer 12a is formed on the upper surface of the insulating layer 11 by electroless plating or sputtering. Furthermore, an electrolytic plating layer 12b is selectively formed on the seed layer 12a. Specifically, first, a plating resist layer having an opening in the area where the electrolytic plating layer 12b is to be formed is formed on the seed layer 12a. Then, the electrolytic plating layer 12b is formed in the opening by electrolytic plating in which power is supplied from the seed layer 12a. Thereafter, the plating resist layer is removed to complete the structure shown in FIG. 2(a). The materials and thicknesses of the insulating layer 11, the seed layer 12a, and the electrolytic plating layer 12b are as described above.

[0023] 2(b), a resist layer 300 is formed on the insulating layer 11 to cover the seed layer 12a and the electrolytic plating layer 12b. For example, a photosensitive dry film resist can be used as the resist layer 300. The resist layer 300 is then exposed and developed to form an opening 300x that exposes a portion of the upper surface of the electrolytic plating layer 12b. The planar shape of the opening 300x can be, for example, a circle.

[0024] 2(c), a first metal layer 14 is formed in the opening 300x. Specifically, for example, the first metal layer 14 is formed on the electrolytic plating layer 12b exposed in the opening 300x by electrolytic plating in which power is supplied from the seed layer 12a. The material of the first metal layer 14 is as described above. The thickness of the first metal layer 14 is set to be sufficient in consideration of the polishing and etching processes described below.

[0025] 3(a), the resist layer 300 is removed by a resist remover or the like. Then, the seed layer 12a exposed from the electrolytic plating layer 12b is removed by wet etching or the like. This completes the wiring layer 12 in which the electrolytic plating layer 12b is laminated on the seed layer 12a.

[0026] 3(b), an insulating layer 17 is formed on the insulating layer 11 to cover the wiring layer 12 and the first metal layer 14. Specifically, for example, a film-like insulating resin in a semi-cured state that covers the upper and side surfaces of the wiring layer 12 and the first metal layer 14 is laminated on the insulating layer 11 and cured to form the insulating layer 17. Alternatively, instead of laminating a film-like insulating resin, a liquid or paste-like insulating resin may be applied and then cured to form the insulating layer 17. The material of the insulating layer 17 is as described above. The thickness of the insulating layer 17 may be a thickness that can cover the upper surface of the first metal layer 14.

[0027] Next, in the step shown in FIG. 3(c), the upper surface side of the insulating layer 17 is polished to expose the upper surface of the first metal layer 14. When polishing the upper surface side of the insulating layer 17, the upper surface side of the first metal layer 14 may also be polished. For example, a chemical mechanical polishing (CMP) method can be used for the polishing. After polishing, the upper surface of the first metal layer 14 and the upper surface of the insulating layer 17 can be made flush with each other, for example. Furthermore, when the upper surface side of the first metal layer 14 is polished together with the upper surface side of the insulating layer 17, even if there is a variation in height of the first metal layer 14 formed in the step shown in FIG. 2(c), the height of the plurality of first metal layers 14 can be made uniform by polishing using the CMP method.

[0028] 4(a), the upper surface of the first metal layer 14 is removed to make the upper surface of the first metal layer 14 lower than the upper surface of the insulating layer 17. The upper surface of the first metal layer 14 can be removed by, for example, wet etching. If the first metal layer 14 is copper, for example, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride, an aqueous solution of ammonium persulfate, or the like can be used for etching.

[0029] 4(b), a second metal layer 15 and a third metal layer 16 are sequentially laminated on the upper surface of the first metal layer 14 to form the protruding electrode 13. For example, a nickel layer is first formed as the second metal layer 15 on the upper surface of the first metal layer 14 by electroless plating. Next, a palladium layer and a gold layer are sequentially formed as the third metal layer 16 on the upper surface of the second metal layer 15 by electroless plating. Since the side surfaces of the first metal layer 14 are all covered with the insulating layer 17, the second metal layer 15 and the third metal layer 16 are formed only on the upper surface of the first metal layer 14.

[0030] Next, in the step shown in Fig. 4(c), a recess 17x that opens to the upper surface side of the insulating layer 17 is formed. The recess 17x can be formed by, for example, isotropic plasma etching. Since an etching reaction occurs in all directions in isotropic plasma etching, the upper surface of the insulating layer 17 and the insulating layer 17 located on the side surface of the protruding electrode 13 are etched by the same amount, forming the recess 17x. Since anisotropic plasma etching causes an etching reaction to occur only in a specific direction, the recess 17x cannot be formed.

[0031] The recess 17x may be, for example, circular in plan view. A part of the protruding electrode 13 is exposed in the recess 17x. Specifically, the lower part of the first metal layer 14 is embedded in the insulating layer 17, and the upper part of the first metal layer 14, the second metal layer 15, and the third metal layer 16 protrude into the recess 17x. The thickness of the insulating layer 17 is thinner than that in the process shown in FIG. 4(b). The upper surface of the third metal layer 16 is located lower than the upper surface of the insulating layer 17. Through the above processes, the wiring board 1 is completed.

[0032] [Comparative Example] 5A to 5C are diagrams illustrating a manufacturing process of a wiring board according to a comparative example. First, in the process shown in Fig. 5A, a wiring layer 12 is formed on an insulating layer 11, and an insulating layer 17 that covers the wiring layer 12 is further formed.

[0033] 5(b), the insulating layer 17 is exposed and developed to form a recess 17x that opens to the upper surface side of the insulating layer 17. Then, a laser beam is irradiated into the recess 17x to form a through hole 17y that communicates with the recess 17x. The recess 17x is, for example, circular in plan view, and the through hole 17y is, for example, circular with a smaller diameter than the recess 17x in plan view. The upper surface of the wiring layer 12 is exposed in the through hole 17y.

[0034] 5(c), a first metal layer 14A is formed in the through hole 17y and the recess 17x. Specifically, for example, a nickel layer is formed by electroless plating to fill the through hole 17y and to serve as the first metal layer 14A extending into the recess 17x. Since the first metal layer 14A grows isotropically by electroless plating, the first metal layer 14A extending into the recess 17x spreads laterally along the inner side surface of the recess 17x.

[0035] 5(d), a second metal layer 15A is formed to cover the first metal layer 14A protruding into the recess 17x, forming the protruding electrode 13A. Specifically, for example, a palladium layer and a gold layer are sequentially formed as the second metal layer 15A on the upper and side surfaces of the first metal layer 14A by electroless plating. This completes the wiring board according to the comparative example.

[0036] In the wiring board according to the comparative example, in a cross-sectional view, the width of the portion of the protruding electrode 13A protruding into the recess 17x is wider than the width of the portion embedded in the insulating layer 17. In the wiring board according to the comparative example, the interval between the portions of the protruding electrode 13A covered by the insulating layer 17 is L2, but the interval between the portions protruding into the recess 17x is L3. That is, the designed interval between the protruding electrodes 13A is L2, but the actual interval between the protruding electrodes 13A is L3, which is shorter than the designed value. Therefore, when a semiconductor element is connected to the protruding electrodes 13A, there is a risk of a short circuit between adjacent protruding electrodes 13A. A specific description will be given below.

[0037] The process of connecting a semiconductor element to a bump electrode is, for example, as shown in Fig. 6. First, in the process shown in Fig. 6(a), a joint 20 is disposed on the second metal layer 15A of the bump electrode 13A. Next, in the process shown in Fig. 6(b), a reflow process is performed to form the joint 20 that covers the upper and side surfaces of the second metal layer 15A. The joint 20 is, for example, solder. Examples of the solder material that can be used include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu.

[0038] Next, in the step shown in Fig. 6(c), a semiconductor element 30 including a semiconductor substrate 31 and electrodes 32 is prepared, and the electrodes 32 and protruding electrodes 13A are joined by joints 20. As shown in Fig. 5(d), the interval L3 between adjacent protruding electrodes 13A is shorter than the design value. Therefore, in the step shown in Fig. 6(c), there is a risk that the joints 20 will overflow and flow onto the upper surface of the insulating layer 17, which may cause a short circuit between adjacent protruding electrodes 13A.

[0039] 1 and other figures, in the wiring board 1, the protruding electrodes 13 have the same width in both the portions covered by the insulating layer 17 and the portions protruding from the insulating layer 17, and there are no portions that extend laterally to narrow the gap between adjacent protruding electrodes 13. In other words, the gap L1 between the protruding electrodes 13 shown in FIG. 1 is the design value.

[0040] That is, in the wiring board 1, the distance L1 between adjacent protruding electrodes 13 is not shortened from the design value. Therefore, when the protruding electrodes 13 are joined to the electrodes 32 of the semiconductor element 30 by the same method as that shown in FIG. 6, it is possible to reduce the risk of the adjacent protruding electrodes 13 short-circuiting due to overflow of solder.

[0041] Fig. 7 is a cross-sectional view illustrating a semiconductor device according to the first embodiment. The semiconductor device 2 shown in Fig. 7 has the wiring board 1 shown in Fig. 1 and a semiconductor element 30 mounted on the wiring board 1. The protruding electrodes 13 of the wiring board 1 and the electrodes 32 of the semiconductor element 30 are electrically connected via conductive joints 20.

[0042] As described above, in wiring board 1, protruding electrodes 13 have a uniform width and there are no portions that narrow the gap between adjacent protruding electrodes 13, so there is little risk of joint portion 20 overflowing and causing a short circuit between adjacent protruding electrodes 13.

[0043] Moreover, the first metal layer 14 and the second metal layer 15, which have good solder wettability, are formed only on the upper surface of the bump electrode 13, and not on the side surfaces. Therefore, the joint 20 is likely to be formed on the first metal layer 14 and the second metal layer 15, which have good solder wettability, and is unlikely to be formed on the side surfaces of the bump electrode 13. Therefore, the joint 20 is unlikely to spread laterally. In particular, when the side surfaces of the bump electrode 13 are oxidized, the joint 20 is unlikely to be formed. Since the joint 20 can be prevented from flowing into the recess 17x, it is easy to keep the height of the joint 20 constant.

[0044] In addition, the recesses 17x are formed deep enough to expose a part of the side surface of the protruding electrode 13. Therefore, even if the amount of the joint portion 20 becomes excessive for some reason and the joint portion 20 flows onto the side surface of the protruding electrode 13 where the solder does not easily wet, the presence of an area for storing the excess joint portion 20 on the bottom side of the recesses 17x can prevent the joint portion 20 from flowing onto the upper surface side of the insulating layer 17.

[0045] It is preferable that the bonding portion 20 is located below the upper surface of the insulating layer 17. This can further reduce the risk of the bonding portion 20 flowing toward the upper surface side of the insulating layer 17.

[0046] Modification of the First Embodiment In the modified example of the first embodiment, an example is shown in which the thickness of the metal layer constituting the bump electrode is different from that of the first embodiment. Note that in the modified example of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0047] Fig. 8 is a cross-sectional view illustrating a wiring board according to a modified example of the first embodiment. Referring to Fig. 8, wiring board 1A differs from wiring board 1 in that first metal layer 14 is thinner and second metal layer 15 is thicker in bump electrode 13.

[0048] In the wiring board 1A, in the protruding electrode 13, the lower part of the second metal layer 15 and the first metal layer 14 are embedded in the insulating layer 17, and the upper part of the second metal layer 15 and the third metal layer protrude into the recess 17x. In the wiring board 1A, the overall thickness and spacing L1 of the protruding electrodes 13 are the same as those in the wiring board 1, and the upper surface of the protruding electrodes 13 is located lower than the upper surface of the insulating layer 17. In the protruding electrode 13, the width W1 of the part protruding into the recess 17x in a cross-sectional view is equal to the width W2 of the part embedded in the insulating layer 17.

[0049] In this way, in the protruding electrode 13, the first metal layer 14 does not necessarily protrude into the recess 17x, and the second metal layer 15 and the third metal layer 16 may protrude into the recess 17x. In this case, the same effects as in the first embodiment are achieved.

[0050] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0051] 1,1A Wiring board 2. Semiconductor Devices 11 Insulating layer 12 wiring layer 12a Seed layer 12b Electrolytic plating layer 13 Protruding electrode 14 1st metal layer 15 Second metal layer 16 Third metal layer 17 Insulating layer 17x recess 17y through hole 20 Joint 30 Semiconductor elements 31 Semiconductor Substrate 32 electrodes

Claims

1. An insulating layer; a recessed portion that opens to an upper surface side of the insulating layer; a protruding electrode including a portion embedded in the insulating layer and a portion protruding into the recess, In a cross-sectional view, a width of a portion protruding into the recess is equal to a width of a portion embedded in the insulating layer; A wiring board, wherein an upper surface of the protruding electrode is located lower than an upper surface of the insulating layer.

2. 2. The wiring board according to claim 1, wherein a space exists between an inner side surface of the recess and an entire periphery of a side surface of the protruding electrode of the portion protruding into the recess.

3. The protruding electrode is A first metal layer; a second metal layer laminated on an upper surface of the first metal layer and not extending to a side surface of the first metal layer; 2. The wiring board according to claim 1, wherein a lower portion of the first metal layer is embedded in the insulating layer, and an upper portion of the first metal layer and the second metal layer protrude into the recess.

4. The protruding electrode is A first metal layer; a second metal layer laminated on an upper surface of the first metal layer and not extending to a side surface of the first metal layer; 2 . The wiring board according to claim 1 , wherein a lower portion of the second metal layer and the first metal layer are embedded in the insulating layer, and an upper portion of the second metal layer protrudes into the recess.

5. 5. The wiring board according to claim 3, wherein the first metal layer is a copper layer, and the second metal layer is a nickel layer.

6. 6. The wiring board according to claim 5, wherein the bump electrode includes a third metal layer laminated on an upper surface of the second metal layer and not extending to a side surface of the second metal layer.

7. The wiring board according to claim 6 , wherein the third metal layer includes a gold layer.

8. The wiring board according to claim 1 ; A semiconductor element mounted on the wiring board, the bump electrode and the electrode of the semiconductor element are electrically connected via a conductive joint; The semiconductor device, wherein the joint is located below an upper surface of the insulating layer.

9. forming an insulating layer covering the protruding electrodes; a step of polishing an upper surface side of the insulating layer to expose an upper surface of the bump electrode from the insulating layer; removing an upper surface side of the protruding electrode to make the upper surface of the protruding electrode lower than the upper surface of the insulating layer; forming a recess that opens to an upper surface side of the insulating layer, In a cross-sectional view, a width of a portion protruding into the recess is equal to a width of a portion embedded in the insulating layer; A method for manufacturing a wiring substrate, wherein an upper surface of the protruding electrode is located lower than an upper surface of the insulating layer.

10. The method for manufacturing a wiring board according to claim 9 , wherein the recess is formed by isotropic plasma etching.

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