Semiconductor device

Abstract

To provide a semiconductor device in which the deterioration of characteristics can be suppressed.SOLUTION: A semiconductor device 100 includes a first transistor 35a including a first source electrode 12a, a first drain electrode 16a, and a first gate electrode 14a, a second transistor 35c including a second source electrode 12c, a second drain electrode 16c, and a second gate electrode 14c, a first gate wire 24 having the second source electrode held between the first gate wire and the second gate electrode, provided in the first source electrode when viewed from a second direction, and electrically connected to the first gate electrode, and a back surface metal layer electrically connected to the first source electrode through a via hole 20a penetrating the substrate. A first end of the via hole that is far from the second transistor is farther from the second transistor than a second end of an active region that is far from the second transistor in a region where the first gate electrode is provided as viewed from a first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] In a field effect transistor (FET) having finger-shaped source, gate and drain electrodes, it is known to arrange a plurality of unit FETs each having a source, gate and drain electrode in the extension direction of the electrodes (e.g., Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A [Patent Document 2] US Patent Application Publication No. 2017 / 0271329 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, by arranging multiple unit FETs in the extension direction of the electrodes, the width of the gate electrode in the unit FET can be shortened. This makes it possible to suppress the gate resistance. However, since the source electrode and the gate wiring overlap in a plan view, the gate-source parasitic capacitance increases, degrading the characteristics.

[0005] The present disclosure has been made in consideration of the above problems, and aims to suppress deterioration of characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure includes a substrate having a main surface and a back surface opposite to the main surface, a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode in a first direction, the first transistor being provided on the main surface in an active region provided in the substrate, a second source electrode provided within the first source electrode when viewed from a second direction intersecting the first direction and electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode sandwiched between the second source electrode and the second drain electrode in the first direction. a first gate wiring provided on the main surface, sandwiching the second source electrode between the first gate electrode and the second gate electrode, provided within the first source electrode as viewed from the second direction, and electrically connected to the first gate electrode; and a back surface metal layer provided on the back surface and electrically connected to the first source electrode through a via hole penetrating the substrate, wherein a first end of the via hole farther from the second transistor as viewed from the first direction is farther from the second transistor than a second end of the active region in a region where the first gate electrode is provided, the first end being farther from the second transistor. Effect of the Invention

[0007] According to the present disclosure, deterioration of characteristics can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line CC in FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line DD in FIG. [Figure 6] FIG. 6 is a plan view of the semiconductor device according to the first comparative example. [Figure 7] FIG. 7 is an enlarged plan view of the semiconductor device in the first embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 9] FIG. 9 is a plan view of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is an enlarged plan view of the semiconductor device in the second embodiment. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to a first modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a substrate having a main surface and a back surface opposite to the main surface, a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode in a first direction, the first transistor being provided on the main surface in an active region of the substrate, a second source electrode provided within the first source electrode when viewed from a second direction intersecting the first direction and electrically connected to the first source electrode, a second drain electrode electrically connected to the first drain electrode, and a second gate electrode sandwiched between the second source electrode and the second drain electrode in the first direction. a second transistor provided on the main surface, a first gate wiring provided on the main surface, sandwiching the second source electrode between the second gate electrode and the first source electrode as viewed from the second direction, the first gate wiring being provided within the first source electrode as viewed from the second direction and electrically connected to the first gate electrode, and a back surface metal layer provided on the back surface and electrically connected to the first source electrode through a via hole penetrating the substrate, wherein a first end of the via hole farther from the second transistor as viewed from the first direction is farther from the second transistor than a second end of the active region in a region where the first gate electrode is provided, the first end being farther from the second transistor as viewed from the first direction. This makes it possible to suppress source inductance and suppress deterioration of characteristics. (2) In the above (1), the via hole may be provided within the first source electrode when viewed in a thickness direction of the substrate, thereby increasing the contact area between the via hole and the first source electrode and reducing the source inductance and source resistance. (3) In the above (2), the first transistor may be sandwiched between the first transistor and the second transistor, a drain bus bar provided on the main surface, and drain wiring connecting the first drain electrode and the second drain electrode to the drain bus bar, wherein a distance between the first source electrode and the drain wiring at a third end of the first source electrode farther from the second transistor as viewed from the first direction may be greater than a distance between the first source electrode and the drain wiring at the second end, thereby suppressing drain-source parasitic capacitance. (4) In the above (3), the third end of the first source electrode may be provided on an inactive region provided on the substrate, thereby making it possible to suppress drain-source parasitic capacitance. (5) In the above (3) or (4), the distance between the first source electrode and the drain wiring may increase from the second end to the third end, thereby suppressing drain-source parasitic capacitance. (6) In any one of the above (1) to (5), the gate width of the first transistor may be 0.9 to 1.1 times the gate width of the second transistor, thereby making it possible to uniformize the characteristics of the transistors. (7) In any one of the above (1) to (6), the first gate electrode and the second gate electrode may be separated between the first transistor and the second transistor, thereby making it possible to suppress deterioration of characteristics. (8) In any one of the above (1) to (6), the first gate electrode and the second gate electrode may be connected between the first transistor and the second transistor, thereby reducing gate resistance. (9) In any one of the above (1) to (8), the semiconductor device may further include a fourth transistor provided on the main surface, the fourth transistor including: a third drain electrode sandwiching the first source electrode between the first source electrode and the first gate electrode; a third gate electrode sandwiched between the first source electrode and the third drain electrode in the first direction and electrically connected to the first gate wiring; a fourth source electrode sandwiching the first gate wiring between the second source electrode and the second source electrode, provided within the first source electrode as viewed from the second direction and electrically connected to the first source electrode; a fourth drain electrode sandwiching the fourth source electrode between the first gate wiring and the first gate wiring; and a fourth gate electrode sandwiched between the fourth source electrode and the fourth drain electrode in the first direction, the fourth transistor provided on the main surface. This allows transistors to be arranged in the first and second directions. (10) In any one of (1) to (9) above, the device may further include a source wiring provided on the main surface and electrically connecting the first source electrode and the second source electrode, and a second gate wiring provided on the main surface and electrically connecting the first gate wiring and the first gate electrode, thereby electrically connecting the first gate electrode and the gate wiring. (11) In any one of (1) to (10) above, the semiconductor device may further include a gate bus bar provided on the main surface and connected to the second gate electrode and the first gate wiring, and a drain bus bar provided on the main surface, sandwiching the first transistor and the second transistor between the gate bus bar in the second direction and electrically connected to the first drain electrode and the second drain electrode. This allows a gate potential to be supplied from the gate bus bar to the gate electrode, and a drain potential to be supplied from the drain bus bar to the drain electrode.

[0010] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] A semiconductor device used in an amplifier for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station for mobile communication will be described as an example. Fig. 1 is a plan view of the semiconductor device in Example 1. Figs. 2 to 5 are AA, BB, CC, and DD cross-sectional views in Fig. 1, respectively. The thickness direction of the substrate 10 is the Z direction, the extension direction of the finger-shaped source electrode 12, gate electrode 14, and drain electrode 16 is the Y direction (a second direction intersecting the first direction), and the arrangement direction of the source electrode 12, gate electrode 14, and drain electrode 16 is the X direction (a first direction).

[0012] 1 and other plan views, it is difficult to see when the source electrode 12 and the drain electrode 16a overlap with the source wiring 22 and the drain wiring 26. For this reason, a thick dashed line showing only the outer periphery of the source wiring 22 and the drain wiring 26 is illustrated inside the source electrode 12 and the drain electrode 16, with the source wiring 22 and the drain wiring 26 seen through.

[0013] In each figure, the active region 11, the source electrode 12, the gate electrode 14, the drain electrode 16, the source wiring 22, the drain wiring 26, and the transistor 35 (unit FET) indicate general elements, and the active regions 11a, 11c, 11d, the source electrodes 12a, 12c, 12d, the gate electrodes 14a to 14d, the drain electrodes 16a to 16d, the source wirings 22a to 22c, the drain wirings 26a and 26b, and the transistors 35a to 35d indicate specific elements included in the general elements. In the following, the transistors 35a to 35d will be mainly described using the active regions 11a, 11c, 11d, the source electrodes 12a, 12c, 12d, the gate electrodes 14a to 14d, the drain electrodes 16a to 16d, the source wirings 22a to 22c, and the drain wirings 26a and 26b.

[0014] 1 to 5, in the semiconductor device 100 of the first embodiment, the substrate 10 has a main surface 50 and a back surface 52 opposing the main surface 50. A plurality of transistors 35a to 35d are provided on the main surface of the substrate 10. The transistors 35, 35a to 35d arranged in the Y direction form transistor groups 38, 38a, and 38b. In the Y direction, the drain bus bar 36 and the gate bus bar 34 are provided on the main surface 50 and sandwich the transistor groups 38, 38a, and 38b between them.

[0015] The transistors 35 closest to the drain bus bar 36 are transistors 35a and 35b. The transistors 35 closer to the gate bus bar 34 than the transistors 35a and 35b are transistors 35c and 35d. The transistor group 38a includes one transistor 35a and three transistors 35c. The transistor group 38b includes one transistor 35b and three transistors 35d. The number of transistors 35c may be one or more, and the number of transistors 35d may be one or more.

[0016] The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In an XY plane parallel to the X and Y directions, a region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is an inactive region 13, and a region that has not been inactivated (a region through which current flows when the transistor is in an on-state) is an active region 11a, 11c, and 11d. The active region 11a extends in the X direction. The active regions 11c and 11d are arranged in the X direction. The three active regions 11c are arranged in the Y direction, and the three active regions 11d are arranged in the Y direction. The active region 11a is provided with transistors 35a and 35b. The active regions 11c and 11d are provided with transistors 35c and 35d, respectively.

[0017] The transistor 35a (first transistor) includes a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode). The source electrode 12a and the drain electrode 16a sandwich the gate electrode 14a in the X direction. The source electrode 12a, the gate electrode 14a, and the drain electrode 16a are arranged in order in the positive direction of the X direction.

[0018] The transistor 35b (third transistor) includes a source electrode 12a, a gate electrode 14b (third gate electrode), and a drain electrode 16b (third drain electrode). The drain electrode 16b and the gate electrode 14a sandwich the source electrode 12a. The source electrode 12a and the drain electrode 16b sandwich the gate electrode 14b in the X direction. The source electrode 12a, the gate electrode 14b, and the drain electrode 16b are arranged in this order in the negative direction of the X direction. The transistors 35a and 35b share the source electrode 12a.

[0019] The transistor 35c (second transistor) includes a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode). The source electrode 12c and the drain electrode 16c sandwich the gate electrode 14c in the X direction. The source electrode 12c is provided inside the source electrode 12a when viewed from the Y direction. That is, the source electrode 12c is not provided outside the source electrode 12a when viewed from the Y direction. The multiple source electrodes 12c overlap each other when viewed from the Y direction. The multiple drain electrodes 16c overlap each other when viewed from the Y direction. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are sequentially arranged in the + direction of the X direction.

[0020] The transistor 35d (fourth transistor) includes a source electrode 12d (third source electrode), a gate electrode 14d (fourth gate electrode), and a drain electrode 16d (fourth drain electrode). The source electrode 12d sandwiches the gate wiring 24 with the source electrode 12c, and is provided inside the source electrode 12a when viewed from the Y direction. That is, the source electrode 12d is not provided outside the source electrode 12a when viewed from the Y direction. The multiple source electrodes 12d overlap each other when viewed from the Y direction. The multiple drain electrodes 16d overlap each other when viewed from the Y direction. The source electrode 12d and the drain electrode 16d sandwich the gate electrode 14d in the X direction. The source electrode 12d, the gate electrode 14d, and the drain electrode 16d are arranged in order in the negative direction of the X direction.

[0021] A source wiring 22c is provided on the source electrode 12a in contact with it. When viewed from the X direction, the positive end of the source electrode 12a in the Y direction is located farther from the transistors 35c and 35d than the positive ends of the gate electrodes 14a and 14b in the Y direction. When viewed from the X direction, a portion 54 of the source electrode 12a farther from the transistors 35c and 35d than the gate electrodes 14a and 14b is provided on the inactive region 13.

[0022] A source wiring 22a (first source wiring) is provided on and in contact with the source electrode 12c. The source wiring 22a extends in the Y direction, electrically connects the source electrodes 12c to one another, and electrically connects the source electrodes 12c to the source wiring 22c. A source wiring 22b (second source wiring) is provided on and in contact with the source electrode 12d. The source wiring 22b extends in the Y direction, electrically connects the source electrodes 12d to one another, and electrically connects the source electrodes 12d to the source wiring 22c.

[0023] A drain wiring 26a is provided on and in contact with the drain electrodes 16a and 16c. The drain wiring 26a extends in the Y direction, electrically connects the drain electrodes 16a and 16c to each other, and electrically connects the drain electrodes 16a and 16c to the drain bus bar 36. A drain wiring 26b is provided on and in contact with the drain electrodes 16b and 16d. The drain wiring 26b extends in the Y direction, electrically connects the drain electrodes 16b and 16d to each other, and electrically connects the drain electrodes 16b and 16d to the drain bus bar 36.

[0024] A gate wiring 24 (first gate wiring) extending in the Y direction is provided on the inactive region 13 between the transistors 35c and 35d. The gate wiring 24 is provided inside the source electrode 12a when viewed from the Y direction. In other words, the gate wiring 24 is not provided outside the source electrode 12a when viewed from the Y direction. The gate wiring 24 is electrically connected to the gate bus bar 34. The gate wiring 24 includes a gate metal layer 24a provided on the substrate 10 and a wiring layer 24b provided on and in contact with the gate metal layer 24a.

[0025] Between the transistors 35a and 35c, and on the inactive region 13 between the transistors 35c, there is provided a gate wiring 25a (second gate wiring) extending in the X direction. The gate wiring 25a crosses the source wiring 22a without contacting it, and electrically connects the gate wiring 24 to the gate electrodes 14a and 14c. Between the transistors 35b and 35d, and on the inactive region 13 between the transistors 35d, there is provided a gate wiring 25b (third gate wiring) extending in the X direction. The gate wiring 25b crosses the source wiring 22b without contacting it, and electrically connects the gate wiring 24 to the gate electrodes 14b and 14d. As a result, the gate electrodes 14a to 14d are electrically connected to the gate bus bar 34 via the gate wirings 24, 25a, and 25b. Gate electrodes 14c and 14d of transistors 35c and 35d which are closest to gate bus bar 34 are electrically connected directly to gate bus bar 34 without passing through gate wirings 24, 25a and 25b.

[0026] The via hole 20a is provided so as to penetrate the substrate 10 and straddle the source electrode 12a on the active region 11a to the source electrode 12a on the inactive region 13. A metal layer 28 is provided on the rear surface 52 of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20a. This allows the metal layer 28 (rear surface metal layer) to be electrically connected to the source electrode 12a via the via hole 20a. The planar shape of the via hole 20a may be an ellipse, an oval, a rounded rectangle, or a circle. The via hole 20a is not connected to the source electrodes 12c and 12d.

[0027] A source potential (e.g., a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrode 12a via the metal layer 28a in the via hole 20a. Furthermore, the source potential is supplied from the source wiring 22c to the source electrodes 12c and 12d via the source wirings 22a and 22b, respectively. A gate potential (e.g., a high-frequency signal and a gate bias voltage) is supplied from the gate bus bar 34 to the gate electrodes 14a to 14d via the gate wirings 24, 25a and 25b. A drain bias voltage is supplied from the drain bus bar 36 to the drain electrodes 16a to 16d via the drain wirings 26a and 26b. The high-frequency signals amplified in the transistors 35a to 35d are output to the drain bus bar 36 from the drain wirings 26a and 26b.

[0028] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the transistors 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes an arsenide semiconductor layer, such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer, etc. The semiconductor device 100 may be a silicon semiconductor device, such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS).

[0029] The source electrodes 12a, 12c, and 12d and the drain electrodes 16a to 16d are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d and the gate metal layer 24a are metal films, for example, nickel films and gold films from the substrate 10 side. The source wirings 22a to 22c, the drain wirings 26a, 26b, the wiring layer 24b, the metal layers 28, 28a, and the drain bus bar 36 are, for example, gold layers, copper layers, or aluminum layers. The insulating layer 30 provided on the substrate 10 so as to cover the transistors 35a to 35d is, for example, an organic insulator layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0030] The width of the source electrode 12a in the X direction is, for example, 50 μm to 150 μm. The width of the source electrodes 12c and 12d in the X direction is, for example, 5 μm to 20 μm. The gate lengths of the gate electrodes 14a to 14d in the X direction are, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a to 16d in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 24 in the X direction is, for example, 5 μm to 20 μm. The width of the gate wirings 25a and 25b in the Y direction is, for example, 3 μm to 20 μm. The gate width of the transistors 35a to 35d in the Y direction is, for example, 100 μm to 400 μm. The width of the via hole 20a in the X direction is, for example, 10 μm to 60 μm.

[0031] The widths in the X direction of the source wirings 22a to 22c and the drain wirings 26a and 26b are the same as, or slightly smaller than, or larger than, the widths in the X direction of the source electrodes 12a, 12c, and 12d and the drain electrodes 16a and 16d, respectively. The thicknesses of the source wirings 22a to 22c and the drain wirings 26a and 26b are, for example, 1 μm to 20 μm.

[0032] [Comparative Example 1] Fig. 6 is a plan view of a semiconductor device according to Comparative Example 1. As shown in Fig. 6, in the semiconductor device 110 of Comparative Example 1, the + end in the Y direction of the source electrode 12a is positioned at approximately the same position as the + end in the Y direction of the active region 11a when viewed from the X direction. The other configurations are the same as those of Example 1.

[0033] In Comparative Example 1, a gate potential is supplied to gate electrodes 14a to 14d via gate wirings 24, 25a, and 25b, so that the gate resistance can be reduced. Since the gate wiring 24 does not overlap with source electrodes 12c and 12d in a plan view, the gate-source parasitic capacitance can be reduced compared to Patent Documents 1 and 2.

[0034] The widths of the active regions 11a, 11c, and 11d in the Y direction of the multiple transistors 35a to 35d correspond to gate widths Wg1 to Wg4. If the gate widths Wg1 to Wg4 are different from one another, the operations of the multiple transistors 35a to 35d will become non-uniform, degrading the high-frequency characteristics of the semiconductor device 110. For this reason, the gate widths Wg1 to Wg4 are made approximately equal.

[0035] By reducing the gate widths Wg1 to Wg4, the gate resistance is reduced, and high frequency characteristics such as gain can be improved. However, if the gate widths Wg1 to Wg4 are equally reduced, the width of the source electrode 12a in the Y direction is reduced. This reduces the width of the via hole 20a in the Y direction. This increases the source inductance and source resistance between the metal layer 28 and the source electrode 12a via the via hole 20a. This reduces the gain. Thus, even if an attempt is made to reduce the gate resistance to improve the gain, the source inductance increases, making it difficult to improve the gain.

[0036] [Explanation of Example 1] 7 is an enlarged plan view of the semiconductor device in Example 1, enlarging the vicinity of the source electrode 12a. The source electrode 12a, source wiring 22c, and via hole 20a (solid lines) in Example 1 are illustrated superimposed with the source electrode 12a, source wiring 22c, and via hole 20a (dotted lines) in Comparative Example 1.

[0037] 7, in Comparative Example 1, the width in the Y direction of the source electrode 12a and the source wiring 22a is approximately the gate width Wg1. In contrast, in Example 1, the width W1 in the Y direction of the source electrode 12a and the source wiring 22a is larger than the gate width Wg1 by a width W2. The width W2 corresponds to the distance between the + end in the Y direction of the active region 11a and the + end in the Y direction of the source electrode 12a.

[0038] As a result, the width W3 in the Y direction of the via hole 20a in Example 1 can be made larger than the width W5 in the Y direction of the via hole 20a in Comparative Example 1 by about width W2. Therefore, in Example 1, as viewed from the X direction, the end Y1 (first end) of the via hole 20a far from the transistor 35c is farther from the transistor 35c than the end Y2 (second end) of the active region 11a in the region where the gate electrode 14a is provided, far from the transistor 35c. In other words, the via hole 20a spans both the active region 11a (first active region) and the inactive region 13 where the substrate 10 is not activated. This allows the area of ​​the via hole 20a to be larger than that of Comparative Example 1. Therefore, by reducing the gate widths Wg1 to Wg4, the gate resistance can be suppressed and the source inductance can be suppressed. Therefore, the deterioration of high-frequency characteristics such as the gain of the semiconductor device can be suppressed.

[0039] From the viewpoint of increasing the area of ​​the via hole 20a, the width W4 between the ends Y1 and Y2 can be set to 0.1 times or more, and 0.2 times or more, the width W3 of the via hole 20a in the Y direction. From the viewpoint of miniaturization, the width W4 can be set to 0.5 times or less the width W2.

[0040] From the viewpoint of increasing the area of ​​the via hole 20a, the width W6 between the end of the source electrode 12a and the end of the via hole 20a in the Y direction can be set to 0.3 times or less, and can be set to 0.2 times or less, the width W1 of the source electrode 12a in the Y direction. The end and width of the via hole 20a are defined at the point where the via hole 20a contacts the main surface 50 of the substrate 10.

[0041] From the viewpoint of equalizing the high frequency characteristics of the transistors 35a to 35d, the gate width Wg1 of the transistor 35a can be set to 0.9 to 1.1 times, or 0.95 to 1.05 times, the gate width Wg2 of the transistor 35c. The gate widths Wg1 to Wg4 can be set to be equal to the manufacturing error.

[0042] As shown in FIGS. 1 to 5, by providing the transistors 35b and 35d, the transistors 35 can be arranged in the X and Y directions.

[0043] The source wiring 22a electrically connects the source electrodes 12a and 12c. The gate wiring 25a electrically connects the gate wiring 24 and the gate electrode 14a. This allows the gate electrode 14a and the gate wiring 24 to be electrically connected.

[0044] The device includes a gate bus bar 34 to which the gate wiring 24 is electrically connected, and a drain bus bar 36 to which the drain wirings 26a and 26b are electrically connected. This allows a gate potential to be supplied from the gate bus bar 34 to the gate electrodes 14a to 14d, and a drain potential to be supplied from the drain bus bar 36 to the drain electrodes 16a to 16d.

[0045] [Modification 1 of Example 1] Fig. 8 is a plan view of a semiconductor device according to Modification 1 of Example 1. As shown in Fig. 8, in a semiconductor device 102 according to Modification 1 of Example 1, the gate electrodes 14 of the transistors 35 in the same transistor group 38 are connected and integrated. The gate electrodes 14a and 14c of the transistor group 38a are connected and integrated. The gate electrodes 14b and 14d of the transistor group 38b are connected and integrated. The other configurations are the same as those of Example 1, and description thereof will be omitted.

[0046] [Example 2] Fig. 9 is a plan view of a semiconductor device in Example 2. As shown in Fig. 9, in a semiconductor device 104 of Example 2, the corners of the + ends in the Y direction of a source electrode 12a and a source wiring 22c are chamfered. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0047] 10 is an enlarged plan view of the semiconductor device in Example 2, enlarging the vicinity of the source electrode 12a. The source electrode 12a and source wiring 22c (solid lines) in Example 2 are illustrated overlapping with the source electrode 12a and source wiring 22c (dotted lines) in Example 1.

[0048] 10, in both Examples 1 and 2, the via hole 20a is provided in the source electrode 12a when viewed from the Z direction. This increases the contact area between the metal layer 28a and the source electrode 12a, thereby reducing the source inductance and source resistance. The positive end Y3 in the Y direction of the source electrode 12a and the source wiring 22c is closer to the drain bus bar 36 than the positive end Y2 in the Y direction of the active region 11a.

[0049] In the first embodiment, in a portion 54 closer to the drain bus bar 36 than the active region 11a, an end side 55 in the X direction in the planar shape of the source electrode 12a and the source wiring 22c is substantially parallel to an end side in the X direction of the drain wirings 26a and 26b. Therefore, a parasitic capacitance C0 occurs between the source electrode 12a and the source wiring 22c and the drain wiring 26a. The parasitic capacitance C0 becomes a drain-source parasitic capacitance, and deteriorates the high frequency characteristics of the semiconductor device.

[0050] In the second embodiment, the distance between the source electrode 12a and the drain wiring 26a at an end Y3 (third end) of the source electrode 12a far from the transistor 35c as viewed in the X direction is defined as D1. The distance between the source electrode 12a and the drain wiring 26a at an end Y2 of the active region 11a far from the transistor 35c as viewed in the X direction is defined as D2. In this case, the distance D1 is greater than the distance D2. This makes it possible to make the parasitic capacitance C1 generated between the source electrode 12a and the source wiring 22c and the drain wiring 26a smaller than the parasitic capacitance C0 in the first embodiment. This makes it possible to suppress the drain-source parasitic capacitance, thereby suppressing the deterioration of the high-frequency characteristics of the semiconductor device.

[0051] Furthermore, the end Y3 of the source electrode 12a is provided on the inactive region 13. This makes it possible to reduce the parasitic capacitance C1. As a result, the drain-source parasitic capacitance can be suppressed, and degradation of the high frequency characteristics of the semiconductor device can be suppressed.

[0052] A width W7 between the position in the X direction of the end side 55 at the end Y2 and the position in the X direction of the end side 55 at the end Y3 (i.e., the difference between the distances D1 and D2) can be 0.2 times or more, 0.5 times or more, or 1.0 times or more of the width W2 between the ends Y2 and Y3 in the Y direction. This can further suppress the parasitic capacitance C1.

[0053] If the distance between the source electrode 12a and the drain wiring 26a at the end Y2 is reduced, the margin between the via hole 20a and the source electrode 12a will become smaller. Therefore, the distance between the source electrode 12a and the drain wiring 26a is increased from the end Y2 to the end Y3. That is, the end side 55 moves toward the inside of the source electrode 12a and the source wiring 22c from the end Y2 to the end Y3. This makes it possible to further reduce the parasitic capacitance C1 generated between the source electrode 12a and the source wiring 22c and the drain wiring 26a. This makes it possible to suppress the drain-source parasitic capacitance, thereby suppressing the deterioration of the high-frequency characteristics of the semiconductor device.

[0054] The planar shape of the edge 55 may be straight or curved. The edge 55 may be straight or curved so as to bulge outward from the source electrode 12a and the source wiring 22c. This ensures a margin between the via hole 20a and the source electrode 12a.

[0055] [Modification 1 of Example 2] 11 is a plan view of a semiconductor device according to Modification 1 of Example 2. As shown in FIG. 11, in a semiconductor device 106 according to Modification 1 of Example 2, similar to Modification 1 of Example 1, the gate electrodes 14 of the transistors 35 of the same transistor group 38 are connected and integrated. The gate electrodes 14a and 14c of the transistor group 38a are connected and integrated. The gate electrodes 14b and 14d of the transistor group 38b are connected and integrated. The other configurations are the same as those of Example 2, and description thereof will be omitted.

[0056] In the first modification of the first embodiment and the first modification of the second embodiment, the gate electrodes 14a and 14c are connected between the transistors 35a and 35c, and the gate electrodes 14b and 14d are connected between the transistors 35b and 35d. As a result, the gate potential is supplied to the gate electrodes 14c and 14d from the + and - ends in the Y direction. This makes it possible to further suppress the gate resistance of the transistors 35c and 35d. In addition, the gate widths Wg2 to Wg4 of the transistors 35c and 35d can be increased.

[0057] However, in the transistors 35c and 35d, the high frequency signal is input from the negative ends in the Y direction of the gate electrodes 14c and 14d. If the high frequency signal is input to the gate electrodes 14c and 14d from both the positive and negative ends in the Y direction of the gate electrodes 14c and 14d, the high frequency characteristics of the transistors 35c and 35d will be degraded due to a phase difference or the like.

[0058] Therefore, in the first and second embodiments, the gate electrodes 14a and 14c are separated between the transistors 35a and 35c, and the gate electrodes 14b and 14d are separated between the transistors 35b and 35d, thereby making it possible to suppress deterioration of the high frequency characteristics of the transistors 35c and 35d.

[0059] In the first and second embodiments and their modified examples, four transistor groups 38a and 38b are arranged in the X direction, but three or more transistor groups 38a and 38b may be arranged in the X direction. One or more transistors 35c and 35d may be arranged in the Y direction. The source wirings sandwiching the drain wiring 26 in the X direction may be connected between the drain wiring and the gate bus bar 34.

[0060] In the first and second embodiments and their modified examples, the plurality of drain electrodes 16 (e.g., drain electrodes 16a and 16c) electrically connected to the same drain wiring 26 (e.g., drain wiring 26a) are separated from each other in the inactive region 13. The plurality of drain electrodes 16 (e.g., drain electrodes 16a and 16c) electrically connected to the drain wiring 26 (e.g., drain wiring 26a) may be connected to each other in the inactive region 13. In the transistor 35 (e.g., transistor 35a), the source electrode 12 and the source wiring 22 (e.g., source electrode 12a and source wiring 22c) can be collectively referred to as the source electrode, and the drain electrode 16 and the drain wiring 26 (e.g., drain electrode 16a and drain wiring 26a) can be collectively referred to as the drain electrode.

[0061] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0062] 10, 10a Board 10b Semiconductor layer 11a, 11c, 11d active area 12, 12a, 12c, 12d Source electrodes 13 Inactive area 14, 14a, 14b, 14c, 14d Gate electrode 16, 16a, 16b, 16c, 16d Drain electrodes 24b wiring layer 20a Beer Hall 22, 22a, 22b, 22c Source wiring 24, 25a, 25b Gate wiring 24a Gate metal layer 26a, 26b Drain wiring 28, 28a metal layer 30 Insulating layer 34 Gate bus bar 35, 35a, 35b, 35c, 35d Transistors 36 Drain busbar 38, 38a, 38b Transistor group 50 Main Surface 52 Back side 54 parts 55 Edge 100, 102, 104, 106, 110 Semiconductor device

Claims

1. A substrate having a main surface and a back surface opposite to the main surface; a first transistor including a first source electrode, a first drain electrode, and a first gate electrode sandwiched between the first source electrode and the first drain electrode in a first direction, the first transistor being provided on the main surface in an active region provided in the substrate; a second transistor provided on the main surface, the second transistor including: a second source electrode provided within the first source electrode when viewed from a second direction intersecting the first direction and electrically connected to the first source electrode; a second drain electrode electrically connected to the first drain electrode; and a second gate electrode sandwiched between the second source electrode and the second drain electrode in the first direction; a first gate wiring provided on the main surface, sandwiching the second source electrode between the first gate electrode and the second gate electrode, provided within the first source electrode when viewed from the second direction, and electrically connected to the first gate electrode; a backside metal layer provided on the backside and electrically connected to the first source electrode through a via hole penetrating the substrate; Equipped with A semiconductor device in which, when viewed from the first direction, a first end of the via hole farther from the second transistor is farther from the second transistor than a second end of the active region in a region in which the first gate electrode is provided, farther from the second transistor.

2. 2. The semiconductor device according to claim 1, wherein the via hole is provided within the first source electrode when viewed in a thickness direction of the substrate.

3. a drain bus bar provided on the main surface, the drain bus bar sandwiching the first transistor between the second transistor and the drain bus bar; a drain wiring that connects the first drain electrode and the second drain electrode to the drain bus bar; Equipped with 3. The semiconductor device according to claim 2, wherein a distance between the first source electrode and the drain wiring at a third end of the first source electrode farther from the second transistor when viewed from the first direction is greater than a distance between the first source electrode and the drain wiring at the second end.

4. The semiconductor device according to claim 3 , wherein the third end of the first source electrode is provided on an inactive region provided on the substrate.

5. 5. The semiconductor device according to claim 3, wherein the distance between the first source electrode and the drain wiring increases from the second end to the third end.

6. 5. The semiconductor device according to claim 1, wherein the gate width of the first transistor is 0.9 to 1.1 times the gate width of the second transistor.

7. 5 . The semiconductor device according to claim 1 , wherein the first gate electrode and the second gate electrode are separated from each other between the first transistor and the second transistor.

8. 5 . The semiconductor device according to claim 1 , wherein the first gate electrode and the second gate electrode are connected between the first transistor and the second transistor.

9. a third transistor provided on the main surface, the third transistor including: a third drain electrode sandwiching the first source electrode between the first source electrode and the first gate electrode; and a third gate electrode sandwiched between the first source electrode and the third drain electrode in the first direction and electrically connected to the first gate wiring; 5. The semiconductor device according to claim 1, further comprising: a fourth source electrode disposed within the first source electrode when viewed from the second direction and electrically connected to the first source electrode, with the first gate wiring sandwiched between the second source electrode and the fourth source electrode; a fourth drain electrode sandwiching the fourth source electrode between the first gate wiring and the fourth gate electrode; and a fourth gate electrode sandwiched between the fourth source electrode and the fourth drain electrode in the first direction, and further comprising a fourth transistor disposed on the main surface.

10. a source wiring provided on the main surface and electrically connecting the first source electrode and the second source electrode; a second gate wiring provided on the main surface and electrically connecting the first gate wiring and the first gate electrode; The semiconductor device according to claim 1 , further comprising:

11. a gate bus bar provided on the main surface and connected to the second gate electrode and the first gate wiring; a drain bus bar provided on the main surface, sandwiching the first transistor and the second transistor between the gate bus bar and the drain bus bar in the second direction, and electrically connected to the first drain electrode and the second drain electrode; The semiconductor device according to claim 1 , further comprising:

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