Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that has high short circuit resistance and a manufacturing method thereof.SOLUTION: A semiconductor device comprises: a first electrode; a second electrode; a first semiconductor layer that contains first impurities being donors and protons, and in which a first position taking a maximum value of the concentration of the first impurities is positioned; a second semiconductor layer that is arranged in a first direction side from the first electrode to the second electrode with respect to the first semiconductor layer, and contains the first impurities and protons, and in which the concentration of the protons is higher than the concentration of the first impurities; and a third semiconductor layer that is arranged on the first direction side of the second semiconductor layer, and contains the first impurities, and in which the concentration of the first impurities is higher than the concentration of the protons. In a portion of the at least second semiconductor layer side in the first semiconductor layer, the concentration of the first impurities is higher than the concentration of the protons. A second position where the concentration of the protons in the first direction takes a maximum value is located on the opposite side in the first direction compared to the first position.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices for power control are required to have a certain short-circuit resistance so that the semiconductor device is not damaged during the period from when a load is short-circuited to when a protection circuit is activated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6662393 [Patent Document 2] Patent No. 5817686 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device with high short circuit resistance and a manufacturing method thereof. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a second electrode, a first semiconductor layer including a first impurity and protons serving as a donor, having an n-type conductivity, and having a first position inside where the concentration of the first impurity is maximum; a second semiconductor layer disposed on a first direction side from the first electrode toward the second electrode with respect to the first semiconductor layer, including the first impurity and protons, the concentration of the protons being higher than the concentration of the first impurity, and having an n-type conductivity; and a third semiconductor layer disposed on the first direction side of the second semiconductor layer, including the first impurity, the concentration of the first impurity being higher than the concentration of the protons, and having an n-type conductivity. In at least a portion of the first semiconductor layer on the second semiconductor layer side, the concentration of the first impurity is higher than the concentration of the protons. A second position where the concentration of the protons in the first direction is maximum is located on the opposite side of the first direction from the first position.

[0006] A manufacturing method of a semiconductor device according to an embodiment includes the steps of injecting a first impurity that acts as a donor into a semiconductor member having an n-type conductivity from a first surface side of the semiconductor member in a first direction to form a first position inside the semiconductor member where the concentration of the first impurity is at a maximum value, arranging an absorber on the first surface side of the semiconductor member, injecting protons into the semiconductor member via the absorber in the first direction to position a second position where the concentration of the protons is at a maximum value on the opposite side of the first direction from the first position, and removing the absorber. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1(a) is a top view showing the semiconductor device according to the first embodiment, and FIG. 1(b) is a cross-sectional view thereof. [Diagram 2] FIG. 2 is a graph showing the concentration profile of each impurity along the Z direction in the first embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. [Diagram 3] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5A to 5C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7A to 7C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8A to 8C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9A to 9C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a graph showing concentration profiles of each impurity along the Z direction in the first modified example of the first embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. [Figure 11] FIG. 11 is a graph showing concentration profiles of each impurity along the Z direction in the second modified example of the first embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. [Figure 12] FIG. 12 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Figure 13] FIG. 13 is a graph showing the concentration profile of each impurity along the Z direction in the second embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. [Figure 14] FIG. 14 is a graph showing the concentration profile of each impurity along the Z direction in the modified example of the second embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. [Figure 15] FIG. 15 is a graph showing the effect of the proton profile on the short circuit withstand capability, with the horizontal axis representing the position where the proton concentration in the Z direction is maximum, and the vertical axis representing the results of the short circuit withstand capability test. [Figure 16]FIG. 16 is a graph showing the concentration profile of each impurity along the Z direction in the test example, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] <First embodiment> (Semiconductor Device) FIG. 1(a) is a top view showing the semiconductor device according to this embodiment, and FIG. 1(b) is a cross-sectional view thereof. In FIG. 1(a), an emitter electrode and an insulating member, which will be described later, are omitted, and the top surface of the semiconductor portion is shown.

[0009] The semiconductor device 1 according to this embodiment is, for example, a power semiconductor for power control, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0010] 1(a) and 1(b), the semiconductor device 1 includes a semiconductor portion 10. The semiconductor portion 10 is made of a semiconductor material, for example, single crystal silicon (Si). In the semiconductor portion 10, impurities that act as donors or acceptors are introduced into each portion, and the conductivity type of each portion is made to be n-type or p-type.

[0011] The semiconductor device 1 is provided with a collector electrode 31, an emitter electrode 32, a gate electrode 33, and a dummy gate electrode 34. One collector electrode 31 and one emitter electrode 32 are provided. A plurality of gate electrodes 33 and a plurality of dummy gate electrodes 34 are provided. The collector electrode 31 is in contact with the lower surface 10a of the semiconductor portion 10, and the emitter electrode 32 is in contact with the upper surface 10b of the semiconductor portion 10. The gate electrode 33 and the dummy gate electrode 34 are disposed in the semiconductor portion 10 and extend in one direction.

[0012] For convenience of explanation, the present specification adopts an XYZ Cartesian coordinate system hereinafter. The direction from the collector electrode 31 toward the emitter electrode 32 is defined as the "Z direction" (first direction), the direction in which the gate electrode 33 and the dummy gate electrode 34 extend is defined as the "Y direction", and the direction perpendicular to the Z direction and the Y direction is defined as the "X direction". The Z direction is also called "up" and the opposite direction (-Z direction) is also called "down", but these expressions are also for convenience and are unrelated to the direction of gravity.

[0013] In the semiconductor portion 10, p + A thin n-type collector layer 11 (fourth semiconductor layer), a thin n-type buffer layer 12 (first semiconductor layer), a thick n-type buffer layer 13 (second semiconductor layer), - a first semiconductor layer, an n-type barrier layer, a p-type base layer, a + Type diffusion layer 17, n + A p-type emitter layer 18 (sixth semiconductor layer) and + A mold contact layer 19 is provided.

[0014] p + The collector layer 11 constitutes the lower surface 10a of the semiconductor portion 10. + The collector layer 11 is disposed on the collector electrode 31 and is in contact with the collector electrode 31. + A collector layer 11, a thin n-type buffer layer 12, a thick n-type buffer layer 13, - The n-type base layer 14, the n-type barrier layer 15, and the p-type base layer 16 are stacked in this order along the Z direction and are connected to each other. In this specification, "connection" refers to electrical connection.

[0015] n + type emitter layer 18 and p + The p-type contact layers 19 are disposed on the p-type base layers 16 and extend in the X direction. + type emitter layer 18 and p + The contact layers 19 are arranged alternately along the Y direction. + type emitter layer 18 and p + The mold contact layer 19 constitutes the upper surface 10 b of the semiconductor portion 10 .

[0016] p + The p-type diffusion layer 17 is connected to the p-type base layer 16 and the n + Between the p-type emitter layer 18 and the p-type base layer 16 and + The gate electrode 34 is disposed in the vicinity of the dummy gate electrode 34 between the gate electrode 34 and the mold contact layer 19, and extends in the Y direction.

[0017] n + On the p-type emitter layer 18 and + An emitter electrode 32 is disposed on the contact layer 19. + type emitter layer 18 and p + The mold contact layer 19 is connected to an emitter electrode 32 .

[0018] The gate electrode 33 and the dummy gate electrode 34 extend downward, that is, from the upper surface 10b side of the semiconductor portion 10, that is, from the emitter electrode 32 side, toward the collector electrode 31 side. + The upper surface of the p-type emitter layer 18 and + The n-type contact layer 19 is electrically connected to the p-type base layer 16 and the n-type barrier layer 15 through the upper surface of the p-type contact layer 19. - The dummy gate electrode 34 reaches into the p-type base layer 14. + The gate electrodes 33 and the dummy gate electrodes 34 also pass through the sides of the type diffusion layer 17. The gate electrodes 33 and the dummy gate electrodes 34 may be arranged alternately one by one along the X direction, or one dummy gate electrode 34 may be arranged for a plurality of gate electrodes 33, or one gate electrode 33 may be arranged for a plurality of dummy gate electrodes 34. Also, the dummy gate electrode 34 may not be provided.

[0019] The semiconductor device 1 is provided with a gate insulating film 21, a dummy gate insulating film 22, a gate insulating member 23, and a dummy gate insulating member 24. The gate insulating film 21 is disposed between the gate electrode 33 and the semiconductor portion 10, and insulates the gate electrode 33 from the semiconductor portion 10. The dummy gate insulating film 22 is disposed between the dummy gate electrode 34 and the semiconductor portion 10, and insulates the dummy gate electrode 34 from the semiconductor portion 10.

[0020] The gate insulating member 23 and the dummy gate insulating member 24 are disposed on the semiconductor portion 10. The gate insulating member 23 is disposed between the gate electrode 33 and the emitter electrode 32, and insulates the gate electrode 33 from the emitter electrode 32. The dummy gate insulating member 24 is disposed so as to cover the upper end of the dummy gate insulating film 22, and protects the upper end of the dummy gate insulating film 22. A part of the emitter electrode 22 is disposed between the dummy gate insulating members 24, and is connected to the dummy gate electrode 34. Therefore, an emitter potential is applied to the dummy gate electrode 34.

[0021] (Impurity concentration profile on the collector side of the semiconductor part) Next, the collector side portion of the semiconductor portion 10, i.e., p + A collector layer 11, a thin n-type buffer layer 12, a thick n-type buffer layer 13, and an n - The impurity concentration profile along the Z direction in the mold base layer 14 will be described.

[0022] The semiconductor portion 10 contains phosphorus (P) and protons (H + ) and contains boron (B) as an impurity that acts as an acceptor. A proton is a positive ion of hydrogen, that is, a proton. The impurity that acts as a donor other than a proton is not limited to phosphorus, and may be other impurities such as arsenic (As) or antimony (Sb). The impurity that acts as an acceptor is also not limited to boron, and may be other impurities such as gallium (Ga) or indium (In).

[0023] FIG. 2 is a diagram showing the concentration profile of each impurity along the Z direction in this embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. 2 is a conceptual diagram qualitatively showing the characteristics of each concentration profile. Actual measurement results will be explained in the examples described later. The vertical axis of FIG. 2 is logarithmic.

[0024] First, an overview of each layer will be described. 1(b) and 2, the thickness of the thick n-type buffer layer 13, i.e., the length in the Z direction, is greater than the thickness of the thin n-type buffer layer 12. The average carrier concentration of the thick n-type buffer layer 13 is lower than the average carrier concentration of the thin n-type buffer layer 12. - The thickness of the n-type base layer 14 is thicker than the thickness of the n-type buffer layer 13. - The average carrier concentration of the n-type base layer 14 is lower than the average carrier concentration of the thick n-type buffer layer 13. The thickness of the n-type barrier layer 15 is - The thickness of the n-type barrier layer 15 is thinner than that of the n-type base layer 14. The average carrier concentration of the n-type barrier layer 15 is - The carrier concentration is higher than the average value of the carrier concentration of the mold base layer 14 .

[0025] Next, the concentration profile of each impurity will be described. As shown in FIG. 2, the boron concentration profile starts from the lower surface 10a of the semiconductor portion 10, increases toward the +Z direction, and + 2, the boron concentration is maximum at peak P1. Therefore, the position 41 where the boron concentration is maximum in the Z direction coincides with the position of peak P1. + In the mold collector layer 11, the concentration of boron is higher than the sum of the concentration of phosphorus and the concentration of protons.

[0026] The phosphorus concentration profile starts from the lower surface 10a of the semiconductor portion 10, increases toward the +Z direction, and has a peak P2 in the thin n-type buffer layer 12. The phosphorus concentration reaches a maximum value at the peak P2, and +In the n-type collector layer 11, the thin n-type buffer layer 12, and the thick n-type buffer layer 13, the impurity concentration monotonically decreases from the peak P2 in both the +Z direction and the -Z direction. Note that the "monotonically decreasing" means that the actual concentration of the impurity decreases along one direction, and does not take into account minute increases and decreases due to measurement noise.

[0027] n - The phosphorus concentration is approximately constant in the n-type base layer 14. Therefore, in the range shown in FIG. 2, the position 42 where the phosphorus concentration is maximum in the Z direction coincides with the position of the peak P2. - In the mold base layer 14, the sum of the concentration of phosphorus and the concentration of protons is higher than the concentration of boron.

[0028] The proton concentration profile starts from the lower surface 10a of the semiconductor portion 10, increases toward the +Z direction, and has a peak P3 in the thin n-type buffer layer 12. The proton concentration reaches a maximum value at peak P3, and decreases monotonically from peak P3 toward both the +Z direction and the -Z direction. Therefore, position 43 where the proton concentration reaches a maximum value in the Z direction coincides with the position of peak P3. In the Z direction, position 43 where the proton concentration reaches a maximum value is located on the -Z direction side, i.e., on the lower surface 10a side of the semiconductor portion 10, of position 42 where the phosphorus concentration reaches a maximum value.

[0029] Next, the relationship between the impurity concentrations of each layer will be described. p + In the collector layer 11, the concentration of boron is higher than the sum of the concentration of phosphorus and the concentration of protons. + In the type collector layer 11, a boron peak P1 is located.

[0030] In the thin n-type buffer layer 12, the sum of the phosphorus concentration and the proton concentration is higher than the boron concentration. In at least the portion of the thin n-type buffer layer 12 on the thick n-type buffer layer 13 side, the phosphorus concentration is higher than the proton concentration. In the thin n-type buffer layer 12, a phosphorus peak P2 and a proton peak P3 are located. The proton peak P3 is located on the -Z direction side of the phosphorus peak P2. + The interface between the n-type collector layer 11 and the thin n-type buffer layer 12 is a position where the magnitude relationship between the concentration of the impurity acting as an acceptor and the concentration of the impurity acting as a donor is reversed. + In n-type collector layer 11, the concentration of impurities that will act as acceptors is higher than the concentration of impurities that will act as donors, and in thin n-type buffer layer 12, the concentration of impurities that will act as donors is higher than the concentration of impurities that will act as acceptors.

[0031] In the thick n-type buffer layer 13, the sum of the phosphorus concentration and the proton concentration is higher than the boron concentration, and the proton concentration is higher than the phosphorus concentration. The interface between the thin n-type buffer layer 12 and the thick n-type buffer layer 13 is a position where the magnitude relationship between the phosphorus concentration and the proton concentration is reversed. At least in the portion of the thin n-type buffer layer 12 on the thick n-type buffer layer 13 side, the phosphorus concentration is higher than the proton concentration, and in the thick n-type buffer layer 13, the proton concentration is higher than the phosphorus concentration. As described above, the overall carrier concentration of the thick n-type buffer layer 13 is lower than the carrier concentration of the thin n-type buffer layer 12. There is no peak of the impurity concentration in the thick n-type buffer layer 13, and the concentration of each impurity monotonically decreases toward the +Z direction.

[0032] n - In the mold base layer 14, the sum of the concentration of phosphorus and the concentration of protons is higher than the concentration of boron, and the concentration of phosphorus is higher than the concentration of protons. - The overall carrier concentration of the n-type base layer 14 is lower than the carrier concentration of the thick n-type buffer layer 13. -There is no peak of the impurity concentration in the type base layer 14, and the carrier concentration is approximately constant in the Z direction. Note that the "carrier concentration" refers to the effective impurity concentration that contributes to the conductivity of a semiconductor material, and when a certain portion contains both impurities that act as donors and impurities that act as acceptors, it refers to the difference concentration excluding the offset amounts.

[0033] (Manufacturing method) Next, a method for manufacturing the semiconductor device according to this embodiment will be described. 3 to 9 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment.

[0034] First, a semiconductor wafer 10w is prepared as shown in Fig. 3. The semiconductor wafer 10w is made of, for example, single crystal silicon, and contains donor impurities, for example, phosphorus, uniformly throughout the wafer. The conductivity type of the semiconductor wafer 10w is n-type. - It is a type.

[0035] 4, impurities are ion-implanted into the upper surface 10b of the semiconductor wafer 10w to form an n-type barrier layer 15. The portion of the semiconductor wafer 10w to which the impurities are not ion-implanted is called an n-type barrier layer 15. - This becomes the mold base layer 14 .

[0036] Next, a gate trench 36 and a dummy gate trench 37 are formed from the upper surface 10b side of the semiconductor wafer 10w. Next, a thermal oxidation process is performed to form a gate insulating film 21 on the inner surface of the gate trench 36, and a dummy gate insulating film 22 on the inner surface of the dummy gate trench 37. Next, a conductive material such as polysilicon is deposited on the entire surface to form a gate electrode 33 in the gate trench 36, and a dummy gate electrode 34 in the dummy gate trench 37. Next, the conductive material deposited on the upper surface 10b of the semiconductor wafer 10w is removed.

[0037] Next, as shown in FIG. 5, impurities are ion-implanted sequentially on the upper surface 10b side of the semiconductor wafer 10w to form p-type base layers 16, + Type diffusion layer 17, p+ Type contact layer 19 (see FIG. 1(a)), + A type emitter layer 18 is then formed. Next, silicon oxide is selectively formed on the upper surface 10b of the semiconductor wafer 10w to form a gate insulating member 23 and a dummy gate insulating member 24. In this manner, the upper structure of the IGBT is formed on the upper portion of the semiconductor wafer 10w.

[0038] Next, as shown in FIG. 6, the semiconductor wafer 10w is thinned by grinding from the bottom surface side. Next, as shown in Fig. 7, phosphorus is ion-implanted from the lower surface 10a side of the semiconductor wafer 10w. At this time, the concentration profile of phosphorus has a peak P2 (see Fig. 2) in the semiconductor wafer 10w. As a result, a thin n-type buffer layer 12 is formed.

[0039] Next, as shown in FIG. 8, boron is ion-implanted from the lower surface 10a side of the semiconductor wafer 10w. At this time, the boron concentration profile has a peak P1 (see FIG. 2) at a position on the -Z direction side of the peak P2 in the semiconductor wafer 10w. + A mold collector layer 11 is formed.

[0040] Next, as shown in FIG. 9, an absorber 90 is placed on the lower surface 10a of the semiconductor wafer 10w. The absorber 90 is formed, for example, by laminating aluminum foil. Then, protons, i.e., hydrogen cations, are injected into the semiconductor wafer 10w in the Z direction through the absorber 90, for example, by a cyclotron. Since protons are smaller than phosphorus, they reach deep positions in the semiconductor wafer 10w. On the other hand, since the protons are injected through the absorber 90, some of the protons remain in the absorber 90. As a result, the peak P3 of the protons (see FIG. 2) is located on the -Z direction side of the peak P2 of phosphorus. This forms the thick n-type buffer layer 13. For silicon constituting the thick n-type buffer layer 13, the protons are defects and impurities that become donors.

[0041] In one example, the proton implantation conditions are set so that the peak P3 of the proton concentration profile is located on the lower surface 10a of the semiconductor wafer 10w. However, the actual position of the peak P3 may be shifted in the +Z direction or the -Z direction from the lower surface 10a. The above-mentioned FIG. 2 shows an example in which the peak P3 is shifted in the +Z direction from the lower surface 10a, that is, toward the inside of the semiconductor wafer 10w. As a result, the proton peak P3 is located in the thin n-type buffer layer 12 and on the -Z direction side from the phosphorus peak P2. Then, the absorber 90 is removed.

[0042] Next, a heat treatment is performed to activate each of the implanted impurities. The implanted protons are activated by the heat treatment, and become an n-type defect layer that is a lattice defect but also functions as a donor. The n-type defect layer functions as an n-type conductive layer, and becomes a thick n-type buffer layer 13.

[0043] 1(a) and 1(b), a collector electrode 31 and an emitter electrode 32 are formed. Next, the semiconductor wafer 10w is diced into individual pieces. In this way, the semiconductor device 1 is manufactured.

[0044] (Action and effect) Next, the effects of this embodiment will be described. In the semiconductor device 1 according to this embodiment, in addition to the thin n-type buffer layer 12, a thick n-type buffer layer 13 is provided. This makes it possible to suppress the expansion of the depletion layer when the semiconductor device 1 is turned off. Therefore, when the depletion layer reaches the thin n-type buffer layer 12, carriers are rapidly discharged, and it is possible to suppress LC resonance between the capacitance (C) of the depletion layer inside the device and the parasitic inductance (L) outside the device. As a result, it is possible to suppress voltage oscillations accompanying switching.

[0045] In this embodiment, the position 43 where the proton concentration is maximum is located on the −Z direction side of the position 42 where the phosphorus concentration is maximum, that is, on the collector electrode 31 side. This can improve the short circuit resistance of the semiconductor device 1.

[0046] If the load connected to the semiconductor device 1 is short-circuited for some reason while the semiconductor device 1 is in the on state, a large current flows through the semiconductor device 1. Normally, in such a case, an external protection circuit is activated to cut off the current flowing through the semiconductor device 1, but it takes time for the protection circuit to activate after the load is short-circuited. It is desirable that the semiconductor device 1 is not destroyed during this time. The short-circuit withstand capability refers to the degree to which the semiconductor device 1 is not destroyed under such circumstances.

[0047] In this embodiment, position 43 where the proton concentration is at its maximum is positioned on the -Z direction side of position 42 where the phosphorus concentration is at its maximum, so that the transport efficiency near the lower surface 10a of the semiconductor portion 10 is increased and the injection of holes is increased. As a result, the electric field near the lower surface 10a is reduced and the short circuit resistance is increased.

[0048] If the position 43 where the proton concentration is at its maximum is the same as the position 42 where the phosphorus concentration is at its maximum, or is located on the +Z side of the position 42, that is, on the emitter electrode 32 side, the transport efficiency in the vicinity of the lower surface 10a decreases, the hole injection decreases, and the electric field in the vicinity of the lower surface 10a increases. As a result, the short circuit resistance decreases.

[0049] <First Modification of the First Embodiment> FIG. 10 is a graph showing the concentration profile of each impurity along the Z direction in this modification, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity.

[0050] As shown in FIG. 10, in this modification, the proton peak P3 is p + The proton concentration is maximum at position 43 in the Z direction. + The second electrode 14 is located in the mold collector layer 11. This also provides the same effects as the previous embodiment. Other than the above, the configuration, operation, and effects of this modified example are the same as those of the first embodiment.

[0051] <Second Modification of the First Embodiment> FIG. 11 is a graph showing the concentration profile of each impurity along the Z direction in this modification, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity.

[0052] 11, in this modification, the proton concentration profile has no peak, and the proton concentration has a maximum value at the lower surface 10a of the semiconductor portion 10 and monotonically decreases as it moves in the Z direction. Therefore, in the semiconductor portion 10, the position 43 where the proton concentration has a maximum value coincides with the lower surface 10a of the semiconductor portion 10.

[0053] 9, protons are injected into the semiconductor portion 10 via the absorber 90 so that the peak P3 of the proton concentration is located on the lower surface 10a of the semiconductor portion 10 or in the absorber 90, and then the absorber 90 is removed. This also makes it possible to obtain the same effect as in the above-mentioned embodiment. The configuration, operation, and effects of this modified example other than those described above are the same as those of the first embodiment.

[0054] <Second embodiment> FIG. 12 is a cross-sectional view showing the semiconductor device according to this embodiment. FIG. 13 is a graph showing the concentration profile of each impurity along the Z direction in this embodiment, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity.

[0055] 12, the semiconductor device 2 according to this embodiment is a pn diode. The semiconductor device 2 includes a semiconductor portion 60, an anode electrode 61, and a cathode electrode 62. The semiconductor portion 60 includes a p-type portion 65 and an n-type portion 66, with the anode electrode 61 in contact with the p-type portion 65 and the cathode electrode 62 in contact with the n-type portion 66.

[0056] The n-type portion 66 is +the thin n-type buffer layer 12, the thick n-type buffer layer 13, and the n - It includes a mold base layer 14. - The thin n-type base layer 14 contacts the p-type portion 65, and the thin n-type buffer layer 12 contacts the cathode electrode 62. + The mold collector layer 11 is not provided.

[0057] As shown in FIG. 13, in this embodiment, there is no peak in the proton concentration profile, and the position 43 where the proton concentration is maximum in the Z direction coincides with the lower surface 60a of the semiconductor portion 60.

[0058] 9, such a profile is realized by disposing an absorber 90 on the lower surface 60a of the semiconductor portion 60 and positioning a proton concentration peak P3 in the absorber 90 or on the lower surface 60a when protons are injected through the absorber 90 to form the thick n-type buffer layer 13. After the protons are injected, the absorber 90 is removed, so that the proton concentration peak P3 does not remain in the semiconductor portion 60.

[0059] In this embodiment as well, the short circuit resistance can be improved since position 43 is located closer to the cathode electrode 62 than position 42. Other configurations, operations, and effects of this embodiment are similar to those of the first embodiment described above.

[0060] <Modification of the second embodiment> FIG. 14 is a graph showing the concentration profile of each impurity along the Z direction in this modification, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity.

[0061] 14, in this modification, a position 43 of a peak P3 of the proton concentration is located closer to the cathode electrode 62 than a position 42 of a peak P2 of the phosphorus concentration in the thin n-type buffer layer 12. This improves the short circuit resistance. Other configurations, operations, and effects of this modification are similar to those of the second embodiment described above.

[0062] <Test Example> FIG. 15 is a graph showing the effect of the proton profile on the short circuit withstand capability, with the horizontal axis representing the position where the proton concentration in the Z direction is maximum, and the vertical axis representing the results of the short circuit withstand capability test.

[0063] 15 is based on the position of the lower surface 10a of the semiconductor portion 10. That is, "0" on the horizontal axis corresponds to the position of the lower surface 10a, negative values ​​correspond to the outside of the semiconductor portion 10, specifically, inside the absorber 90, and positive values ​​correspond to the inside of the semiconductor portion 10. Position 42 where the phosphorus concentration is maximum is located near +4 μm.

[0064] In this test example, a plurality of semiconductor devices 1 according to the first embodiment were manufactured. In the plurality of semiconductor devices 1 manufactured, the position 43 at which the proton concentration was maximum was made different from one another. Then, the short circuit resistance of each semiconductor device 1 was evaluated. A semiconductor device that did not break down under the specified conditions was determined to be "non-destructive," and a semiconductor device that broke down was determined to be "destructive."

[0065] 15, a semiconductor device in which position 43 where the proton concentration is at its maximum is located on the -Z side of position 42 where the phosphorus concentration is at its maximum is determined to be "non-destroyed." In contrast, a semiconductor device in which position 43 is located on the +Z side of position 42 is determined to be "destroyed." In the destroyed semiconductor device, the semiconductor portion 10 is melted.

[0066] Next, an example of measuring the impurity concentration profile in an actual product will be shown. FIG. 16 is a graph showing the concentration profile of each impurity along the Z direction in this test example, with the horizontal axis representing the position in the Z direction and the vertical axis representing the concentration of each impurity. The concentration of each impurity was measured by SIMS (Secondary Ionization Mass Spectrometer). The coordinates of the horizontal axis in Fig. 16 are based on the position of the lower surface 10a of the semiconductor portion 10. In Fig. 16, a region R is an area where the influence of a surface adsorbate appears, and therefore is excluded from the following discussion.

[0067] 16, in this measurement example as well, the position 43 of the peak P3 of the proton concentration was located on the -Z direction side of the position 42 of the peak P2 of the phosphorus concentration. When this device was evaluated in the same manner as in the test example shown in FIG. 15, the short circuit resistance was good.

[0068] According to the embodiment described above, a semiconductor device with high short circuit resistance and a manufacturing method thereof can be realized.

[0069] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments and their modifications can be implemented in combination with each other.

[0070] The present invention includes the following aspects.

[0071] (Appendix 1) A first electrode; A second electrode; a first semiconductor layer including a first impurity serving as a donor and protons, having an n-type conductivity, and having a first position located therein where the concentration of the first impurity is at a maximum value; a second semiconductor layer that is disposed on a first direction side from the first electrode toward the second electrode with respect to the first semiconductor layer, contains the first impurity and protons, a concentration of the protons is higher than a concentration of the first impurity, and has an n-type conductivity; a third semiconductor layer that is disposed on the first direction side of the second semiconductor layer, contains the first impurity, a concentration of the first impurity is higher than a concentration of the protons, and has an n-type conductivity; Equipped with a concentration of the first impurity is higher than a concentration of the protons at least in a portion of the first semiconductor layer on the second semiconductor layer side; The second position where the concentration of the protons in the first direction is maximum is located on the opposite side of the first position in the first direction.

[0072] (Appendix 2) 2. The semiconductor device of claim 1, wherein the second location is located within the first semiconductor layer.

[0073] (Appendix 3) The semiconductor device according to claim 1, wherein the second position is located on a surface of the first semiconductor layer on the first electrode side.

[0074] (Appendix 4) Further comprising a fourth semiconductor layer having a p-type conductivity; 4. The semiconductor device according to claim 1, wherein the first semiconductor layer is located on a side of the fourth semiconductor layer in the first direction.

[0075] (Appendix 5) The semiconductor device of claim 4, wherein the second position is located within the fourth semiconductor layer.

[0076] (Appendix 6) 5. The semiconductor device according to claim 4, wherein the second position is located on a surface of the fourth semiconductor layer opposite to the first semiconductor layer.

[0077] (Appendix 7) 7. The semiconductor device according to claim 4, further comprising a fifth semiconductor layer that is disposed on the first direction side of the third semiconductor layer and has a p-type conductivity.

[0078] (Appendix 8) a sixth semiconductor layer that is disposed on the first direction side of the fifth semiconductor layer and has an n-type conductivity; a gate electrode facing the fifth semiconductor layer; a gate insulating film disposed between the fifth semiconductor layer and the gate electrode; Further equipped with the first electrode is a collector electrode connected to the fourth semiconductor layer, 8. The semiconductor device according to claim 7, wherein the second electrode is an emitter electrode connected to the sixth semiconductor layer.

[0079] (Appendix 9) 9. The semiconductor device according to claim 1, wherein the first impurity is phosphorus.

[0080] (Appendix 10) A step of injecting a first impurity serving as a donor into a semiconductor member having an n-type conductivity from a first surface side of the semiconductor member in a first direction to form a first position inside the semiconductor member where the concentration of the first impurity is at a maximum value; A step of disposing an absorber on a first surface side of the semiconductor member; a step of injecting protons into the semiconductor member in the first direction via the absorber, and positioning a second position where the concentration of the protons is maximum on an opposite side to the first position in the first direction; removing the absorber; A method for manufacturing a semiconductor device comprising the steps of:

[0081] (Appendix 11) 11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of implanting protons, a target position of the second position is set to the first surface. [Explanation of symbols]

[0082] 1, 2 Semiconductor device 10 Semiconductor part 10a Bottom side 10b Top side 10w semiconductor wafer 11 p +Mold Collector Layer 12 Thin n-type buffer layer 13 Thick n-type buffer layer 14 n - Mold Base Layer 15 n-type barrier layer 16 p-type base layer 17 p + Mold diffusion layer 18n + Type emitter layer 19 p + Mold contact layer 21 Gate insulating film 22 Dummy gate insulating film 23 Gate insulation material 24 Dummy gate insulating material 31 Collector electrode 32 Emitter electrode 33 Gate electrode 34 Dummy gate electrode 36 Gate Trench 37 Dummy gate trench 41 Position where boron concentration reaches its maximum 42 Position where phosphorus concentration is maximum 43 Position where proton concentration is maximum 51 n + Mold contact layer 60 Semiconductor part 60a Bottom 61 Anode electrode 62 Cathode electrode 65 p type part 66 n-type part 90 Absorber P1 Boron peak P2 phosphorus peak P3 proton peak

Claims

1. A first electrode; A second electrode; a first semiconductor layer including a first impurity serving as a donor and protons, having an n-type conductivity, and having a first position located therein where the concentration of the first impurity is at a maximum value; a second semiconductor layer disposed on a first direction side from the first electrode toward the second electrode with respect to the first semiconductor layer, containing the first impurity and protons, a concentration of the protons being higher than a concentration of the first impurity, and having an n-type conductivity; a third semiconductor layer that is disposed on the first direction side of the second semiconductor layer, contains the first impurity, a concentration of the first impurity is higher than a concentration of the protons, and has an n-type conductivity; Equipped with a concentration of the first impurity is higher than a concentration of the protons in at least a portion of the first semiconductor layer on the second semiconductor layer side; A second position where the concentration of the protons in the first direction is maximum is located on the opposite side of the first position in the first direction.

2. The semiconductor device of claim 1 , wherein the second location is located within the first semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the second position is located on a surface of the first semiconductor layer on a side facing the first electrode.

4. Further comprising a fourth semiconductor layer having a p-type conductivity; 4. The semiconductor device according to claim 1, wherein the first semiconductor layer is located on the first direction side of the fourth semiconductor layer.

5. The semiconductor device of claim 4 , wherein the second location is located within the fourth semiconductor layer.

6. The semiconductor device according to claim 4 , wherein the second position is located on a surface of the fourth semiconductor layer opposite to the first semiconductor layer.

7. The semiconductor device according to claim 4 , further comprising a fifth semiconductor layer that is disposed on the first direction side of the third semiconductor layer and has a p-type conductivity.

8. a sixth semiconductor layer that is disposed on the first direction side of the fifth semiconductor layer and has an n-type conductivity; a gate electrode facing the fifth semiconductor layer; a gate insulating film disposed between the fifth semiconductor layer and the gate electrode; Further equipped with the first electrode is a collector electrode connected to the fourth semiconductor layer, 8. The semiconductor device according to claim 7, wherein the second electrode is an emitter electrode connected to the sixth semiconductor layer.

9. 2. The semiconductor device according to claim 1, wherein the first impurity is phosphorus.

10. A step of injecting a first impurity serving as a donor into a semiconductor member having an n-type conductivity from a first surface side of the semiconductor member in a first direction to form a first position inside the semiconductor member where the concentration of the first impurity is at a maximum value; A step of disposing an absorber on a first surface side of the semiconductor member; a step of injecting protons into the semiconductor member in the first direction via the absorber, and positioning a second position where the concentration of the protons is maximum on an opposite side to the first direction from the first position; removing the absorber; A method for manufacturing a semiconductor device comprising the steps of:

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of implanting protons, a target position of the second position is the first surface.

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