Laminate, method for manufacturing patterning substrate, electronic device, and mounting apparatus

Abstract

To provide a laminate that can reduce the amount by which the cross-sectional shape of a conductive layer becomes shorter on one side opposite the insulating layer than on the other side of the insulating layer when the conductive layer is etched in the laminate including a copper clad laminate.SOLUTION: A laminate 100 has an insulating layer 10, a conductive layer 30 provided on the insulating layer 10, and an etching delay layer 20 provided on one side of the conductive layer 30, the other side or both sides of the one and the other side. The conductive layer 30 and the etching delay layer 20 are not patterned.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a laminate having an insulating layer and a conductive layer, a method for manufacturing the laminate, an electronic device, and a mounting device. [Background technology]

[0002] Conventionally, laminates having a conductor layer provided on an insulating layer have been known. As an example, Patent Document 1 proposes a copper-clad laminate having an insulating layer made of polyimide and a first copper foil layer laminated on one side of the insulating layer made of polyimide. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-60138 A Summary of the Invention [Problem to be solved by the invention]

[0004] When etching a conductor layer in a laminate including a copper-clad laminate, the etching rate in the conductor layer located on the upper side becomes faster than the etching rate in the conductor layer located on the lower side, and a pattern in which the upper side is shorter than the lower side tends to be formed. If the upper side is shorter than the lower side in the cross-sectional shape of the conductor layer, a problem may occur in which the designed amount of current does not flow in the conductor layer.

[0005] The present invention provides a laminate that can reduce the amount by which the length of one side of a conductor layer opposite an insulating layer is shorter than the length of the other side of the insulating layer, a method for manufacturing the laminate, an electronic device, and a mounting device. [Means for solving the problem]

[0006] [Concept 1] The laminate according to the present invention comprises: An insulating layer; A conductor layer provided on the insulating layer; an etching retardation layer provided on one surface, the other surface, or both the one surface and the other surface of the conductor layer; Equipped with The conductive layer and the etch retardation layer may be unpatterned.

[0007] [Concept 2] In the laminate according to concept 1, The etching retardation layer may be provided on substantially the entire surface of one side of the conductor layer.

[0008] [Concept 3] In a laminate according to either concept 1 or 2, An oxide layer may be provided between the insulating layer and the conductor layer.

[0009] [Concept 4] A laminate according to any one of concepts 1 to 3, the conductor layer is a layer containing copper as a main component, The etching retardation layer may be a layer whose main component is an alloy containing nickel, titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten, platinum, chromium, lead, or cobalt.

[0010] [Concept 5] A laminate according to any one of concepts 1 to 4, The etching retardation layer may have a thickness that is 1 / 2 to 1 / 1000 of the thickness of the conductive layer.

[0011] [Concept 6] In the laminate according to Concept 5, The thickness of the etching retardation layer may be 1 / 2 to 1 / 10 of the thickness of the conductor layer.

[0012] [Concept 7] A laminate according to any one of concepts 1 to 6, The etch retardation layer may be provided on both sides of the conductor layer.

[0013] [Concept 8] A laminate according to any one of concepts 1 to 7, The conductor layer may have a thickness of 100 μm or more.

[0014] [Concept 9] A laminate according to any one of concepts 1 to 8, An oxide layer may be provided on both the one surface and the other surface of the conductor layer.

[0015] [Concept 10] The method for producing a patterned substrate according to the present invention includes the steps of: A step of preparing a laminate having an insulating layer, a conductor layer provided on the insulating layer, and an etching retardation layer provided on one side or both the one side and the other side of the conductor layer; patterning the conductor layer and the etching retardation layer by etching the substrate; The present invention may also include:

[0016] [Concept 11] The electronic device according to the present invention comprises: A laminate according to any one of concepts 1 to 9; An electronic component provided on the laminate; The present invention may also include:

[0017] [Concept 12] The mounting device according to the present invention comprises: The electronic device according to claim 11 may be provided. Effect of the Invention

[0018] In an unpatterned laminate, when an etching retardation layer is provided on one side of a conductor layer, the amount by which the length of one side of the conductor layer opposite the insulating layer (the length of the upper side) is shorter than the length of the other side of the conductor layer on the insulating layer side (the length of the lower side) can be reduced, and the cross-sectional shape of the conductor layer can be made closer to a rectangle or square. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a side cross-sectional view of a laminate according to an example of the first embodiment of the present invention. [Diagram 2] FIG. 2(a) is a side cross-sectional view of a laminate according to another example of the first embodiment of the present invention, and FIG. 2(b) is a side cross-sectional view of a laminate according to yet another example of the first embodiment of the present invention. [Diagram 3] FIG. 3 is a side cross-sectional view showing a state in which a part of a conductor layer before being patterned is pressed into an insulating layer. [Figure 4] FIG. 4 is a side cross-sectional view showing a state in which a part of the conductor layer after patterning is pressed into the insulating layer. [Diagram 5] FIG. 5 is a side cross-sectional view showing a state in which the entire side surface of a conductor layer before patterning is pressed into an insulating layer. [Figure 6] FIG. 6 is a cross-sectional side view showing an embodiment in which the entire side surface of the patterned conductor layer is pressed into the insulating layer. [Figure 7] FIG. 7 is a side cross-sectional view showing an embodiment in which a part of a conductor layer after patterning is pressed into an insulating layer in an embodiment having a redox layer. [Figure 8] FIG. 8 is a cross-sectional side view showing an embodiment having a redox layer in which the entire side surface of the patterned conductor layer is pressed into the insulating layer. [Figure 9] FIG. 9(a) is a cross-sectional side view of a laminate having an etching retardation layer, FIG. 9(b) is a cross-sectional side view of the etching retardation layer patterned after FIG. 9(a), FIG. 9(c) is a cross-sectional side view of the conductor layer patterned after FIG. 9(b), FIG. 9(d) is a cross-sectional side view of the etch retardation layer removed after FIG. 9(c), and FIG. 9(e) is a cross-sectional side view of the conductor layer pressed into the insulating layer after FIG. 9(d). [Figure 10] FIG. 10(a) is a side cross-sectional view showing one example of an embodiment for generating a redox layer, and FIG. 10(b) is a side cross-sectional view showing an embodiment having a first redox layer and a second redox layer. [Figure 11] FIG. 11 is a side cross-sectional view showing an example of a state in which an etching process is carried out after a part of a conductor layer is pressed in. In FIG. [Figure 12] FIG. 12(a) is a side cross-sectional view illustrating the state in which etching is performed when an etching retardation layer is not provided, and FIG. 12(b) is a side cross-sectional view illustrating the state in which etching is performed when an etching retardation layer is provided. [Figure 13] 13(a) is a side cross-sectional view showing how the conductor layer is pushed into the insulating layer after the etching retardation layer is removed, FIG. 13(b) is a side cross-sectional view corresponding to FIG. 13(a) showing how an oxidation-reduction layer is provided on the lower and side surfaces of the conductor layer, and FIG. 13(c) is a side cross-sectional view corresponding to FIG. 13(a) showing how an oxidation-reduction layer is provided on the lower, side and upper surfaces of the conductor layer. [Figure 14] FIG. 14 is a side cross-sectional view showing an embodiment in which an unevenly shaped oxidation-reduction layer is provided. [Figure 15A] FIG. 15A is a side cross-sectional view of a laminate according to an example of the second embodiment of the present invention. [Figure 15B] FIG. 15B(a) is a side cross-sectional view of a laminate according to another example of the second embodiment of the present invention, and FIG. 15B(b) is a side cross-sectional view of a laminate according to yet another example of the second embodiment of the present invention. [Figure 16] FIG. 16(a) is a side cross-sectional view of a laminate according to an example of the third embodiment of the present invention, FIG. 16(b) is a side cross-sectional view of a laminate showing an example in which a redox layer is provided in the third embodiment of the present invention, FIG. 16(c) is a side cross-sectional view of a laminate showing another example in which a redox layer is provided, and FIG. 16(d) is a side cross-sectional view of yet another example of a laminate according to the present invention in which a redox layer is provided. [Figure 17] FIG. 17 is a diagram showing an example of an electronic device that can be provided by the present invention. [Figure 18] FIG. 18 is a side cross-sectional view showing an example of a multilayer substrate that can be used in the present invention. [Figure 19]FIG. 19 is a side cross-sectional view showing an example of a double-sided board that can be used in the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] First embodiment "composition" As shown in FIG. 1, the laminate 100 according to the present embodiment may have an insulating layer 10, a conductor layer 30 provided on the insulating layer 10, and an etching retardation layer 20 provided on one side of the conductor layer 30 (the upper side in FIG. 1). The conductor layer 30 and the etching retardation layer 20 may not be patterned. In other words, the laminate 100 may be before etching or the like is performed. The laminate 100 provided in the present embodiment may be a printed circuit board, a metal-clad laminate such as a copper clad laminate (CCL), or the like. It may be a double-sided board in which the conductor layer 30 is provided on both sides of the insulating layer 10 (see FIG. 19).

[0021] The conductor layer 30 may be provided on substantially the entire surface of one side of the insulating layer 10, and the etching retardation layer 20 may be provided on substantially the entire surface of one side of the conductor layer 30. The conductor layer 30 being provided on substantially the entire surface of one side of the insulating layer 10 means that, in a plan view from one side (the upper side of FIG. 1), the conductor layer 30 covers 95% or more of the area of ​​the insulating layer 10, and the area of ​​the insulating layer 10 that is not covered by the conductor layer 30 is 5% or less. Similarly, the etching retardation layer 20 being provided on substantially the entire surface of one side of the conductor layer 30 means that, in a plan view from one side (the upper side of FIG. 1), the etching retardation layer 20 covers 95% or more of the area of ​​the conductor layer 30, and the area of ​​the conductor layer 30 that is not covered by the etching retardation layer 20 is 5% or less.

[0022] The conductor layer 30 may be a metal foil, a metal plating, a rolled plate, or the like. The conductor layer 30 may be a copper layer made of copper. The conductor layer 30 may be made of a material other than copper, such as gold, silver, aluminum, or an alloy containing these metals. The conductor layer 30 may be a metal containing copper as a main component. In this application, the term "main component" means that the content is more than 50% by weight. The thickness of the conductor layer 30 may be 100 μm or more, or 150 μm or more. The thickness of the conductor layer 30 may be 500 μm or less, or 300 μm or less.

[0023] The etching retardation layer 20 may be a nickel layer made of nickel. The etching retardation layer 20 may be made of any material that retards etching, and may be made of any material other than nickel, but it is advantageous to use nickel from the viewpoints of versatility and cost. The etching retardation layer 20 may be made of a material mainly composed of nickel. The etching retardation layer 20 may also be made of a material mainly composed of titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten, platinum, or an alloy containing two or more of these metals.

[0024] It is beneficial for the thickness of the etching retardation layer 20 to be in the range of 1 / 2 to 1 / 1000 of the thickness of the conductor layer 30. Generally speaking, when the thickness of the conductor layer 30 is increased, the ratio of the thickness of the etching retardation layer 20 becomes relatively smaller.

[0025] The etch retardation layer 20 may be removed after the etching process is completed, in which case the etch retardation layer 20 is not provided on the laminate 100 having the patterned conductor layer 30 after the etching process has been performed.

[0026] The insulating layer 10 may be made of, for example, resin, glass, ceramic, etc. The insulating layer 10 may be a mixture of two or more kinds of insulating materials. For example, the insulating layer 10 may contain a fibrous or granular insulator. The insulating layer 10 may be a semi-cured sheet (prepreg) that is made by impregnating a base material such as paper or glass fiber with resin and drying it. The insulating layer 10 may contain a thermally conductive material such as silicon nitride. The semi-cured state is a state in which the material is not completely hardened and is deformable.

[0027] The material of the insulating layer 10 may be a thermosetting resin, an ultraviolet curing resin, or the like. If the material has a certain degree of heat resistance, a thermoplastic resin may be used as the material of the insulating layer 10. As the thermosetting resin, a polyimide resin, an epoxy resin, a phenolic resin, a cyanate resin, or the like may be used. The thermoplastic resin may have a heat distortion temperature of 50 degrees or more.

[0028] A redox layer 40 may be provided between the insulating layer 10 and the conductor layer 30. The redox layer 40 may have an uneven shape on the surface facing the insulating layer 10 (see FIG. 14).

[0029] The redox layer 40 may contain an oxide of the material constituting the conductor layer 30. The redox layer 40 may have a concave-convex shape in whole or in part. The concave-convex shape may have a cross section that is substantially triangular, substantially rectangular, substantially semicircular, or substantially circular, or may have a mesh shape like entangled fibers, and the concave-convex shape may be configured in various shapes. In this embodiment, "substantially XX shape" means that it is roughly XX shape when viewed by a person skilled in the art.

[0030] As shown in Fig. 2(a), the redox layer 40 may be provided between the conductor layer 30 and the etching retardation layer 20. The redox layer 40 may be provided on one surface of the conductor layer 30, on the other surface (see Fig. 2(a)), or on both the one surface and the other surface (see Fig. 2(b)).

[0031] The redox layer 40 may contain copper oxide as a main component. The copper oxide may contain cuprous oxide, cupric oxide, or both cuprous oxide and cupric oxide. Here, "main component" means that the copper oxide is contained in an amount of more than 50% by weight.

[0032] 10(b), the redox layer 40 may have a first redox layer 41 and a second redox layer 42 provided on the insulating layer 10 side of the first redox layer 41. When the redox layer 40 is made of copper oxide, for example, the first redox layer 41 may contain cuprous oxide (Cu2O) and the second redox layer 42 may contain cupric oxide (CuO). Alternatively, the first redox layer 41 may be made of cuprous oxide (Cu2O) and the second redox layer 42 may be made of cupric oxide (CuO).

[0033] The redox layer 40 may be composed only of copper oxide. In other words, the entire redox layer 40 may be composed of copper oxide. In this case, the redox layer 40 is composed of an oxidized layer (oxidized layer). The copper oxide may be cuprous oxide (Cu2O), cupric oxide (CuO), or both cuprous oxide and cupric oxide. Since cuprous oxide becomes cupric oxide as the oxidation reaction progresses, the mixing ratio of cuprous oxide and cupric oxide may be adjusted by adjusting the treatment time with the treatment liquid 120 (see FIG. 10(a)) placed in the container 110.

[0034] The insulating layer 10 may be in a semi-cured state. The patterned conductor layer 30 may be partially or entirely embedded in the semi-cured insulating layer 10 by, for example, pushing it in (see FIGS. 3 to 6). When embedding the conductor layer 30 in the insulating layer 10, a pressing force may be applied to the conductor layer 30, but this is not limited to the above embodiment, and the conductor layer 30 may be embedded in the insulating layer 10 by its own weight. When embedding the conductor layer 30 in the insulating layer 10, the conductor layer 30 after patterning may be embedded in the insulating layer 10 (see FIGS. 4 and 6), or the conductor layer 30 before patterning may be embedded in the insulating layer 10 (see FIGS. 3 and 5). In addition, if the etching retardation layer 20 is removed, the entire conductor layer 30 including one surface (upper surface) may be completely embedded inside the insulating layer 10 (see FIGS. 13(a)-(c)).

[0035] 13(b) shows an embodiment in which the redox layer 40 is provided over the entire lower and side surfaces of the conductor layer 30, but is not provided on the upper surface where the etching retardation layer 20 was provided. This embodiment can be realized by performing an etching process, followed by an oxidation-reduction reaction or an oxidation reaction of the conductor layer 30, and then removing the etching retardation layer 20. On the other hand, if an oxidation-reduction reaction or an oxidation reaction of the conductor layer 30 is performed after performing an etching process and removing the etching retardation layer 20, the redox layer 40 will be formed over the entire surface of the conductor layer 30 (see FIG. 13(c)).

[0036] After the patterned conductor layer 30 is partially or entirely embedded in the semi-cured insulating layer 10 by, for example, pressing it in, the insulating layer 10 may be cured by applying heat or irradiating it with ultraviolet light. When a thermoplastic resin is used as the insulating layer 10, the insulating layer 10 may be cured by being allowed to cool or by being cooled.

[0037] In an embodiment in which the redox layer 40 is provided, the redox layer 40 may be provided in a region recessed into the insulating layer 10, and the redox layer 40 may not be provided in a region (side surface) exposed from the insulating layer 10 (see FIG. 7). Such an embodiment can be produced by removing the region protruding from the insulating layer 10 from the redox layer 40 formed on the entire side surface of the conductor layer 30. The redox layer 40 may be provided on the entire side surface of the conductor layer 30, and the conductor layer 30 and the redox layer 40 may be entirely provided within the insulating layer 10 (see FIG. 8).

[0038] ≪Manufacturing process≫ An example of a processing step using the laminate according to this embodiment will be described with reference to FIG.

[0039] A laminate 100 having an insulating layer 10, a conductor layer 30 provided on the insulating layer 10, and an etching retardation layer 20 provided on one surface of the conductor layer 30 is prepared (see FIG. 9(a)).

[0040] Next, in a state where the laminate 100 is appropriately masked, etching is performed to pattern the conductor layer 30 and the etching retardation layer 20 (see FIGS. 9(b) and (c)). Note that the etching solution (first etching solution) used for patterning the etching retardation layer 20 and the etching solution (second etching solution) used for patterning the conductor layer 30 may have different components.

[0041] As an example, the etching retardation layer 20 is patterned with a first etching solution while being appropriately masked (see FIG. 9(b)). After that, the conductor layer 30 is patterned with a second etching solution while being appropriately masked (see FIG. 9(c)).

[0042] After the etching is completed, the etching retardation layer 20 is removed by a chemical solution (a removal solution for removing the etching retardation layer 20 or a second etching solution) (see FIG. 9(d)).

[0043] Thereafter, a part or the whole of the patterned conductor layer 30 is pressed into the semi-cured insulating layer 10 (see FIG. 9(e)).

[0044] Next, the semi-cured insulating layer 10 is allowed to cool or is cooled to harden the insulating layer 10. As a result, a laminate 100 in which a part of the conductor layer 30 is embedded in the insulating layer 10 is produced.

[0045] In the above, the embodiment in which the conductor layer 30 is pressed into the semi-cured insulating layer 10 after removing the etching retardation layer 20 has been described, but the present invention is not limited to this. For example, the etching retardation layer 20 may be removed after the conductor layer 30 is pressed into the semi-cured insulating layer 10. Alternatively, the conductor layer 30 may be pressed into the semi-cured insulating layer 10, followed by etching, and then the etching retardation layer 20 may be removed, and then the insulating layer 10 may be cured. Even in this case, by removing a part of the conductor layer 30 by etching, the semi-cured insulating layer 10 may move to match the height, and an insulating layer 10 having the same height may be obtained in the region where the conductor layer 30 is not provided, as shown in FIG. 9(e). However, the present invention is not limited to this embodiment, and the insulating layer 10 may be cured early to produce a laminate 100 in which the insulating layer 10 has a different height, as shown in FIG. 11. In the embodiment shown in FIG. 11, the insulating layer 10 has a recessed shape at the location where the conductor layer 30 was present.

[0046] "effect" Next, effects of the present embodiment having the above-mentioned configuration, which have not yet been described, will be described.

[0047] When a laminate in which the etching retardation layer 20 is provided on one side of the conductor layer 30 and the conductor layer 30 and the etching retardation layer 20 are not patterned is used, the cross-sectional shape of the conductor layer 30 can be made closer to a rectangular shape or a square shape. When performing an etching process, the conductor layer 30 located on the upper side is etched more than the conductor layer 30 located on the lower side, and a pattern in which the upper side is shorter than the lower side tends to be formed (see FIG. 12(a)). In this regard, by providing the etching retardation layer 20 on one side of the conductor layer 30, the etching speed of the conductor layer 30 located on the upper side can be slowed down, and as a result, the shape of the conductor layer 30 to be patterned can be made closer to a rectangular shape or a square shape (see FIG. 12(b)).

[0048] In this embodiment, since the focus is on the etching process, it is an important point that the conductor layer 30 and the etching retardation layer 20 are not patterned. Generally, attempts are made to reduce costs by increasing the etching speed and shortening the processing time, but in this embodiment, the disadvantage of slower processing time is accepted in order to make the conductor layer 30 closer to a rectangular or square shape, and this is based on an idea completely opposite to that of those generally skilled in the art.

[0049] This embodiment is advantageous in that the conductor layer 30 is made closer to a rectangular or square shape, allowing a current amount close to the design value to flow. In other words, when designing, calculations are performed on the assumption that the cross section of the conductor pattern of copper or the like is rectangular or square, but in reality, the cross section of the conductor pattern of copper or the like is trapezoidal, so that a current amount different from the amount used in the design value flows. In this respect, the adoption of the embodiment is advantageous in that this point can be improved.

[0050] The thicker the conductor layer 30, the stronger the tendency for the upper side of the cross section of the conductor layer 30 to be shorter than the lower side, so it is beneficial to adopt this embodiment. In particular, for a conductor layer 30 having a thickness of 100 μm or more (typically a thick copper type conductor layer), the difference in shape of the conductor layer 30 between when the etching retardation layer 20 is provided and when the etching retardation layer 20 is not provided becomes significant. For this reason, it is beneficial to adopt this embodiment when employing a conductor layer 30 having a thickness of 100 μm or more.

[0051] The etching rate on one side (upper side) can be adjusted by adjusting the thickness of the etching retardation layer 20. In particular, when the thickness of the etching retardation layer 20 is 1 / 10 or more of the thickness of the conductor layer 30, it is useful for adjusting the etching rate, and when it is 1 / 5 or more, it is even more useful.

[0052] Second embodiment Next, a second embodiment of the present invention will be described.

[0053] As shown in FIG. 15A, in this embodiment, the etching retardation layer 20 is provided on both one side and the other side of the conductor layer 30. The other configurations are the same as those in the first embodiment, and any aspect described in the first embodiment can be adopted. The same reference numerals are used for the members described in the first embodiment. In this embodiment, the etching retardation layer 20 provided on one side (upper side) of the conductor layer 30 is also called the first etching retardation layer 20a, and the etching retardation layer 20 provided on the other side (lower side) of the conductor layer 30 is also called the second etching retardation layer 20b.

[0054] By providing the second etching retardation layer 20b on the other side, the height position of the bottom surface of the conductor layer 30 can be increased. As a result, the conductor layer 30 is not positioned at a position where the etching solution stagnates (the etching solution does not circulate) and the etching effect is reduced, but the lower end of the conductor layer 30 can be positioned at a position where the etching solution flows smoothly and an etching effect can be expected. This makes it possible to prevent the etching rate of the conductor layer 30 located on the insulating layer 10 side (lower side) from slowing down, and the cross-sectional shape of the conductor layer 30 located between the first etching retardation layer 20a and the second etching retardation layer 20b can be made closer to a rectangular or square shape.

[0055] From the viewpoint of increasing the height position of the bottom surface of the conductor layer 30, it is beneficial for the thickness of the second etching retardation layer 20b to be equal to or greater than 1 / 5 of the thickness of the conductor layer 30. By employing the second etching retardation layer 20b having such a thickness, it is possible to prevent the conductor layer 30 from being located on the lower side where the etching process does not progress easily.

[0056] The thickness of the first etching retardation layer 20a and the thickness of the second etching retardation layer 20b may be different, and the thickness of the second etching retardation layer 20b may be two or more times the thickness of the first etching retardation layer 20a. For example, the thickness of the first etching retardation layer 20a may be 1 / 10 or more of the thickness of the conductor layer 30, and the thickness of the second etching retardation layer 20b may be 1 / 5 or more of the thickness of the conductor layer 30.

[0057] The first etch retardation layer 20a and the second etch retardation layer 20b may be composed of the same material (eg, nickel), but each may be composed of a different material.

[0058] When the insulating layer 10 is in a semi-cured state, the conductive layer 30 may be pressed in such that a substantial portion (80% or more) of the second etching retardation layer 20b is embedded in the insulating layer 10. The conductive layer 30 may be pressed in such that the entire second etching retardation layer 20b is embedded in the insulating layer 10. Such pressing may be performed after patterning is performed.

[0059] 15B(a)(b), the redox layer (oxidation layer) 40 may be provided between the conductor layer 30 and the etching retardation layer 20. The redox layer 40 may be provided on one surface of the conductor layer 30, the other surface (see FIG. 15B(a)), or both the one surface and the other surface (see FIG. 15B(b)).

[0060] Third embodiment Next, a third embodiment of the present invention will be described.

[0061] As shown in Fig. 16(a), in this embodiment, an etching retardation layer 20 (second etching retardation layer 20b) is provided on the other surface of the conductor layer 30. The other configurations are the same as those in the first embodiment, and any aspect described in the first and second embodiments can be adopted. The same reference numerals will be used to describe the members described in the first and second embodiments.

[0062] Unlike the first and second embodiments, in this embodiment, the etching retardation layer 20 (first etching retardation layer 20a) is not provided on one side, and the etching retardation layer 20 is provided only on the other side. Even in this embodiment, for the reasons explained in the second embodiment, the cross-sectional shape of the conductor layer 30 can be made closer to a rectangular shape or a square shape.

[0063] As shown in Fig. 16(b), a redox layer (oxidation layer) 40 may be provided between the conductor layer 30 and the etching retardation layer 20. The redox layer 40 may be provided on one surface of the conductor layer 30 (see Fig. 16(c)), on the other surface (see Fig. 16(c)), or on both the one surface and the other surface (see Fig. 16(d)).

[0064] ≪Multilayer board≫ A multilayer substrate in which a plurality of laminates such as those shown in the first to third embodiments are stacked may be employed. For each of the conductor layers 30, an etching retardation layer 20 and / or an oxidation-reduction layer 40 may be provided.

[0065] In Fig. 18, a laminate shown in Fig. 2(a) is shown in a multi-layer structure, but the present invention is not limited thereto. A laminate shown in any one of Figs. 1, 2(b), 15A, 15B(a), 15B(b), 16(a), 16(b), 16(c) and 16(d) may be used in a multi-layer structure, or a multi-layer board may be used in which a laminate having two or more of the laminates shown in Figs. 1, 2(a), 2(b), 15A, 15B(a), 15B(b), 16(a), 16(b), 16(c) and 16(d) is used in a multi-layer structure. A laminate located on the outermost surface (topmost surface) may have a different configuration from the other laminates (laminates located inside).

[0066] The description of each of the above-mentioned embodiments and the disclosure of the drawings are merely examples for explaining the invention described in the claims, and the invention described in the claims is not limited by the description of the above-mentioned embodiments or the disclosure of the drawings.

[0067] Electronic components 210 such as semiconductor elements, capacitors, resistors, etc. are placed on the laminate 100 in the above-described embodiment, and the electronic components are encapsulated in a sealing resin 220 to provide an electronic device 200 (see FIG. 17). Such an electronic device may be incorporated in any mounting device, such as an automobile, an airplane, a ship, a helicopter, a personal computer, or a home appliance. [Explanation of symbols]

[0068] 10 Insulating layer 20 Etching retardation layer 30 Conductor Layer 100 Laminate

Claims

1. An insulating layer; A conductor layer provided on the insulating layer; an etching retardation layer provided on one surface, the other surface, or both the one surface and the other surface of the conductor layer; Equipped with The laminate in which the conductor layer and the etch retardation layer are unpatterned.

2. The laminate according to claim 1 , wherein the etching retardation layer is provided over substantially the entire surface of one side of the conductor layer.

3. The laminate according to claim 1 or 2, further comprising an oxide layer between the insulating layer and the conductor layer.

4. the conductor layer is a layer containing copper as a main component, 4. The laminate according to claim 1, wherein the etching retardation layer is a layer whose main component is an alloy containing nickel, titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten, platinum, chromium, lead or cobalt.

5. 5. The laminate according to claim 1, wherein the thickness of the etching retardation layer is 1 / 2 to 1 / 1000 of the thickness of the conductor layer.

6. 6. The laminate according to claim 5, wherein the thickness of the etching retardation layer is 1 / 2 to 1 / 10 of the thickness of the conductor layer.

7. 7. The laminate according to claim 1, wherein the etching retardation layer is provided on both sides of the conductor layer.

8. The laminate according to claim 1 , wherein the conductor layer has a thickness of 100 μm or more.

9. 9. The laminate according to claim 1, wherein an oxide layer is provided on both one side and the other side of the conductor layer.

10. The laminate according to claim 1 , wherein the insulating layer is in a semi-cured state.

11. A step of preparing a laminate having an insulating layer, a conductor layer provided on the insulating layer, and an etching retardation layer provided on one side or both the one side and the other side of the conductor layer; patterning the conductor layer and the etching retardation layer by etching the substrate; A method for manufacturing a patterned substrate comprising the steps of:

12. A laminate according to any one of claims 1 to 10; An electronic component provided on the laminate; An electronic device comprising:

13. A mounting device comprising the electronic device according to claim 12.

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