Semiconductor memory element

Abstract

To provide a semiconductor memory element with a structure in which memory cells are easily miniaturized and integrated highly.SOLUTION: A semiconductor memory element includes a word line extending in a horizontal direction, a sensing line overlapping with the word line at a position apart from the word line in a vertical direction and extending in the horizontal direction, a vertical semiconductor structure including a vertical channel region penetrating the word line and the sensing line in the vertical direction and facing the word line in the horizontal direction, and a gate dielectric film existing between the vertical channel region and the word line. The vertical semiconductor structure includes a first conductivity type first high-concentration doping film, a second conductivity type first low-concentration doping film, a first conductivity type second low-concentration doping film, and a second conductivity type second high-concentration doping film that are stacked sequentially along the vertical direction. The vertical channel region includes any one selected from the first low-concentration doping film and the second low-concentration doping film. The sensing line is in contact with the first high-concentration doping film of the vertical semiconductor structure.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a plurality of memory cells arranged three-dimensionally. [Background technology]

[0002] 2. Description of the Related Art In recent years, with the development of electronic technology, down-scaling of semiconductor devices has progressed rapidly. This has created a demand for miniaturization of memory cells, but existing memory cells have limitations in terms of high integration and reliability. Therefore, there is a need to develop a semiconductor memory device having a structure that facilitates miniaturization and high integration of memory cells. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in consideration of the above-mentioned problems with conventional semiconductor memory devices, and an object of the present invention is to provide a semiconductor memory device having a structure that facilitates miniaturization and high integration of memory cells. [Means for solving the problem]

[0004] In order to achieve the above object, a semiconductor memory device according to the present invention includes word lines extending in a horizontal direction, sensing lines extending in the horizontal direction and overlapping the word lines in a vertical direction at a position spaced apart from the word lines, a vertical semiconductor structure having a vertical channel region passing through the word lines and the sensing lines in the vertical direction and facing the word lines in the horizontal direction, and a gate dielectric layer interposed between the vertical channel region and the word lines, wherein the vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially stacked along the vertical direction, and the vertical channel region is made of any one selected from the first lightly doped film and the second lightly doped film, and the sensing line is in contact with the first heavily doped film of the vertical semiconductor structure.

[0005] In order to achieve the above object, a semiconductor memory device according to the present invention includes a memory cell string including a plurality of memory cells arranged in a row along a vertical direction, and each of the plurality of memory cells includes a word line extending in a horizontal direction, a sensing line extending in the horizontal direction and overlapping the word line in a vertical direction at a position spaced apart from the word line, a vertical semiconductor structure having a vertical channel region passing through the word line and the sensing line in the vertical direction and facing the word line in the horizontal direction, and a gate interposed between the vertical channel region and the word line. and a gate dielectric film, wherein the vertical semiconductor structure in each of the plurality of memory cells includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially stacked along the vertical direction, the vertical channel region in each of the plurality of memory cells is formed of one selected from the first lightly doped film and the second lightly doped film, and the sensing line in each of the plurality of memory cells is in contact with the first heavily doped film of the vertical semiconductor structure.

[0006] In order to achieve the above object, a semiconductor memory device according to the present invention has a memory cell array section including a plurality of memory cells that are three-dimensionally repeatedly arranged on a substrate along first and second horizontal directions perpendicular to each other and a vertical direction perpendicular to each of the first and second horizontal directions, the memory cell array section including a plurality of sensing lines and a plurality of word lines that are alternately arranged one by one along the vertical direction and spaced apart from each other in the vertical direction, a plurality of insulating films interposed between the plurality of sensing lines and the plurality of word lines, a stack structure including a plurality of vertical semiconductor structures that penetrate the plurality of sensing lines, the plurality of word lines, and the plurality of insulating films in the vertical direction, each having a vertical channel region, and overlapping each other in the vertical direction, and a stack structure including a plurality of vertical semiconductor structures that interpose the plurality of vertical semiconductor structures in the vertical direction. a plurality of insulating pillars extending vertically through the plurality of vertical semiconductor structures, a plurality of gate dielectric films interposed between the vertical channel region of each of the plurality of vertical semiconductor structures and the plurality of word lines, and a plurality of bit lines extending vertically through the plurality of insulating films, wherein memory cells arranged in a row along the vertical direction among the plurality of memory cells share one bit line selected from the plurality of bit lines, and the plurality of vertical semiconductor structures each include a first highly doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second highly doped film of the second conductivity type, which are sequentially stacked along the vertical direction, and the vertical channel region of each of the plurality of vertical semiconductor structures is any one selected from the first lightly doped film and the second lightly doped film. Effect of the Invention

[0007] The semiconductor memory device according to the present invention has a structure in which one memory cell includes one transistor and does not include a capacitor. The semiconductor memory element according to the present invention can be miniaturized and provides a structure that is advantageous for high-density three-dimensional arrays. In addition, the semiconductor memory device according to the present invention includes a 3D stacked memory cell array in which a plurality of memory cells overlap each other in the vertical direction share one bit line that extends long in the vertical direction. Therefore, it is possible to overcome the problem of bit line density limitations faced by semiconductor memory devices having existing two-dimensional structures, provide a structure that is advantageous for high integration of semiconductor memory devices, and provide excellent competitiveness in various aspects including performance, power, chip size, and cost. [Brief description of the drawings]

[0008] [Figure 1] 1 is a plan view illustrating a schematic configuration of a portion of a semiconductor memory device according to an embodiment of the present invention; [Figure 2A] 2 is a cross-sectional view taken along the line X1-X1' in FIG. [Figure 2B] 2 is a cross-sectional view taken along the line Y1-Y1' in FIG. [Figure 2C] FIG. 2B is an enlarged cross-sectional view of a portion indicated by "EX1" in FIG. 2A. [Figure 2D] FIG. 2C is an enlarged cross-sectional view of the portion indicated by "EX2" in FIG. 2B. [Figure 3A] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor memory device according to another embodiment of the present invention; [Figure 3B] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor memory device according to another embodiment of the present invention; [Figure 3C] FIG. 3B is an enlarged cross-sectional view of the portion indicated by "EX3" in FIG. 3A. [Figure 3D] FIG. 3C is an enlarged cross-sectional view of a portion indicated by "EX4" in FIG. 3B. [Figure 4] 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor memory device according to still another embodiment of the present invention. [Figure 5A] 11 is a partially cutaway perspective view of a memory cell included in a semiconductor memory device according to still another embodiment of the present invention; FIG. [Figure 5B] FIG. 5B is an equivalent circuit diagram of the memory cell illustrated in FIG. 5A. [Figure 5C] 5C is a graph for explaining the operating characteristics of the memory cell illustrated in FIGS. 5A and 5B. [Figure 6A] 11 is a partially cutaway perspective view of a memory cell included in a semiconductor memory device according to still another embodiment of the present invention; FIG. [Figure 6B] FIG. 6B is an equivalent circuit diagram of the memory cell illustrated in FIG. 6A. [Figure 6C] 7 is a graph for explaining the operating characteristics of the memory cell illustrated in FIGS. 6A and 6B. [Figure 7] 1 is an exemplary circuit diagram of a semiconductor memory device according to an embodiment of the inventive concept; [Figure 8] 8 is a timing diagram of one memory cell selected from a semiconductor memory device having the circuit configuration illustrated in FIG. 7. [Figure 9] 8 is a schematic perspective view of semiconductor memory elements arranged in a 3×3×3 array according to the circuit configuration illustrated in FIG. 7. [Figure 10] 8 is a schematic side view of semiconductor memory elements arranged in a 3×3×3 array according to the circuit configuration illustrated in FIG. 7. [Figure 11] 11 is an exemplary circuit diagram of a semiconductor memory device according to another embodiment of the inventive concept; [Figure 12] 12 is a timing diagram of one memory cell selected from a semiconductor memory device having the circuit configuration illustrated in FIG. 11. [Figure 13A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 13B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 14A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 14B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 15A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 15B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 18A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 18B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 18C] FIG. 18B is an enlarged cross-sectional view of the portion indicated by “EXA” in FIG. [Figure 19A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 19B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 19C] FIG. 19B is an enlarged cross-sectional view of the portion marked "EXA" in FIG. 19A. [Figure 20]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 22A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 22B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 23] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 24A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 24B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 25A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 25B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 26A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 26B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 27A]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 27B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 28] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 29] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Diagram 30] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Diagram 31] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 32A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 32B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. [Figure 33A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, in a process sequence corresponding to a cross section taken along line X1-X1' of FIG. [Figure 33B] 2A to 2C are cross-sectional views of a portion corresponding to a cross section taken along line Y1-Y1' in FIG. 1 in a process sequence. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, a specific example of an embodiment of a semiconductor memory device according to the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference symbols, and duplicated explanations thereof will be omitted.

[0010] 1 and 2A to 2D are drawings for explaining a semiconductor memory device 100 according to an embodiment of the present invention, in which FIG. 1 is a plan view showing a schematic configuration of a portion of the semiconductor memory device 100, FIG. 2A is a cross-sectional view taken along line X1-X1' in FIG. 1, FIG. 2B is a cross-sectional view taken along line Y1-Y1' in FIG. 1, FIG. 2C is an enlarged cross-sectional view of a portion marked "EX1" in FIG. 2A, and FIG. 2D is an enlarged cross-sectional view of a portion marked "EX2" in FIG. 2B.

[0011] 1 and 2A to 2D, the semiconductor memory device 100 includes a substrate 102, a memory cell array unit MCA arranged on the substrate 102, and a first connection unit AR1 and a second connection unit AR2 arranged on the substrate 102 and spaced apart in a first horizontal direction (X direction) across the memory cell array unit MCA. The memory cell array section MCA includes a plurality of memory cells MC three-dimensionally arranged in a repeated manner along a first horizontal direction (X direction) and a second horizontal direction (Y direction) that are perpendicular to each other, and a vertical direction (Z direction) that is perpendicular to each of the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0012] The substrate 102 is a semiconductor substrate including Si, Ge, or SiGe. The memory cell array unit MCA includes a plurality of sensing lines SL and a plurality of word lines WL that are alternately arranged along a vertical direction (Z direction) and spaced apart from each other in the vertical direction (Z direction). An insulating film selected from a plurality of insulating films (110A, 110B, 110C) is interposed between the bottom sensing line SL of the plurality of sensing lines SL and the substrate 102, and between each of the plurality of sensing lines SL and the plurality of word lines WL. In the memory cell array section MCA, a plurality of stack structures SST each including a plurality of vertical semiconductor structures VSS overlapping each other in the vertical direction (Z direction) are arranged. The vertical semiconductor structures VSS each penetrate the word line WL, the sensing line SL, and the insulating films 110A, 110B, and 110C in a vertical direction (Z direction).

[0013] The word lines WL and the sensing lines SL extend flat in a horizontal direction (along the XY plane) parallel to the major surface 102M of the substrate 102, respectively. The word lines WL and the sensing lines SL are arranged to overlap each other in the vertical direction (Z direction). The word lines WL and the sensing lines SL may each be made of, but are not limited to, W, Al, Mo, Ru, Al, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or combinations thereof. The insulating films (110A, 110B, 110C) are each made of a silicon oxide film, but are not limited to this.

[0014] The multiple vertical semiconductor structures VSS each include a first highly doped film HDS1, a first lightly doped film DS1, a second lightly doped film DS2, and a second highly doped film HDS2, which are sequentially stacked along the vertical direction (Z direction) from the portion closest to the substrate 102. In each of the multiple vertical semiconductor structures VSS, the first heavily doped film HDS1 and the second lightly doped film DS2 have a first conductivity type, and the first lightly doped film DS1 and the second heavily doped film HDS2 have a second conductivity type that is the opposite conductivity type of the first conductivity type. As used herein, the terms "heavily doped" and "lightly doped" are relative terms, with a heavily doped film having a higher doping concentration than a lightly doped film, and a lightly doped film having a lower doping concentration than a heavily doped film.

[0015] In an exemplary embodiment, in each of the multiple vertical semiconductor structures VSS, the first highly doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, and the second highly doped film HDS2 are made of doped silicon (Si) films, and the doping concentrations in the first highly doped film HDS1 and the second highly doped film HDS2 are higher than the doping concentrations in the first lightly doped film DS1 and the second lightly doped film DS2, respectively. For example, the first highly doped film HDS1 and the second lightly doped film DS2 are each made of a polysilicon film doped with n-type impurities, and the doping concentration of the n-type impurities in the first highly doped film HDS1 is higher than the doping concentration of the n-type impurities in the second lightly doped film DS2. In addition, the first lightly doped film DS1 and the second heavily doped film HDS2 are each made of a polysilicon film doped with p-type impurities, and the doping concentration of the p-type impurities in the second heavily doped film HDS2 is higher than the doping concentration of the p-type impurities in the first lightly doped film DS1.

[0016] In an exemplary embodiment, the n-type impurities may be selected from p (phosphorus), As (arsenic), and Sb (antimony), and the p-type impurities may be selected from B (boron) and Ga (gallium). In one example, the n-type impurity doping concentration in the first highly doped film HDS1 and the p-type impurity doping concentration in the second highly doped film HDS2 are 1×10 19 atoms / cm 3 ~9×10 20 atoms / cm 3 The doping concentration of the p-type impurity in the first lightly doped film DS1 and the doping concentration of the n-type impurity in the second lightly doped film DS2 are selected within the range of 1×10 17 atoms / cm 3 ~9×10 18 atoms / cm 3The range may be selected, but is not limited to these.

[0017] Each of the vertical semiconductor structures VSS may include a vertical channel region, and the vertical channel region may be formed of one selected from a first lightly doped film DS1 and a second lightly doped film DS2. 2A to 2D show an example of a structure in which the vertical channel region in each of the multiple vertical semiconductor structures VSS is made of the second lightly doped film DS2. In each of the multiple vertical semiconductor structures VSS, the second lightly doped film DS2 used in the vertical channel region faces the word line WL in a horizontal direction parallel to the main surface 102 of the substrate 102 (a direction along the XY plane). The plurality of sensing lines SL contact the first highly doped film HDS1 of each of the plurality of vertical semiconductor structures VSS.

[0018] In another exemplary embodiment, unlike the examples of FIGS. 2A to 2D, the vertical channel region in each of the multiple vertical semiconductor structures VSS is made of a first lightly doped film DS1. In this case, the word lines WL are arranged to face the first lightly doped film DS1 of the vertical semiconductor structure VSS, respectively. A gate dielectric layer 130 is interposed between each vertical channel region (second lightly doped layer DS2 in FIGS. 2A to 2D) of each of the vertical semiconductor structures VSS and the adjacent word line WL. In an exemplary embodiment, the gate dielectric 130 is made of a paraelectric material. For example, the gate dielectric 130 may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In another exemplary embodiment, the gate dielectric 130 is made of a high dielectric material. High dielectric constant materials have a dielectric constant of about 10-25. For example, the high dielectric material may be, but is not limited to, hafnium oxide, aluminum oxide, zirconium oxide, or combinations thereof. In yet another exemplary embodiment, the gate dielectric 130 may be comprised of a combination of paraelectric and high-k materials.

[0019] The semiconductor memory device 100 includes an insulating pillar 124 that penetrates in the vertical direction (Z direction) through a plurality of vertical semiconductor structures VSS that are aligned to overlap each other in the vertical direction (Z direction). In each of the multiple vertical semiconductor structures VSS, the first highly doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, and the second highly doped film HDS2 have a hollow HH that accommodates the insulating pillar 124. Each of the vertical semiconductor structures VSS has a pipe shape surrounding the insulating pillar 124, and has a ring shape in a plan view (XY plane).

[0020] As illustrated in FIGS. 2B and 2D, the semiconductor memory device 100 includes a plurality of bit lines BL passing through a plurality of insulating layers 110B and 110C in a vertical direction (Z direction). The bit lines BL are disposed spaced apart from the word lines WL and the sensing lines SL in a second horizontal direction (Y direction). The plurality of bit lines BL are configured to be connected to a second highly doped layer HDS2 included in the vertical semiconductor structure VSS via conductive connection structures CNS, respectively. The conductive connection structure CNS contacts the second highly doped film HDS2 included in the vertical semiconductor structure VSS and surrounds the second highly doped film HDS2. The plurality of bit lines BL and the plurality of conductive connection structures CNS connected to the plurality of bit lines BL are each made of, but not limited to, W, Al, Mo, Ru, Al, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or combinations thereof.

[0021] The bit lines BL are extended in a vertical direction (Z direction) and face the vertical semiconductor structures VSS in a second horizontal direction (Y direction) with the word lines WL and the sensing lines SL interposed therebetween. In the semiconductor memory device 100, a plurality of memory cells MC arranged in a line along the vertical direction (Z direction) constitute one memory cell string. A plurality of memory cells MC included in one memory cell string share one bit line BL selected from a plurality of bit lines BL. The semiconductor memory element 100 includes a plurality of inter-cell insulating films 118 interposed between each of a plurality of memory cells MC arranged in a row along the vertical direction (Z direction), and a plurality of inter-cell local insulating films 120 interposed between an insulating pillar 124 and the inter-cell insulating film 118 to surround the insulating pillar 124. The inter-cell insulating film 118 and the inter-cell local insulating film 120 constitute an inter-cell insulating structure that separates two memory cells MC adjacent to each other in the vertical direction (Z direction).

[0022] A part of the buried insulating film 126 covers the memory cells MC, the insulating pillars 124, the uppermost inter-cell insulating film 118, and the inter-cell local insulating films 120 in the memory cell array section MCA. As illustrated in FIG. 2A, other portions of the buried insulating film 126 contact ends of the word lines WL and the sensing lines SL in the first horizontal direction (X direction) at first connection portions AR1 and second connection portions AR2. As illustrated in FIGS. 1 and 2B, the semiconductor memory device 100 includes a plurality of isolation insulating films 140. As illustrated in FIG. The isolation insulating layers 140 have a bar-shaped planar shape extending long along a first horizontal direction (X direction) in the memory cell array portion MCA. The isolation insulating films 140 are arranged one by one between the memory cell strings arranged in a row along the second horizontal direction (Y direction). The multiple isolation insulating films 140 penetrate the multiple insulating films (110A, 110B, 110C), the multiple inter-cell insulating films 118, and the buried insulating film 126 in the vertical direction (Z direction), and each contacts the multiple word lines WL and the multiple sensing lines SL included in the adjacent memory cell string on one side in the second horizontal direction (Y direction). The insulating pillars 124, the inter-cell insulating films 118, the inter-cell local insulating films 120, the buried insulating film 126, and the isolation insulating films 140 are each made of a silicon oxide film, but are not limited to such.

[0023] As illustrated in FIG. 2A, in the first connecting portion AR1 and the second connecting portion AR2, the word lines WL and the sensing lines SL have lengths along the first horizontal direction (X direction) that decrease as they move away from the substrate 102. As a result, a plurality of steps including the word lines WL and the sensing lines SL are formed in the first connecting portion AR1 and the second connecting portion AR2. In the first connecting portion AR1 and the second connecting portion AR2, the space defined by the steps is filled with the mold insulating film 119. The mold insulating film 119 is made of a silicon oxide film. A plurality of word line contacts WLC are arranged in the first connection portion AR1. Each of the word line contacts WLC is connected to one of the word lines WL at a position spaced apart from the vertical semiconductor structure VSS of the memory cell MC in the first horizontal direction (X direction).

[0024] A plurality of sensing line contacts SLC are disposed in the second connection portion AR2. Each of the plurality of sensing line contacts SLC is connected to one sensing line SL selected from the plurality of sensing lines SL at a position spaced apart from the vertical semiconductor structure VSS of the memory cell MC in a first horizontal direction (X direction). A plurality of word line contacts WLC and a plurality of sensing line contacts SLC each penetrate an insulating structure including the buried insulating layer 126 and the mold insulating layer 119 in a vertical direction (Z direction). The word line contacts WLC and the sensing line contacts SLC may each be made of, but are not limited to, W, Al, Mo, Ru, Al, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof.

[0025] A typical DRAM element has a structure in which one memory cell includes one transistor and one capacitor (1T-1C structure). In such a conventional DRAM device, as the integration density increases, the aspect ratio of the capacitor increases, which increases leakage current and poses an obstacle to scaling through a vertical stack structure. Memory devices based on feedback field-effect transistors (FBFETs) have a low operating voltage and a steep subthreshold swing (SS) of less than 60 mV / decade using a positive feedback loop, and unlike existing DRAM devices, they have the advantages of not requiring a refresh operation and of low power consumption. In addition, a semiconductor memory device based on an FBFET has an advantage in that it has a wide current sensing margin due to a high on-off current ratio and can ensure compatibility with existing complementary metal-oxide-semiconductor (CMOS) transistor manufacturing processes.

[0026] In the plurality of vertical semiconductor structures VSS included in the semiconductor memory device 100 according to the embodiment of the present invention, the first highly doped layer HDS1 is an n-type doped layer. + The first lightly doped film DS1 is a p-doped region doped with a p-type dopant, the second lightly doped film DS2 is an n-doped region doped with an n-type dopant, and the second heavily doped film HDS2 is a p-doped region doped with a p-type dopant. + It consists of a doped region. The n-type dopant may be selected from P (phosphorus), As (arsenic), and Sb (antimony). The p-type dopant may be selected from B (boron) and Ga (gallium).

[0027] In the exemplary embodiment, in each of the multiple vertical semiconductor structures VSS, the second lightly doped film DS2 consisting of an n-doped region is used as a vertical channel region. In this case, the word line WL is arranged to face horizontally the second lightly doped film DS2 consisting of an n-doped region across the gate dielectric film 130, and the memory cell MC does not include a capacitor but constitutes a p-FBFET-based DRAM cell consisting of one transistor. In another exemplary embodiment, in each of the multiple vertical semiconductor structures VSS, the first lightly doped film DS1 consisting of a p-doped region is used for the vertical channel region. In this case, the word line WL is arranged to face the first lightly doped film DS1 consisting of a p-doped region in the horizontal direction across the gate dielectric film 130, and the memory cell MC does not include a capacitor but constitutes an n-FBFET-based DRAM cell consisting of one transistor.

[0028] As described above, the semiconductor memory device 100 according to the embodiment of the present invention is implemented as a p-FBFET-based DRAM cell or an n-FBFET-based DRAM cell, ensuring compatibility with existing CMOS transistor manufacturing processes. In addition, by utilizing a memory cell based on an FBFET that does not require a capacitor as a DRAM cell having one transistor, a structure that is advantageous for high integration is provided. In addition, in the semiconductor memory device 100 according to an embodiment of the present invention, each of the memory cells MC has a structure including one transistor and no capacitor, which allows miniaturization and provides a high-density, compact three-dimensional array structure. In addition, in the semiconductor memory device 100 according to the embodiment of the present invention, a plurality of memory cells MC overlapping each other in the vertical direction (Z direction) include a three-dimensional stacked memory cell array sharing one bit line BL. Therefore, it overcomes the problem of bit line density limitations in semiconductor memory devices having existing two-dimensional structures, provides a structure that is advantageous for high integration of semiconductor memory devices, and provides excellent competitiveness in various aspects including performance, power, chip size, and cost.

[0029] 3A to 3D are diagrams for explaining the schematic configuration of a semiconductor memory device 200 according to another embodiment of the present invention, in which FIG. 3A is a cross-sectional view of a portion corresponding to the cross-section cut along line X1-X1' in FIG. 1, FIG. 3B is a cross-sectional view of a portion corresponding to the cross-section cut along line Y1-Y1' in FIG. 1, FIG. 3C is an enlarged cross-sectional view of a portion indicated by "EX3" in FIG. 3A, and FIG. 3D is an enlarged cross-sectional view of a portion indicated by "EX4" in FIG. 3B. The semiconductor memory device 200 has a planar layout substantially the same as the planar layout illustrated in FIG. 3A to 3D, the same reference symbols as those in FIG. 1 and FIG. 2A to FIG. 2D indicate the same members, and detailed descriptions relating thereto will be omitted here.

[0030] 3A to 3D, a semiconductor memory device 300 has substantially the same configuration as the semiconductor memory device 100 described with reference to FIG. 1 and FIGS. 2A to 2D. However, the semiconductor memory device 200 includes a plurality of word lines WL2 instead of the plurality of word lines WL illustrated in FIGS. 2A-2D, and includes a gate dielectric layer 230 instead of the gate dielectric layer 130 illustrated in FIGS. 2A-2D. The plurality of word lines WL2 and the gate dielectric layer 230 have substantially the same configuration as the plurality of word lines WL and the gate dielectric layer 130 described with reference to FIGS. 1 and 2A-2D. However, in the plurality of word lines WL2, the sidewalls facing the second lightly doped layer DS2 included in the vertical semiconductor structure VSS, the bottom surfaces facing the insulating layer 110B, and the top surfaces facing the insulating layer 110C are each covered with the gate dielectric layer 230. As illustrated in FIG. 3A, the word line contacts WLC at the first connection portion AR1 each penetrate the gate dielectric layer 230 and are connected to one of the word lines WL.

[0031] FIG. 4 is a cross-sectional view illustrating a schematic configuration of a semiconductor memory device 300 according to still another embodiment of the present invention. FIG. 4 illustrates a cross-sectional configuration of a portion corresponding to the cross section taken along line X1-X1' in FIG. 4, the same reference numerals as those in FIG. 1 and FIGS. 2A to 2D indicate the same members, and detailed description thereof will be omitted here. 4, a semiconductor memory device 300 has substantially the same configuration as that described for the semiconductor memory device 100 with reference to FIG. 1 and FIGS. 2A to 2D. However, the semiconductor memory device 300 includes a peripheral circuit structure PCS that overlaps the memory cell array portion MCA, the first connecting portion AR1, and the second connecting portion AR2 in the vertical direction (Z direction).

[0032] The peripheral circuit structure PCS includes a plurality of peripheral circuits formed on the peripheral circuit substrate 352 and a multilayer wiring structure MWS for interconnecting the plurality of peripheral circuits or connecting the plurality of peripheral circuits to conductive components in the memory cell array portion MCA, the first connection portion AR1, and the second connection portion AR2. In the peripheral circuit substrate 352, an active area PA is defined by an element isolation film 354. Further details relating to the peripheral circuit board 352 are generally the same as those described for board 102 with reference to Figures 2A and 2B. On the active area PA of the peripheral circuit substrate 352, a plurality of transistors TR3 are formed. Each of the plurality of transistors TR3 includes a peripheral gate PG and peripheral source / drain regions PSD formed in the active region PA on both sides of the peripheral gate PG. In an exemplary embodiment, the peripheral circuit structure PCS further includes unit elements such as resistors and capacitors. An interlayer insulating film 370 is formed on the plurality of transistors TR3. The interlayer insulating film 370 may include a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, or a combination thereof.

[0033] In the peripheral circuit structure PCS, the multilayer wiring structure MWS includes a plurality of peripheral circuit wiring layers (ML30, ML31, ML32) and a plurality of peripheral circuit contacts (MC30, MC31, MC32). Some of the multiple peripheral circuit wiring layers (ML30, ML31, ML32) are configured to be electrically connectable to the multiple transistors TR3. The plurality of peripheral circuit contacts (MC30, MC31, MC32) are configured to interconnect a selected portion of the plurality of peripheral circuit wiring layers (ML30, ML31, ML32). The multiple peripheral circuit wiring layers (ML30, ML31, ML32) and the multiple peripheral circuit contacts (MC30, MC31, MC32) are covered with an interlayer insulating film 370. The peripheral circuit wiring layers (ML30, ML31, ML32) and the peripheral circuit contacts (MC30, MC31, MC32) may each be made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the peripheral circuit wiring layers (ML30, ML31, ML32) and the peripheral circuit contacts (MC30, MC31, MC32) may each include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0034] In FIG. 4, multiple peripheral circuit wiring layers (ML30, ML31, ML32) are illustrated as having a three-layer wiring structure along the vertical direction (Z direction), but the embodiment of the present invention is not limited to the example shown in FIG. For example, the multiple peripheral circuit wiring layers (ML30, ML31, ML32) have a multi-layer wiring structure of two layers or four or more layers. In an exemplary embodiment, a plurality of word line contacts WLC arranged in the first connection portion AR1, a plurality of sensing line contacts SLC arranged in the second connection portion AR2, and a plurality of bit lines BL (see FIG. 2B) arranged in the memory cell array portion MCA are each configured to be connected to one peripheral circuit wiring layer selected from a plurality of peripheral circuit wiring layers (ML30, ML31, ML32) included in the peripheral circuit structure PCS.

[0035] 5A and 5B are diagrams illustrating a semiconductor memory device 400A according to another embodiment of the present invention. More specifically, FIG. 5A is a partially cutaway perspective view illustrating an exemplary structure of a memory cell MCP included in the semiconductor memory device 400A, and FIG. 5B is an equivalent circuit diagram of the memory cell MCP illustrated in FIG. 5A. FIG. 5A does not show the insulating films between the conductive components for insulating them. 5A and 5B, the same reference symbols as those in FIG. 1 and FIGS. 2A to 2D indicate the same members, and detailed descriptions relating thereto will be omitted here.

[0036] 5A and 5B, a semiconductor memory device 400A has substantially the same configuration as the semiconductor memory device 100 described with reference to FIG. 1 and FIGS. 2A to 2D. However, the semiconductor memory device 400A includes memory cells MCP instead of memory cells MC. The memory cell MCP has approximately the same configuration as the memory cell MC described with reference to FIGS. 2A to 2D. The memory cell MCP includes a vertical semiconductor structure VSS. The vertical semiconductor structure VSS is + A first highly doped film HDS1 consisting of a p-doped region, a first lightly doped film DS1 consisting of a p-doped region, a second lightly doped film DS2 consisting of an n-doped region, and + and a second highly doped film HDS2 consisting of a doped region.

[0037] In the semiconductor memory device 400A, the bit line BL4 passes through each of the word lines WL and the sensing lines WL in a vertical direction (Z direction). The bit line BL4 is spaced apart from the word line WL and the sensing line WL in the horizontal direction (along the XY plane). An insulating film is interposed between the bit line BL4 and the word line WL, and between the bit line BL4 and the sensing line WL. The memory cell MCP does not include a capacitor, but constitutes a 1T-DRAM cell of a vertical channel structure including one transistor having a p-FBFET-based structure. In the vertical semiconductor structure VSS of the memory cell MCP, the second lightly doped film DS2, which is an n-doped region, is used as a vertical channel region, and a gate dielectric film 130 is interposed between the word line WL and the second lightly doped film DS2. The sensing line SL is n +The conductive connection structure CNS is in contact with the first highly doped film HDS1 and connected to the bit line BL. + It contacts the second highly doped film HDS2 which is a doped region.

[0038] FIG. 5C is a graph for explaining the operating characteristics of the memory cell MCP illustrated in FIGS. 5A and 5B. In FIG. 5C, the horizontal axis represents the voltage V WL The vertical axis represents the current I SL Shows. Table 1 below illustrates operating conditions for the memory cell MCP illustrated in FIGS. 5A and 5B. [Table 1]

[0039] In Table 1, V BL is the voltage on the bit line BL, and V DD and -V DD are the voltages applied to the bit line BL, and V WL is the voltage at the word line WL, and V Wp is the voltage applied to the word line WL. In an exemplary embodiment, V DD is selected within the range of about 0.5V to 3V, and -V DD is selected within the range of about -3V to about -0.5V, and V Wp can be selected within the range of about -2 V to about -0.5 V, but is not limited thereto.

[0040] Referring to FIG. 5C and Table 1, for a write operation, V WL =V Wp When V is applied to the bit line BL, DD Apply a voltage of V to write "1" and WL =V Wp When the bit line BL is DDA voltage is applied to write "0". For a read operation, V BL =V DD When V WL Apply 0V as the input. V BL =V DD When V WL If 0V is applied as the potential, the memory cell MCP has bistable characteristics, so that a read operation becomes possible. That is, V BL =V DD When V WL = 0V is applied and the current I SL The state of the memory cell MCP can be read via the value of For the hold operation, no external voltage is applied. That is, V BL = 0V and V WL =0V. The memory cell MCP maintains a memory state for a certain period of time by charges stored inside the vertical channel region even when no voltage is applied from the outside.

[0041] In FIG. 5C, the voltage V on the bit line BL BL The current I in the sensing line SL due to the change in SL The change in is shown as line L1. In FIG. 5C, the arrows labeled R11, R12, and R13 indicate the current I SL This shows the path along which the signal is changed along line L1. In FIG. 5C, the current I at the position within the dotted circle marked A1 SL corresponds to the off-state current Ioff, and the current I SL corresponds to the on-current Ion, and is the current I SL is the voltage at the word line WL, V Wp , this corresponds to a current value at which a write "0" operation or a write "1" operation is executed.

[0042] 6A and 6B are diagrams illustrating a semiconductor memory device 400B according to another embodiment of the present invention. More specifically, FIG. 6A is a partially cutaway perspective view illustrating an exemplary structure of a memory cell MCN included in the semiconductor memory device 400B, and FIG. 6B is an equivalent circuit diagram of the memory cell MCN illustrated in FIG. 6A. FIG. 6A does not show the insulating films between the conductive components for insulating them. 6A and 6B, the same reference numerals as those in FIGS. 1, 2A to 2D, and 5A indicate the same members, and detailed descriptions relating thereto will be omitted here.

[0043] 6A and 6B, a semiconductor memory device 400B has substantially the same configuration as the semiconductor memory device 400A described with reference to FIG. 5A. However, the semiconductor memory device 400B includes a memory cell MCN. The memory cell MCN has approximately the same configuration as the memory cell MCP described with reference to FIG. 5A. The memory cell MCN includes a vertical semiconductor structure VSS. The vertical semiconductor structure VSS is + A first highly doped film HDS1 consisting of a p-doped region, a first lightly doped film DS1 consisting of a p-doped region, a second lightly doped film DS2 consisting of an n-doped region, and + and a second highly doped film HDS2 consisting of a doped region.

[0044] The memory cell MCN does not include a capacitor, but constitutes a 1T-DRAM cell of a vertical channel structure including one transistor having an n-FBFET-based structure. In the vertical semiconductor structure VSS of the memory cell MCN, the first lightly doped film DS1, which is a p-doped region, is used as a vertical channel region, and a gate dielectric film 130 is interposed between the word line WL and the first lightly doped film DS1. The sensing line SL is n +The conductive connection structure CNS is in contact with the first highly doped film HDS1 and connected to the bit line BL. + It contacts the second highly doped film HDS2 which is a doped region.

[0045] FIG. 6C is a graph for explaining the operating characteristics of the memory cell MCN illustrated in FIGS. 6A and 6B. In FIG. 6C, the horizontal axis represents the voltage V WL The vertical axis represents the current I SL Shows. Table 2 below shows examples of operating conditions for the memory cell MCN illustrated in FIGS. 6A and 6B. [Table 2]

[0046] In Table 2, V BL is the voltage on the bit line BL, and V DD and -V DD are the voltages applied to the bit line BL, and V WL is the voltage at the word line WL, and V Wn is the voltage applied to the word line WL. In an exemplary embodiment, V DD is selected within the range of about 0.5V to 3V, and -V DD is selected within the range of about -3V to about -0.5V, and V Wn can be selected within the range of about 0.5V to 2V, but is not limited thereto.

[0047] Referring to FIG. 6C and Table 2, for a write operation, V WL =V Wn When V is applied to the bit line BL, DD Apply a voltage of V to write "1" and WL =V Wn When the bit line BL is DDA voltage is applied to write "0". For a read operation, V BL =V DD When V WL Apply 0V as the input. V BL =V DD When V WL If 0V is applied as the MOS transistor, the memory cell MCN has bistable characteristics, so that a read operation becomes possible. That is, V BL =V DD When V WL = 0V is applied and the current I SL The state of the memory cell MCN is read via the value of For the hold operation, no external voltage is applied. That is, V BL = 0V and V WL =0V. The memory cell MCN maintains a memory state for a certain period of time by charges stored inside the vertical channel region even when no voltage is applied from the outside.

[0048] In FIG. 6C, the voltage V on the bit line BL BL The current I in the sensing line SL due to the change in SL The change in is shown as line L2. In FIG. 6C, the arrows labeled R21, R22, and R23 indicate the current I SL This shows the path along which the line L2 is changed. In FIG. 6C, the current I at the position within the dotted circle marked B1 SL corresponds to the off-state current Ioff, and the current I SL corresponds to the on-current Ion, and the current I at the position within the circular dotted line shown in B3 SL is the voltage at the word line WL, V Wn , this corresponds to a current value at which a write '0' operation or a write '1' operation is performed.

[0049] FIG. 7 is an exemplary circuit diagram of a semiconductor memory device 500 according to an embodiment of the invention. FIG. 7 illustrates a circuit configuration in which a plurality of memory cells MC1, each of which is made up of vertical 1T-DRAM cells, are arranged in a 3×3×3 array. In FIG. 7, a group of memory cells MC1 arranged in a row along the vertical direction (Z direction) constitutes one memory cell string MCS1. In the exemplary embodiment, each of the memory cells MC1 illustrated in FIG. 7 has the configuration as described for the memory cells MC with reference to FIGS. 2A to 2D. In another exemplary embodiment, the memory cells MC1 illustrated in FIG. 7 each have a configuration as described for the memory cell MCP with reference to FIG. 5A. In the semiconductor memory device 500 having the circuit configuration illustrated in FIG. 7, a plurality of memory cells MC1 included in one memory cell string MCS1 share one bit line BL. A plurality of memory cells MC1 included in one memory cell string MCS1 are connected to different word lines WL and sensing lines SL. A plurality of memory cells MC1 arranged on one plane (XY plane) at the same vertical level share one word line WL and one sensing line SL.

[0050] FIG. 8 is a timing diagram of one memory cell MC1 selected in the semiconductor memory device 500 having the circuit configuration illustrated in FIG. Referring to Figures 7 and 8, one bit line BL from among a plurality of bit lines BL is selected to determine a desired memory cell string MCS1, and one word line WL from among a plurality of word lines WL and one sensing line SL from among a plurality of sensing lines SL are selected to select one memory cell MC1. The signal of the memory cell MC1 selected in this manner is read through the sensing line SL. The required voltages (e.g., the voltages described with reference to Table 1) are applied to the selected bit line BL and the selected word line WL, respectively, to selectively perform write, read, and hold operations only on the selected memory cell MC1.

[0051] FIG. 9 is a schematic perspective view of a semiconductor memory element 500 arranged in a 3×3×3 array using the circuit configuration illustrated in FIG. 7, and FIG. 10 is a schematic side view of a semiconductor memory element 500 arranged in a 3×3×3 array using the circuit configuration illustrated in FIG. 7. 9 and 10, a plurality of word lines WL and a plurality of sensing lines SL are indicated by dotted lines. Although the semiconductor memory devices 500 arranged in a 3×3×3 array are illustrated in FIGS. 7, 9, and 10, the embodiments of the present invention are not limited thereto. The number of memory cells MC1 in the first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction) is not particularly limited, and a three-dimensional structure consisting of various numbers of memory cells MC1 may be formed as necessary.

[0052] FIG. 11 is an exemplary circuit diagram of a semiconductor memory device 600 according to another embodiment of the invention. FIG. 11 illustrates a circuit configuration in which a plurality of memory cells MC2 each consisting of a vertical 1T-DRAM cell are arranged in a 3×3×3 array. In FIG. 11, a group of memory cells MC2 arranged in a row along the vertical direction (Z direction) constitutes one memory cell string MCS2. In an exemplary embodiment, the plurality of memory cells MC2 illustrated in FIG. 11 each have a configuration as described for the memory cell MCN with reference to FIG. 6a. In the semiconductor memory device 600 having the circuit configuration illustrated in FIG. 11, a plurality of memory cells MC2 included in one memory cell string MCS2 share one bit line BL. A plurality of memory cells MC2 included in one memory cell string MCS2 are connected to different word lines WL and sensing lines SL. A plurality of memory cells MC2 arranged on one plane (XY plane) at the same vertical level share one word line WL and one sensing line SL.

[0053] FIG. 12 is a timing diagram of one memory cell MC2 selected in the semiconductor memory device 600 having the circuit configuration illustrated in FIG. Referring to Figures 11 and 12, one bit line BL from among a plurality of bit lines BL is selected to determine a desired memory cell string MCS2, and one word line WL from among a plurality of word lines WL and one sensing line SL from among a plurality of sensing lines SL are selected to select one memory cell MC2. The signal of the memory cell MC2 selected in this manner is read through the sensing line SL. The required voltages (e.g., the voltages described with reference to Table 2) are applied to the selected bit line BL and the selected word line WL, respectively, to selectively perform write, read, and hold operations only in the selected memory cell MC2. The semiconductor memory device 600 having the circuit configuration illustrated in FIG. 11 may be embodied as a 3×3×3 array arrangement similar to that described with reference to FIGS. 9 and 10, or as a three-dimensional structure that is variously modified and altered within the scope of embodiments of the present invention.

[0054] In the semiconductor memory devices (100, 200, 300, 400A, 400B, 500, 600) according to the embodiments of the present invention described with reference to FIGS. 1 to 12, the memory cells have a structure including one transistor and no capacitor. Therefore, according to the semiconductor memory devices (100, 200, 300, 400A, 400B, 500, 600) according to embodiments of the present invention, unlike conventional techniques in which charges are stored in a capacitor, it is possible to implement a DRAM cell in a single transistor by storing charges inside a vertical channel region of the transistor, which is advantageous in providing a miniaturized and compact three-dimensional array structure. In addition, the semiconductor memory devices 100, 200, 300, 400A, 400B, 500, and 600 according to the embodiments of the present invention include a three-dimensional stacked memory cell array in which a plurality of memory cells overlap each other in a vertical direction and share one bit line. Therefore, the present invention overcomes the problem of the density limit of the bit lines faced in the existing semiconductor memory device having a two-dimensional structure, and provides a structure advantageous for high integration of the semiconductor memory device.

[0055] In addition, the semiconductor memory devices (100, 200, 300, 400A, 400B, 500, 600) according to embodiments of the present invention have a relatively low operating voltage and a relatively steep subthreshold swing (SS) using a positive feedback loop, and unlike existing DRAM devices, have the advantages of not requiring a refresh operation and consuming relatively low power. In addition, a relatively high on-off current ratio provides a wide current sensing margin and a fast operating speed. Therefore, the semiconductor memory devices 100, 200, 300, 400A, 400B, 500, and 600 according to embodiments of the present invention can provide excellent competitiveness in various aspects including performance, power, chip size, and cost.

[0056] Next, a method for manufacturing a semiconductor memory device according to an embodiment of the present invention will be described in detail. 13A to 33B are views for explaining a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, and FIGS. 13A, 14A, 15A, 16, 17, 18A, 19A, 20, 21, 22A, 24A, 25A, 26A, 27A, 29, 30, 32A, and 33A are cross-sectional views according to a process sequence of a portion corresponding to the cross section cut along line X1-X1' in FIG. 1, and FIGS. 13B, Figures 14B, 15B, 18B, 19B, 22B, 23, 24B, 25B, 26B, 27B, 28, 31, 32B, and 33B are cross-sectional views in the process sequence corresponding to the cross section cut along line Y1-Y1' in Figure 1, Figure 18C is an enlarged cross-sectional view of the portion marked "EXA" in Figure 18A, and Figure 19C is an enlarged cross-sectional view of the portion marked "EXA" in Figure 19A. An exemplary method for manufacturing the semiconductor memory device 100 illustrated in FIGS. 1 and 2A to 2D will be described with reference to FIGS. 13A to 33B. 13A to 33B, the same reference symbols as those in FIG. 1 and FIGS. 2A to 2D indicate the same members, and detailed descriptions relating thereto will be omitted here.

[0057] 13A and 13B, an insulating film 110A, a plurality of first sacrificial patterns 112, an insulating film 110B, a plurality of second sacrificial patterns 114, and an insulating film 110C are sequentially formed on a substrate 102. The multiple first sacrificial patterns 112 are intended to secure a space for forming sensing lines SL (see Figures 2A to 2D), and the multiple second sacrificial patterns 114 are intended to secure a space for forming word lines WL (see Figures 2A to 2D). The first sacrificial patterns 112 and the second sacrificial patterns 114 are formed to have a line shape extending long along a first horizontal direction (X direction).

[0058] The insulating film 110B is formed on the insulating film 110A so as to cover the upper surfaces and side walls of each of the multiple first sacrificial patterns 112, and the insulating film 110C is formed on the insulating film 110B so as to cover the upper surfaces and side walls of each of the multiple second sacrificial patterns 114. The insulating films (110A, 110B, 110C) are made of silicon oxide films. The first sacrificial pattern 112 and the second sacrificial pattern 114 are each made of a material different from a silicon oxide film and have an etching selectivity different from that of a silicon oxide film. In an exemplary embodiment, the first sacrificial pattern 112 and the second sacrificial pattern 114 are made of different films selected from a silicon nitride film (SiN), a silicon nitride film, a SiON film, a SiCN film, a SiOCN film, and an aluminum oxide film (AlO). As used herein, the terms SiN, SiON, SiCN, SiOCN, and AlO refer to materials composed of the elements contained within each term and do not refer to chemical formulas indicating stoichiometric relationships. For example, the first sacrificial pattern 112 is made of a silicon nitride film, and the second sacrificial pattern 114 is made of a SiON film, but is not limited thereto.

[0059] 14A and 14B, a plurality of third sacrificial patterns 116 and an inter-cell insulating layer 118 are sequentially formed on the resultant structure of FIGS. 13A and 13B. The third sacrificial patterns 116 are formed to have a line shape extending long along the second horizontal direction (Y direction). Each of the third sacrificial patterns 116 is intended to secure a space for forming a conductive connection structure CNS (see FIGS. 2A to 2D). The third sacrificial patterns 116 are made of a material different from the respective constituent materials of the first sacrificial patterns 112 and the second sacrificial patterns 114, and are made of any one film selected from a silicon nitride film (SiN), a silicon nitride film, a SiON film, a SiCN film, a SiOCN film, and an aluminum oxide film (AlO). For example, when the first sacrificial patterns 112 are made of a silicon nitride film and the second sacrificial patterns 114 are made of a SiON film, the third sacrificial patterns 116 are made of an aluminum oxide film, but are not limited to this. The inter-cell insulating film 118 is formed on the insulating film 110C so as to cover the upper surface and sidewalls of each of the third sacrificial patterns 116. The inter-cell insulating film 118 is made of a silicon oxide film.

[0060] In Figures 14A and 14B, a laminated structure RP including multiple first sacrificial patterns 112, an insulating film 110B, multiple second sacrificial patterns 114, an insulating film 110C, multiple third sacrificial patterns 116, and an inter-cell insulating film 118, which are stacked in sequence on a substrate 102, is a structure necessary for forming multiple memory cells MC (see Figures 2A to 2D) arranged in one horizontal plane (XY plane) at the same vertical level on the substrate 102.

[0061] 15A and 15B, in the resultant product of FIGS. 14A and 14B, the laminated structure RP is repeatedly formed a required number of times along the vertical direction (Z direction). The number of stacked structures RP stacked along the vertical direction (Z direction) corresponds to the number of memory cells MC (see Figures 2A to 2D) included in one memory cell string extending long along the vertical direction (Z direction). Although Figures 15A and 15B illustrate an example in which two stacked structures RP are formed along the vertical direction (Z direction), the embodiment of the present invention is not limited thereto, and the stacked structures RP may be repeatedly formed in the number of memory cells MC required to constitute one memory cell string.

[0062] Referring to FIG. 16, at the first connection portion AR1 and the second connection portion AR2 of the resultant structure of FIGS. 15A and 15B, a portion of each of the multiple stacked structures RP is etched to form multiple steps, and a mold insulating film 119 is formed to cover the multiple steps. 17, in the memory cell array unit MCA, a plurality of channel holes H1 are formed penetrating a plurality of stacked structures RP in the vertical direction (Z direction). At the bottom of each of the plurality of channel holes H1, the insulating film 110A closest to the substrate 102 is exposed. An anisotropic dry etching process can be used to form the plurality of channel holes H1.

[0063] Referring to Figures 18A, 18B, and 18C, inside each of the multiple channel holes H1, a first highly doped film HDS1, a first lightly doped film DS1, a second lightly doped film DS2, a second highly doped film HDS2, and an inter-cell local insulating film 120 are repeatedly formed in sequence along the vertical direction (Z direction) from the bottom of each channel hole H1.

[0064] 19A, 19B, and 19C, in the result of FIGS. 18A, 18B, and 18C, a hollow HH is formed that penetrates vertically (Z direction) through the stacked structure of the first highly doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, the second highly doped film HDS2, and the inter-cell local insulating film 120 inside each of the multiple channel holes H1, and the hollow HH is filled with an insulating pillar 124. As a result, the first highly doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, the second highly doped film HDS2, and the inter-cell local insulating film 120 remain in a ring shape surrounding the insulating pillar 124, and a plurality of vertical semiconductor structures VSS each including the first highly doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, and the second highly doped film HDS2 are obtained.

[0065] Referring to FIG. 20, a mask pattern MP1 having a plurality of holes MPH is formed on the resultant structure of FIGS. 19A, 19B, and 19C. After the mask pattern MP1 is formed, the upper surface of the inter-cell insulating film 118 and the upper surface of the mold insulating film 119 are exposed through the plurality of holes MPH at the first connecting portion AR1 and the second connecting portion AR2. In an exemplary embodiment, the mask pattern MP1 is made of polysilicon, but is not limited to such. Thereafter, the lower structure exposed through the plurality of holes MPH is etched using the mask pattern MP1 as an etching mask to form a plurality of contact holes H2. At the bottom of each of the contact holes H2, the insulating film 110A closest to the substrate 102 is exposed. An anisotropic dry etching process can be used to form the contact holes H2.

[0066] Referring to FIG. 21, in the resultant product of FIG. 20, a portion of each of the insulating films (110A, 110B, 110C), the inter-cell insulating films 118, and the mold insulating film 119 exposed through the contact holes H2 are selectively removed, and a portion of each of the contact holes H2 is expanded in the horizontal direction (direction along the XY plane) and vertical direction (Z direction) to form a plurality of expanded contact holes H2A. A wet etching process can be used to form the multiple extended contact holes H2A.

[0067] 22A and 22B, the mask pattern MP1 is removed from the resultant structure of FIG. 21 to expose the upper surfaces of the top inter-cell insulating film 118 and the mold insulating film 119, and then a buried insulating film 126 is formed to fill the multiple extended contact holes H2A and cover the upper surfaces of the top inter-cell insulating film 118 and the mold insulating film 119.

[0068] Referring to FIG. 23, in the resultant structure of FIGS. 22A and 22B, a portion of the memory cell array portion MCA is etched to form a plurality of slits SH having a bar-shaped planar shape extending long along a first horizontal direction (X direction). The insulating film 110A closest to the substrate 102 is exposed at the bottom of each of the slits SH, and a plurality of first sacrificial patterns 112, a plurality of second sacrificial patterns 114, and a plurality of third sacrificial patterns 116 are exposed at the inner sidewalls of each of the slits SH.

[0069] 24A and 24B, the second sacrificial patterns 114 are selectively removed through the slits SH to form word line spaces WLH. To selectively remove the plurality of second sacrificial patterns 114, a wet etching process may be utilized. The first lightly doped layer DS1 is exposed in the plurality of word line spaces WLH.

[0070] 25A and 25B, a gate dielectric layer 130 is formed to cover the surface of the first lightly doped layer DS1 exposed in the word line spaces WLH. In an exemplary embodiment, a selective atomic layer deposition (ALD) process is performed to form the gate dielectric film 130 . In another exemplary embodiment, instead of the gate dielectric film 130, a gate dielectric film 230 is formed as illustrated in FIGS. 3A to 3D. To form the gate dielectric layer 230, an ALD process is used to form the gate dielectric layer 230 conformally covering the exposed surfaces of the resultant structure of FIGS. 24A and 24B, and then the remaining portions of the gate dielectric layer 230 except for the portions within the word line spaces WLH are removed.

[0071] 26A and 26B, a plurality of first sacrificial patterns 112 are selectively removed through a plurality of slits SH to form a plurality of sensing line spaces SLH. To selectively remove the plurality of first sacrificial patterns 112, a wet etching process may be utilized. The first highly doped layer HDS1 is exposed in the plurality of sensing line spaces SLH.

[0072] 27A and 27B, the result of FIGS. 26A and 26B forms a plurality of word lines WL filling a plurality of word line spaces WLH and a plurality of sensing lines SL filling a plurality of sensing line spaces SLH. In order to form a plurality of word lines WL and a plurality of sensing lines SL, in the resultant structure of Figures 26A and 26B, an ALD process or a CVD (chemical vapor deposition) process is used to form a conductive layer that fills the plurality of word line spaces WLH and the plurality of sensing line spaces SLH through the plurality of slits SH, and then unnecessary portions of the conductive layer except for portions inside each of the plurality of word line spaces WLH and the plurality of sensing line spaces SLH are removed. The conductive layer may be comprised of, but is not limited to, W, Al, Mo, Ru, Al, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or combinations thereof.

[0073] Referring to FIG. 28, a plurality of isolation insulating layers 140 are formed to fill the plurality of slits SH in the resultant structure of FIGS. 27A and 27B. To form the multiple isolation insulating films 140, a silicon oxide film having a thickness sufficient to fill the multiple slits SH is formed in the resultant structure of Figures 27A and 27B, and then a portion of the silicon oxide film is removed to expose the upper surface of the buried insulating film 126.

[0074] Referring to FIG. 29, a plurality of word line contact holes WLCH are formed in the first connection portion AR1, penetrating an insulating structure including the buried insulating film 126 and the mold insulating film 119 in a vertical direction (Z direction), and a plurality of sensing line contact holes SLCH are formed in the second connection portion AR2, penetrating an insulating structure including the buried insulating film 126 and the mold insulating film 119 in a vertical direction (Z direction). At the first connection portion AR1, the plurality of word lines WL and the buried insulating film 126 are exposed through the plurality of word line contact holes WLCH, and at the second connection portion AR2, the plurality of sensing lines SL and the buried insulating film 126 are exposed through the plurality of sensing line contact holes SLCH.

[0075] Referring to FIG. 30, a plurality of word line contacts WLC are formed in a plurality of word line contact holes WLCH in the first connection part AR1, and a plurality of sensing line contacts SLC are formed in a plurality of sensing line contact holes SLCH in the second connection part AR2.

[0076] Referring to FIG. 31, in the memory cell array section MCA, a plurality of bit line holes BLH are formed at a position horizontally spaced apart from a plurality of vertical semiconductor structures VSS across a plurality of word lines WL and a plurality of sensing lines SL, penetrating a plurality of insulating films (110A, 110B, 110C), a plurality of third sacrificial patterns 116, a plurality of inter-cell insulating films 118, and a buried insulating film 126 in a vertical direction (Z direction). At the bottom of each of the plurality of bit line holes BLH, the insulating film 110A closest to the substrate 102 is exposed. To form the plurality of bit line holes BLH, an anisotropic dry etching process may be used.

[0077] 32A and 32B, in the resultant structure of FIG. 31, the third sacrificial patterns 116 are selectively removed through the bit line holes BLH to form a plurality of connection spaces CNH. The second highly doped film HDS2 is exposed in each of the plurality of connection spaces CNH.

[0078] 33A and 33B, in the resultant structure of FIGS. 32A and 32B, a plurality of connection spaces CNH and a plurality of bit line holes BLH are filled with a conductive material to form a plurality of conductive connection structures CNS and a plurality of bit lines BL.

[0079] An exemplary manufacturing method for the semiconductor memory device 100 described with reference to FIGS. 1 and 2A to 2D has been described above with reference to FIGS. 13A to 33B. However, based on what has been described with reference to FIGS. 13A to 33B, a person skilled in the art will understand that various modifications and changes can be made within the scope of the embodiments of the present invention, and that semiconductor memory devices having various structures that are modified and changed in various ways within the scope of the embodiments of the present invention can be manufactured.

[0080] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0081] 100 Semiconductor memory element 102 Substrate 110A, 110B, 110C Insulating film 112 First Sacrifice Pattern 118 Inter-cell insulating film 119 Mold insulating film 120 Inter-cell local insulating film 124 Insulating pillar 126 Buried insulating film 130 Gate dielectric film 140 Inter-string isolation insulating film AR1 1st connection part AR2 2nd connection part BL Bit Line CNS conductive connection structure DS1 First low concentration doping film DS2 Second low concentration doping film HDS1 First highly doped film HDS2 Second highly doped film MC memory cell MCA Memory Cell Array SL Sensing Line SLC Sensing Line Contact VSS Vertical Semiconductor Structure WL Wordline. WLC Word Line Contact

Claims

1. A word line extending in a horizontal direction; a sensing line extending in the horizontal direction and vertically overlapping the word line at a position spaced apart from the word line; a vertical semiconductor structure having a vertical channel region that passes through the word lines and the sensing lines in the vertical direction and faces the word lines in the horizontal direction; a gate dielectric layer interposed between the vertical channel region and the word line; the vertical semiconductor structure includes a first highly doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second highly doped film of the second conductivity type, which are sequentially stacked along the vertical direction; the vertical channel region is formed of one of the first lightly doped film and the second lightly doped film; The semiconductor memory device, wherein the sensing line contacts the first highly doped layer of the vertical semiconductor structure.

2. an insulating pillar extending through the vertical semiconductor structure in the vertical direction and spaced apart from each of the word lines and the sensing lines in the horizontal direction; 2. The semiconductor memory device of claim 1, wherein the first highly doped film, the first lightly doped film, the second lightly doped film, and the second highly doped film each have a hollow that accommodates the insulating pillar.

3. 2. The semiconductor memory device of claim 1, further comprising a bit line spaced apart from each of the word lines and the sensing lines in the horizontal direction and configured to be connected to the second highly doped layer.

4. 4. The semiconductor memory device of claim 3, wherein the bit lines extend long in the vertical direction and face the vertical semiconductor structures in the horizontal direction across the word lines and the sensing lines.

5. In the vertical semiconductor structure, The first highly doped film is n ＋ a doping region; the first lightly doped film is a p-doped region; the second lightly doped film is an n-doped region; The second highly doped film is p ＋ a doping region; the vertical channel region is made of the n-doped region, 2. The semiconductor memory device of claim 1, wherein the word line faces the n-doped region in the horizontal direction with the gate dielectric layer interposed therebetween.

6. In the vertical semiconductor structure, The first highly doped film is n ＋ a doping region; the first lightly doped film is a p-doped region; the second lightly doped film is an n-doped region; The second highly doped film is p ＋ a doping region; the vertical channel region is made of the p-doped region; 2. The semiconductor memory device of claim 1, wherein the word line faces the p-doped region in the horizontal direction with the gate dielectric layer interposed therebetween.

7. a conductive connection structure in contact with and surrounding the second highly doped film; a bit line connected to the second highly doped layer through the conductive connection structure, 2. The semiconductor memory device of claim 1, wherein the bit lines extend in the vertical direction at positions spaced apart from the word lines and the sensing lines in the horizontal direction.

8. a conductive connection structure in contact with and surrounding the second highly doped film; a bit line connected to the second highly doped layer through the conductive connection structure, 2. The semiconductor memory device of claim 1, wherein the bit lines pass through the word lines and the sensing lines in the vertical direction and are spaced apart from the word lines and the sensing lines.

9. A memory cell string including a plurality of memory cells arranged in a row along a vertical direction; Each of the plurality of memory cells A word line extending in a horizontal direction; a sensing line extending in the horizontal direction and vertically overlapping the word line at a position spaced apart from the word line; a vertical semiconductor structure having a vertical channel region that passes through the word lines and the sensing lines in the vertical direction and faces the word lines in the horizontal direction; a gate dielectric layer interposed between the vertical channel region and the word line; In each of the plurality of memory cells, the vertical semiconductor structure includes a first highly doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second highly doped film of the second conductivity type, which are sequentially stacked along the vertical direction, the vertical channel region of each of the plurality of memory cells is formed of one of the first lightly doped film and the second lightly doped film; The semiconductor memory device, wherein the sensing line of each of the plurality of memory cells contacts the first highly doped layer of the vertical semiconductor structure.

10. a bit line extending in the vertical direction at a position spaced apart from the word line and the sensing line in the horizontal direction and facing the vertical semiconductor structure of each of the plurality of memory cells in the horizontal direction across the word line and the sensing line; The semiconductor memory device of claim 9 , wherein the memory cells share the bit line.

11. 10. The semiconductor memory device of claim 9, wherein each of the plurality of memory cells includes one transistor and does not include a capacitor.

12. an insulating pillar extending vertically through the vertical semiconductor structure of each of the plurality of memory cells; 10. The semiconductor memory device of claim 9, wherein in each of the plurality of memory cells, the first highly doped film, the first lightly doped film, the second lightly doped film, and the second highly doped film each have a hollow that accommodates the insulating pillar.

13. The memory cell array further includes a plurality of inter-cell insulating structures interposed between the plurality of memory cells, The vertical semiconductor structures of each of the plurality of memory cells are arranged in a straight line extending in the vertical direction, 10. The semiconductor memory device of claim 9, wherein the vertical semiconductor structure of a first memory cell selected from the plurality of memory cells and the vertical semiconductor structure of a second memory cell adjacent to the first memory cell selected from the plurality of memory cells are spaced apart in the vertical direction by an inter-cell insulation structure selected from a plurality of inter-cell insulation structures.

14. The horizontal direction includes a first horizontal direction and a second horizontal direction that are perpendicular to each other, a word line contact connected to the word line at a position spaced apart from the vertical semiconductor structure of each of the plurality of memory cells in the first horizontal direction; a sensing line contact spaced apart from the vertical semiconductor structure of each of the plurality of memory cells in the first horizontal direction and spaced apart from the word line contact across the vertical semiconductor structure in the first horizontal direction; 10. The semiconductor memory device of claim 9, further comprising: a bit line extending in the vertical direction at a position spaced apart from the word line and the sensing line in the second horizontal direction.

15. In the vertical semiconductor structure of each of the plurality of memory cells, The first highly doped film is n ＋ a doping region; the first lightly doped film is a p-doped region; the second lightly doped film is an n-doped region; The second highly doped film is p ＋ a doping region; the vertical channel region is made of the n-doped region, 10. The semiconductor memory device of claim 9, wherein the word line faces the n-doped region in the horizontal direction with the gate dielectric layer interposed therebetween.

16. In the vertical semiconductor structure of each of the plurality of memory cells, The first highly doped film is n ＋ a doping region; the first lightly doped film is a p-doped region; the second lightly doped film is an n-doped region; The second highly doped film is p ＋ a doping region; the vertical channel region is made of the p-doped region; 10. The semiconductor memory device of claim 9, wherein the word line faces the p-doped region in the horizontal direction with the gate dielectric layer interposed therebetween.

17. a memory cell array portion including a plurality of memory cells three-dimensionally arranged in a repeated manner along a first horizontal direction and a second horizontal direction perpendicular to each other and a vertical direction perpendicular to each of the first horizontal direction and the second horizontal direction on a substrate; The memory cell array unit includes: a plurality of sensing lines and a plurality of word lines alternately arranged along the vertical direction and spaced apart from each other in the vertical direction; a plurality of insulating films interposed between the plurality of sensing lines and the plurality of word lines, one each; a stack structure including a plurality of vertical semiconductor structures that penetrate the plurality of sensing lines, the plurality of word lines, and the plurality of insulating films in the vertical direction, each having a vertical channel region, and overlapping each other in the vertical direction; an insulating pillar extending vertically through the plurality of vertical semiconductor structures; a plurality of gate dielectric layers interposed between the vertical channel regions of each of the plurality of vertical semiconductor structures and the plurality of word lines; a plurality of bit lines passing through the insulating films in the vertical direction; Among the plurality of memory cells, memory cells arranged in a row along the vertical direction share one bit line selected from the plurality of bit lines; Each of the vertical semiconductor structures includes a first highly doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second highly doped film of the second conductivity type, which are sequentially stacked along the vertical direction, 20. The semiconductor memory device, wherein the vertical channel region of each of the plurality of vertical semiconductor structures is one selected from the first lightly doped film and the second lightly doped film.

18. the first highly doped film of each of the plurality of vertical semiconductor structures is in contact with a selected one of the plurality of sensing lines; 20. The semiconductor memory device of claim 17, wherein the second highly doped layer of each of the plurality of vertical semiconductor structures contacts a selected one of the plurality of bit lines.

19. a first connection portion and a second connection portion disposed on the substrate and spaced apart from each other in the first horizontal direction with the memory cell array portion therebetween; a plurality of word line contacts each connected to the plurality of word lines in the first connection portion and extending in the vertical direction; 18. The semiconductor memory device of claim 17, further comprising: a plurality of sensing line contacts, each of which is connected to one of the plurality of sensing lines at the second connection portion and extends long in the vertical direction.

20. 20. The semiconductor memory device of claim 17, wherein each of the plurality of memory cells includes one transistor and does not include a capacitor.

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