Semiconductor device

Abstract

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device 10 has a first substrate 20, a second substrate 30 provided away from the first substrate 20, and a first semiconductor element 50 mounted on the top surface 21A of the first substrate 20 and the top surface 30A of the second substrate 30 so as to span the first substrate 20 and the second substrate 30. The semiconductor device 10 has a second semiconductor element 60 mounted on the top surface 30A of the second substrate 30 and a third semiconductor element 70 mounted on the bottom surface 30B of the second substrate 30. The third semiconductor element 70 is provided so that it overlaps the second semiconductor element 60 in plan view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices in which a plurality of semiconductor elements are mounted on a substrate are known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-107681 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional semiconductor devices, a plurality of semiconductor elements are arranged side by side on a substrate, which causes a problem that the planar size of the semiconductor device becomes large. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: a first substrate; a second substrate disposed apart from the first substrate; a first semiconductor element mounted on an upper surface of the first substrate and an upper surface of the second substrate so as to straddle the first substrate and the second substrate; and a second semiconductor element mounted on the upper surface of the second substrate. and a third semiconductor element mounted on the lower surface of the second substrate, the third semiconductor element being provided so as to overlap the second semiconductor element in a plan view. Effect of the Invention

[0006] According to one aspect of the present invention, an effect of miniaturization is achieved. [Brief description of the drawings]

[0007] [Figure 1]FIG. 1 is a schematic cross-sectional view (cross-sectional view taken along line 1-1 in FIG. 2) showing the semiconductor device of the first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing the semiconductor device of the first embodiment. [Diagram 3] FIG. 3 is a schematic plan view showing the semiconductor device of the first embodiment. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of the first embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of the first embodiment. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment will be described below with reference to the attached drawings. In addition, for convenience, the attached drawings may show characteristic parts in an enlarged manner to make the characteristics easier to understand, and the dimensional ratios of each component may differ from one drawing to another. In addition, in the cross-sectional views, in order to make the cross-sectional structure of each member easier to understand, the hatching of some members is shown instead of a matte pattern, and the hatching of some members is omitted. In each drawing, the X-axis, Y-axis, and Z-axis, which are mutually perpendicular, are illustrated. In the following description, for convenience, the direction extending along the X-axis is referred to as the X-axis direction, the direction extending along the Y-axis is referred to as the Y-axis direction, and the direction extending along the Z-axis is referred to as the Z-axis direction. In this specification, "planar view" refers to viewing an object from the Z-axis direction unless otherwise specified. In this specification, "planar shape" refers to the shape of an object viewed from the Z-axis direction unless otherwise specified. In this specification, "same" includes cases where the objects are exactly the same, as well as cases where there is some difference between the objects to be compared due to the influence of dimensional tolerances, etc.

[0009] (First embodiment) The first embodiment will be described below with reference to FIGS. (Overall Configuration of Semiconductor Device 10) 1, the semiconductor device 10 has a first substrate 20, a second substrate 30, a first semiconductor element 50, a second semiconductor element 60, and a third semiconductor element 70. In this specification, the side of the first semiconductor element 50 and the second semiconductor element 60 in the Z-axis direction is defined as the upper side, and the side of the third semiconductor element 70 in the Z-axis direction is defined as the lower side. However, the semiconductor device 10 may be manufactured and used upside down, or in any position.

[0010] The first semiconductor element 50 is mounted on the upper surface 21A of the first substrate 20 and the upper surface 30A of the second substrate 30 so as to straddle the first substrate 20 and the second substrate 30. The second semiconductor element 60 is mounted on the upper surface 30A of the second substrate 30. The third semiconductor element 70 is mounted on the lower surface 30B of the second substrate 30 opposite to the upper surface 30A on which the first semiconductor element 50 and the second semiconductor element 60 are mounted.

[0011] The semiconductor device 10 is, for example, an optical semiconductor device used for optical communication etc. The semiconductor device 10 of the present embodiment is an optical semiconductor device in which an optical IC (Photonic Integrated Circuit: PIC) and an electrical IC (EIC: Electrical Integrated Circuit) are co-mounted.

[0012] Here, the second semiconductor element 60 is, for example, an optical IC having an optical circuit. As the optical IC, for example, a silicon photonics chip can be used. The optical circuit of the second semiconductor element 60 has, for example, a photodetector and an optical modulator. The third semiconductor element 70 is, for example, an electrical IC having an electrical circuit. The electrical circuit of the third semiconductor element 70 has, for example, a drive circuit for driving an optical modulator of the optical circuit. That is, the third semiconductor element 70 of this example is an electrical IC for driving an optical circuit. Note that the electrical circuit of the third semiconductor element 70 may have an amplifier circuit for amplifying a signal from the optical detector. The first semiconductor element 50 is, for example, an electrical IC having an electrical circuit. The first semiconductor element 50 is, for example, an LSI (Large Scale Integration) chip incorporating a digital signal processor (DSP: Digital Signal Processor) that processes a signal from the optical detector, an amplifier, and the like. That is, the first semiconductor element 50 is an LSI having an electrical circuit for signal processing. The first semiconductor element 50 generates a larger amount of heat than the second semiconductor element 60, for example. The first semiconductor element 50 generates a larger amount of heat than the third semiconductor element 70, for example.

[0013] (Configuration of the first substrate 20) The first substrate 20 has a substrate body 21 having an upper surface 21A and a lower surface 21B opposite to the upper surface 21A, and a wiring layer 22 provided on the upper surface 21A of the substrate body 21. A first semiconductor element 50 is mounted on the first substrate 20. The first substrate 20 may be mounted with optical functional elements and electronic components other than the first semiconductor element 50, the second semiconductor element 60, and the third semiconductor element 70. Examples of optical functional elements include light-emitting elements, light-receiving elements, optical amplifiers, optical attenuators, and the like. Examples of electronic components include chip components such as chip capacitors, chip resistors, and chip inductors, and crystal oscillators, and the like. The first substrate 20 is, for example, a wiring substrate having wiring (such as the wiring layer 22) electrically connected to the electronic components mounted on the first substrate 20.

[0014] The substrate body 21 may be a wiring structure in which insulating resin layers and wiring layers are alternately laminated. The wiring structure may have, for example, a core substrate, or may not have a core substrate. The insulating resin layer may be made of, for example, a thermosetting insulating resin. The thermosetting insulating resin may be made of, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin. The insulating resin layer may be made of, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin. The insulating resin layer may contain, for example, a filler such as silica (SiO2) or alumina (Al2O3).

[0015] The thickness of the substrate body 21 is formed to be thicker than, for example, the second substrate 30. The thickness of the substrate body 21 is formed to be thicker than, for example, the combined thickness of the second substrate 30 and the third semiconductor element 70. The thickness of the substrate body 21 can be, for example, about 400 μm to 1500 μm.

[0016] The wiring layer 22 is provided on the upper surface 21A of the substrate body 21, which is the mounting surface on which the first semiconductor element 50 is mounted. The wiring layer 22 is electrically connected to a wiring layer (not shown) formed on the lower surface 21B of the substrate body 21, for example, via a wiring layer or a through electrode in the substrate body 21. The wiring layer 22 has a first connection pad P1 electrically connected to the first semiconductor element 50. The thickness of the wiring layer 22 can be, for example, about 10 μm to 20 μm. The material of the wiring layer 22 can be, for example, copper (Cu) or a copper alloy.

[0017] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or only the top surface) of the first connection pad P1. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating a Ni layer and a Pd layer in this order), and a Pd layer / Au layer (a metal layer formed by laminating a Pd layer and an Au layer in this order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer) or a metal layer formed by electrolytic plating (electrolytic plated metal layer). The surface treatment layer may be an OSP film formed by performing an oxidation prevention treatment such as an OSP (Organic Solderability Preservative) treatment on the surface of the first connection pad P1. The OSP film may be an organic coating such as an azole compound or an imidazole compound.

[0018] The first substrate 20 has a through hole 23 that penetrates the substrate body 21 in the thickness direction (here, the Z-axis direction). The through hole 23 is formed so as to penetrate from the upper surface 21A to the lower surface 21B of the substrate body 21. The through hole 23 is formed to a size capable of accommodating the second substrate 30 and the third semiconductor element 70 mounted on the lower surface 30B of the second substrate 30.

[0019] 2 and 3, the planar shape of the through hole 23 is, for example, similar to the planar shape of the second substrate 30, here a rectangular shape. The through hole 23 has a size larger than the second substrate 30 in a planar view. The planar size of the through hole 23 is formed to a size capable of accommodating the entire second substrate 30. The through hole 23 has a size larger than the second semiconductor element 60 in a planar view, for example.

[0020] The through hole 23 is formed, for example, in a notch shape. The through hole 23 is formed so as to be recessed from the end face of the substrate body 21 in the X-axis direction toward the inside of the substrate body 21. The through hole 23 is formed so as to open in the X-axis direction. The through hole 23 is provided, for example, only in the middle part of the substrate body 21 in the Y-axis direction.

[0021] (Configuration of second substrate 30) The second substrate 30 is a substrate different from the first substrate 20. The second substrate 30 is provided away from the first substrate 20. The second substrate 30 is provided so as not to overlap with the first substrate 20 in a plan view. The second substrate 30 is accommodated in the internal space of the through hole 23. The second substrate 30 is provided in the internal space of the through hole 23, for example, away from the entire inner surface of the through hole 23. That is, a gap is provided between the side surface of the second substrate 30 and the inner wall surface of the through hole 23.

[0022] 1, the second substrate 30 has an upper surface 30A and a lower surface 30B provided on the opposite side of the upper surface 30A. The upper surface 30A is provided, for example, on the same plane as the upper surface 21A of the first substrate 20. The lower surface 30B is provided, for example, above the lower surface 21B of the first substrate 20.

[0023] The second substrate 30 has a second connection pad P2 electrically connected to the first semiconductor element 50, a third connection pad P3 electrically connected to the second semiconductor element 60, and a fourth connection pad P4 electrically connected to the third semiconductor element 70.

[0024] The second substrate 30 is a multilayer wiring substrate having a structure in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated. The second substrate 30 has a structure in which a wiring layer 31, an insulating layer 32, a wiring layer 33, an insulating layer 34, a wiring layer 35, an insulating layer 36, a wiring layer 37, an insulating layer 38, and a wiring layer 39 are laminated in this order. The second substrate 30 of this embodiment has a form of a so-called coreless substrate that does not include a supporting substrate, unlike a wiring substrate manufactured using a general build-up method, that is, a substrate in which a required number of build-up layers are sequentially formed and laminated on both sides or one side of a core substrate as a supporting substrate.

[0025] The wiring layers 31, 33, 35, 37, and 39 may be made of, for example, copper or a copper alloy. The wiring layers 31, 33, 35, 37, and 39 may have a thickness of, for example, about 10 μm to 20 μm. The lines and spaces (L / S) of the wiring layers 31, 33, 35, 37, and 39 may have a line and space (L / S) of, for example, about 10 μm / 10 μm to 20 μm / 20 μm. Here, the line in the line and space (L / S) represents the width of the wiring, and the space represents the distance between adjacent wirings. For example, when L / S is described as 20 μm / 20 μm, this represents that the wiring width is 20 μm and the distance between adjacent wirings is 20 μm.

[0026] The insulating layers 32, 34, 36, 38 may be made of insulating resin mainly composed of photosensitive resin such as phenolic resin or polyimide resin. The insulating layers 32, 34, 36, 38 may contain filler such as silica or alumina. The insulating layers 32, 34, 36, 38 may be made of insulating resin with reinforcement material such as glass, aramid, or LCP (Liquid Crystal Polymer) fiber woven or nonwoven fabric impregnated with thermosetting resin such as epoxy resin or polyimide resin. The insulating layers 32, 34, 36, 38 may have a thickness of about 20 μm to 45 μm.

[0027] The wiring layer 31 is formed on the outermost layer (here, the bottom layer) of the second substrate 30. The lower surface of the wiring layer 31 is exposed from the lower surface of the insulating layer 32, i.e., the lower surface 30B of the second substrate 30. The lower surface of the wiring layer 31 is formed, for example, flush with the lower surface of the insulating layer 32. The wiring layer 31 has a fourth connection pad P4 electrically connected to the third semiconductor element 70. That is, the fourth connection pad P4 is provided on the lower surface 30B of the second substrate 30.

[0028] If necessary, a surface treatment layer may be formed on the surface (here, the lower surface) of the fourth connection pad P4. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd layer / Au layer, or an OSP film.

[0029] The insulating layer 32 is formed on the outermost layer (here, the bottom layer) of the second substrate 30. The insulating layer 32 is formed so as to cover the upper and side surfaces of the wiring layer 31 and to expose the bottom surface of the wiring layer 31. The bottom surface of the insulating layer 32 is the bottom surface 30B of the second substrate 30.

[0030] The wiring layer 33 is laminated on the upper surface of the insulating layer 32. The wiring layer 33 is, for example, formed integrally with via wiring penetrating the insulating layer 32 in the thickness direction, and is electrically connected to the wiring layer 31 through the via wiring. The insulating layer 34 is laminated on the upper surface of the insulating layer 32 so as to cover the wiring layer 33. The wiring layer 35 is laminated on the upper surface of the insulating layer 34. The wiring layer 35 is, for example, formed integrally with via wiring penetrating the insulating layer 34 in the thickness direction, and is electrically connected to the wiring layer 33 through the via wiring. The insulating layer 36 is laminated on the upper surface of the insulating layer 34 so as to cover the wiring layer 35. The wiring layer 37 is laminated on the upper surface of the insulating layer 36. The wiring layer 37 is, for example, formed integrally with via wiring penetrating the insulating layer 36 in the thickness direction, and is electrically connected to the wiring layer 35 through the via wiring. The insulating layer 38 is laminated on the upper surface of the insulating layer 36 so as to cover the wiring layer 37. The insulating layer 38 is formed on the outermost layer (here, the uppermost layer) of the second substrate 30. The upper surface of the insulating layer 38 is the upper surface 30A of the second substrate 30. The upper surface of the insulating layer 38 is provided on the same plane as the upper surface 21A of the substrate body 21.

[0031] The wiring layer 39 is formed on the outermost layer (here, the uppermost layer) of the second substrate 30. The wiring layer 39 is laminated on the upper surface of the insulating layer 38, that is, on the upper surface 30A of the second substrate 30. The wiring layer 39 is formed integrally with, for example, via wiring penetrating the insulating layer 38 in the thickness direction, and is electrically connected to the wiring layer 37 through the via wiring. The wiring layer 39 has a second connection pad P2 electrically connected to the first semiconductor element 50 and a third connection pad P3 electrically connected to the second semiconductor element 60. That is, the second connection pad P2 and the third connection pad P3 are provided on the upper surface 30A of the second substrate 30. In other words, the second connection pad P2 and the third connection pad P3 are provided on the same plane.

[0032] If necessary, a surface treatment layer may be formed on the surfaces (top and side surfaces, or only top surfaces) of the second connection pads P2 and the third connection pads P3. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd layer / Au layer, and an OSP film.

[0033] (Configuration of First Semiconductor Element 50) The first semiconductor element 50 has, for example, a plurality of bumps 51 formed on the circuit formation surface (here, the lower surface) of the first semiconductor element 50. The first semiconductor element 50 is mounted on the upper surface 21A of the first substrate 20 and the upper surface 30A of the second substrate 30 so as to straddle the gap formed between the first substrate 20 and the second substrate 30. The first semiconductor element 50 is flip-chip mounted on the upper surface 21A of the first substrate 20 and is also flip-chip mounted on the upper surface 30A of the second substrate 30. The first semiconductor element 50 is electrically connected to the first connection pads P1 of the first substrate 20 and the second connection pads P2 of the second substrate 30 via the bumps 51. As a result, the first semiconductor element 50 is electrically connected to the wiring layer 22 of the first substrate 20 via the bumps 51 and is also electrically connected to the wiring layer 39 of the second substrate 30 via the bumps 51. The first substrate 20 and the second substrate 30 are connected to each other via such a first semiconductor element 50. In other words, the first semiconductor element 50 is mounted on the first substrate 20 and the second substrate 30 so as to connect the first substrate 20 and the second substrate 30 to each other.

[0034] For example, a gold bump or a solder bump can be used as the bump 51. For example, an alloy containing Pb, an alloy of Sn and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used as the material of the solder bump.

[0035] As shown in FIG. 2, the first semiconductor element 50 has a larger size than the second semiconductor element 60 in a plan view, for example. The first semiconductor element 50 has a larger size than the third semiconductor element 70 in a plan view, for example. The dimension of the first semiconductor element 50 along the Y-axis direction is larger than the dimension of the third semiconductor element 70 along the Y-axis direction, for example. The dimension of the first semiconductor element 50 along the Y-axis direction is larger than the dimension of the second semiconductor element 60 along the Y-axis direction, for example. The dimension of the first semiconductor element 50 along the Y-axis direction is larger than the dimension of the second substrate 30 along the Y-axis direction, for example. The dimension of the first semiconductor element 50 along the Y-axis direction is larger than the dimension of the through-hole 23 along the Y-axis direction, for example.

[0036] (Configuration of the second semiconductor element 60) 1, the second semiconductor element 60 has, for example, a plurality of bumps 61 formed on a circuit formation surface (here, the lower surface) of the second semiconductor element 60. The second semiconductor element 60 is mounted on the upper surface 30A of the second substrate 30. The second semiconductor element 60 is flip-chip mounted on the upper surface 30A of the second substrate 30. The second semiconductor element 60 is electrically connected to the third connection pads P3 of the second substrate 30 via the bumps 61. As a result, the second semiconductor element 60 is electrically connected to the wiring layer 39 of the second substrate 30 via the bumps 61.

[0037] For example, a gold bump or a solder bump can be used as the bump 61. For example, an alloy containing Pb, an alloy of Sn and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used as the material of the solder bump.

[0038] The second semiconductor element 60 is provided, for example, on the same plane as the first semiconductor element 50. The second semiconductor element 60 is provided adjacent to the first semiconductor element 50. The second semiconductor element 60 is provided adjacent to the first semiconductor element 50 in, for example, the X-axis direction. For example, the distance in the X-axis direction between the first semiconductor element 50 and the second semiconductor element 60 is smaller than the distance in the X-axis direction between the inner wall surface of the through-hole 23 and the side surface of the second substrate 30.

[0039] As shown in FIG. 2, the second semiconductor element 60 has a size larger than the third semiconductor element 70 in a plan view, for example. The size of the second semiconductor element 60 along the Y-axis direction is larger than the size of the third semiconductor element 70 along the Y-axis direction, for example. The size of the second semiconductor element 60 along the Y-axis direction is the same as the size of the second substrate 30 along the Y-axis direction. Each side surface of the second semiconductor element 60 in the Y-axis direction is formed, for example, flush with each side surface of the second substrate 30 in the Y-axis direction. The end portion of the second semiconductor element 60 in the X-axis direction (the end portion on the right side in the figure) protrudes toward the X-axis direction (to the right in the figure), for example, beyond the end face in the X-axis direction of the second substrate 30 (the end face on the right side in the figure). In other words, the end portion of the second semiconductor element 60 in the X-axis direction is provided so as not to overlap the second substrate 30 in a plan view. An optical transmission path such as an optical fiber (not shown) is optically connected to the end portion of the second semiconductor element 60 in the X-axis direction.

[0040] (Configuration of the third semiconductor element 70) As shown in FIG. 1, the third semiconductor element 70 has, for example, a plurality of bumps 71 formed on the circuit formation surface (here, the upper surface) of the third semiconductor element 70. The third semiconductor element 70 is mounted on the lower surface 30B of the second substrate 30. The third semiconductor element 70 is flip-chip mounted on the lower surface 30B of the second substrate 30. The third semiconductor element 70 is electrically connected to the fourth connection pads P4 of the second substrate 30 via the bumps 71. As a result, the third semiconductor element 70 is electrically connected to the wiring layer 31 of the second substrate 30 via the bumps 71. The third semiconductor element 70 is electrically connected to the first semiconductor element 50 via the wiring layers 31, 33, 35, 37, and 39. The third semiconductor element 70 is electrically connected to the second semiconductor element 60 via the wiring layers 31, 33, 35, 37, and 39.

[0041] For example, a gold bump or a solder bump can be used as the bump 71. For example, an alloy containing Pb, an alloy of Sn and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used as the material of the solder bump.

[0042] As shown in FIG. 2, the third semiconductor element 70 is provided so as to overlap the second semiconductor element 60 in a planar view. The third semiconductor element 70 is provided so as to partially overlap the second semiconductor element 60 in a planar view. The third semiconductor element 70 is provided so as to overlap the first semiconductor element 50 in a planar view, for example. The third semiconductor element 70 is provided so as to partially overlap the first semiconductor element 50 in a planar view, for example. The third semiconductor element 70 is provided so as to straddle the first semiconductor element 50 and the second semiconductor element 60 in a planar view. The third semiconductor element 70 is provided so as not to overlap the first substrate 20 in a planar view.

[0043] (Method of Manufacturing Semiconductor Device 10) Next, a description will be given of an example of a method for manufacturing the semiconductor device 10. For convenience of explanation, the parts that will ultimately become the components of the semiconductor device 10 will be described by using the reference numerals of the final components.

[0044] 4, first, a second substrate 30 is prepared in which a wiring layer 31, an insulating layer 32, a wiring layer 33, an insulating layer 34, a wiring layer 35, an insulating layer 36, a wiring layer 37, an insulating layer 38, and a wiring layer 39 are laminated in this order. The second substrate 30 can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0045] Next, the third semiconductor element 70 is mounted on the lower surface 30B of the second substrate 30. More specifically, the bumps 71 of the third semiconductor element 70 are flip-chip bonded onto the fourth connection pads P4 provided on the lower surface 30B of the second substrate 30.

[0046] 5, a second semiconductor element 60 is mounted on the upper surface 30A of the second substrate 30. More specifically, bumps 61 of the second semiconductor element 60 are flip-chip bonded onto third connection pads P3 provided on the upper surface 30A of the second substrate 30.

[0047] 6, a first substrate 20 having a through hole 23 is prepared. Next, a second substrate 30 having a second semiconductor element 60 and a third semiconductor element 70 mounted thereon is disposed in the internal space of the through hole 23 of the first substrate 20. At this time, the second substrate 30 is disposed in the through hole 23 such that, for example, an upper surface 30A of the second substrate 30 is provided on the same plane as an upper surface 21A of the first substrate 20.

[0048] Next, the first semiconductor element 50 is mounted on the upper surface 21A of the first substrate 20 and the upper surface 30A of the second substrate 30. More specifically, the bumps 51 of the first semiconductor element 50 are flip-chip bonded to the first connection pads P1 provided on the upper surface 21A of the first substrate 20 and the second connection pads P2 provided on the upper surface 30A of the second substrate 30.

[0049] Through the above manufacturing steps, the semiconductor device 10 shown in FIG. 1 can be manufactured. Next, the effects of this embodiment will be described. (1-1) The first semiconductor element 50 is mounted on the upper surface 21A of the first substrate 20 and the upper surface 30A of the second substrate 30 so as to straddle the first substrate 20 and the second substrate 30. The second semiconductor element 60 is mounted on the upper surface 30A of the second substrate 30, and the third semiconductor element 70 is mounted on the lower surface 30B of the second substrate 30. Furthermore, the third semiconductor element 70 is provided so as to overlap the second semiconductor element 60 in a plan view. According to this configuration, the third semiconductor element 70 can be mounted on the lower surface 30B of the second substrate 30 in a portion overlapping the second semiconductor element 60 in a plan view. As a result, the second semiconductor element 60 and the third semiconductor element 70 can be mounted on both the upper surface 30A and the lower surface 30B of the second substrate 30 in a state where they overlap each other in a plan view. Therefore, the planar size of the semiconductor device 10 can be reduced compared to a conventional semiconductor device in which three semiconductor elements are mounted side by side on one substrate.

[0050] (1-2) Incidentally, a structure in which three semiconductor elements are mounted on one substrate, for example, a structure in which two semiconductor elements are mounted on the upper surface of the substrate and one semiconductor element is mounted on the lower surface of the substrate, is also conceivable. However, in this structure, the thickness of one substrate places a restriction on the distance between the semiconductor element mounted on the upper surface of the substrate and the semiconductor element mounted on the lower surface of the substrate. In other words, if one substrate is formed thick, the distance between the semiconductor elements mounted on both the upper and lower surfaces of the substrate becomes long.

[0051] In contrast, in the semiconductor device 10 of the present embodiment, three semiconductor elements, that is, a first semiconductor element 50, a second semiconductor element 60, and a third semiconductor element 70, are mounted on the first substrate 20 and the second substrate 30 provided at a distance from the first substrate 20. In this configuration, the first substrate 20 and the second substrate 30 can be formed independently of each other. Therefore, even if the first substrate 20 is formed thick, the second substrate 30 can be formed thin, so that the distance between the second semiconductor element 60 mounted on the upper surface 30A of the second substrate 30 and the third semiconductor element 70 mounted on the lower surface 30B of the second substrate 30 can be suitably shortened. As a result, even if the first substrate 20 is formed thick, the wiring length between the second semiconductor element 60 and the third semiconductor element 70 can be shortened, so that the electrical characteristics can be suitably improved.

[0052] (1-3) Furthermore, since the first substrate 20 and the second substrate 30 can be formed independently of each other, it is possible to improve the design freedom of the semiconductor device 10, particularly the design freedom of the first substrate 20 and the second substrate 30, compared to a case in which three semiconductor elements are mounted on one substrate. For example, the thicknesses of the wiring layers and insulating layers of the first substrate 20 and the thicknesses of the wiring layers 31, 33, 35, 37, 39 and insulating layers 32, 34, 36, 38 of the second substrate 30 can be set to different thicknesses.

[0053] (1-4) The third semiconductor element 70 is provided so as to overlap the first semiconductor element 50 in a plan view. According to this configuration, the third semiconductor element 70 can be mounted on the lower surface 30B of the second substrate 30 so as to straddle the first semiconductor element 50 and the second semiconductor element 60 in a plan view. This allows the three semiconductor elements, the first semiconductor element 50, the second semiconductor element 60, and the third semiconductor element 70, to be mounted on the first substrate 20 and the second substrate 30 in a state in which they are close to each other. Therefore, the planar size of the semiconductor device 10 can be suitably reduced compared to a conventional semiconductor device in which three semiconductor elements are mounted side by side on one substrate.

[0054] (1-5) The second substrate 30 is provided in the internal space of the through hole 23 penetrating the first substrate 20 in the thickness direction. In this configuration, the second substrate 30 can be provided so as not to overlap the first substrate 20 in a plan view. This allows the third semiconductor element 70 mounted on the lower surface 30B of the second substrate 30 to be provided so as not to overlap the first substrate 20 in a plan view. This allows other components, such as a heat sink, to be mounted on the lower surface of the third semiconductor element 70. This allows for greater freedom in designing the semiconductor device 10 than when, for example, the third semiconductor element 70 is built into the first substrate 20.

[0055] (1-6) Furthermore, by providing the through holes 23, it is possible to prevent the second substrate 30 from being provided at a position that protrudes outward from the side surface of the first substrate 20. This makes it possible to suitably reduce the planar size of the semiconductor device 10.

[0056] (1-7) The through hole 23 is formed in a notch shape. In the semiconductor device 10 of this embodiment, the through hole 23 is formed to open in the X-axis direction. Therefore, when another component such as an optical fiber is connected to the end of the second semiconductor element 60 in the X-axis direction, interference of the other component with the first substrate 20 can be suitably suppressed.

[0057] (1-8) The thickness of the first substrate 20 is formed to be thicker than the combined thickness of the second substrate 30 and the third semiconductor element 70. In this configuration, the first substrate 20 is formed to be thick, while the second substrate 30 is formed to be thin. Therefore, even if the first substrate 20 is formed to be thick, the distance between the second semiconductor element 60 mounted on the upper surface 30A of the second substrate 30 and the third semiconductor element 70 mounted on the lower surface 30B of the second substrate 30 can be suitably shortened. This allows the wiring length between the second semiconductor element 60 and the third semiconductor element 70 to be shortened, thereby suitably improving the electrical characteristics.

[0058] Second embodiment Next, a second embodiment will be described with reference to Fig. 7. The following description will focus on the differences from the first embodiment. Note that the same members as those shown in Figs. 1 to 6 are denoted by the same reference numerals, and detailed description of each element will be omitted.

[0059] (Overall Configuration of Semiconductor Device 10A) 7, the semiconductor device 10A has a first substrate 20, a second substrate 30, a first semiconductor element 50, a second semiconductor element 70A, and a third semiconductor element 60A. The first semiconductor element 50 is mounted on the upper surface 21A of the first substrate 20 and the upper surface 30A of the second substrate 30 so as to straddle the first substrate 20 and the second substrate 30. The second semiconductor element 70A is mounted on the upper surface 30A of the second substrate 30. The third semiconductor element 60A is mounted on the lower surface 30B of the second substrate 30.

[0060] The second substrate 30 of this embodiment is formed to extend long in the X-axis direction. The wiring layers 31, 33, 35, 37, and 39 of the second substrate 30 have, for example, a wiring pattern that routes wiring, lands, etc. in a planar direction (here, the X-axis direction).

[0061] (Configuration of First Semiconductor Element 50) The first semiconductor element 50 is an LSI having an electric circuit for signal processing. The first semiconductor element 50 generates more heat than the second semiconductor element 70A. The first semiconductor element 50 generates more heat than the third semiconductor element 60A. The first semiconductor element 50, which generates more heat, is mounted on the upper surface 21A of the first substrate 20 and the upper surface 30A of the second substrate 30 so as to connect the first substrate 20 and the second substrate 30. The first semiconductor element 50 is flip-chip mounted on the upper surface 21A of the first substrate 20 and on the upper surface 30A of the second substrate 30.

[0062] (Configuration of second semiconductor element 70A) The second semiconductor element 70A is, for example, an electric IC for driving an optical circuit, similar to the third semiconductor element 70 shown in FIG. 1. The second semiconductor element 70A is a semiconductor element having a smaller thermal resistance than the first semiconductor element 50. The second semiconductor element 70A is a semiconductor element having a smaller thermal resistance than the first semiconductor element 50 and being weak against heat. The second semiconductor element 70A is flip-chip mounted on the upper surface 30A of the second substrate 30. The second semiconductor element 70A is electrically connected to the third connection pad P3 of the second substrate 30 via the bump 71 formed on the circuit formation surface (here, the lower surface) of the second semiconductor element 70A.

[0063] The second semiconductor element 70A is provided, for example, on the same plane as the first semiconductor element 50. The second semiconductor element 70A is provided at a predetermined distance from the first semiconductor element 50 in the X-axis direction. For example, the distance in the X-axis direction between the first semiconductor element 50 and the second semiconductor element 70A is larger than the distance in the X-axis direction between the inner wall surface of the through-hole 23 and the side surface of the second substrate 30. For example, the distance in the X-axis direction between the first semiconductor element 50 and the second semiconductor element 70A is smaller than the dimension of the second semiconductor element 70A along the X-axis direction.

[0064] (Configuration of third semiconductor element 60A) The third semiconductor element 60A is, for example, an optical IC, similar to the second semiconductor element 60 shown in FIG. 1. The third semiconductor element 60A is a semiconductor element having a smaller thermal resistance than the first semiconductor element 50. The third semiconductor element 60A is a semiconductor element having a smaller thermal resistance than the first semiconductor element 50 and being more vulnerable to heat. The third semiconductor element 60A is a semiconductor element having a smaller thermal resistance than the second semiconductor element 70A. That is, the third semiconductor element 60A is the semiconductor element having the smallest thermal resistance and being the most vulnerable to heat among the first semiconductor element 50, the second semiconductor element 70A, and the third semiconductor element 60A.

[0065] The third semiconductor element 60A, which is vulnerable to heat, is mounted on the lower surface 30B of the second substrate 30, which is opposite to the upper surface 30A on which the first semiconductor element 50 is mounted. The third semiconductor element 60A is flip-chip mounted on the lower surface 30B of the second substrate 30. The third semiconductor element 60A is electrically connected to the fourth connection pad P4 of the second substrate 30 via the bump 61 formed on the circuit formation surface (here, the upper surface) of the third semiconductor element 60A. Furthermore, the third semiconductor element 60A is provided so as to overlap the second semiconductor element 70A and not to overlap the first semiconductor element 50 in a plan view. This allows the third semiconductor element 60A, which is vulnerable to heat, and the first semiconductor element 50, which generates a large amount of heat, to be preferably separated by a predetermined distance. Therefore, the third semiconductor element 60A can be preferably prevented from being affected by the heat generated by the first semiconductor element 50. On the other hand, the third semiconductor element 60A can be provided in close proximity to the second semiconductor element 70A.

[0066] An end portion in the X-axis direction of the third semiconductor element 60A (the end portion on the right side in the figure) protrudes, for example, in the X-axis direction (to the right in the figure) further than the end face in the X-axis direction (the end face on the right side in the figure) of the second substrate 30. In other words, the end portion in the X-axis direction of the third semiconductor element 60A is provided so as not to overlap with the second substrate 30 in a plan view. An optical transmission path such as an optical fiber (not shown) is optically connected to the end portion in the X-axis direction of such a third semiconductor element 60A.

[0067] According to the present embodiment described above, in addition to the advantageous effects (1-1) to (1-3) and (1-5) to (1-8) of the first embodiment, the following advantageous effects can be achieved. (2-1) The third semiconductor element 60A, which is sensitive to heat, is provided so as to overlap the second semiconductor element 70A in plan view, but not so as to overlap the first semiconductor element 50, which generates a large amount of heat. This makes it possible to preferably separate the third semiconductor element 60A, which is sensitive to heat, from the first semiconductor element 50, which generates a large amount of heat, by a predetermined distance. This makes it possible to preferably prevent the third semiconductor element 60A from being affected by the heat generated by the first semiconductor element 50.

[0068] (Other embodiments) The above-described embodiments may be modified as follows: The above-described embodiments and the following modifications may be combined with each other to the extent that no technical contradiction occurs.

[0069] As shown in FIG. 8, a first heat sink 80 may be mounted on the upper surface of the first semiconductor element 50. The first heat sink 80 is thermally connected to the first semiconductor element 50. The first heat sink 80 of this modified example is also thermally connected to the second semiconductor element 60. The first heat sink 80 is bonded to the upper surface of the first semiconductor element 50 and the upper surface of the second semiconductor element 60 via an adhesive layer (not shown). For example, a thermosetting adhesive such as an epoxy-based, polyimide-based, or silicone-based adhesive, or a thermal interface material (TIM) can be used as the adhesive layer. The first heat sink 80 is also called a heat spreader. The first heat sink 80 has a function of dispersing the density of heat generated by the first semiconductor element 50.

[0070] According to this configuration, by providing the first heat sink 80, it is possible to efficiently dissipate heat generated in the first semiconductor element 50. Furthermore, by providing the first heat sink 80, it is possible to efficiently dissipate heat generated in the second semiconductor element 60. As a result, it is possible to suppress a rise in temperature of the first semiconductor element 50 and the second semiconductor element 60.

[0071] As shown in FIG. 8, a second heat sink 90 may be mounted on the lower surface of the third semiconductor element 70. The second heat sink 90 is thermally connected to the third semiconductor element 70. The second heat sink 90 is bonded to the lower surface of the third semiconductor element 70 via an adhesive layer (not shown). For example, a thermosetting adhesive such as an epoxy-based, polyimide-based, or silicone-based adhesive, or a heat-conductive material may be used as the adhesive layer. The second heat sink 90 is also called a heat spreader. The second heat sink 90 has a function of dispersing the density of heat generated by the third semiconductor element 70. The lower surface of the second heat sink 90 is provided, for example, above the lower surface 21B of the first substrate 20. In other words, the thickness of the first substrate 20 in this modified example is formed to be thicker than the combined thickness of the second substrate 30, the third semiconductor element 70, and the second heat sink 90.

[0072] According to this configuration, by providing the second heat sink 90, it is possible to efficiently dissipate the heat generated in the third semiconductor element 70. As a result, it is possible to suppress a rise in temperature of the third semiconductor element 70.

[0073] Furthermore, by providing the first heat sink 80 and the second heat sink 90, it is possible to form separate heat dissipation paths for the first semiconductor element 50 and the third semiconductor element 70. Therefore, the first semiconductor element 50 and the third semiconductor element 70 can efficiently dissipate heat without depending on each other's heat dissipation conditions.

[0074] As in the modification shown in FIG. 8, the semiconductor device 10A may be provided with a first heat sink 80 and a second heat sink 90. 8, the first heat sink 80 may be mounted only on the upper surface of the first semiconductor element 50. In other words, the first heat sink 80 may be modified so as not to be mounted on the upper surface of the second semiconductor element 60. In this case, a heat sink other than the first heat sink 80 may be mounted on the upper surface of the second semiconductor element 60.

[0075] In the modification shown in FIG. 8, either the first heat dissipation plate 80 or the second heat dissipation plate 90 may be omitted. In each of the above embodiments, the accommodation portion for accommodating the second substrate 30 in the internal space is embodied as the through hole 23 penetrating the first substrate 20 in the thickness direction, but is not limited thereto. For example, the accommodation portion for accommodating the second substrate 30 in the internal space may be embodied as a recess having a bottom surface. In this case, the accommodation portion is formed, for example, so as to be recessed from the upper surface 21A toward the lower surface 21B of the substrate body 21 of the first substrate 20. That is, the accommodation portion in this case does not penetrate the first substrate 20 in the thickness direction.

[0076] In each of the above-described embodiments, the through hole 23 is formed in a notch shape so as to open in the X-axis direction, but is not limited thereto. For example, the through hole 23 may be formed so as not to open in the X-axis direction.

[0077] The through hole 23 in each of the above embodiments may be omitted. In this case, for example, the second substrate 30 may be provided at a position protruding outward from any side surface of the first substrate 20.

[0078] The number of wiring layers and insulating layers in the second substrate 30 in each of the above embodiments, the layout of the wiring, and the like can be modified and changed in various ways. In the above-described embodiments, the second substrate 30 is embodied as a coreless substrate, but the present invention is not limited to this. For example, the second substrate 30 may be embodied as a wiring substrate having a core substrate.

[0079] In each of the above embodiments, the second substrate 30 may be disposed upside down. In this case, in the second substrate 30, the second connection pads P2 and the third connection pads P3 are provided on the wiring layer 31, and the fourth connection pads P4 are provided on the wiring layer 39.

[0080] In each of the above embodiments, the mounting form (flip-chip mounting, wire bonding mounting, solder mounting, or a combination thereof, etc.) of the first semiconductor element 50, the second semiconductor elements 60, 70A, and the third semiconductor elements 70, 60A can be modified or changed in various ways.

[0081] In the first embodiment, the arrangement of the first semiconductor element 50, the second semiconductor element 60, and the third semiconductor element 70 may be changed as appropriate. For example, the third semiconductor element 70 may be mounted on the upper surface 30A of the second substrate 30, and the second semiconductor element 60 may be mounted on the lower surface 30B of the second substrate 30.

[0082] In the above embodiments, the semiconductor device 10, 10A is embodied as an optical semiconductor device, but the semiconductor device 10, 10A may be embodied as a semiconductor device other than an optical semiconductor device. For example, the first semiconductor element 50, the second semiconductor element 60, 70A, and the third semiconductor element 70, 60A may be embodied as a semiconductor element other than an LSI for signal processing, an optical IC, and an electric IC for driving an optical circuit. For example, logic chips such as a CPU (Central Processing Unit) chip and a GPU (Graphics Processing Unit) chip may be used as the first semiconductor element 50, the second semiconductor element 60, 70A, and the third semiconductor element 70, 60A. In addition, for example, memory chips such as a DRAM (Dynamic Random Access Memory) chip and a flash memory chip may be used as the first semiconductor element 50, the second semiconductor element 60, 70A, and the third semiconductor element 70, 60A. [Explanation of symbols]

[0083] 10,10A Semiconductor Device 20 First board 21 Board body 21A Top 21B Bottom surface 23 Through hole 30 Second board 30A top 30B Bottom 50 First semiconductor element 60 Second semiconductor element 60A Third Semiconductor Element 70 Third semiconductor element 70A Second semiconductor element 80 1st heat sink 90 Second heat sink

Claims

1. A first substrate; a second substrate provided separately from the first substrate; a first semiconductor element mounted on an upper surface of the first substrate and an upper surface of the second substrate so as to straddle the first substrate and the second substrate; A second semiconductor element mounted on an upper surface of the second substrate; a third semiconductor element mounted on the lower surface of the second substrate; The third semiconductor element is provided so as to overlap the second semiconductor element in a plan view.

2. The semiconductor device according to claim 1 , wherein the third semiconductor element is provided so as to overlap the first semiconductor element in a plan view.

3. The semiconductor device according to claim 1 , wherein the third semiconductor element is provided so as not to overlap the first semiconductor element in a plan view.

4. the first semiconductor element is a semiconductor element that generates a larger amount of heat than each of the second semiconductor element and the third semiconductor element, 4. The semiconductor device according to claim 3, wherein the third semiconductor element is a semiconductor element having a smaller thermal resistance than the first semiconductor element.

5. the third semiconductor element is an optical IC having an optical circuit, the second semiconductor element is an electrical IC having an electrical circuit for driving an optical circuit, 5. The semiconductor device according to claim 4, wherein said first semiconductor element is an LSI having an electric circuit for signal processing.

6. The semiconductor device according to claim 1 , wherein the second substrate is provided so as not to overlap the first substrate in a plan view.

7. the first substrate has a through hole penetrating the first substrate in a thickness direction, The semiconductor device according to claim 6 , wherein the second substrate is provided in an internal space of the through hole.

8. The semiconductor device according to claim 7 , wherein the through hole is formed in a notch shape.

9. the second substrate is a coreless substrate, 2. The semiconductor device according to claim 1, wherein a thickness of said first substrate is greater than a combined thickness of said second substrate and said third semiconductor element.

10. a first heat sink mounted on an upper surface of the first semiconductor element; The semiconductor device according to claim 1 , further comprising: a second heat sink mounted on a lower surface of said third semiconductor element.

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